Wafer correction detection method, system, computer and storage medium

Abstract

The present invention provides a wafer correction detection method, system, computer and storage medium, which includes the following steps: controlling each probe in a probe group to detect a target area of ​​a wafer in sequence to obtain multiple verification data corresponding to each probe; using the verification data corresponding to any probe in the probe group as standard data, and obtaining multiple correction coefficients corresponding to other probes in the probe group based on the standard data; performing batch detection on wafers to obtain multiple detection data corresponding to each grain; and correcting the detection data based on the correction coefficient to obtain multiple target data corresponding to each grain. Before testing the wafer, the correction coefficient corresponding to each probe is calculated based on the differences between the verification data of each probe, and then the detection data subsequently obtained is corrected based on the correction coefficient, thereby eliminating the influence of the channel difference between each probe, obtaining target data with high stability and consistency, and improving the stability of product yield.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a wafer correction detection method, system, computer and storage medium. Background Art

[0002] In the LED semiconductor chip industry, after a 4-inch wafer is lit by a testing machine, a test document including the optoelectronic data corresponding to each grain can be generated. Based on the number of grains with abnormal optoelectronic data, the yield of the corresponding wafer can be obtained, thereby screening out abnormal wafers that do not meet the preset yield.

[0003] In the existing technology, automated testing machines use 8-channel testing. During normal automatic testing, probe wear causes errors between channels. The system and the machine are unable to make real-time corrections, resulting in large differences between the upper and lower lines of the tested data, which in turn causes abnormal brightness data. Usually, after the test is completed, the system will delete data that exceeds ±5% of the upper and lower lines based on screening to eliminate errors. However, due to the errors between channels, the amount of deleted data will be too large, thereby affecting the accuracy of the product yield. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a wafer correction detection method, which aims to solve the technical problem of poor accuracy of product yield in the prior art.

[0005] In order to achieve the above object, a first aspect of the present invention provides a wafer correction detection method, comprising the following steps:

[0006] Controlling each probe in the probe group to detect the target area of ​​the wafer in sequence to obtain a plurality of verification data corresponding to each probe;

[0007] using the calibration data corresponding to any probe in the probe group as standard data, so as to obtain a plurality of correction coefficients corresponding to other probes in the probe group based on the standard data;

[0008] Performing batch inspection on wafers based on each probe in the probe group to obtain a plurality of inspection data corresponding to each die;

[0009] The detection data is corrected based on the correction coefficient to obtain a plurality of target data corresponding to each grain.

[0010] According to one aspect of the above technical solution, the step of controlling each probe in the probe group to detect the target area of ​​the wafer in sequence to obtain a plurality of verification data corresponding to each probe specifically includes:

[0011] Performing positioning scanning on the fixed wafer to be inspected to identify a target area corresponding to the center point of the wafer;

[0012] Moving the probe group so that a first probe in the probe group is aligned with the target area for detection, and obtaining first verification data corresponding to the first probe;

[0013] The probe group is repeatedly moved to control other probes in the probe group to align with the target area for detection in sequence, until a plurality of verification data corresponding to each probe is obtained.

[0014] According to one aspect of the above technical solution, after the step of obtaining a plurality of verification data corresponding to each of the probes, the method further includes:

[0015] Uploading each verification data to the cloud, and determining whether there is any abnormal data in each verification data;

[0016] If there is abnormal data, the probe corresponding to the abnormal data will be marked and an alarm will be issued.

[0017] According to one aspect of the above technical solution, before the step of controlling each probe in the probe group to sequentially detect the target area of ​​the wafer, the method further includes:

[0018] Each probe in the probe group is cleaned.

[0019] According to one aspect of the above technical solution, the detection data includes voltage data, brightness data and wavelength data.

[0020] In a second aspect, the present invention provides a wafer correction detection system, comprising:

[0021] A verification module, configured to control each probe in the probe group to detect a target area of ​​the wafer in sequence, so as to obtain a plurality of verification data corresponding to each probe;

[0022] a correction module, configured to use the calibration data corresponding to any probe in the probe group as standard data, so as to obtain a plurality of correction coefficients corresponding to other probes in the probe group based on the standard data;

[0023] A detection module, configured to perform batch detection on wafers based on each probe in the probe group to obtain a plurality of detection data corresponding to each die;

[0024] The data module is used to correct the detection data based on the correction coefficient to obtain a plurality of target data corresponding to each grain.

[0025] According to one aspect of the above technical solution, the verification module is specifically used to:

[0026] Performing positioning scanning on the fixed wafer to be inspected to identify a target area corresponding to the center point of the wafer;

[0027] Moving the probe group so that a first probe in the probe group is aligned with the target area for detection, and obtaining first verification data corresponding to the first probe;

[0028] The probe group is repeatedly moved to control other probes in the probe group to align with the target area for detection in sequence, until a plurality of verification data corresponding to each probe is obtained.

[0029] According to one aspect of the above technical solution, the wafer correction detection system further includes:

[0030] An exception module is used to upload each verification data to the cloud and determine whether there is any abnormal data in each verification data;

[0031] If there is abnormal data, the probe corresponding to the abnormal data will be marked and an alarm will be issued.

[0032] According to one aspect of the above technical solution, the wafer correction detection system further includes:

[0033] The cleaning module is used to clean each probe in the probe group.

[0034] In a third aspect, an embodiment of the present application provides a computer comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the computer program, it implements a wafer correction detection method as described in the first aspect.

[0035] In a fourth aspect, an embodiment of the present application provides a storage medium on which a computer program is stored, which, when executed by a processor, implements a wafer correction detection method as described in the first aspect.

[0036] Compared with the prior art, the beneficial effect of the present invention lies in: before testing the wafer, each probe in the probe group is used to detect the same target area to obtain verification data corresponding to each probe, and further based on the differences between the verification data, the correction coefficient corresponding to each probe is calculated, and then the subsequent detection data obtained is corrected based on the correction coefficient, thereby eliminating the influence of the channel difference of each probe, obtaining target data with higher stability and consistency, and improving the stability of product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Flowchart of the wafer correction detection method according to the first embodiment of the present invention;

[0038] Figure 2 2 is a block diagram of a wafer correction and detection system according to a second embodiment of the present invention;

[0039] Figure 3 1 is a schematic diagram of the hardware structure of a computer in a third embodiment of the present invention;

[0040] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0041] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The drawings illustrate several embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0042] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] See also Figure 1 , which is a flow chart of a wafer correction detection method in a first embodiment of the present invention, as shown in the figure, the method includes the following steps:

[0045] Step S100 is to control each probe in the probe group to detect the target area of ​​the wafer in turn to obtain a plurality of verification data corresponding to each probe. Specifically, in this embodiment, the above step S100 specifically includes:

[0046] Step S110, positioning scanning is performed on the fixed wafer to be inspected to identify a target area corresponding to the center point of the wafer. Specifically, in this embodiment, after the fixed wafer to be inspected is scanned, the center point of the wafer is selected as the target area for subsequent verification data acquisition.

[0047] Step S120: Move the probe group so that the first probe in the probe group is aligned with the target area for detection, and obtain first verification data corresponding to the first probe. By way of example and not limitation, in some application scenarios of this embodiment, the number of probes in the probe group is eight. By moving the probe group, the first probe is aligned with the center point of the wafer for detection. At this time, of the eight data obtained by the probe group, only the data corresponding to the target area is used as verification data.

[0048] Step S130 : repeatedly moving the probe group to control other probes in the probe group to align with the target area for detection in sequence, until a plurality of verification data corresponding to each probe is obtained.

[0049] Preferably, in this embodiment, after the step of obtaining a plurality of verification data corresponding to each of the probes, the method further comprises:

[0050] In step S140, each of the calibration data is uploaded to the cloud, and it is determined whether there is any abnormal data in the calibration data. Specifically, in some application scenarios of this embodiment, if there is no abnormal data, the correction coefficients corresponding to other probes are calculated based on the calibrated standard data, and the correction coefficients are uploaded to the cloud network disk system.

[0051] Step S150: If there is abnormal data, the probe corresponding to the abnormal data is marked and an alarm is issued.

[0052] Specifically, the above-mentioned abnormal data refers to verification data, that is, the detection value of voltage data, brightness data or wavelength data, which exceeds the normal wear range of the probe, that is, the data is too high or too low, indicating that the probe itself has wear and other failure conditions. By analyzing the verification data, the probe can be self-tested before wafer testing to avoid large quantities of abnormal data during the automatic testing process, which affects the accuracy of product yield.

[0053] Preferably, in this embodiment, before the step of controlling each probe in the probe group to detect the target area of ​​the wafer in sequence, the method further includes:

[0054] Step S101 : performing a cleaning process on each probe in the probe group.

[0055] Step S200: Using the calibration data corresponding to any probe in the probe group as standard data, a plurality of correction coefficients corresponding to other probes in the probe group are obtained based on the standard data. Specifically, the calculation formula of the correction coefficient is K=S n / S1, K is the correction coefficient, S1 is the standard data, S n is the verification data corresponding to the nth probe.

[0056] Step S300: batch testing wafers based on each probe in the probe group to obtain a plurality of test data corresponding to each die. Specifically, in this embodiment, batch testing wafers by configuring a probe group with eight probes can improve test efficiency.

[0057] Specifically, in this embodiment, the detection data includes voltage data, brightness data, and wavelength data.

[0058] Step S400: Correct the test data based on the correction coefficients to obtain target data corresponding to each die. Specifically, in this embodiment, the test machine retrieves the correction coefficients corresponding to the probes through the cloud network disk system, and then corrects the data to obtain target data.

[0059] In some application scenarios of this embodiment, after completing a stage of testing, the above step S101 can be repeated to clean the probe and then update the correction coefficient. It can be understood that the above stage can be a partial area of ​​a single wafer, an entire wafer, or the detection of several wafers. In this embodiment, the test of a single wafer is selected as a stage. After completing the single wafer test, it is necessary to re-acquire a new correction coefficient to reduce errors, cope with large-scale chip testing, and improve the stability and consistency of product test data.

[0060] In summary, the wafer correction detection method in the above-mentioned embodiment of the present invention obtains verification data corresponding to each probe by having each probe in the probe group detect the same target area before testing the wafer, calculates the correction coefficient corresponding to each probe based on the difference between the verification data, and then corrects the subsequent detection data based on the correction coefficient, thereby eliminating the influence of the channel difference of each probe, obtaining target data with higher stability and consistency, and improving the stability of product yield.

[0061] The second embodiment of the present invention provides a wafer correction detection system, such as Figure 2 FIG. 1 is a block diagram of a wafer correction detection system according to a second embodiment of the present invention. As shown in the figure, the system includes:

[0062] The verification module 100 is used to control each probe in the probe group to detect the target area of ​​the wafer in sequence to obtain a plurality of verification data corresponding to each probe;

[0063] A correction module 200 is configured to use the calibration data corresponding to any probe in the probe group as standard data to obtain a plurality of correction coefficients corresponding to other probes in the probe group based on the standard data;

[0064] The detection module 300 is configured to perform batch detection on wafers based on each probe in the probe group to obtain a plurality of detection data corresponding to each die;

[0065] The data module 400 is configured to correct the detection data based on the correction coefficient to obtain a plurality of target data corresponding to each grain.

[0066] Preferably, in this embodiment, the verification module 100 is specifically used for:

[0067] Performing positioning scanning on the fixed wafer to be inspected to identify a target area corresponding to the center point of the wafer;

[0068] Moving the probe group so that a first probe in the probe group is aligned with the target area for detection, and obtaining first verification data corresponding to the first probe;

[0069] The probe group is repeatedly moved to control other probes in the probe group to align with the target area for detection in sequence, until a plurality of verification data corresponding to each probe is obtained.

[0070] Preferably, in this embodiment, the wafer correction detection system further includes:

[0071] An exception module is used to upload each verification data to the cloud and determine whether there is any abnormal data in each verification data;

[0072] If there is abnormal data, the probe corresponding to the abnormal data will be marked and an alarm will be issued.

[0073] Preferably, in this embodiment, the wafer correction detection system further includes:

[0074] The cleaning module is used to clean each probe in the probe group.

[0075] In summary, the wafer correction detection system in the above-mentioned embodiment of the present invention, by setting the verification module 100, detects the same target area with each probe in the probe group before testing the wafer, and obtains verification data corresponding to each probe. The correction module 200 calculates the correction coefficient corresponding to each probe based on the difference between the verification data, and then the detection data subsequently obtained is corrected based on the correction coefficient by the detection module 300 and the data module 400, thereby eliminating the influence of the channel difference of each probe, obtaining target data with higher stability and consistency, and improving the stability of product yield.

[0076] The third embodiment of the present application provides a computer, which may include a processor 81 and a memory 82 storing computer program commands. It is understood that the principles described in the wafer correction detection system of this embodiment correspond to the wafer correction detection method of the first embodiment of the present application. For details of related principles not described herein, please refer to the first embodiment and will not be elaborated upon here.

[0077] Specifically, the processor 81 may include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0078] Among them, the memory 82 may include a large-capacity memory for data or commands. By way of example and not limitation, the memory 82 may include a hard disk drive (HDD), a floppy disk drive, a solid-state drive (SSD), a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 82 may include a removable or non-removable (or fixed) medium. Where appropriate, the memory 82 may be inside or outside the data processing device. In a specific embodiment, the memory 82 is a non-volatile memory. In a specific embodiment, the memory 82 includes a read-only memory (ROM) and a random access memory (RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically alterable ROM (EAROM) or a flash memory (FLASH), or a combination of two or more of these. Under appropriate circumstances, the RAM can be a static random access memory (SRAM) or a dynamic random access memory (DRAM), where the DRAM can be a fast page mode dynamic random access memory (FPMDRAM), an extended data output dynamic random access memory (EDODRAM), a synchronous dynamic random access memory (SDRAM), etc.

[0079] The memory 82 may be used to store or cache various data files that need to be processed and / or used for communication, as well as possible computer program commands executed by the processor 81 .

[0080] The processor 81 reads and executes computer program commands stored in the memory 82 to implement any one of the wafer correction detection methods in the above embodiments.

[0081] In some embodiments, the computer may further include a communication interface 83 and a bus 80. Figure 3 As shown, the processor 81, the memory 82, and the communication interface 83 are connected via a bus 80 and communicate with each other.

[0082] The communication interface 83 is used to implement communication between the various modules, devices, units, and / or devices in the embodiments of the present application. The communication interface 83 can also implement data communication with other components such as: external devices, image / data acquisition equipment, databases, external storage, and image / data processing workstations.

[0083] The bus 80 includes hardware, software, or both, and couples the components of the computer to each other. The bus 80 includes, but is not limited to, at least one of the following: a data bus, an address bus, a control bus, an expansion bus, and a local bus. By way of example and not limitation, bus 80 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses, or a combination of two or more of these. Bus 80 may include one or more buses, where appropriate. Although embodiments herein describe and illustrate a particular bus, this application contemplates any suitable bus or interconnect.

[0084] The technical features of the above-described embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A wafer correction detection method, characterized in that: The following steps are involved: Controlling each probe in the probe group to detect the target area of ​​the wafer in turn to obtain a plurality of verification data corresponding to each probe; using the calibration data corresponding to any probe in the probe group as standard data, so as to obtain a plurality of correction coefficients corresponding to other probes in the probe group based on the standard data; Performing batch inspection on wafers based on each probe in the probe group to obtain a plurality of inspection data corresponding to each die; The detection data is corrected based on the correction coefficient to obtain a plurality of target data corresponding to each grain.

2. The wafer correction detection method according to claim 1, characterized in that: The steps of controlling each probe in the probe group to detect the target area of ​​the wafer in sequence to obtain a plurality of verification data corresponding to each probe specifically include: Performing positioning scanning on the fixed wafer to be inspected to identify a target area corresponding to the center point of the wafer; Moving the probe group so that a first probe in the probe group is aligned with the target area for detection, and obtaining first verification data corresponding to the first probe; The probe group is repeatedly moved to control other probes in the probe group to align with the target area for detection in sequence, until a plurality of verification data corresponding to each probe is obtained.

3. The wafer correction detection method according to claim 2, characterized in that: After the step of obtaining a plurality of verification data corresponding to each of the probes, the method further comprises: Uploading each verification data to the cloud, and determining whether there is any abnormal data in each verification data; If there is abnormal data, the probe corresponding to the abnormal data will be marked and an alarm will be issued.

4. The wafer correction detection method according to claim 1, characterized in that: Before the step of controlling each probe in the probe group to sequentially detect the target area of ​​the wafer, the method further includes: Each probe in the probe group is cleaned.

5. The wafer correction detection method according to claim 1, characterized in that: The detection data includes voltage data, brightness data and wavelength data.

6. A wafer correction detection system, characterized in that: include: A verification module is used to control each probe in the probe group to detect the target area of ​​the wafer in sequence to obtain a plurality of verification data corresponding to each probe; a correction module, configured to use the calibration data corresponding to any probe in the probe group as standard data, so as to obtain a plurality of correction coefficients corresponding to other probes in the probe group based on the standard data; A detection module, configured to perform batch detection on wafers based on each probe in the probe group to obtain a plurality of detection data corresponding to each die; The data module is used to correct the detection data based on the correction coefficient to obtain a plurality of target data corresponding to each grain.

7. The wafer correction detection system according to claim 6, characterized in that: The verification module is specifically used for: Performing positioning scanning on the fixed wafer to be inspected to identify a target area corresponding to the center point of the wafer; Moving the probe group so that a first probe in the probe group is aligned with the target area for detection, and obtaining first verification data corresponding to the first probe; The probe group is repeatedly moved to control other probes in the probe group to align with the target area for detection in sequence, until a plurality of verification data corresponding to each probe is obtained.

8. The wafer correction detection system according to claim 6, characterized in that: The wafer correction detection system further includes: An exception module is used to upload each verification data to the cloud and determine whether there is any abnormal data in each verification data; If there is abnormal data, the probe corresponding to the abnormal data will be marked and an alarm will be issued.

9. A computer comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the wafer correction detection method according to any one of claims 1 to 5 is implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the wafer correction detection method according to any one of claims 1 to 5 is implemented.

Images