Micro display chip preparation method and micro display chip

Abstract

The application provides a micro display chip preparation method and a micro display chip, and the preparation method comprises the following steps: providing a growth substrate and a CMOS driving wafer, growing a light emitting structure on the growth substrate, connecting the light emitting structure and the CMOS driving wafer through a bonding layer, removing the growth substrate and part of the light emitting structure, performing multiple etching on the surface of the epitaxial layer after removing part of the light emitting structure, forming a plurality of independent micro display units, depositing an insulating medium layer on the surface of the epitaxial layer to completely cover the micro display units, etching the insulating medium layer between the micro display units to obtain a groove, depositing a conductive material in the groove to form a conductive groove, depositing a conductive metal between adjacent conductive grooves to form a metal electrode, and obtaining a target micro display chip, wherein the axis direction of the metal electrode is perpendicular to the axis direction of the conductive groove. The micro display chip prepared by the application reduces the shielding of the chip light emission by the electrode and improves the light emission efficiency of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor wafer preparation, and particularly relates to a micro display chip preparation method and a micro display chip. BACKGROUND

[0002] In recent years, LED chips are widely used in lighting and display fields due to their high efficiency, energy saving, environmental protection and many other advantages. The manufacturing process of the LED chip includes preparing a substrate, depositing an epitaxial layer on the substrate to form a wafer, and then preparing a required LED chip on the wafer.

[0003] A micro LED display chip is composed of an array of micron semiconductor light-emitting units, is an electroluminescent device that can convert electrical energy into light energy, and can be transferred to a driving circuit substrate in batches. The micro LED display chip has the advantages of self-luminescence, high efficiency, low power consumption, high integration, high stability and all-weather working, and is considered to be one of the most promising next-generation new display and light-emitting devices. At present, in order to realize the electrical connection of the micro LED driving substrate and the electrical connection between each micro LED, an electrode needs to be led out on the micro LED light-emitting mesa, and this part of the electrode will block the light of the chip and affect the light efficiency of the chip. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a micro display chip preparation method to solve the problems in the prior art.

[0005] In one aspect, the present application provides a micro display chip preparation method, comprising the following steps:

[0006] Step one, providing a growth substrate, growing a light-emitting structure on the growth substrate, and sequentially depositing a P electrode layer and a first bonding layer on the surface of the light-emitting structure;

[0007] Step two, providing a CMOS driving wafer, depositing a second bonding layer on the surface of the CMOS driving wafer, and bonding the first bonding layer and the second bonding layer;

[0008] Step three, removing the growth substrate and part of the light-emitting structure, performing first etching on the surface of the epitaxial layer of the removed part of the light-emitting structure to form a plurality of independent light-emitting mesas, and performing second etching between the plurality of light-emitting mesas until the surface of the CMOS driving wafer is etched to obtain a plurality of independent micro display units;

[0009] Step four, depositing an insulating medium layer between the plurality of micro display units, wherein the height of the insulating medium layer filled is greater than the height of the micro display units, so that the plurality of micro display units are covered by the insulating medium layer;

[0010] Step five, etching the insulating medium layer between the micro display units to form a groove between the micro display units, filling the groove with conductive material to obtain a conductive groove;

[0011] Step six, depositing a conductive metal between adjacent conductive grooves to form a metal electrode, obtaining a target micro display chip, the axis direction of the metal electrode being perpendicular to the axis direction of the conductive groove.

[0012] The micro display chip preparation method provided by the present application, first, a light emitting structure, a P electrode layer and a first bonding layer are prepared on a growth substrate, a second bonding layer is deposited on the surface of a CMOS driving wafer, and the first bonding layer and the second bonding layer are bonded, then the growth substrate and part of the light emitting structure are removed, a first etching is performed on the epitaxial layer after removing part of the light emitting structure to form a plurality of independent light emitting platforms, a second etching is performed between the light emitting platforms until the surface of the CMOS driving wafer is etched to form a connecting platform at the bottom of the light emitting platform, thereby obtaining a plurality of independent micro display units. Then, an insulating medium layer is deposited between the micro display units, and the micro display units are covered by the insulating medium layer. The insulating medium layer is etched to form a groove between the micro display units, and the groove is filled with conductive material to obtain a conductive groove. A conductive metal is deposited between adjacent conductive grooves to form a metal electrode to obtain a target micro display chip, and the axis direction of the metal electrode is perpendicular to the axis direction of the conductive groove. The micro display chip prepared by the micro display chip preparation method provided by the present application realizes electrical connection between chips through the conductive groove and the metal electrode perpendicular to the conductive groove, and the conductive groove and the metal electrode are both located on the side edge of the light emitting chip and do not block the light emission of the chip, thereby improving the light emitting effect of the micro display chip and being suitable for wide promotion.

[0013] Preferably, in the step one, the light emitting structure comprises a buffer layer, an N-type GaN layer, a multi-quantum well layer and a P-type GaN layer deposited on the growth substrate in sequence, the P electrode layer is made of ITO or Pt, the first bonding layer is an alloy layer formed by Cr, Ti, Pt, Ni, Sn and Au, and the thickness of the first bonding layer is 0.3-0.5 μm.

[0014] Preferably, the step three specifically comprises:

[0015] The growth substrate, the buffer layer and part of the N-type GaN layer are removed in sequence;

[0016] The N-type GaN layer, the multi-quantum well layer and the P-type GaN layer are etched in sequence along the direction close to the CMOS driving wafer to the surface of the P electrode layer to obtain a plurality of independent light emitting platforms.

[0017] A second etching is performed in a direction close to the CMOS driving wafer between the light emitting platforms, and the P electrode layer, the first bonding layer and the second bonding layer are sequentially etched until the surface of the CMOS driving wafer, so that the P electrode layers of the light emitting platforms are disconnected, and a plurality of independent micro display units are obtained.

[0018] Preferably, the insulating medium layer is a transparent medium layer, and the insulating medium layer is made of one of SiO2, SiN, SiON and polyimide material.

[0019] Preferably, the bottom of the trench is located between the N-type GaN layer and the multi-quantum well layer.

[0020] Preferably, the conductive material is made of one of ITO, FTO and AZO, the conductive metal is a combination of Cr, Al, Ni, Ti, Pt and Au, and the thickness of the metal electrode is 500-3000 nm.

[0021] Preferably, in the second step, the second bonding layer is made of the same element as the first bonding layer, and the thickness of the second bonding layer is the same as that of the first bonding layer.

[0022] The CMOS driving wafer is provided with a micro display array driving circuit, the second bonding layer is in communication with a metal contact on the surface of the CMOS driving wafer, and the first bonding layer and the second bonding layer are connected by hot-press bonding.

[0023] Another aspect of the present application provides a micro display chip prepared by the above-mentioned micro display chip preparation method.

[0024] Additional aspects and advantages of the present application will be partially given in the following description, partially will become obvious from the following description, or will be understood by the practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A flow chart of the micro display chip preparation method provided by the present application is shown in the following figure;

[0026] Figure 2 A structure diagram after depositing a light emitting structure on a growth substrate is shown in the following figure;

[0027] Figure 3 A structure diagram after depositing a second bonding layer on a CMOS driving wafer is shown in the following figure;

[0028] Figure 4 An epitaxial layer structure diagram after the first bonding layer and the second bonding layer are connected is shown in the following figure;

[0029] Figure 5 Process schematic diagram for removing part of the light emitting structure;

[0030] Figure 6 Schematic diagram of the structure of the light emitting mesa;

[0031] Figure 7 Schematic diagram of the structure of the micro display unit;

[0032] Figure 8 Schematic diagram of the structure after depositing the insulating medium layer;

[0033] Figure 9 Schematic diagram of the structure of the trench bottom after etching the trench;

[0034] Figure 10 Schematic diagram of the cross section structure of the conductive trench;

[0035] Figure 11 Schematic diagram of the top view of the conductive trench;

[0036] Figure 12 Schematic diagram of the cross section structure of the target micro display chip after forming the metal electrode;

[0037] Figure 13 Schematic diagram of the top view of the target micro display chip after forming the metal electrode.

[0038] Main component symbol explanation:

[0039] 10, growth substrate; 11, buffer layer; 12, N-type GaN layer; 13, multi-quantum well layer; 14, P-type GaN layer; 15, P electrode layer; 16, first bonding layer; 17, insulating medium layer; 18, conductive trench; 19, metal electrode; 20, CMOS driving wafer; 21, second bonding layer; 22, micro display array driving circuit; 30, light emitting mesa; 40, micro display unit.

[0040] The following specific embodiments will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0041] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The drawings show several embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0042] It should be understood that when an element as a layer, region or plate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In addition, it should be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can also be present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] Embodiment one

[0045] Referring to Figure 1 , a micro display chip preparation method in the first embodiment of the present application is shown, the preparation method comprises the following steps:

[0046] Step one, providing a growth substrate, growing a light emitting structure on the growth substrate, and depositing a P electrode layer and a first bonding layer on the surface of the light emitting structure in sequence;

[0047] It should be explained that in the embodiment, the substrate can be selected from one of sapphire substrate, SiO2sapphire composite substrate, silicon substrate, silicon carbide substrate, gallium nitride substrate, zinc oxide substrate, GaAs substrate, and in the embodiment, silicon is selected as the growth substrate 10, and the light emitting structure is deposited in a metal organic chemical vapor deposition (MOCVD) device. Optionally, as shown in Figure 2 , the light emitting structure comprises a buffer layer 11, an N type GaN layer 12, a multi quantum well layer 13, and a P type GaN layer 14 deposited on the growth substrate in sequence; the P electrode layer 15 is one of ITO (indium tin oxide) or Pt; the first bonding layer 16 is an alloy layer formed by Cr, Ti, Pt, Ni, Sn, and Au, and the thickness of the first bonding layer 16 can be 0.3 μm-0.5 μm, and in the embodiment, the P electrode layer 15 is an ITO layer, and the thickness of the first bonding layer 16 is 0.4 μm.

[0048] Step two, providing a CMOS driving wafer, depositing a second bonding layer on the surface of the CMOS driving wafer, and bonding the first bonding layer and the second bonding layer;

[0049] Optionally, as shown in Figure 3 ,Figure 3 This is a structural diagram of the second bonding layer 21 deposited on the surface of a CMOS (Complementary Metal Oxide Semiconductor) driving wafer according to this application. In this embodiment, the constituent elements of the second bonding layer 21 are the same as those of the first bonding layer 16, and the thickness of the second bonding layer 21 is the same as that of the first bonding layer 16. That is, the second bonding layer 21 is an alloy layer formed by a combination of Cr, Ti, Pt, Ni, Sn, and Au. The thickness of the second bonding layer 21 can be 0.3μm-0.5μm. In this embodiment, the thickness of the second bonding layer 21 is 0.4μm.

[0050] Furthermore, the CMOS driver wafer 20 is pre-installed with a microdisplay array driving circuit 22. A second bonding layer 21 is deposited on the surface of the CMOS driver wafer 20, and the second bonding layer 21 is connected to the metal contacts on the surface of the CMOS driver wafer 20. Then, the bonding metal faces of the first bonding layer 16 and the second bonding layer 21 are aligned, and the first bonding layer and the second bonding layer are connected by thermocompression bonding. The epitaxial layer structure after the first bonding layer 16 and the second bonding layer 21 are bonded is as follows. Figure 4 As shown.

[0051] Step 3: Remove the growth substrate and part of the light-emitting structure, perform a first etching on the surface of the epitaxial layer with the removed light-emitting structure to form a number of independent light-emitting mesa, and perform a second etching between the number of light-emitting mesa until etching reaches the surface of the CMOS driving wafer to obtain a number of independent micro-display units.

[0052] Optional, such as Figure 5 As shown, the light-emitting structure includes a buffer layer 11, an N-type GaN layer 12, a multiple quantum well layer 13, and a P-type GaN layer 14 sequentially deposited on a growth substrate; the growth substrate 10, the buffer layer 11, and a portion of the N-type GaN layer 12 after the bonded epitaxial layer are sequentially removed; as shown... Figure 6 As shown, a first etching is then performed on the surface where part of the N-type GaN layer 12 has been removed. The first etching direction is along the direction close to the CMOS driving wafer 20, sequentially etching the N-type GaN layer 12, the multiple quantum well layer 13, and the P-type GaN layer 14 until the surface of the P-electrode layer 15, resulting in several independent light-emitting mesa 30; as shown Figure 7As shown, after forming the light-emitting mesa 30, a second etching is further performed between the light-emitting mesa 30, the direction of the second etching is similar to that of the first etching, and the P electrode layer 15, the first bonding layer 16 and the second bonding layer 21 are etched in sequence until the surface of the CMOS driving wafer 20, the P electrode layer of the several light-emitting mesa 30 is disconnected by the second etching, and the several independent micro display units 40 are obtained. Optionally, in the embodiment, the first etching and the second etching are both plasma etching, the etching gas of the plasma etching in the first etching is a mixed gas composed of Cl2, Ar, BCl3, etc., and the etching gas of the plasma etching in the second etching is Ar.

[0053] It can be understood that the light-emitting chip can include several independent light-emitting units, that is, several light-emitting mesa 30, the preparation process and structure of one of them are described, and the rest of the light-emitting units are similar, which will not be described here again. The epitaxial layer after two etchings is as shown in Figure 7 .

[0054] Step four, depositing an insulating medium layer between the several micro display units, wherein the filling height of the insulating medium layer is greater than the height of the micro display unit, so that the several micro display units are covered by the insulating medium layer;

[0055] Optionally, in the embodiment, the insulating medium layer 17 is deposited on the surface of the epitaxial layer after the two etchings, preferably, the insulating material can be a transparent insulating material, and the insulating medium layer is made of one of SiO2, SiN, SiON and polyimide material; optionally, in the embodiment, the insulating medium layer is made of polyimide; as shown in Figure 8 , the insulating medium layer is deposited between the several micro display units, the gap between the micro display units is filled in sequence, and the height of the insulating medium layer is higher than the height of the micro display unit 40, and the insulating medium layer covers the entire mesa.

[0056] Step five, etching the insulating medium layer between the several micro display units to form a groove between the several micro display units, and filling the groove with a conductive material to obtain a conductive groove;

[0057] Optionally, in the embodiment, as shown in Figure 9As shown, the part of the insulating medium layer between the adjacent micro display units is etched to form a trench between the adjacent micro display units 40, and the bottom of the trench is between the N-type GaN layer 12 and the multi-quantum well layer 13. In this embodiment, the insulating medium layer can be etched by plasma, and the etching gas is a mixed gas composed of CF4, SF6, Ar, O2, etc. Preferably, in this embodiment, the etching to form the trench can be carried out in stages. The first stage is high-power rapid etching, and the second stage is low-power etching connected to the first stage. The etching effect is improved by the stage etching. The etching trench is etched to the bottom between the N-type GaN layer 12 and the multi-quantum well layer 13. Then, the trench is filled with a conductive material to form a conductive trench 18, and the conductive material is made of one of ITO, FTO and AZO. In this embodiment, the conductive material is made of ITO. The depth of the trench is set between the N-type GaN layer 12 and the multi-quantum well layer 13, so that the insulating partition can be effectively formed between the N-type GaN layer 12 and the P-type GaN layer 14, preventing the device from leaking after the conductive material is filled in the trench. The device structure after the conductive material is filled is shown in Figure 10 and Figure 11 .

[0058] Step six, depositing a conductive metal between the adjacent conductive trenches to form a metal electrode, and obtaining a target micro display chip, the axis direction of the metal electrode is perpendicular to the axis direction of the conductive trench.

[0059] Optionally, as shown in Figure 12 and Figure 13 , a conductive metal is deposited between the adjacent micro display units 40 in a direction perpendicular to the conductive trench 18 to form a metal electrode 19. The metal electrode can effectively enhance the current spreading capability of the micro display chip micro LED array. The conductive metal can be Cr, Al, Ni, Ti, Pt, Au combination metal, and the thickness of the metal electrode can be 500-3000 nm. In this embodiment, the thickness of the metal electrode is 1000 nm.

[0060] The micro display chip preparation method provided in the application first prepares a light emitting structure, a P electrode layer and a first bonding layer on a growth substrate, deposits a second bonding layer on the surface of a CMOS driving wafer, bonds the first bonding layer and the second bonding layer, then removes the growth substrate and part of the light emitting structure, performs first etching on the epitaxial layer after removing part of the light emitting structure to form a plurality of independent light emitting mesas, performs second etching between the plurality of light emitting mesas until the CMOS driving wafer surface is etched to form a connecting mesa at the bottom of the light emitting mesa, and a plurality of independent micro display units are obtained. Then, an insulating medium layer is deposited between the micro display units, and the plurality of micro display units are covered by the insulating medium layer. The insulating medium layer is etched to form a groove between the plurality of micro display units, and a conductive material is filled in the groove to obtain a conductive groove. A conductive metal is deposited between adjacent conductive grooves to form a metal electrode, and a target micro display chip is obtained. The axis direction of the metal electrode is perpendicular to the axis direction of the conductive groove. The micro display chip prepared by the micro display chip preparation method provided in the application realizes electrical connection between chips through the conductive groove and the metal electrode perpendicular to the conductive groove. The conductive groove and the metal electrode are both located at the side edge of the light emitting chip and do not block the light emission of the chip, thereby improving the light emitting effect of the micro display chip and being suitable for wide promotion.

[0061] Embodiment two

[0062] The embodiment provides a micro display chip prepared by the micro display chip preparation method in embodiment one.

[0063] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0064] The above-described embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it cannot be understood as a limitation on the patent scope of the present application. It should be noted that, for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for fabricating a microdisplay chip, characterized in that, The method comprises the following steps: Step 1: providing a growth substrate, growing a light emitting structure on the growth substrate, and sequentially depositing a P electrode layer and a first bonding layer on the surface of the light emitting structure; Step 2: providing a CMOS driving wafer, depositing a second bonding layer on the surface of the CMOS driving wafer, and bonding the first bonding layer and the second bonding layer; Step 3: removing the growth substrate and part of the light emitting structure, performing first etching on the surface of the epitaxial layer of the removed part of the light emitting structure to form a plurality of independent light emitting mesas, and performing second etching between the plurality of light emitting mesas until the surface of the CMOS driving wafer is etched to obtain a plurality of independent micro display units; Step 4: depositing an insulating medium layer between the plurality of micro display units, wherein the filling height of the insulating medium layer is greater than the height of the micro display units, so that the plurality of micro display units are covered by the insulating medium layer; Step 5: etching the insulating medium layer between the plurality of micro display units to form a groove between the plurality of micro display units, filling the groove with a conductive material to obtain a conductive groove; Step 6: depositing a conductive metal between adjacent conductive grooves to form a metal electrode, and obtaining a target micro display chip, wherein the axis direction of the metal electrode is perpendicular to the axis direction of the conductive groove, and the conductive groove and the metal electrode are located on the side edge of the chip to prevent the light emitted by the chip from being blocked.

2. The method of claim 1, wherein the microdisplay chip is prepared by a method comprising: In the step 1, the light emitting structure comprises a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer deposited on the growth substrate in sequence, the P electrode layer is made of ITO or Pt, the first bonding layer is an alloy layer formed by Cr, Ti, Pt, Ni, Sn, and Au, and the thickness of the first bonding layer is 0.3-0.5 μm.

3. The method of claim 2, wherein the microdisplay chip is prepared by a method comprising: The step 3 specifically comprises: sequentially removing the growth substrate, the buffer layer, and part of the N-type GaN layer; performing first etching on the N-type GaN layer in the direction close to the CMOS driving wafer to sequentially etch the N-type GaN layer, the multi-quantum well layer, and the P-type GaN layer until the surface of the P electrode layer, and obtaining a plurality of independent light emitting mesas; performing second etching between the plurality of light emitting mesas in the direction close to the CMOS driving wafer to sequentially etch the P electrode layer, the first bonding layer, and the second bonding layer until the surface of the CMOS driving wafer, so that the P electrode layers of the plurality of light emitting mesas are disconnected, and a plurality of independent micro display units are obtained.

4. The method of claim 3, wherein the microdisplay chip is prepared by a method comprising: The insulating medium layer is a transparent medium layer, and the insulating medium layer is made of one of SiO2, SiN, SiON, and polyimide material.

5. The method of claim 3, wherein the microdisplay chip is prepared by a method comprising: The bottom of the groove is located between the N-type GaN layer and the multi-quantum well layer.

6. The method of claim 1, wherein the microdisplay chip is prepared by a method comprising: The conductive material is made of one of ITO, FTO, and AZO, the conductive metal is a combined metal of Cr, Al, Ni, Ti, Pt, and Au, and the thickness of the metal electrode is 500-3000 nm.

7. The method of claim 1, wherein the microdisplay chip is prepared by a method comprising: In the second step, the second bonding layer has the same composition elements as the first bonding layer, and the second bonding layer has the same thickness as the first bonding layer; ​ The CMOS driving wafer is provided with a micro display array driving circuit in advance, the second bonding layer is in communication with a metal contact on the surface of the CMOS driving wafer, and the first bonding layer and the second bonding layer are connected by means of thermal compression bonding.

8. A microdisplay chip, characterized by The micro display chip is prepared by the method according to any one of claims 1-7.

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