A load switch circuit output short circuit protection circuit and control method thereof
By using the combination of fast_off circuit and current limiting loop circuit in the load switch circuit, the falling edge sampling and timing modules are used to achieve fast shutdown and current limit protection, the problem of instantaneous high current in the prior art is solved, and the problem of rapid short circuit is reduced. Circuit space and power consumption achieve rapid recovery.
Patent Information
- Application Number
- CN202411397781.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2044-10-09
AI Technical Summary
Existing load switching circuits may generate large instantaneous current when the fast output short circuit is shorted, resulting in device damage. The existing fast_off circuits require expansion of the current sampling circuit bandwidth and use complex fast voltage comparators, resulting in large circuit space and static power consumption. high.
A load switch circuit output short circuit protection circuit is designed, using fast_off circuit and current limiting loop circuit, which can achieve rapid shutdown through falling edge sampling circuit and timing module, and current limiting protection is achieved through current limiting loop circuit, avoiding fast current sampling and the use of high-speed voltage comparators.
It realizes the current control in the range of several amperes in a few tens of microseconds during fast short circuit at the us level, and the current limit protection is achieved through delay reset. The circuit space is small and the static power consumption is low, so it can quickly restore normal operation.
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Figure CN118899803B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a short circuit protection circuit and a control method thereof, in particular to a load switch circuit output short circuit protection circuit and a control method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art
[0002] A load switch circuit refers to a circuit that is connected in series between the power supply and the load for current sampling and current control. It generally has current limiting and short-circuit overcurrent protection functions.
[0003] The existing output short-circuit protection technology mainly adopts Figure 6 As shown, 101 is a load switch tube, and the current sampling circuit 102 is used to sample the proportionally reduced sampling current Isense, and the sampling current Isense is allowed to flow through the resistor. By taking different sampling points on the resistor or taking different Vref voltages, the current limiting loop circuit 103 and the fast_off circuit 104 perform voltage comparison to generate a fast off signal 105 and a current limiting loop signal 106, and control the conduction of the load switch tube 101 to limit the current. The triggering of fast off in this method requires current sampling first, and then voltage comparison. Therefore, when the output is short-circuited quickly, a relatively large current may still be generated instantly, and there is a risk of damage to the circuit components. Therefore, the existing fast_off circuit needs to shorten the sampling delay time as much as possible. In order to increase the speed, the existing fast_off circuit will expand the bandwidth of the current sampling circuit and use a complex fast voltage comparator, etc. The circuit occupies a large space and consumes a large static power consumption. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide a load switch circuit output short-circuit protection circuit and a control method thereof, so as to realize comprehensive and rapid current limiting protection.
[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:
[0006] A load switch circuit output short-circuit protection circuit comprises a load switch tube NM1, a current sampling MOS tube NM2, a current sampling circuit, a fast_off circuit, a current limiting loop circuit, a NGATE_CTR circuit and a pull-up current source circuit, wherein the drain of the load switch tube NM1 and the drain of the current sampling MOS tube NM2 are connected to an input signal VIN, the gate of the load switch tube NM1 is connected to the gate of the current sampling MOS tube NM2, the output end of the NGATE_CTR circuit and the output end of the pull-up current source circuit, the source of the load switch tube NM1 is connected to the first input end of the current sampling circuit and the input end of the fast_off circuit and generates an output signal VOUT, the output end of the fast_off circuit is connected to the first input end of the NGATE_CTR circuit, the source of the current sampling MOS tube NM2 is connected to the second input end of the current sampling circuit, the output end of the current sampling circuit is connected to the input end of the current limiting loop circuit, and the output end of the current limiting loop circuit is connected to the second input end of the NGATE_CTR circuit.
[0007] Furthermore, the current sampling circuit includes an operational amplifier A1 and a PMOS tube PM1, the non-inverting input terminal of the operational amplifier A1 serves as a first input terminal of the current sampling circuit, the reverse input terminal of the operational amplifier A1 is connected to the source of the PMOS tube PM1 and serves as a second input terminal of the current sampling circuit, the output terminal of the operational amplifier A1 is connected to the gate of the PMOS tube PM1, and the drain of the PMOS tube PM1 serves as an output terminal of the current sampling circuit.
[0008] Furthermore, the fast_off circuit includes a falling edge sampling circuit, a D flip-flop DFF and a timing module circuit, the input end of the falling edge sampling circuit serves as the input end of the fast_off circuit and is connected to the output signal VOUT, the output end of the falling edge sampling circuit is connected to the CLK end of the D flip-flop DFF, the Q end of the D flip-flop DFF is connected to the input end of the timing module circuit, the first output end of the timing module is connected to the RESET end of the D flip-flop DFF, and the second output end of the timing module serves as the output end of the fast_off circuit.
[0009] Furthermore, the falling edge sampling circuit includes a resistor R1, a capacitor C1, a PMOS tube PM2, an NMOS tube NM3, an NMOS tube NM4 and a bias current source Ibias, one end of the resistor R1 is connected to the gate of the PMOS tube PM2 and serves as the input end of the falling edge sampling circuit, the other end of the resistor R1 is connected to one end of the capacitor C1 and the source of the PMOS tube PM2, the other end of the capacitor C1 is grounded, the drain of the PMOS tube PM2 is connected to the drain of the NMOS tube NM3 and serves as the output end of the falling edge sampling circuit, the gate of the NMOS tube NM3 is connected to the gate of the NMOS tube NM4, the drain of the NMOS tube NM4 and the output end of the bias current source Ibias, the input end of the bias current source Ibias is connected to the power supply VDD, and the source of the NMOS tube NM3 and the source of the NMOS tube NM4 are grounded.
[0010] Further, the current limiting loop circuit includes an operational amplifier A2, a fold back comparator A3, an NMOS tube NM5, an NMOS tube NM6, a voltage dividing resistor R2, a voltage dividing resistor R3 and a voltage dividing resistor R4, the same-direction input end of the operational amplifier A2 is connected to the drain of the NMOS tube NM5 and the drain of the NMOS tube NM6 and serves as the input end of the current limiting loop circuit, the reverse input end of the operational amplifier A2 is connected to one end of the voltage dividing resistor R2 and connected to the reference current Iref, the output end of the operational amplifier A2 serves as the output end of the current limiting loop circuit, the source of the NMOS tube NM5 is connected to one end of the voltage dividing resistor R3, the source of the NMOS tube NM6 is connected to one end of the voltage dividing resistor R4, the other end of the voltage dividing resistor R2, the other end of the voltage dividing resistor R3 and the other end of the voltage dividing resistor R4 are grounded, the same-direction input end of the foldback comparator A3 is connected to the external bias voltage VREF, the reverse input end of the fold back comparator A3 is connected to the output signal VOUT, and the fold back comparator A3 is connected to the output signal VOUT. The output end of the back comparator A3 is connected to the input end of the inverter INV1 and the gate of the NMOS transistor NM5 to generate a first feedback signal ctl1 , and the output end of the inverter INV1 is connected to the gate of the NMOS transistor NM6 to generate a second feedback signal ctl2 .
[0011] Furthermore, the gate of the NMOS transistor NM5 is connected to the first feedback signal, the gate of the NMOS transistor NM6 is connected to the second feedback signal, and the first feedback signal and the second feedback signal are a group of inverted signals.
[0012] A method for controlling a load switch circuit output short-circuit protection circuit comprises the following steps:
[0013] During normal operation, the pull-up current source circuit pulls up the gate voltage V1 of the load switch NM1, and the load switch NM1 is turned on;
[0014] When the output is short-circuited, the fast_off circuit detects that the output voltage VOUT drops, and its internal timing module circuit starts timing. At the same time, the output signal of the fast_off circuit controls the NGATE_CTR circuit to pull down the gate voltage V1 of the load switch NM1, and finally turns off the load switch NM1 and the current sampling MOS tube NM2;
[0015] When the timing module circuit inside the fast_off circuit ends, the D flip-flop DFF is cleared, the output signal of the fast_off circuit is released, and the pull-up current source circuit slowly pulls up the gate voltage V1 of the load switch NM1 and turns on the load switch NM1 and the current sampling MOS tube NM2;
[0016] If the output is still in a short-circuit state at this time, the sampling current Isense sampled by the current sampling circuit will become larger and larger, which will trigger the current limiting loop circuit to enter the current limiting mode. The output signal of the current limiting loop circuit will pull down the gate voltage V1 of the load switch NM1 through the NGATE_CTR circuit, control the conduction state of the load switch NM1 and the current sampling MOS tube NM2, and finally realize the function of the current limiting loop.
[0017] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a load switch circuit output short-circuit protection circuit and a control method thereof, which can realize comprehensive and rapid current limiting protection; the fast_off circuit and the current limiting loop circuit of the present invention respectively sample the output signal VOUT and the sampled current Isense, and the fast_off circuit directly samples the output signal VOUT to quickly turn off the load switch, so that when the output is a rapid short circuit at the us level, the load switch circuit will only have a current of a few amperes for a short time of at most tens of us, and then after a delayed reset, the current limiting loop circuit realizes current limiting protection, so that the short-circuit current is kept below the current limiting value, and once the output short circuit is released, the circuit can quickly resume normal operation; the present invention solves the problem of instantaneous large current in the prior art by improving the sampling signals of the fast_off circuit and the current limiting loop circuit, and cooperating with the delayed circuit switching, and does not need to use a fast current sampling loop and a high-speed voltage comparator as in the prior art, so only the simplest falling edge sampling circuit and timing module need to be used to form the fast_off circuit, and the circuit occupies a small space and has low static power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 The present invention is a schematic diagram of a load switch circuit output short-circuit protection circuit.
[0019] Figure 2 is a circuit diagram of the fast_off circuit of the present invention.
[0020] Figure 31 is a circuit diagram of a current limiting loop circuit of the present invention.
[0021] Figure 4 The present invention is a flow chart of a method for controlling a load switch circuit output short-circuit protection circuit.
[0022] Figure 5 1 is a waveform diagram of a load switch circuit output short-circuit protection circuit according to an embodiment of the present invention.
[0023] Figure 6 The diagram is a schematic diagram of a load switch circuit output short-circuit protection circuit in the prior art. DETAILED DESCRIPTION
[0024] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.
[0025] like Figure 1 As shown, a load switch circuit output short-circuit protection circuit of the present invention comprises a load switch tube NM1, a current sampling MOS tube NM2, a current sampling circuit, a fast_off circuit, a current limiting loop circuit, a NGATE_CTR circuit and a pull-up current source circuit, the drain of the load switch tube NM1 and the drain of the current sampling MOS tube NM2 are connected to the input signal VIN, the gate of the load switch tube NM1 is connected to the gate of the current sampling MOS tube NM2, the output end of the NGATE_CTR circuit and the output end of the pull-up current source circuit, the source of the load switch tube NM1 is connected to the first input end of the current sampling circuit and the input end of the fast_off circuit and generates an output signal VOUT, the output end of the fast_off circuit is connected to the first input end of the NGATE_CTR circuit, the source of the current sampling MOS tube NM2 is connected to the second input end of the current sampling circuit, the output end of the current sampling circuit is connected to the input end of the current limiting loop circuit, and the output end of the current limiting loop circuit is connected to the second input end of the NGATE_CTR circuit.
[0026] The current sampling circuit includes an operational amplifier A1 and a PMOS tube PM1. The non-inverting input terminal of the operational amplifier A1 serves as the first input terminal of the current sampling circuit. The reverse input terminal of the operational amplifier A1 is connected to the source of the PMOS tube PM1 and serves as the second input terminal of the current sampling circuit. The output terminal of the operational amplifier A1 is connected to the gate of the PMOS tube PM1. The drain of the PMOS tube PM1 serves as the output terminal of the current sampling circuit.
[0027] like Figure 2 As shown, the fast_off circuit includes a falling edge sampling circuit, a D flip-flop DFF and a timing module circuit. The input end of the falling edge sampling circuit serves as the input end of the fast_off circuit and is connected to the output signal VOUT. The output end of the falling edge sampling circuit is connected to the CLK end of the D flip-flop DFF, the Q end of the D flip-flop DFF is connected to the input end of the timing module circuit, the first output end of the timing module is connected to the RESET end of the D flip-flop DFF, and the second output end of the timing module serves as the output end of the fast_off circuit.
[0028] like Figure 2 As shown, the falling edge sampling circuit includes a resistor R1, a capacitor C1, a PMOS tube PM2, an NMOS tube NM3, an NMOS tube NM4 and a bias current source Ibias, one end of the resistor R1 is connected to the gate of the PMOS tube PM2 and serves as the input end of the falling edge sampling circuit, the other end of the resistor R1 is connected to one end of the capacitor C1 and the source of the PMOS tube PM2, the other end of the capacitor C1 is grounded, the drain of the PMOS tube PM2 is connected to the drain of the NMOS tube NM3 and serves as the output end of the falling edge sampling circuit, the gate of the NMOS tube NM3 is connected to the gate of the NMOS tube NM4, the drain of the NMOS tube NM4 and the output end of the bias current source Ibias, the input end of the bias current source Ibias is connected to the power supply VDD, and the source of the NMOS tube NM3 and the source of the NMOS tube NM4 are grounded. When the output signal VOUT is short-circuited, due to the existence of resistor R1 and capacitor C1, the source voltage of PMOS tube PM2 is still equal to the voltage of output signal VOUT when it works normally. The gate voltage of PMOS tube PM2 decreases with the output signal VOUT after the short circuit. When the voltage difference between the source and gate of PMOS tube PM2 is greater than the threshold voltage Vth, PMOS tube PM2 is turned on to pull up the output voltage of the fast_off circuit. The rising edge of the output voltage of the fast_off circuit triggers the Q end of D flip-flop DFF to output a high level, and the timing module circuit starts timing. At the same time, the second output end of the timing module circuit controls the NGATE_CTR circuit to pull down the gate voltage V1 of the load switch NM1, so that the load switch NM1 and the current sampling MOS tube NM2 are turned off. When the timing module circuit ends, the first output end of the timing module circuit triggers the RESET end of the D flip-flop DFF to clear the Q end of the D flip-flop DFF. In addition, the first output end of the timing module circuit will also trigger the RESET end of the D flip-flop DFF to clear the Q end of the D flip-flop DFF every time the circuit is powered on.
[0029] like Figure 3As shown, the current limiting loop circuit includes an operational amplifier A2, a fold back comparator A3, an NMOS tube NM5, an NMOS tube NM6, a voltage dividing resistor R2, a voltage dividing resistor R3 and a voltage dividing resistor R4, the same-direction input terminal of the operational amplifier A2 is connected to the drain of the NMOS tube NM5 and the drain of the NMOS tube NM6 and serves as the input terminal of the current limiting loop circuit, the reverse input terminal of the operational amplifier A2 is connected to one end of the voltage dividing resistor R2 and is connected to the reference current Iref, the output terminal of the operational amplifier A2 serves as the output terminal of the current limiting loop circuit, the source of the NMOS tube NM5 is connected to one end of the voltage dividing resistor R3, the source of the NMOS tube NM6 is connected to one end of the voltage dividing resistor R4, the other end of the voltage dividing resistor R2, the other end of the voltage dividing resistor R3 and the other end of the voltage dividing resistor R4 are grounded, the same-direction input terminal of the foldback comparator A3 is connected to the external bias voltage VREF, the reverse input terminal of the fold back comparator A3 is connected to the output signal VOUT, and the fold back comparator A3 is connected to the output signal VOUT. The output end of the back comparator A3 is connected to the input end of the inverter INV1 and the gate of the NMOS transistor NM5 to generate a first feedback signal ctl1 , and the output end of the inverter INV1 is connected to the gate of the NMOS transistor NM6 to generate a second feedback signal ctl2 .
[0030] The gate of the NMOS tube NM5 is connected to the first feedback signal, and the gate of the NMOS tube NM6 is connected to the second feedback signal. The first feedback signal and the second feedback signal are a set of inverse signals generated by the fold back comparator circuit A3. The first feedback signal and the second feedback signal are used to control the conduction of the NMOS tubes NM5 and NMOS tubes NM6 to achieve normal current limiting and fold back current limiting. The operational amplifier A2 compares the sampling current Isense at the same input end with the reference current Iref at the reverse input end to obtain the output signal of the current limiting loop circuit, and controls the conduction state of the load switch NM1 and the current sampling MOS tube NM2 through the NGATE_CTR circuit to limit the current.
[0031] like Figure 4 As shown, a method for controlling a load switch circuit output short-circuit protection circuit comprises the following steps:
[0032] During normal operation, the pull-up current source circuit pulls up the gate voltage V1 of the load switch NM1, and the load switch NM1 is turned on.
[0033] When the output is short-circuited, the fast_off circuit detects that the output voltage VOUT drops, and its internal timing module circuit starts timing. At the same time, the output signal of the fast_off circuit controls the NGATE_CTR circuit to pull down the gate voltage V1 of the load switch NM1, and finally turns off the load switch NM1 and the current sampling MOS tube NM2.
[0034] When the timing module circuit inside the fast_off circuit ends, the D flip-flop DFF is cleared, the output signal of the fast_off circuit is released, and the pull-up current source circuit slowly pulls up the gate voltage V1 of the load switch NM1. When the gate voltage V1 of the load switch NM1 is greater than the threshold voltage of the load switch NM1 and the current sampling MOS tube NM2, the load switch NM1 and the current sampling MOS tube NM2 are turned on. The pull-up speed of the gate voltage V1 of the load switch NM1 can be controlled by changing the current size of the pull-up current source circuit.
[0035] If the output is still in a short-circuit state at this time, the sampling current Isense sampled by the current sampling circuit will become larger and larger, which will trigger the current limiting loop circuit to enter the current limiting mode. The output signal of the current limiting loop circuit will pull down the gate voltage V1 of the load switch NM1 through the NGATE_CTR circuit, control the conduction state of the load switch NM1 and the current sampling MOS tube NM2, and finally realize the function of the current limiting loop.
[0036] When the output is released from the short-circuit state, the sampling current Isense decreases, the current limiting loop circuit stops controlling the NGATE_CTR circuit, and the pull-up current source circuit pulls up the gate voltage V1 of the load switch NM1, so that the load switch NM1 and the current sampling MOS tube NM2 are in a fully turned-on state.
[0037] like Figure 5 As shown, the present invention provides protection in two stages when the output is short-circuited. In the first stage, the load switch circuit is turned off for a period of time t by a fast off circuit. OFF In the second stage, the load switch circuit is slowly turned on to put the circuit into the current limiting loop protection to ensure that it does not have a large current. The conduction state of NM1 and NM2 is controlled by the fast off and current limiting loop modules to control the magnitude of the current flowing through the load circuit, thereby realizing the function of current limiting protection.
[0038] The present invention provides a load switch circuit output short-circuit protection circuit and a control method thereof, which can realize comprehensive and rapid current limiting protection; the fast_off circuit and the current limiting loop circuit of the present invention respectively sample an output signal VOUT and a sampled current Isense, and the fast_off circuit directly samples the output signal VOUT to quickly turn off the load switch, so that when the output is at the us level and a rapid short circuit occurs, the load switch circuit will only have a current of a few amperes for a short time of at most tens of us, and then after a delayed reset, the current limiting protection is realized by the current limiting loop circuit, so that the short-circuit current is maintained at the current limiting value, and once the output short circuit is released, the circuit can quickly resume normal operation; the present invention solves the problem of instantaneous large current in the prior art by improving the sampling signals of the fast_off circuit and the current limiting loop circuit, and cooperating with the delayed circuit switching, and does not need to use a fast current sampling loop and a high-speed voltage comparator as in the prior art, so only the simplest falling edge sampling circuit and a timing module are needed to form the fast_off circuit, and the circuit occupies a small space and has low static power consumption.
[0039] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.
Claims
1. A load switch circuit output short-circuit protection circuit, characterized in that: It comprises a load switch tube NM1, a current sampling MOS tube NM2, a current sampling circuit, a fast shutdown circuit, a current limiting loop circuit, a NGATE_CTR circuit and a pull-up current source circuit, wherein the drain of the load switch tube NM1 and the drain of the current sampling MOS tube NM2 are connected to an input signal VIN, the gate of the load switch tube NM1 is connected to the gate of the current sampling MOS tube NM2, the output end of the NGATE_CTR circuit and the output end of the pull-up current source circuit, the source of the load switch tube NM1 is connected to the first input end of the current sampling circuit and the input end of the fast shutdown circuit and generates an output signal VOUT, the output end of the fast shutdown circuit is connected to the first input end of the NGATE_CTR circuit, the source of the current sampling MOS tube NM2 is connected to the second input end of the current sampling circuit, the output end of the current sampling circuit is connected to the input end of the current limiting loop circuit, and the output end of the current limiting loop circuit is connected to the second input end of the NGATE_CTR circuit; The fast shutdown circuit comprises a falling edge sampling circuit, a D flip-flop DFF and a timing module circuit, the input end of the falling edge sampling circuit serves as the input end of the fast shutdown circuit and is connected to the output signal VOUT, the output end of the falling edge sampling circuit is connected to the CLK end of the D flip-flop DFF, the Q end of the D flip-flop DFF is connected to the input end of the timing module circuit, the first output end of the timing module is connected to the RESET end of the D flip-flop DFF, and the second output end of the timing module serves as the output end of the fast shutdown circuit; The falling edge sampling circuit comprises a resistor R1, a capacitor C1, a PMOS tube PM2, an NMOS tube NM3, an NMOS tube NM4 and a bias current source Ibias, one end of the resistor R1 is connected to the gate of the PMOS tube PM2 and serves as an input end of the falling edge sampling circuit, the other end of the resistor R1 is connected to one end of the capacitor C1 and the source of the PMOS tube PM2, the other end of the capacitor C1 is grounded, the drain of the PMOS tube PM2 is connected to the drain of the NMOS tube NM3 and serves as an output end of the falling edge sampling circuit, the gate of the NMOS tube NM3 is connected to the gate of the NMOS tube NM4, the drain of the NMOS tube NM4 and the output end of the bias current source Ibias, the input end of the bias current source Ibias is connected to the power supply VDD, and the source of the NMOS tube NM3 and the source of the NMOS tube NM4 are grounded; The current limiting loop circuit comprises an operational amplifier A2, a foldback comparator A3, an NMOS tube NM5, an NMOS tube NM6, a voltage dividing resistor R2, a voltage dividing resistor R3 and a voltage dividing resistor R4. The same-direction input end of the operational amplifier A2 is connected to the drain of the NMOS tube NM5 and the drain of the NMOS tube NM6 and serves as the input end of the current limiting loop circuit. The reverse input end of the operational amplifier A2 is connected to one end of the voltage dividing resistor R2 and is connected to a reference current Iref. The output end of the operational amplifier A2 serves as the output end of the current limiting loop circuit. The source of the NMOS tube NM5 is connected to one end of the voltage dividing resistor R3. , the source of the NMOS tube NM6 is connected to one end of the voltage-dividing resistor R4, the other end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R3 and the other end of the voltage-dividing resistor R4 are grounded, the non-inverting input end of the return comparator A3 is connected to the external bias voltage VREF, the reverse input end of the return comparator A3 is connected to the output signal VOUT, the output end of the return comparator A3 is connected to the input end of the inverter INV1 and the gate of the NMOS tube NM5 and generates a first feedback signal ctl1, and the output end of the inverter INV1 is connected to the gate of the NMOS tube NM6 and generates a second feedback signal ctl2; The NGATE_CTR circuit is used to pull down the gate voltage V1 of the load switch NM1 when the output is short-circuited.
2. The load switch circuit output short circuit protection circuit according to claim 1, characterized in that: The current sampling circuit comprises an operational amplifier A1 and a PMOS tube PM1, wherein the non-inverting input terminal of the operational amplifier A1 serves as the first input terminal of the current sampling circuit, the reverse input terminal of the operational amplifier A1 is connected to the source of the PMOS tube PM1 and serves as the second input terminal of the current sampling circuit, the output terminal of the operational amplifier A1 is connected to the gate of the PMOS tube PM1, and the drain of the PMOS tube PM1 serves as the output terminal of the current sampling circuit.
3. The load switch circuit output short circuit protection circuit according to claim 1, characterized in that: The gate of the NMOS transistor NM5 is connected to the first feedback signal ctl1, and the gate of the NMOS transistor NM6 is connected to the second feedback signal ctl2. The first feedback signal ctl1 and the second feedback signal ctl2 are a group of inverted signals.
4. A method for controlling a load switch circuit output short-circuit protection circuit according to any one of claims 1 to 3, characterized in that The following steps are involved: During normal operation, the pull-up current source circuit pulls up the gate voltage V1 of the load switch NM1, and the load switch NM1 is turned on; When the output is short-circuited, the fast shutdown circuit detects that the output voltage VOUT drops, and its internal timing module circuit starts timing. At the same time, the output signal of the fast shutdown circuit controls the NGATE_CTR circuit to pull down the gate voltage V1 of the load switch NM1, and finally turns off the load switch NM1 and the current sampling MOS tube NM2; When the timing of the internal timing module circuit of the fast shutdown circuit ends, the D flip-flop DFF is cleared, the output signal of the fast shutdown circuit is released, and the pull-up current source circuit slowly pulls up the gate voltage V1 of the load switch NM1 and turns on the load switch NM1 and the current sampling MOS tube NM2; If the output is still in a short-circuit state at this time, the sampling current Isense sampled by the current sampling circuit will become larger and larger, which will trigger the current limiting loop circuit to enter the current limiting mode. The output signal of the current limiting loop circuit will pull down the gate voltage V1 of the load switch NM1 through the NGATE_CTR circuit, control the conduction state of the load switch NM1 and the current sampling MOS tube NM2, and finally realize the function of the current limiting loop.