Test Circuit and Test Method for Components of Converter Valve Group

Abstract

The present application relates to a test circuit and a test method for a component of a converter valve group. The test circuit includes: at least one first current module, at least one second current module, at least one module switch, and a device under test. Among them, the first current module is connected in parallel with the device under test, the second current module is connected in parallel with the device under test through the corresponding module switch. The first current module is used to generate a first current during the process of applying current stress to the device under test, and the second current module is used to generate a second current during the process of applying current stress to the device under test. The first current is less than the second current, and the duration of the first current is greater than the duration of the second current. The above test circuit provides a small current platform and a large current platform for the device under test by controlling the module switch, which can not only enable the device under test to achieve a stress experiment equivalent to or accelerated from the application working condition, but also obtain accurate junction temperature fluctuation data of the device under test in the equivalent experiment of the application working condition.

Description

Technical Field

[0001] The present application relates to the technical field of power electronics, and particularly to a test circuit and a test method for components of a converter valve group. Background Art

[0002] The equivalent application condition experiment is an important means to verify the functional integrity and long-term reliability of the components of the converter valve group during actual operation. During the experiment, it is usually necessary to measure the junction temperature of the power semiconductor device to measure its package thermal impedance, monitor the operating state, and evaluate the reliability of the long-term use of the components of the converter valve group.

[0003] The existing equivalent application condition experiment usually adopts a test circuit composed of a current source subsystem and a voltage source subsystem to apply current stress and voltage stress at both ends of the components of the converter valve group. However, it is difficult for the above test circuit of the equivalent application condition experiment to accurately measure the junction temperature of the power semiconductor device. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a test circuit and a test method for components of a converter valve group that can accurately measure the junction temperature of the components of the converter valve group.

[0005] In a first aspect, the present application provides a test circuit for components of a converter valve group, and the test circuit includes: at least one first current module, at least one second current module, at least one module switch, and a device under test; the first current module is connected in parallel with the device under test, and the second current module is connected in parallel with the device under test through the corresponding module switch;

[0006] The first current module is configured to generate a first current during the process of applying current stress to the device under test;

[0007] The second current module is configured to generate a second current during the process of applying current stress to the device under test; the first current is less than the second current.

[0008] In one embodiment, the first current module includes: a first charging sub-module and a first discharging sub-module; the first charging sub-module is connected in parallel with the first discharging sub-module; the first discharging sub-module is connected in parallel with the device under test;

[0009] The first charging sub-module is configured to supply power to the first discharging sub-module;

[0010] The first discharging sub-module is configured to generate a first current during the process of applying current stress to the device under test.

[0011] In one embodiment, the first electron - discharging module includes: a first capacitor, a first free - wheeling switch, and a first inductor; the first capacitor is connected in parallel with the first electron - charging module, the first free - wheeling switch is connected in parallel with the first capacitor, one end of the first inductor is connected to the first common end of the first capacitor and the first free - wheeling switch, the other end of the first inductor is connected to the first end of the device under test, and the second end of the device under test is connected to the second common end of the first capacitor and the first sub - switch.

[0012] In one embodiment, the first electron - charging module includes: a first power supply, a first charging switch, a first steering switch, and a second inductor;

[0013] Wherein, one end of the first power supply is connected to one end of the first charging switch, the other end of the first charging switch is respectively connected to one end of the first steering switch and one end of the second inductor, and the other end of the second inductor is connected to the common end of the first capacitor, the first free - wheeling switch, and the first inductor;

[0014] The other end of the first power supply is connected to the common end of the first steering switch, the first capacitor, and the first free - wheeling switch.

[0015] In one embodiment, the second current module includes: a second electron - charging module and a second electron - discharging module; the second electron - charging module is connected in parallel with the second electron - discharging module; the second electron - discharging module is connected in parallel with the device under test through a corresponding module switch;

[0016] The second electron - charging module is used to supply power to the second electron - discharging module;

[0017] The second electron - discharging module is used to generate a second current during the process of applying current stress to the device under test.

[0018] In one embodiment, the second electron - discharging module includes: a second capacitor, a second free - wheeling switch, a third free - wheeling switch, and a third inductor;

[0019] The second capacitor is connected in parallel with the second electron - charging module, the second free - wheeling switch is connected in parallel with the second capacitor, one end of the third inductor is connected to the first common end of the second capacitor and the second free - wheeling switch, the other end of the third inductor is respectively connected to the first end of the third free - wheeling switch and one end of the module switch, the second end of the third free - wheeling switch is connected to the common end of the second free - wheeling switch, the second capacitor, and the second electron - charging module, and the other end of the module switch is connected in parallel with the device under test.

[0020] In one embodiment, the second electron - charging module includes: a second power supply, a second charging switch, a second steering switch, and a fourth inductor;

[0021] One end of the second power supply is connected to one end of the second charging switch. The other end of the second charging switch is respectively connected to one end of the second steering switch and one end of the fourth inductor. The other end of the fourth inductor is connected to the common end of the second capacitor, the second freewheeling switch, and the third inductor.

[0022] The other end of the second power supply is connected to the common end of the second steering switch, the second capacitor, the second freewheeling switch, and the third freewheeling switch.

[0023] In one embodiment, the test circuit includes a plurality of first current modules. The plurality of first current modules are connected in series and share a power supply.

[0024] In one embodiment, the test circuit includes a plurality of second current modules. The plurality of second current modules are connected in parallel and share a power supply.

[0025] In one embodiment, the plurality of second current modules share the third freewheeling switch.

[0026] In a second aspect, the present application further provides a method for testing a converter valve group component. The testing method is applied to a test system. The test system includes a controller and a test circuit according to any one of the above embodiments. The method includes:

[0027] Controlling the first current module to generate a first current to apply current stress to the device under test;

[0028] Controlling the second current module to generate a second current to apply current stress to the device under test by closing the module switch.

[0029] In one embodiment, controlling the first current module to generate a first current to apply current stress to the device under test includes:

[0030] Controlling the first charging sub-module to charge the first discharging sub-module, and after determining that the first discharging sub-module is fully charged, controlling the first discharging sub-module to generate a first current to apply current stress to the device under test.

[0031] In one embodiment, controlling the first charging sub-module to charge the first discharging sub-module includes:

[0032] Closing the first charging switch in the first charging sub-module to control the first power supply in the first charging sub-module to charge the first discharging sub-module.

[0033] In one embodiment, after determining that the first discharging sub-module is fully charged, controlling the first discharging sub-module to generate a first current includes:

[0034] When it is determined that the first electron emission module is fully charged, close the device under test to control the first electron emission module to generate a first current;

[0035] When it is determined that the first current output by the first electron emission module reaches the peak current, close the first freewheeling switch in the first electron emission module to control the first electron emission module to maintain the output of the peak current.

[0036] In one embodiment, controlling the second current module to generate a second current by closing the module switch to apply a current stress to the device under test includes:

[0037] Controlling the second charging electron module to charge the second electron emission module, and after determining that the second electron emission module is fully charged, controlling the second electron emission module to generate a second current and closing the module switch to apply a current stress to the device under test.

[0038] In one embodiment, controlling the second charging electron module to charge the second electron emission module includes:

[0039] Closing the second charging switch in the second charging electron module to control the second power supply in the second charging electron module to charge the second electron emission module.

[0040] In one embodiment, after determining that the second electron emission module is fully charged, controlling the second electron emission module to generate a second current includes:

[0041] When it is determined that the second electron emission module is fully charged, close the module switch to control the second electron emission module to generate a second current;

[0042] When it is determined that the second current output by the second electron emission module reaches the peak current, close the second freewheeling switch in the second electron emission module to control the second electron emission module to maintain the output of the peak current.

[0043] In one embodiment, the method further includes:

[0044] Closing the third freewheeling switch and disconnecting the module switch.

[0045] In one embodiment, the method further includes:

[0046] Disconnecting the second freewheeling switch in the second electron emission module;

[0047] When it is determined that the voltage across the second capacitor in the second electron emission module reaches the negative maximum voltage value, close the second steering switch in the second charging electron module;

[0048] When it is determined that the voltage across the second capacitor changes from a negative voltage to a positive voltage, close the second charging switch.

[0049] In one embodiment, the method further includes:

[0050] Disconnect the module switch, and control the first current module to generate a voltage on the device under test to apply a voltage stress on the device under test.

[0051] In one embodiment, controlling the first current module to generate a voltage on the device under test includes:

[0052] Disconnect the first freewheeling switch in the first electron emission module;

[0053] When it is determined that the voltage across the device under test reaches the negative maximum voltage value, close the first steering switch in the first electron charging module;

[0054] When it is determined that the voltage across the device under test changes from a negative voltage to a positive voltage, close the first charging switch.

[0055] In one embodiment, the duration of the first current is greater than the duration of the second current.

[0056] In a third aspect, the present application further provides a testing device, which includes:

[0057] A first control module, configured to control the first current module to generate a first current to apply a current stress on the device under test.

[0058] A second control module, configured to control the second current module to generate a second current by closing the module switch to apply a current stress on the device under test.

[0059] In a fourth aspect, the present application further provides a computer device, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0060] Control the first current module to generate a first current to apply a current stress on the device under test;

[0061] Control the second current module to generate a second current by closing the module switch to apply a current stress on the device under test.

[0062] In a fifth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0063] Control the first current module to generate a first current to apply a current stress on the device under test;

[0064] Control the second current module to generate a second current by closing the module switch to apply a current stress on the device under test.

[0065] In a sixth aspect, the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the following steps are implemented:

[0066] Control the first current module to generate a first current to apply current stress to the device under test;

[0067] Control the second current module to generate a second current to apply current stress to the device under test by closing the module switch.

[0068] The above test circuit and test method for the converter valve group components. The test circuit includes: at least one first current module, at least one second current module, at least one module switch, and the device under test; the first current module is connected in parallel with the device under test, and the second current module is connected in parallel with the device under test through the corresponding module switch; the first current module is used to generate a first current during the process of applying current stress to the device under test; the second current module is used to generate a second current during the process of applying current stress to the device under test; the first current is less than the second current. Since in the existing method of measuring the junction temperature of the device under test using the temperature-sensitive parameter measurement method, the sensitivity of the temperature-sensitive electrical parameter to the junction temperature of the device under test decreases with the increase of the conduction current, so measuring the junction temperature in the small conduction current amplitude platform stage can improve the accuracy and anti-interference ability. The above test circuit provides a small current platform and a large current platform for the device under test by controlling the module switch. In the large current platform, the device under test can achieve a stress experiment equivalent to or accelerated from the application working condition. In the small current platform, accurate junction temperature fluctuation data of the device under test in the equivalent experiment of the application working condition can be obtained, which is beneficial to improving the accuracy of the analysis of the device life degradation process. Description of the Drawings

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0070] Figure 1 The test circuit of the converter valve group components in an embodiment;

[0071] Figure 2 For Figure 1 The structures of the first current module and the second current module in

[0072] Figure 3 The test circuit of the converter valve group components in a specific embodiment;

[0073] Figure 4 The test circuit for the converter valve group components of another specific embodiment;

[0074] Figure 5 The test circuit for the converter valve group components of another specific embodiment;

[0075] Figure 6 The test circuit for the converter valve group components of another specific embodiment;

[0076] Figure 7 The test circuit for the converter valve group components of another specific embodiment;

[0077] Figure 8 The test circuit for the converter valve group components of another specific embodiment;

[0078] Figure 9 The test circuit for the converter valve group components of another specific embodiment;

[0079] Figure 10 The test circuit for the converter valve group components of another specific embodiment;

[0080] Figure 11 The test method for the converter valve group components of an embodiment;

[0081] Figure 12 The test method for the converter valve group components of another embodiment;

[0082] Figure 13 The test method for the converter valve group components of another embodiment;

[0083] Figure 14 The stress waveform of the device under test in a specific embodiment;

[0084] Figure 15 The internal structure diagram of the computer device.

[0085] Description of the reference numerals:

[0086] The first current module 10; the second current module 20; the module switch 30;

[0087] The device under test 40; the first charging sub-module 101; the first power supply 1011;

[0088] The first charging switch 1012; the first steering switch 1013; the second inductor 1014;

[0089] The third capacitor 1015; the first discharging sub-module 102; the first capacitor 1021;

[0090] The first freewheeling switch 1022; the first inductor 1023; the second charging sub-module 201;

[0091] The second power supply 2011; the second charging switch 2012; the second steering switch 2013;

[0092] The fourth inductor 2014; the fourth capacitor 2015; the second discharging sub-module 202;

[0093] The second capacitor 2021; the second freewheeling switch 2022; the third freewheeling switch 2023;

[0094] The third inductor 2024. Detailed implementation manners

[0095] For ease of understanding the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is more thorough and comprehensive.

[0096] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0097] It can be understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. For example, without departing from the scope of this application, the first resistor can be called the second resistor, and similarly, the second resistor can be called the first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0098] It can be understood that "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is an electrical signal or data transfer between the connected circuits, modules, units, etc.

[0099] It can be understood that "at least one" means one or more, and "a plurality" means two or more. "At least part of an element" means part or all of the element.

[0100] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / including" etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0101] First, before specifically introducing the technical solutions of the embodiments of the present disclosure, the technical background or the technical evolution context based on which the embodiments of the present disclosure are described will be introduced first. The equivalent application condition experiment is an important means to verify the functional integrity and long-term reliability of power semiconductor devices during actual operation. During the experiment, it is usually necessary to measure the junction temperature of the power semiconductor device to measure the package thermal impedance, monitor the operating state, and evaluate the reliability of the device during long-term use. The existing equivalent application condition experiment usually adopts a test circuit composed of a current source subsystem and a voltage source subsystem to apply current stress and voltage stress across the device under test. However, it is difficult for the above-mentioned test circuit of the equivalent application condition experiment to accurately measure the junction temperature of the device under test. The present application provides a test circuit and a test method to solve the above technical problems. The following embodiments will specifically illustrate the test circuit and the test method described in the present application.

[0102] In one embodiment, as Figure 1 shown, a test circuit for a converter valve group component is provided. The test circuit includes at least one first current module 10, at least one second current module 20, at least one module switch 30, and a device under test 40; the first current module 10 is connected in parallel with the device under test 40, and the second current module 20 is connected in parallel with the device under test 40 through the corresponding module switch 30.

[0103] Wherein, the first current module 10 is configured to generate a first current during the process of applying current stress to the device under test 40; the second current module 20 is configured to generate a second current during the process of applying current stress to the device under test 40; the first current is less than the second current. The duration of the first current is greater than the duration of the second current.

[0104] The above-mentioned device under test 40 is a component of a converter valve group. Specifically, the device under test 40 can be any one of semiconductor power devices, power units, valve segments, valve assemblies, and single valves. A power unit is a collection of a semiconductor power device and its peripheral circuits, and the peripheral circuits include at least one of an absorption circuit, a clamping circuit, a voltage equalizing circuit, and an energy extraction circuit; a valve segment is formed by combining power units, and the combination methods include at least one of series connection and parallel connection; a valve assembly is formed by combining valve segments, and the combination methods include at least one of series connection and parallel connection; a single valve is a bridge arm of a converter valve and is formed by combining valve assemblies, and the combination methods include at least one of series connection and parallel connection.

[0105] The above-mentioned first current module 10 is a current module capable of providing a small current stress, which can generate a small current platform with a relatively small conduction current amplitude on the device under test 40, that is, a small current measurement platform for extracting the junction temperature of temperature-sensitive electrical parameters, providing a measurement window for accurate on-line monitoring of the junction temperature of the device under test 40. The above-mentioned second current module 20 is a current module capable of providing a large current stress. By applying a relatively large load current stress to the device under test 40, conduction loss and junction temperature fluctuations can be generated on the power semiconductor device, equivalently or accelerating the device life degradation process, thereby realizing the equivalent experiment of the application conditions of the device under test 40 and realizing the junction temperature measurement of the device under test 40.

[0106] When the above-mentioned module switch 30 is disconnected, the device under test 40 is only provided with an applied current stress or voltage stress by the first current module 10. When the module switch 30 is closed, the device under test 40 is provided with an applied current stress by the first current module 10 and the second current module 20 simultaneously. The above-mentioned module switch 30 can be a semi-controlled power device or a reverse-blocking fully-controlled power device. A semi-controlled power device refers to a power semiconductor device and combination that can only be controlled to turn on but not turn off through the gate, including but not limited to thyristors. A reverse-blocking fully-controlled power device refers to a power semiconductor device and combination with bidirectional voltage blocking ability that can be controlled to turn on and off through the gate, including but not limited to gate turn-off thyristors, integrated gate-commutated thyristors, reverse-blocking IGBTs, power semiconductor devices that can be controlled to turn on and off through the gate and can only block single-directional voltage with a series diode, MOSFETs or IGBTs in series connection of common source / emitter, MOSFETs or IGBTs in series connection of common drain / collector, IGBTs with anti-parallel diodes in series connection of common collector, and IGBTs with anti-parallel diodes in series connection of common emitter.

[0107] The connection method of the above-mentioned second current module 20 being connected in parallel with the device under test 40 through the corresponding module switch 30 can adopt Figure 1 the connection method shown (low potential floating), optionally, it can also adopt Figure 2 the connection method shown (low potential grounded).

[0108] The test circuit for the converter valve group components provided by the embodiments of the present application. When measuring the junction temperature of the device under test using the temperature-sensitive parameter temperature measurement method, the sensitivity of the temperature-sensitive electrical parameter to the junction temperature of the device under test decreases as the conduction current increases. Therefore, measuring the junction temperature at the small-current platform stage with a small conduction current amplitude can improve the accuracy and anti-interference ability. The above test circuit provides a small-current platform and a large-current platform for the device under test through the control module switch. In the large-current platform, the device under test can be made to perform a stress experiment equivalent to or accelerated from the application working condition. In the small-current platform, accurate junction temperature fluctuation data of the device under test in the equivalent experiment of the application working condition can be obtained, which is beneficial to improving the accuracy of the analysis of the device life degradation process.

[0109] In one embodiment, as Figure 2 shown, the above first current module 10 includes: a first charging sub-module 101 and a first discharging sub-module 102; the first charging sub-module 101 is connected in parallel with the first discharging sub-module 102; the first discharging sub-module 102 is connected in parallel with the device under test 40. Among them, the first charging sub-module 101 is used to supply power to the first discharging sub-module 102; the first discharging sub-module 102 is used to generate a first current during the process of applying current stress to the device under test 40.

[0110] The above first charging sub-module 101 includes: a first power supply 1011, a first charging switch 1012, a first steering switch 1013, and a second inductor 1014; one end of the first power supply 1011 is connected to one end of the first charging switch 1012, the other end of the first charging switch 1012 is respectively connected to one end of the first steering switch 1013 and one end of the second inductor 1014, the other end of the second inductor 1014 is connected to the common end of the first capacitor 1021, the first freewheeling switch 1022, and the first inductor 1023; the other end of the first power supply 1011 is connected to the common end of the first steering switch 1013, the first capacitor 1021, and the first freewheeling switch 1022.

[0111] The above first charging sub-module 101 further includes: a third capacitor 1015, and the second capacitor 2021 is connected in parallel with the first power supply 1011 and is used to provide a stable input DC voltage for the test circuit.

[0112] The above first discharging sub-module 102 includes: a first capacitor 1021, a first freewheeling switch 1022, and a first inductor 1023; the first capacitor 1021 is connected in parallel with the first charging sub-module 101, the first freewheeling switch 1022 is connected in parallel with the first capacitor 1021, one end of the first inductor 1023 is connected to the first common end of the first capacitor 1021 and the first freewheeling switch 1022, the other end of the first inductor 1023 is connected to the first end of the device under test 40, and the second end of the device under test is connected to the second common end of the first capacitor 1021 and the first sub-switch.

[0113] In one embodiment, as Figure 2 shown, the second current module 20 includes: a second charging sub-module 201 and a second discharging sub-module 202; the second charging sub-module 201 is connected in parallel with the second discharging sub-module 202; the second discharging sub-module 202 is connected in parallel with the device under test 40 through a corresponding module switch 30; wherein, the second charging sub-module 201 is used to supply power to the second discharging sub-module 202; the second discharging sub-module 202 is used to generate a second current during the process of applying a current stress to the device under test 40.

[0114] The above-mentioned second charging sub-module 201 includes: a second power supply 2011, a second charging switch 2012, a second steering switch 2013, and a fourth inductor 2014;

[0115] wherein, one end of the second power supply 2011 is connected to one end of the second charging switch 2012, the other end of the second charging switch 2012 is respectively connected to one end of the second steering switch 2013 and one end of the fourth inductor 2014, the other end of the fourth inductor 2014 is connected to the common end of a second capacitor 2021, a second freewheeling switch 2022, and a third inductor 2024; the other end of the second power supply 2011 is connected to the common end of the second steering switch 2013, the second capacitor 2021, the second freewheeling switch 2022, and a third freewheeling switch 2023.

[0116] The above-mentioned second charging sub-module 201 further includes: a fourth capacitor 2015, the fourth capacitor 2015 is connected in parallel with the second power supply 2011, and is used to provide a stable input DC voltage for the test circuit.

[0117] The above-mentioned second discharging sub-module 202 includes: a second capacitor 2021, a second freewheeling switch 2022, a third freewheeling switch 2023, and a third inductor 2024; the second capacitor 2021 is connected in parallel with the second charging sub-module 201, the second freewheeling switch 2022 is connected in parallel with the second capacitor 2021, one end of the third inductor 2024 is connected to the first common end of the second capacitor 2021 and the second freewheeling switch 2022, the other end of the third inductor 2024 is respectively connected to the first end of the third freewheeling switch 2023 and one end of the module switch 30, the second end of the third freewheeling switch 2023 is connected to the common end of the second freewheeling switch 2022, the second capacitor 2021, and the second charging sub-module 201, and the other end of the module switch 30 is connected in parallel with the device under test 40.

[0118] The above-mentioned first charging switch 1012, first steering switch 1013, first freewheeling switch 1022, second charging switch 2012, second steering switch 2013, second freewheeling switch 2022, and third freewheeling switch 2023 can be semi-controlled power devices or reverse-block fully-controlled power devices. The third freewheeling switch 2023 and the module switch 30 are auxiliary control switches for increasing the control freedom.

[0119] The above-mentioned first capacitor 1021, second capacitor 2021, third capacitor 1015, and fourth capacitor 2015 can be single capacitors or can be composed of multiple groups of capacitors connected in series and parallel; optionally, they can be fixed inductors, adjustable inductors, or can be composed of multiple groups of inductors connected in series and parallel.

[0120] In one embodiment, the above-mentioned test circuit includes a plurality of first current modules 10, the plurality of first current modules 10 are connected in series, and the plurality of first current modules 10 share a power supply.

[0121] Optionally, the above-mentioned test circuit includes a plurality of second current modules 20, the plurality of second current modules 20 are connected in parallel, and the plurality of second current modules 20 share a power supply. Optionally, the plurality of second current modules 20 share the third freewheeling switch 2023. Optionally, the plurality of second current modules 20 share the module switch 30.

[0122] Optionally, the above-mentioned test circuit includes a plurality of first current modules 10 and a plurality of second current modules 20, the plurality of first current modules 10 are connected in series, and the plurality of first current modules 10 share a power supply, the plurality of second current modules 20 are connected in parallel, and the plurality of second current modules 20 share a power supply. Optionally, the plurality of second current modules 20 share the third freewheeling switch 2023. Optionally, it can be directly powered by the DC voltage sources u DCH and u DCL for the test circuit. Optionally, when the power supply voltages of the first current module 10 and the second current module 20 are the same, u DCH and u DCL can share the same DC voltage source.

[0123] For the test circuit of the converter valve group components described in all the above embodiments, as Figure 3 shown, the present application also provides a test circuit for converter valve group components, and this test circuit includes:

[0124] A first current module 10 (corresponding to the small current module in the figure), a second current module 20 (corresponding to the large current module in the figure), a module switch 30 (corresponding to V 10H ) and a device under test 40;

[0125] The above-mentioned first current module 10 includes a first power supply 1011 (corresponding to u DCL), the third capacitor 1015 (corresponding to C in the figure 4L ), the first charging switch 1012 (corresponding to V in the figure 8L ), the first steering switch 1013 (corresponding to V in the figure 7L ), and the second inductor 1014 (corresponding to L in the figure 5L ), the first capacitor 1021 (corresponding to C in the figure 3L ), the first freewheeling switch 1022 (corresponding to V in the figure 6L ), and the first inductor 1023 (corresponding to L in the figure 4L ).

[0126] Among them, the module switch 30 (corresponding to V in the figure 10H ), and the first freewheeling switch 1022 (corresponding to V in the figure 6L ) can adopt reverse-blocking fully controlled power devices. The first charging switch 1012 (corresponding to V in the figure 8L ), and the first steering switch 1013 (corresponding to V in the figure 7L ) adopt semi-controlled power devices. The first power supply 1011 (corresponding to u in the figure DCL ) is a non-ideal DC voltage source.

[0127] Among them, the third capacitor 1015 (corresponding to C in the figure 4L ) is connected in parallel with the first power supply 1011 (corresponding to u in the figure DCL ) to provide a stable input DC voltage for the circuit. The anode of the first charging switch 1012 (corresponding to V in the figure 8L ) is connected to the positive pole of the first power supply 1011 (corresponding to u in the figure DCL ), the cathode of the first charging switch 1012 (corresponding to V in the figure 8L ) is connected to the cathode of the first steering switch 1013 (corresponding to V in the figure 7L ); the anode of the first steering switch 1013 (corresponding to V in the figure 7L ) is connected to the negative pole of the first power supply 1011 (corresponding to u in the figure DCL ); one end of the second inductor 1014 (corresponding to L in the figure 5L ) is connected to the cathode of the first steering switch 1013 (corresponding to V in the figure 7L ), the other end of the second inductor 1014 (corresponding to L in the figure 5L ) is connected to one end of the first capacitor 1021 (corresponding to C in the figure 3L ) and the cathode of the first freewheeling switch 1022 (corresponding to V in the figure 6L ), the other end of the first capacitor 1021 (corresponding to C in the figure 3L ) and the cathode of the first freewheeling switch 1022 (corresponding to V in the figure 6LThe anode of ) is coupled to the first power supply 1011 (corresponding to u in the figure DCL ), and the negative electrode of ) is coupled; the first inductor 1023 (corresponding to L in the figure 4L ), one end of which is coupled to the cathode of the first freewheeling switch 1022 (corresponding to V in the figure 6L ), and the other end of the first inductor 1023 (corresponding to L in the figure 4L ) is coupled to the current injection port of the device under test 40.

[0128] The above-mentioned second current module 20 includes a second power supply 2011 (corresponding to u in the figure DCH ), a fourth capacitor 2015 (corresponding to C in the figure 4H ), a second charging switch 2012 (corresponding to V in the figure 8H ), a second steering switch 2013 (corresponding to V in the figure 7H ), a fourth inductor 2014 (corresponding to L in the figure 5H ), a second capacitor 2021 (corresponding to C in the figure 3H ), a second freewheeling switch 2022 (corresponding to V in the figure 6H ), a third freewheeling switch 2023 (corresponding to V in the figure 9H ) and a third inductor 2024 (corresponding to L in the figure 4H ).

[0129] Among them, the second freewheeling switch 2022 (corresponding to V in the figure 6H ) can adopt a reverse-blocking fully controlled power device. The second charging switch 2012 (corresponding to V in the figure 8H ), the second steering switch 2013 (corresponding to V in the figure 7H ) and the third freewheeling switch 2023 (corresponding to V in the figure 9H ) adopt semi-controlled power devices. The second power supply 2011 (corresponding to u in the figure DCH ) is a non-ideal DC voltage source.

[0130] Among them, the fourth capacitor 2015 (corresponding to C in the figure 4H ) is coupled in parallel with the second power supply 2011 (corresponding to u in the figure DCH ) to provide a stable input DC voltage for the circuit; the anode of the second charging switch 2012 (corresponding to V in the figure 8H ) is coupled to the positive electrode of the second power supply 2011 (corresponding to u in the figure DCH ), and the cathode is coupled to the cathode of the second steering switch 2013 (corresponding to V in the figure 7H ); the anode of the second steering switch 2013 (corresponding to V in the figure 7H ) is coupled to the negative electrode of the second power supply 2011 (corresponding to u in the figure DCH ); the fourth inductor 2014 (corresponding to L in the figure5H ) One end of is coupled to the cathode of the second steering switch 2013 (V in the corresponding figure) 7H ), and the fourth inductor 2014 (L in the corresponding figure) 5H ) The other end of is coupled to one end of the second capacitor 2021 (C in the corresponding figure) 3H ) and the cathode of the second freewheeling switch 2022 (V in the corresponding figure) 6H ), and the other end of the second capacitor 2021 (C in the corresponding figure) 3H ) and the cathode of the second freewheeling switch 2022 (V in the corresponding figure) 6H ) The anode of is coupled to the negative pole of the second power supply 2011 (u in the corresponding figure) DCH ); One end of the third inductor 2024 (L in the corresponding figure) 4H ) is coupled to the cathode of the second freewheeling switch 2022 (V in the corresponding figure) 6H ), and the other end of the third inductor 2024 (L in the corresponding figure) 4H ) is coupled to the anode of the third freewheeling switch 2023 (V in the corresponding figure) 9H ) and the anode of the module switch 30 (V in the corresponding figure) 10H ); The cathode of the third freewheeling switch 2023 (V in the corresponding figure) 9H ) is coupled to the anode of the second freewheeling switch 2022 (V in the corresponding figure) 6H ); The cathode of the module switch 30 (V in the corresponding figure) 10H ) is coupled to the current injection port of the device under test; The reference ground potential of the high-current module is the negative pole of the second power supply 2011 (u in the corresponding figure) DCH ). The output impedance of the second power supply 2011 (u in the corresponding figure) DCH ) can be parasitic parameters or can be additionally connected in series.

[0131] Among them, the reference ground potential of the first current module 10 (the small-current module in the corresponding figure) is the negative pole of the first power supply 1011 (u in the corresponding figure) DCL ). The reference ground potential of the second current module 20 (the high-current module in the corresponding figure) and the first current module 10 (the small-current module in the corresponding figure) is the same, and is coupled to the current outflow port of the device under test 40. The second power supply 2011 (u in the corresponding figure) DCH ) and the first power supply 1011 (u in the corresponding figure) DCL ) can be implemented by, but not limited to, independent power supply devices.

[0132] In one embodiment, as Figure 4 shown, in Figure 3Based on the embodiments, the above test circuit includes one first current module 10 and two second current modules 20. The two second current modules 20 are connected in parallel, and the two second current modules 20 share a power supply.

[0133] The embodiments of the present application provide a test circuit for directly paralleling high-current modules to increase the test current. By directly paralleling the same high-current modules, the purpose of increasing the test current is achieved. The number of parallel stages is 2, and there is potential to further increase the number of parallel stages. Each high-current module shares a second power supply 2011 (corresponding to u in the figure) DCH to reduce costs.

[0134] In one embodiment, as Figure 5 shown, based on the Figure 3 embodiments, the above test circuit includes one first current module 10 and two second current modules 20. The two second current modules 20 are connected in parallel, and the two second current modules 20 share a power supply and a third freewheeling switch 2023 (corresponding to V in the figure) 9H and a module switch 30 (corresponding to V in the figure) 10H .

[0135] The embodiments of the present application provide a test circuit for indirectly paralleling high-current modules to increase the test current. By indirectly paralleling the same high-current modules, the purpose of increasing the test current is achieved. The number of parallel stages is 2, and there is potential to further increase the number of parallel stages.

[0136] In one embodiment, as Figure 6 shown, based on the Figure 5 embodiments, the above test circuit includes one first current module 10 and four second current modules 20. The four second current modules 20 are connected in parallel, the four second current modules 20 share a power supply, and two of the four second current modules 20 share a third freewheeling switch 2023 (corresponding to V in the figure) 9H and a module switch 30 (corresponding to V in the figure) 10H .

[0137] The embodiments of the present application provide a test circuit for hybrid paralleling high-current modules to increase the test current: By indirectly paralleling the same high-current modules, the purpose of increasing the test current is achieved. The number of parallel stages is 4, and there is potential to further increase the number of parallel stages. Each high-current module shares a DC voltage source u DCH , some high-current modules share grouped semi-controlled power devices V 9H and reverse-blocking fully-controlled devices V 10H to reduce costs.

[0138] In one embodiment, as Figure 7 shown, based on the Figure 3Based on the embodiments, the above test circuit includes two first current modules 10 and one second current module 20. The two first current modules 10 are connected in series, and the two first current modules 10 share a power supply.

[0139] The embodiments of the present application provide a test circuit for expanding the test voltage by connecting small current modules in series: the purpose of expanding the test voltage is achieved by connecting the same small current modules in series, the series connection level is 2, and there is the potential to continue increasing the series connection level. The voltage-doubling rectifier power supply generates the DC input voltage for the two-stage series-connected small current modules, and it can also be realized by a series-connected DC voltage source.

[0140] In one embodiment, as Figure 8 shown, on the basis of Figure 4 and Figure 7 embodiments, the above test circuit includes two first current modules 10 and two second current modules 20. The two first current modules 10 are connected in series, the two second current modules 20 are connected in parallel, the two first current modules 10 share a power supply, and the two second current modules 20 share a power supply.

[0141] The embodiments of the present application provide a test circuit for directly paralleling large current modules to expand the test current and connecting small current modules in series to expand the test voltage: the purpose of expanding the test current is achieved by directly paralleling the same large current modules, and the purpose of expanding the test voltage is achieved by connecting the same small current modules in series. The parallel connection level and the series connection level are both 2, and there is the potential to continue increasing the parallel connection level and the series connection level.

[0142] In one embodiment, as Figure 9 shown, on the basis of Figure 5 and Figure 7 embodiments, the above test circuit includes two first current modules 10 and two second current modules 20. The two first current modules 10 are connected in series, the two second current modules 20 are connected in parallel, the two first current modules 10 share a power supply, the two second current modules 20 share a power supply, share a third freewheeling switch 2023 (corresponding to V in the figure 9H ), and share a module switch 30 (corresponding to V in the figure 10H ).

[0143] The embodiments of the present application provide a test circuit for indirectly paralleling large current modules to expand the test current and connecting small current modules in series to expand the test voltage: the purpose of expanding the test current is achieved by indirectly paralleling the same large current modules, and the purpose of expanding the test voltage is achieved by connecting the same small current modules in series. The parallel connection level and the series connection level are both 2, and there is the potential to continue increasing the parallel connection level and the series connection level.

[0144] In one embodiment, as Figure 10 shown, on the basis of Figure 6Based on the embodiments, the above test circuit includes two first current modules 10 and four second current modules 20. The two first current modules 10 are connected in series, and the four second current modules 20 are connected in parallel. The two first current modules 10 share a power supply, and the four second current modules 20 share a power supply. Moreover, two of the four second current modules 20 share a third freewheeling switch 2023 (corresponding to V in the figure) 9H ), and a module switch 30 (corresponding to V in the figure) 10H ).

[0145] The embodiments of the present application provide a test circuit for a large current module to mix and parallelly expand the test current and a small current module to series-expand the test voltage: By indirectly paralleling the same large current modules, the purpose of expanding the test current is achieved, and by series-connecting the same small current modules, the purpose of expanding the test voltage is achieved. The parallel connection level is 4 and the series connection level is 2, and the parallel connection level and the series connection level have the potential to continue to increase.

[0146] The test circuit described in the embodiments of the present application has the following beneficial effects: (1) The test circuit provided by the present application can generate a small current platform that cooperates with the on-line monitoring of the junction temperature on the power semiconductor device of the device under test, and can obtain accurate junction temperature fluctuation data during the experiment, which is beneficial to improving the accuracy of the analysis of the device life degradation process; (2) The test circuit topology provided by the present application is simple, the number of components is less than that of the existing equivalent application condition experiment circuit, and the construction cost of the experimental platform is low; (3) The test circuit provided by the present application only needs to sequentially execute the trigger signals of each power semiconductor device, avoiding the mutual cooperation of the current source and the voltage source, the control logic is simple, and the power semiconductor components of the circuit are all mature thyristor-like devices, and the overall operation reliability is high; (4) In the test circuit provided by the present application, the power supply only needs to supplement the capacitor voltage drop caused by the loss, eliminating a large amount of reactive power caused by the drag inductance in the current source, and also avoiding a large amount of active power caused by directly charging the negative voltage capacitor, and the operation cost is low, which is beneficial to carrying out long-term equivalent reliability verification experiments; (5) The test circuit provided by the present application has a high degree of modularity, can configure the number of modules according to experimental needs, and can also increase the number of modules according to the development requirements of the converter valve assembly, with high construction flexibility and effectively reducing duplicate investment.

[0147] Regarding the test circuit of the converter valve group components described in all the above embodiments, as Figure 11 shown, the present application also provides a test method for converter valve group components. This test method is applied to a test system. The test system includes a controller and a test circuit as described in any one of the above embodiments. This test method includes:

[0148] S101, controlling the first current module to generate a first current to apply current stress to the device under test.

[0149] In the embodiment of the present application, the controller can control the first charge sub-module to charge the first discharge sub-module, and after determining that the first discharge sub-module is fully charged, control the first discharge sub-module to generate a first current to apply current stress to the device under test.

[0150] Specifically, controlling the first charge sub-module to charge the first discharge sub-module includes: closing the first charging switch in the first charge sub-module to control the first power supply in the first charge sub-module to charge the first discharge sub-module.

[0151] Specifically, after determining that the first discharge sub-module is fully charged, controlling the first discharge sub-module to generate a first current includes: when it is determined that the first discharge sub-module is fully charged, closing the device under test to control the first discharge sub-module to generate a first current; when it is determined that the first current output by the first discharge sub-module reaches the peak current, closing the first freewheeling switch in the first discharge sub-module to control the first discharge sub-module to maintain the output of the peak current.

[0152] In the embodiment of the present application, the method for determining that the first discharge sub-module is fully charged can be: by setting a preset time, after reaching the preset time, it indicates that the first discharge sub-module is fully charged, and the preset time can be determined according to actual needs, as long as it is ensured that the first discharge sub-module is fully charged within this preset time. Optionally, the method for determining that the first discharge sub-module is fully charged can also be: detecting the off state of a certain switch in the first discharge sub-module to determine that the first discharge sub-module is fully charged. For example, when it is detected that the first charging switch is disconnected, it can indicate that the first discharge sub-module is fully charged. Optionally, the method for determining that the first discharge sub-module is fully charged can also be: detecting the relationship between a certain potential in the first discharge sub-module and a preset potential to determine that the first discharge sub-module is fully charged. For example, when it is detected that the voltage of the first capacitor is equal to or exceeds the voltage of the first power supply, it can indicate that the first discharge sub-module is fully charged.

[0153] It should be noted that a preset time period can be set in advance before each control node. After the controller executes the previous action, it can execute the next action after reaching the preset time period. Among them, the preset time period can be zero or non-zero. For example, when it is determined that the first discharge sub-module is fully charged, after waiting for the preset time period, then close the device under test to control the first discharge sub-module to generate a first current. Another example is that when it is determined that the first current output by the first discharge sub-module reaches the peak current, after waiting for the preset time period, then close the first freewheeling switch in the first discharge sub-module to control the first discharge sub-module to maintain the output of the peak current.

[0154] S102, control the second current module to generate a second current by closing the module switch to apply current stress to the device under test.

[0155] In the embodiment of the present application, the controller can control the second charging sub-module to charge the second discharging sub-module, and after determining that the second discharging sub-module is fully charged, control the second discharging sub-module to generate a second current and close the module switch to apply a current stress to the device under test.

[0156] Specifically, controlling the second charging sub-module to charge the second discharging sub-module includes: closing the second charging switch in the second charging sub-module to control the second power supply in the second charging sub-module to charge the second discharging sub-module.

[0157] Specifically, after determining that the second discharging sub-module is fully charged, controlling the second discharging sub-module to generate a second current includes: when it is determined that the second discharging sub-module is fully charged, closing the module switch to control the second discharging sub-module to generate a second current; when it is determined that the second current output by the second discharging sub-module reaches the peak current, closing the second freewheeling switch in the second discharging sub-module to control the second discharging sub-module to maintain the output of the peak current.

[0158] In the embodiment of the present application, the method for determining that the second discharging sub-module is fully charged can be: by setting a preset time, after reaching the preset time, it indicates that the second discharging sub-module is fully charged, and the preset time can be determined according to actual needs, as long as it is ensured that the second discharging sub-module is fully charged within this preset time. Optionally, the method for determining that the second discharging sub-module is fully charged can also be: detecting the off state of a certain switch in the second discharging sub-module to determine that the second discharging sub-module is fully charged. For example, when detecting that the second charging switch is disconnected, it can indicate that the second discharging sub-module is fully charged. Optionally, the method for determining that the second discharging sub-module is fully charged can also be: detecting the relationship between a certain point potential in the second discharging sub-module and a preset potential to determine that the second discharging sub-module is fully charged. For example, when detecting that the voltage of the second capacitor is equal to or exceeds the voltage of the second power supply, it can indicate that the second discharging sub-module is fully charged.

[0159] It should be noted that a preset time period can be set in advance before each control node. After the controller executes the previous action, it can execute the next action after reaching the preset time period. Among them, the preset time period can be zero or non-zero. For example, when it is determined that the second discharging sub-module is fully charged, after waiting for the preset time period, then close the device under test to control the second discharging sub-module to generate a second current. Another example is that when it is determined that the second current output by the second discharging sub-module reaches the peak current, after waiting for the preset time period, then close the second freewheeling switch in the second discharging sub-module to control the second discharging sub-module to maintain the output of the peak current.

[0160] In the test method for the converter valve group components provided by the embodiments of the present application, when measuring the junction temperature of the converter valve group components by using the temperature-sensitive parameter temperature measurement method, the sensitivity of the temperature-sensitive electrical parameter to the junction temperature of the converter valve group components decreases with the increase of the conduction current. Therefore, measuring the junction temperature in the small current amplitude platform stage can improve the accuracy and anti-interference ability. The above test circuit provides a small current platform and a large current platform for the device under test through the control module switch. In the large current platform, the device under test can be made to perform a stress experiment equivalent to or accelerated from the application working condition. In the small current platform, accurate junction temperature fluctuation data of the device under test in the equivalent experiment of the application working condition can be obtained, which is beneficial to improving the accuracy of the analysis of the device life degradation process.

[0161] In one embodiment, as Figure 12 shown, the test method for the above converter valve group components further includes:

[0162] S201, disconnect the second freewheeling switch in the second discharge sub-module.

[0163] S202, when it is determined that the voltage across the second capacitor in the second discharge sub-module reaches the negative maximum voltage value, close the second steering switch in the second charge sub-module.

[0164] S203, when it is determined that the voltage across the second capacitor changes from a negative voltage to a positive voltage, close the second charging switch.

[0165] In one embodiment, the test method for the above converter valve group components further includes: disconnect the module switch, and control the first current module to generate a voltage on the device under test to apply a voltage stress on the device under test.

[0166] In one embodiment, as Figure 13 shown, controlling the first current module to generate a voltage on the device under test includes:

[0167] S301, disconnect the first freewheeling switch in the first discharge sub-module.

[0168] S302, when it is determined that the voltage across the device under test reaches the negative maximum voltage value, close the first steering switch in the first charge sub-module.

[0169] S303, when it is determined that the voltage across the device under test changes from a negative voltage to a positive voltage, close the first charging switch.

[0170] In the embodiments of the present application, when the controller executes step S102, it can directly execute step S301. Optionally, when the controller executes step S102, it can first execute the step of "closing the third freewheeling switch and disconnecting the module switch", and then execute step S301.

[0171] Combining all the above embodiments, an exemplary test method is provided. The stress waveforms generated by the test circuit and the test method in the device under test are as follows Figure 14 shown, and the method includes:

[0172] t 1 Before the moment, the device under test is in a blocking state. The voltages of the energy storage capacitors C 4H and C 3H of the high-current module reach a steady state and are the same as the voltage of the DC power supply u DCH ; the voltages of the energy storage capacitors C 4L and C 3H of the low-current module also reach a steady state and are the same as the voltage of the DC power supply u DCL ; the reverse-blocking fully-controlled device V 10H is in a blocking state. The capacitor C 3L applies a positive voltage stress to the device under test through the inductor L 4L , and the magnitude of the voltage stress is the same as the voltage of the capacitor C 3L ;

[0173] t 1 At the moment, the device under test conducts, and the capacitor C 3L resonates in series with the inductor L 4L . The voltage of the capacitor C 3L decreases, and the current of the inductor L 4L increases. The current stress of the device under test is the series resonance current;

[0174] t 2 At the moment, the series resonance current of the capacitor C 3L and the inductor L 4L reaches the peak value. The controller controls the reverse-blocking fully-controlled device V 6L to conduct, and the resonance current continues to flow through the device under test and the reverse-blocking fully-controlled device V 6L . The current stress of the device under test maintains the peak value of the series resonance current unchanged, and a small-current measurement platform for the junction temperature is formed between t 2 and t 3 ;

[0175] t 3 At the moment, the controller controls the reverse-blocking fully-controlled device V 10H to conduct, and the capacitor C 3H resonates in series with the inductor L 4H . The voltage of the capacitor C 3H decreases, and the current of the inductor L 4H increases. The current stress of the device under test is the superposition of the series resonance current and the current amplitude of the junction temperature measurement platform;

[0176] t 4 At the moment, the capacitor C 3Hand the inductor L 4H The series resonance current reaches its peak value, and the reverse-blocking fully-controlled device V 6H conducts. The current stress of the device under test maintains the peak value of this series resonance current while adding the current amplitude of the junction temperature measurement platform unchanged. Between t 4 and t 5 an equivalent or accelerated large current stress platform with fluctuating junction temperature is formed;

[0177] At time t 5 when the current stress duration of the device under test reaches the equivalent or accelerated condition, the controller controls the semi-controlled power device V 9H to conduct, and the reverse-blocking fully-controlled device V 10H to turn off. The series resonance current of the capacitor C 3H and the inductor L 4H flows through the semi-controlled power device V 9H and the reverse-blocking fully-controlled device V 6H for freewheeling and no longer passes through the device under test. The current stress of the device under test is only the peak value of the series resonance current of the capacitor C 3L and the inductor L 4L A second small current measurement platform for junction temperature is formed between t5 and t6;

[0178] After time t 5 the controller controls the reverse-blocking fully-controlled device V 6H to turn off. The capacitor C 3H and the inductor L 4H continue series resonance. The voltage of the capacitor C 3H increases negatively. The semi-controlled power device V 9H resumes the blocking state after the current of the inductor L 4H drops to zero. The voltage of the capacitor C 3H reaches the negative peak value;

[0179] At time t 6 the controller controls the reverse-blocking fully-controlled device V 6L to turn off. The capacitor C 3L and the inductor L4L continue series resonance. The voltage of the capacitor C 3L increases negatively, and the current of L 4L drops;

[0180] At time t 7 the current of L 4L drops to zero, the device under test resumes the blocking state, and the voltage of the capacitor C 3L reaches the negative peak value and applies a negative voltage stress to the device under test through the inductor L 4L ;

[0181] After time t 7 the controller controls the semi-controlled power device V 7HConduct, capacitor C 3H and inductor L 5H Series resonance, inductor L 5H The current first rises and then falls. After falling to zero, the semi-controlled power device V 7H Returns to the blocking state, and the voltage of capacitor C 3H Reverses;

[0182] After that, the controller controls the semi-controlled power device V 8H To conduct, the DC voltage source u DCH And capacitor C 4H Charge capacitor C 5H Through inductor L 3H To supplement the loss consumption. The voltage of capacitor C 3H Eventually becomes the same as the voltage of capacitor C 4H And the DC voltage source u DCH Voltage, with the ability to repeat the test in the next cycle;

[0183] t 8 At this moment, the controller controls the semi-controlled power device V 7L To conduct, capacitor C 3L And inductor L 5L Series resonance, inductor L 5L The current first rises and then falls. After falling to zero, the semi-controlled power device V 7L Returns to the blocking state, and the voltage of capacitor C 3L The voltage reverses and continues to apply voltage stress to the device under test through inductor L 4L ;

[0184] t 9 At this moment, the controller controls the semi-controlled power device V 8L To conduct, the DC voltage source u DCL And capacitor C 4L Charge capacitor C 5L Through inductor L 3L To supplement the loss consumption. The voltage of capacitor C 3L Eventually becomes the same as the voltage of capacitor C 4L And the DC voltage source u DCL Voltage, with the ability to repeat the test in the next cycle.

[0185] In the embodiment of this application, between t 2 And t 3 Is for the small-amplitude current platform that cooperates to realize the junction temperature monitoring of the temperature-sensitive electrical parameter monitoring device before the large-amplitude load current between t 3 And t 5 Heats the power semiconductor device of the device under test; between t 5 And t 6 Is between t 3 And t 5After a large - magnitude load current between them heats the power semiconductor device of the device under test, a small - magnitude current platform is used to cooperate to realize the monitoring of the junction temperature of the temperature - sensitive electrical parameter monitoring device; two measurement windows can obtain the accurate junction temperature of the device at two key time points in a single experimental cycle, and the difference between the two junction temperatures is the junction temperature fluctuation of the device within the experimental cycle. In the above - mentioned control method, t 1 -t 9 The time points only represent the sequence of events, and each time interval is adjustable according to experimental requirements and circuit parameters.

[0186] The above - mentioned Figure 4 The test method in the above - mentioned embodiment is the same as the test method in the above - mentioned embodiment. The large - current stress between t3 and t5 is the superposition of the resonant current of each large - current module and the small - current measurement platform of the junction temperature. Increasing the parallel connection level of the large - current modules can linearly increase the amplitude of the large - current stress.

[0187] The above - mentioned Figure 5 The test method in the above - mentioned embodiment is the same as the test method in the above - mentioned embodiment. Each large - current module shares a DC voltage source u DCH , a semi - controlled power device V 9H and a reverse - blocking fully - controlled device V 10H to reduce costs. The operation control logic of the third embodiment is the same as that of the first embodiment. The large - current stress between t 3 and t 5 is the superposition of the resonant current of each large - current module and the small - current measurement platform of the junction temperature. Increasing the parallel connection level of the large - current modules can linearly increase the amplitude of the large - current stress.

[0188] The above - mentioned Figure 6 The test method in the above - mentioned embodiment is the same as the test method in the above - mentioned embodiment. The large - current stress between t 3 and t 5 is the superposition of the resonant current of each large - current module and the small - current measurement platform of the junction temperature. Increasing the parallel connection level of the large - current modules can linearly increase the amplitude of the large - current stress.

[0189] The above - mentioned Figure 7 The test method in the above - mentioned embodiment is the same as the test method in the above - mentioned embodiment. The voltage stress after t 7 is the superposition of the voltages of the capacitors C 3L of each small - current module. Increasing the series connection level of the small - current modules can linearly increase the amplitude of the large - voltage stress.

[0190] The above - mentioned Figure 8 The test method in the above - mentioned embodiment is the same as the test method in the above - mentioned embodiment. Increasing the parallel connection level of the large - current modules can linearly increase the amplitude of the large - current stress; increasing the series connection level of the small - current modules can linearly increase the amplitude of the large - voltage stress.

[0191] The above - mentioned Figure 9The test method in the embodiment is the same as that in the above embodiment. By increasing the parallel connection stage number of the large-current module, the amplitude of the large-current stress can be linearly increased; by increasing the series connection stage number of the small-current module, the amplitude of the large-voltage stress can be linearly increased.

[0192] The above Figure 10 The test method in the embodiment is the same as that in the above embodiment. By increasing the parallel connection stage number of the large-current module, the amplitude of the large-current stress can be linearly increased; by increasing the series connection stage number of the small-current module, the amplitude of the large-voltage stress can be linearly increased.

[0193] For the test method described in the embodiment of the present application, based on the integrated voltage-current source topology structure and the enlarged test current parallel configuration scheme, an auxiliary control switch is added, thereby generating additional control degrees of freedom. Different control degrees of freedom are used to generate a small-current measurement platform and a large-current stress respectively. The small-current measurement platform improves the sensitivity of the temperature-sensitive electrical parameters for on-line monitoring of the junction temperature, and the large-current stress generates a life degradation stress equivalent to or accelerated from the application working condition in the device under test. The topology structure has the characteristics of high modularity. Increasing the parallel connection stage number of the module can expand the experimental current range, and increasing the series connection stage number of the module can expand the experimental voltage range. It can simplify the circuit structure of the equivalent experimental platform and reduce its construction and operation costs; a short-time platform with a small conduction current amplitude is generated on the power semiconductor device of the device under test, providing a measurement window for accurate on-line monitoring of the device junction temperature.

[0194] The methods described in the above steps are all described in the foregoing embodiments. For detailed content, please refer to the foregoing description and will not be elaborated here.

[0195] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps in other steps.

[0196] Based on the same inventive concept, an embodiment of the present application further provides a test device for a converter valve group component for implementing the test method of the converter valve group component involved above. The solution provided by this device for solving problems is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the test device for the converter valve group component provided below can refer to the limitations on the test method of the converter valve group component in the above text, and will not be elaborated here.

[0197] In one embodiment, a test device for a converter valve group component is provided, including:

[0198] A first control module, configured to control a first current module to generate a first current to apply a current stress to a device under test.

[0199] A second control module, configured to control a second current module to generate a second current by closing a module switch to apply a current stress to a device under test.

[0200] In one embodiment, the above first control module is configured to control a first charge sub-module to charge a first discharge sub-module, and after determining that the first discharge sub-module is fully charged, control the first discharge sub-module to generate a first current to apply a current stress to a device under test.

[0201] In one embodiment, the above first control module is further configured to close a first charging switch in the first charge sub-module to control a first power supply in the first charge sub-module to charge the first discharge sub-module.

[0202] In one embodiment, the above first control module is further configured to close the device under test to control the first discharge sub-module to generate a first current when it is determined that the first discharge sub-module is fully charged; and close a first freewheeling switch in the first discharge sub-module to control the first discharge sub-module to maintain the output of the peak current when it is determined that the first current output by the first discharge sub-module reaches the peak current.

[0203] In one embodiment, the above second control module is configured to control a second charge sub-module to charge a second discharge sub-module, and after determining that the second discharge sub-module is fully charged, control the second discharge sub-module to generate a second current and close the module switch to apply a current stress to a device under test.

[0204] In one embodiment, the above second control module is configured to close a second charging switch in the second charge sub-module to control a second power supply in the second charge sub-module to charge the second discharge sub-module.

[0205] In one embodiment, the second control module is configured to close the module switch to control the second discharge sub-module to generate a second current when it is determined that the charging of the second discharge sub-module is completed; and to close the second freewheeling switch in the second discharge sub-module to control the second discharge sub-module to maintain the output of the peak current when it is determined that the second current output by the second discharge sub-module reaches the peak current.

[0206] In one embodiment, the first control module is configured to close the third freewheeling switch and open the module switch.

[0207] In one embodiment, the second control module is configured to open the second freewheeling switch in the second discharge sub-module; to close the second steering switch in the second charge sub-module when it is determined that the voltage across the second capacitor in the second discharge sub-module reaches the negative maximum voltage value; and to close the second charging switch when it is determined that the voltage across the second capacitor changes from a negative voltage to a positive voltage.

[0208] In one embodiment, the first control module is configured to open the module switch and control the first current module to generate a voltage across the device under test to apply a voltage stress across the device under test.

[0209] In one embodiment, the first control module is configured to open the first freewheeling switch in the first discharge sub-module; to close the first steering switch in the first charge sub-module when it is determined that the voltage across the device under test reaches the negative maximum voltage value; and to close the first charging switch when it is determined that the voltage across the device under test changes from a negative voltage to a positive voltage.

[0210] Each module in the test device for the commutation valve group components can be implemented in whole or in part by software, hardware, and their combination. Each of the above modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form so that the processor can call and execute the operations corresponding to each of the above modules.

[0211] In one embodiment, a computer device is provided. The computer device can be a terminal, and its internal structure diagram can be as Figure 15As shown in the figure. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner, and the wireless manner can be achieved through WIFI, a mobile cellular network, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a test method for a converter valve group component. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the computer device housing, or an external keyboard, touchpad, or mouse, etc.

[0212] Those skilled in the art can understand that Figure 15 the structure shown in the figure is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0213] In one embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above method embodiments are implemented.

[0214] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by the processor, the steps in the above method embodiments are implemented.

[0215] In one embodiment, a computer program product is provided, including a computer program. When the computer program is executed by the processor, the steps in the above method embodiments are implemented.

[0216] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the various embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tapes, floppy disks, flash memories, optical memories, high-density embedded non-volatile memories, resistive random access memories (ReRAM), magnetoresistive random access memories (MRAM), ferroelectric random access memories (FRAM), phase change memories (PCM), graphene memories, etc. Volatile memories can include random access memory (RAM) or external cache memories, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the various embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the various embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0217] In the description of this specification, the description referring to terms such as "some embodiments", "other embodiments", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0218] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0219] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A test circuit for a converter valve assembly, characterized in that: The test circuit comprises: at least one first current module, at least one second current module, at least one module switch and a device to be tested; the first current module is connected in parallel with the device to be tested, and the second current module is connected in parallel with the device to be tested through a corresponding module switch; The first current module is used to generate a first current during the process of applying current stress on the device under test; the first current module includes: a first charging submodule and a first discharging submodule; the first charging submodule is connected in parallel with the first discharging submodule; the first discharging submodule is connected in parallel with the device under test; the first charging submodule is used to supply power to the first discharging submodule; the first discharging submodule is used to generate a first current during the process of applying current stress on the device under test; The second current module is used to generate a second current during the process of applying current stress on the device under test; the first current is less than the second current; the second current module includes: a second charging submodule and a second discharging submodule; the second charging submodule is connected in parallel with the second discharging submodule; the second discharging submodule is connected in parallel with the device under test through a corresponding module switch; the second charging submodule is used to supply power to the second discharging submodule; the second discharging submodule is used to generate a second current during the process of applying current stress on the device under test.

2. The test circuit according to claim 1, characterized in that: The first discharge submodule includes: a first capacitor, a first freewheeling switch and a first inductor; the first capacitor is connected in parallel with the first charging submodule, the first freewheeling switch is connected in parallel with the first capacitor, one end of the first inductor is connected to a first common end of the first capacitor and the first freewheeling switch, the other end of the first inductor is connected to a first end of the device under test, and a second end of the device under test is connected to a second common end of the first capacitor and the first freewheeling switch.

3. The test circuit according to claim 2, characterized in that: The first charging submodule includes: a first power supply, a first charging switch, a first steering switch and a second inductor; One end of the first power supply is connected to one end of the first charging switch, the other end of the first charging switch is respectively connected to one end of the first steering switch and one end of the second inductor, and the other end of the second inductor is connected to a common end of the first capacitor, the first freewheeling switch and the first inductor; The other end of the first power supply is connected to a common end of the first steering switch, the first capacitor, and the first freewheeling switch.

4. The test circuit according to claim 1, characterized in that: The second discharge submodule includes: a second capacitor, a second freewheeling switch, a third freewheeling switch and a third inductor; The second capacitor is connected in parallel with the second charging submodule, the second freewheeling switch is connected in parallel with the second capacitor, one end of the third inductor is connected to the first common end of the second capacitor and the second freewheeling switch, the other end of the third inductor is respectively connected to the first end of the third freewheeling switch and one end of the module switch, the second end of the third freewheeling switch is connected to the common end of the second freewheeling switch, the second capacitor and the second charging submodule, and the other end of the module switch is connected in parallel with the device under test.

5. The test circuit according to claim 4, characterized in that: The second charging submodule includes: a second power supply, a second charging switch, a second steering switch and a fourth inductor; One end of the second power supply is connected to one end of the second charging switch, the other end of the second charging switch is respectively connected to one end of the second steering switch and one end of the fourth inductor, and the other end of the fourth inductor is connected to a common end of the second capacitor, the second freewheeling switch and the third inductor; The other end of the second power supply is connected to a common end of the second steering switch, the second capacitor, the second freewheeling switch, and the third freewheeling switch.

6. The test circuit according to any one of claims 1 to 5, characterized in that: The test circuit includes a plurality of first current modules, the plurality of first current modules are connected in series, and the plurality of first current modules share a power supply.

7. The test circuit according to any one of claims 1 to 5, characterized in that: The test circuit includes a plurality of the second current modules, the plurality of the second current modules are connected in parallel, and the plurality of the second current modules share a power supply.

8. The test circuit according to claim 7, characterized in that: The plurality of second current modules share a third freewheeling switch.

9. A method for testing a converter valve assembly component, characterized in that: The test method is applied to a test system, the test system comprising a controller and a test circuit according to any one of claims 1 to 8, the method comprising: Controlling the first current module to generate a first current to apply current stress to the device under test; Controlling the second current module to generate a second current by closing the module switch to apply current stress on the device under test; The controlling the first current module to generate the first current to apply current stress on the device under test includes: controlling the first charging submodule to charge the first discharging submodule, and after determining that the first discharging submodule has been charged, controlling the first discharging submodule to generate a first current to apply current stress to the device under test; The method of controlling the second current module to generate a second current by closing the module switch to apply current stress on the device under test includes: The second charging submodule is controlled to charge the second discharge submodule, and after determining that the second discharge submodule has finished charging, the second discharge submodule is controlled to generate a second current and close the module switch to apply current stress on the device under test.

10. The method according to claim 9, characterized in that The controlling the first charging submodule to charge the first discharging submodule comprises: The first charging switch in the first charging submodule is closed to control the first power supply in the first charging submodule to charge the first discharging submodule.

11. The method according to claim 10, characterized in that After determining that the first discharge submodule has completed charging, controlling the first discharge submodule to generate a first current includes: When it is determined that the first discharge submodule has been fully charged, closing the device under test to control the first discharge submodule to generate a first current; When it is determined that the first current output by the first discharge submodule reaches the peak current, a first freewheeling switch in the first discharge submodule is closed to control the first discharge submodule to keep outputting the peak current.

12. The method according to claim 9, characterized in that The controlling the second charging submodule to charge the second discharging submodule comprises: The second charging switch in the second charging submodule is closed to control the second power supply in the second charging submodule to charge the second discharging submodule.

13. The method according to claim 12, characterized in that After determining that the second discharge submodule has completed charging, controlling the second discharge submodule to generate a second current includes: When it is determined that the second discharge submodule has been fully charged, closing the module switch to control the second discharge submodule to generate a second current; When it is determined that the second current output by the second discharge submodule reaches the peak current, the second freewheeling switch in the second discharge submodule is closed to control the second discharge submodule to keep outputting the peak current.

14. The method according to claim 13, characterized in that The method further comprises: The third freewheeling switch is closed, and the module switch is opened.

15. The method according to claim 13 or 14, characterized in that The method further comprises: Disconnecting the second freewheeling switch in the second discharge submodule; When it is determined that the voltage across the second capacitor in the second discharge submodule reaches the maximum negative voltage value, closing the second steering switch in the second charging submodule; When it is determined that the voltage across the second capacitor changes from a negative voltage to a positive voltage, the second charging switch is closed.

16. The method according to claim 10, characterized in that The method further comprises: The module switch is turned off, and the first current module is controlled to generate a voltage on the device under test, so as to apply voltage stress on the device under test.

17. The method according to claim 16, characterized in that The controlling the first current module to generate a voltage on the device under test includes: Disconnecting the first freewheeling switch in the first discharge submodule; When it is determined that the voltage at both ends of the device under test reaches the maximum negative voltage value, closing the first steering switch in the first charging submodule; When it is determined that the voltage across the device under test changes from a negative voltage to a positive voltage, a first charging switch in the first charging submodule is closed.

18. The method according to claim 9, characterized in that The duration of the first current is greater than the duration of the second current.

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