Method and system for booting up memory bar with abnormal CPU jumping

Abstract

The present invention provides a startup method and system for CPU to jump abnormal memory stick to read memory stick. When a memory stick is inserted, the data channel of the inserted memory stick on the baseboard controller is opened, so that the baseboard controller obtains the inserted memory stick to read information to try to obtain SPD information; if the SPD information of the inserted memory stick cannot be obtained, the inserted memory is determined to be an abnormal memory stick, the power of the abnormal memory stick is turned off through a preset load switch, and the information of the next inserted memory stick inserted on the baseboard controller is read in turn, so that even if there is an abnormal memory stick in front, the abnormal memory stick can be skipped by cutting off the power of the abnormal memory stick without unplugging the abnormal memory stick, and the normal memory stick behind can be read smoothly, so as to complete the initialization of all normal memory sticks and then start up normally.

Description

Technical Field

[0001] The present invention relates to the field of computer communication technology, and more specifically, to a startup method and system for reading a memory bar when a CPU jumps abnormally. Background Art

[0002] In today's digital society, servers are everywhere. As the core of the server, it is important for all digital enterprises to ensure that the CPU stably supports OS booting and lasting operation. However, the Sapphire Rapids CPU platform, Intel's fourth-generation server CPU, has a fatal error. For example, before booting, a DDR5 memory stick that cannot read SPD is inserted into the first slot of the Memory Controller (not limited to the first slot of the memory controller, this is just for better illustration), and a DDR5 memory stick that can be initialized and booted is inserted behind the DDR5 memory stick that can no longer read SPD at the same position of the Memory Controller. In this way, when the BIOS initializes the DDR5 memory stick that cannot read SPD and is under the same Memory Controller during the PEI Memory initialization phase, the memory stick initialization will inevitably fail.

[0003] Therefore, there is an urgent need for a startup method in which the CPU jumps over the abnormal memory stick to read the memory stick, by which the BIOS cannot read the memory stick SPD after booting up on the Sapphire Rapids CPU platform, and the abnormal memory stick can be shielded without pulling out the stick, so that the CPU can correctly identify the DDR5 memory stick inserted later under the same memory controller. Summary of the invention

[0004] In view of the above problems, the purpose of the present invention is to provide a method for booting up a memory stick when a CPU jumps abnormally, so as to solve the technical problem that a DDR5 memory stick that cannot read SPD is inserted into the first slot of a memory controller (not limited to the first slot of the memory controller, just for better illustration) before booting up a CPU platform of Sapphire Rapids, and a DDR5 memory stick that can be initialized and booted up normally is inserted at the same position of the memory controller behind the DDR5 memory stick that can no longer read SPD, so that when the BIOS initializes the DDR5 memory stick that cannot read SPD and is under the same memory controller in the PEI Memory initialization stage, the memory stick initialization failure will inevitably occur.

[0005] The present invention provides a method for booting a computer by reading a memory bar when a CPU jumps abnormally, which includes:

[0006] The CPU platform is powered on, and the baseboard controller in the CPU platform is powered on and works;

[0007] Performing insertion status detection on the powered-on baseboard controller through a preset insertion status detection unit, when a memory stick is inserted, the insertion status detection unit displays the insertion level;

[0008] If the insertion level is displayed, the data channel of the inserted memory stick inserted on the baseboard controller is opened, so that the baseboard controller obtains the inserted memory stick to read information in order to try to obtain SPD information; wherein, if the SPD information of the inserted memory stick cannot be obtained, the inserted memory is determined to be an abnormal memory stick, the power supply of the abnormal memory stick is turned off through a preset load switch, and the information of the next inserted memory stick inserted on the baseboard controller is read in turn; if the SPD information of the inserted memory stick is successfully read, the information of the next inserted memory stick inserted on the baseboard controller is read in turn;

[0009] After information is read from all the inserted memory sticks on the baseboard controller, a command is sent to the CPU board of the CPU platform to complete the booting.

[0010] Preferably, a detection pin of the insertion status detection unit is inserted into a GPIO of the substrate controller.

[0011] Preferably, the insertion level is GPIO ground;

[0012] When a memory stick is inserted, the GPIO to which the insertion status detection unit is connected is grounded;

[0013] When the memory stick is disconnected, the GPIO to which the insertion status detection unit is connected presents a 3.3V level.

[0014] Preferably, two groups of power inputs are provided on the inserted memory stick, one group is a power supply voltage for powering a PMIC chip on the memory stick, and the other group is an internal voltage for serving as a DCDC input voltage of a voltage regulator inside the PMIC chip.

[0015] Preferably, shutting down the power supply of the abnormal memory bar by using a preset load switch includes:

[0016] The supply voltage is turned off through a preset load switch; wherein an enable pin of the load switch is connected to a GPIO of the substrate controller so that the substrate controller controls the load switch.

[0017] Preferably, the supply voltage is 3.3V and the internal voltage is 12V.

[0018] Preferably, the CPU platform is the CPU platform of Intel's fourth-generation server Sapphire Rapids.

[0019] Preferably, the memory stick is a DDR5 memory stick in the same memory controller.

[0020] The present invention also provides a system for booting a memory bar when a CPU jumps abnormally, wherein the method for booting a memory bar when a CPU jumps abnormally comprises a CPU platform, a baseboard controller integrated on the CPU platform, an insertion status detection unit connected to the baseboard controller, and a reading program and an execution program parasitic on the baseboard controller; wherein,

[0021] The insertion status detection unit is used to detect the insertion status of the baseboard controller when it is powered on. When a memory stick is inserted, the insertion status detection unit displays the insertion level.

[0022] The reading program is used to open the data channel of the inserted memory bar inserted on the baseboard controller when the insertion level is displayed, so that the baseboard controller obtains the inserted memory bar to read information in order to try to obtain SPD information; wherein, if the SPD information of the inserted memory bar cannot be obtained, the inserted memory is determined to be an abnormal memory bar, the power supply of the abnormal memory bar is turned off through a preset load switch, and the information of the next inserted memory bar inserted on the baseboard controller is read in sequence; if the SPD information of the inserted memory bar is successfully read, the information of the next inserted memory bar inserted on the baseboard controller is read in sequence;

[0023] The execution program is used to send a command to the CPU board of the CPU platform to complete the startup after information has been read from all the inserted memory sticks on the baseboard controller.

[0024] Preferably, an enable pin of the load switch is connected to a GPIO of the substrate controller.

[0025] It can be seen from the above technical scheme that the power-on method and system for reading a memory stick when a CPU jumps to an abnormal memory stick provided by the present invention performs insertion status detection on a baseboard controller in a powered-on CPU platform through a preset insertion status detection unit. When a memory stick is inserted, the insertion status detection unit displays an insertion level; if the insertion level is displayed, the data channel of the inserted memory stick on the baseboard controller is opened, so that the baseboard controller obtains the inserted memory stick for information reading to try to obtain SPD information; wherein, if the SPD information of the inserted memory stick cannot be obtained, the inserted memory is determined to be an abnormal memory stick, and the preset load switch is used to close the inserted memory stick. The power supply of the abnormal memory stick is turned on, and the information of the next inserted memory stick inserted on the baseboard controller is read in turn; if the SPD information of the inserted memory stick is successfully read, the information of the next inserted memory stick inserted on the baseboard controller is read in turn. When the information of all the inserted memory sticks on the baseboard controller has been read, a command is sent to the CPU board of the CPU platform to complete the startup. Therefore, even if there is an abnormal memory stick in front, the abnormal memory stick can be cut off in the form of power supply without unplugging the abnormal memory stick, and the normal memory stick behind can be read smoothly to complete the initialization of all normal memory sticks and then start normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more clear and easy to understand. In the accompanying drawings:

[0027] Figure 1 It is a flowchart of a method for booting a computer by reading a memory bar when a CPU jumps abnormally according to an embodiment of the present invention;

[0028] Figure 2 A schematic diagram of a booting system for reading a memory bar when a CPU jumps abnormally according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] Before starting up the Sapphire Rapids CPU platform, insert a DDR5 memory stick that cannot read SPD into the first slot of the Memory Controller (not limited to the first slot of the memory controller, this is just for better illustration), and insert a DDR5 memory stick that can be initialized and started up normally into the same position of the Memory Controller behind the DDR5 memory stick that cannot read SPD. In this way, when the BIOS initializes the DDR5 memory stick that cannot read SPD and is under the same Memory Controller during the PEI Memory initialization phase, the memory stick initialization will inevitably fail.

[0030] In view of the above problems, the present invention provides a method and system for booting a computer and reading a memory bar when a CPU jumps abnormally. The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0031] In order to illustrate the memory read and write test acceleration method and system provided by the present invention, Figure 1 , Figure 2 The embodiments of the present invention are exemplarily indicated.

[0032] The following description of exemplary embodiments is merely illustrative in nature and is not intended to limit the present invention and its application or use. Technologies and devices known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the technologies and devices should be considered as part of the specification.

[0033] like Figure 1 , Figure 2 As shown together, the present invention provides a method for booting a computer by which a CPU jumps to an abnormal memory bar to read the memory bar, comprising:

[0034] S1: Power on the CPU platform, and the baseboard controller (BMC) in the CPU platform is powered on and works;

[0035] S2: Performing insertion status detection on the powered-on baseboard controller through a preset insertion status detection unit, and when a memory stick is inserted, the insertion status detection unit displays an insertion level;

[0036] S3: If the insertion level is displayed, the data channel of the inserted memory stick inserted on the baseboard controller is opened, so that the baseboard controller obtains the inserted memory stick to read information in order to try to obtain SPD information; wherein, if the SPD information of the inserted memory stick cannot be obtained, the inserted memory is determined to be an abnormal memory stick, the power supply of the abnormal memory stick is turned off through a preset load switch, and the information of the next inserted memory stick inserted on the baseboard controller is read in turn; if the SPD information of the inserted memory stick is successfully read, the information of the next inserted memory stick inserted on the baseboard controller is read in turn

[0037] S4: After information is read from all the memory modules inserted in the baseboard controller, a command is sent to the CPU board of the CPU platform to complete the booting.

[0038] In this embodiment, in step S2, the detection pin of the insertion state detection unit is inserted into the GPIO of the substrate controller, the GPIO is a general input and output pin of the substrate controller, and the insertion level is GPIO grounding;

[0039] When a memory stick is inserted, the GPIO to which the insertion status detection unit is connected is grounded;

[0040] When the memory stick is disconnected, the GPIO to which the insertion status detection unit is connected presents a 3.3V level.

[0041] In a specific embodiment, a memory socket with an insertion status detection pin is used. The insertion status detection unit is integrated in the memory socket of the insertion status detection pin in hardware. The pin of the insertion status detection unit is connected to the GPIO (general input output pin) of the BMC (baseboard controller). When the memory stick is inserted, the GPIO is grounded, and when disconnected, the GPIO presents a 3.3V level.

[0042] In this embodiment, two groups of power inputs are provided on the inserted memory stick, one group is a power supply voltage for powering the PMIC chip on the memory stick, and the other group is an internal voltage for serving as a DCDC input voltage of a voltage regulator inside the PMIC chip. For example, in a specific embodiment, there are two groups of power inputs on an RDIMM memory stick (a type of memory stick inserted on a CPU platform), one group is 3.3V (used to power the PMIC chip); wherein PMIC is (Power Management IC, power management integrated circuit), which is the abbreviation of power management; the other group is 12V (12V is the DCDC input voltage of the voltage regulator inside the PMIC). Furthermore, the 3.3V power supply provides energy to the PMIC chip on the RDIMM memory stick, and the PMIC can adjust the 12V power supply to a suitable working voltage to power the memory chip on the memory stick. Therefore, in the power-on method of the present invention in which the CPU jumps to an abnormal memory stick to read the memory stick, a load switch can be added to a path of a power supply voltage such as 3.3V in hardware design, and the enable pin of the load switch is connected to the GPIO of the BMC. The BMC can control the power supply of the PMIC, thereby turning off the power supply of the memory stick.

[0043] That is, in this embodiment, turning off the power supply of the abnormal memory stick through a preset load switch includes: turning off the power supply voltage through a preset load switch; wherein the enable pin of the load switch is connected to the GPIO of the baseboard controller so that the baseboard controller controls the load switch, and in this specific embodiment, the power supply voltage is 3.3V, and the internal voltage is 12V. In other words, by controlling the power supply voltage based on the load switch to control the power supply of the PMIC chip, when the power supply of the PMIC chip is turned off, the memory stick (inserted memory stick) where it is located can turn off the power failure.

[0044] Therefore, in steps S3 and S4, in a specific embodiment, when the host is powered on, the CPU board is not powered on, and the baseboard controller (BMC, Baseboard Management Controller, baseboard controller, also known as baseboard management controller) is powered on and works. If the insertion level is displayed, it indicates that a memory stick is inserted at the position, that is, there is an inserted memory stick. The insertion status detection unit turns on the power supply voltage 3.3V of the corresponding inserted memory stick according to the insertion status of the memory pin, and then opens the data channel of the inserted memory stick inserted on the BMC by switching the I3C channel to the BMC. The BMC can obtain the SPD information of the corresponding inserted memory stick. At this time, if it is found that the SPD information cannot be obtained, it is determined that the inserted memory stick is abnormal and it is used as an abnormal memory stick. For example, if the RDIMM / DIMM (a type of memory stick, not limited to this type) inserted in this specific embodiment is abnormal, the 3.3V and 12V power supplies of the corresponding memory are turned off at the same time. In actual hardware operation, the load switch only turns off the 3.3V power supply voltage. After the voltage regulator used to power the internal PMIC stops working, the 12V power supply to the memory chip on the memory stick is turned off. After the load switch turns off the power supply of the abnormal memory stick, the abnormal information is recorded and reported to the console after all memories are detected. If the SPD information of the inserted memory stick can be successfully read, the information of the next inserted memory stick inserted on the BMC is read in turn until all memory sticks have been attempted to read the information. Then, a command is sent to the CPU board of the CPU platform through the console in the CPU platform to complete the startup, thereby solving the problem of repairing the DDR5 memory stick that cannot work properly when the SPD is read during the startup BIOS PEI Memory initialization phase on the Sapphire Rapids CPU platform. The subsequent DDR5 memory sticks under the same Memory Controller will have a serious problem of being unable to read. In this way, even if the abnormal memory stick in front is not pulled out, the abnormal memory stick can be skipped for normal startup, so even if there is an abnormal memory stick that cannot obtain SPD information, there is no need to perform a "stick pulling operation".

[0045] As described above, the power-on method for reading a memory stick by jumping an abnormal memory stick provided by the present invention performs insertion status detection on a baseboard controller in a powered-on CPU platform through a preset insertion status detection unit, and when a memory stick is inserted, the insertion status detection unit displays an insertion level; if the insertion level is displayed, the data channel of the inserted memory stick on the baseboard controller is opened, so that the baseboard controller obtains the inserted memory stick for information reading to try to obtain SPD information; wherein, if the SPD information of the inserted memory stick cannot be obtained, the inserted memory is determined to be an abnormal memory stick, and the abnormal memory stick is closed through a preset load switch. The power supply of the memory stick is turned on, and the information of the next memory stick inserted on the baseboard controller is read in turn; if the SPD information of the inserted memory stick is successfully read, the information of the next memory stick inserted on the baseboard controller is read in turn. When the information of all the inserted memory sticks on the baseboard controller has been read, a command is sent to the CPU board of the CPU platform to complete the startup. Therefore, even if there is an abnormal memory stick in front, the abnormal memory stick can be cut off in the form of power supply without unplugging the abnormal memory stick, and the normal memory stick behind can be read smoothly to complete the initialization of all normal memory sticks, and then the computer can be started normally.

[0046] In addition, if Figure 2 As shown, the present invention also provides a booting system 100 for reading a memory bar when a CPU jumps abnormally, which implements the booting method for reading a memory bar when a CPU jumps abnormally, comprising a CPU platform 110, a baseboard controller 111 integrated on the CPU platform, an insertion status detection unit 112 communicating with the baseboard controller, and a reading program 1121 and an execution program 1122 parasitic on the baseboard controller; wherein,

[0047] The insertion status detection unit 112 is used to detect the insertion status of the baseboard controller when it is powered on. When a memory stick is inserted, the insertion status detection unit displays the insertion level.

[0048] The reading program 1121 is used to open the data channel of the inserted memory bar inserted on the baseboard controller when the insertion level is displayed, so that the baseboard controller obtains the inserted memory bar to read information in order to try to obtain SPD information; wherein, if the SPD information of the inserted memory bar cannot be obtained, the inserted memory is determined to be an abnormal memory bar, the power supply of the abnormal memory bar is turned off through a preset load switch, and the information of the next inserted memory bar inserted on the baseboard controller is read in turn; if the SPD information of the inserted memory bar is successfully read, the information of the next inserted memory bar inserted on the baseboard controller is read in turn;

[0049] The execution program 1122 is used to send a command to the CPU board of the CPU platform to complete the startup after information has been read from all the inserted memory sticks on the baseboard controller.

[0050] It should be emphasized that the enable pin of the load switch is connected to the GPIO of the baseboard controller, so that when the power supply of the PMIC chip is turned off, the memory stick where it is located (the memory stick is inserted) can turn off the power failure.

[0051] The specific implementation example can refer to the specific implementation method of the boot method for reading the memory bar when the CPU jumps abnormally, which will not be described again.

[0052] As shown above, the present invention provides a boot system for reading a memory stick by jumping an abnormal CPU stick. The baseboard controller 111 in the powered-on CPU platform 110 is detected for insertion status by a preset insertion status detection unit. When a memory stick is inserted, the insertion status detection unit 112 displays the insertion level. If the insertion level is displayed, the data channel of the inserted memory stick on the baseboard controller is opened, so that the baseboard controller obtains the inserted memory stick for information reading to try to obtain SPD information. If the SPD information of the inserted memory stick cannot be obtained, the inserted memory is determined to be an abnormal memory stick, and the preset load switch is used to close the inserted memory stick. The power supply of the abnormal memory stick is turned on, and the information of the next inserted memory stick inserted on the baseboard controller is read in turn; if the SPD information of the inserted memory stick is successfully read, the information of the next inserted memory stick inserted on the baseboard controller is read in turn. When the information of all the inserted memory sticks on the baseboard controller has been read, a command is sent to the CPU board of the CPU platform to complete the startup. Therefore, even if there is an abnormal memory stick in front, the abnormal memory stick can be cut off in the form of power supply without unplugging the abnormal memory stick, and the normal memory stick behind can be read smoothly to complete the initialization of all normal memory sticks and then start normally.

[0053] As described above with reference to the accompanying drawings, the booting method and system for reading a memory bar when a CPU jumps abnormally according to the present invention are described by way of example. However, those skilled in the art should understand that various improvements can be made to the booting method and system for reading a memory bar when a CPU jumps abnormally according to the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the attached claims.

Claims

1. A method for booting a computer by reading a memory bar when a CPU jumps abnormally, characterized in that: include: The CPU platform is powered on. After the host is powered on, the CPU board part of the CPU platform is not powered on, and the baseboard controller in the CPU platform is powered on and works; The insertion state of the powered-on baseboard controller is detected by a preset insertion state detection unit, and when a memory stick is inserted, the insertion state detection unit displays the insertion level; wherein two groups of power inputs are arranged on the inserted memory stick, one group is a power supply voltage for powering a PMIC chip on the memory stick, and the other group is an internal voltage for serving as a DCDC input voltage of a voltage regulator inside the PMIC chip; If the insertion level is displayed, the data channel of the inserted memory stick inserted on the baseboard controller is opened, so that the baseboard controller obtains the inserted memory stick to read information in order to try to obtain SPD information; wherein, if the SPD information of the inserted memory stick cannot be obtained, the inserted memory is determined to be an abnormal memory stick, the power supply of the abnormal memory stick is turned off through a preset load switch, and the information of the next inserted memory stick inserted on the baseboard controller is read in sequence; if the SPD information of the inserted memory stick is successfully read, the information of the next inserted memory stick inserted on the baseboard controller is read in sequence; wherein, turning off the power supply of the abnormal memory stick through a preset load switch includes: The supply voltage is turned off through a preset load switch; wherein the enable pin of the load switch is connected to the GPIO of the substrate controller so that the substrate controller controls the load switch; the supply voltage is 3.3V and the internal voltage is 12V; After all the inserted memory sticks on the baseboard controller have been read, a command is sent to the CPU board to complete the booting.

2. The method for booting a computer by reading a memory bar when a CPU jumps abnormally according to claim 1, characterized in that: The detection pin of the insertion state detection unit is inserted into the GPIO of the baseboard controller.

3. The method for booting a computer by reading a memory bar when a CPU jumps abnormally according to claim 2, characterized in that: The insertion level is GPIO grounding; When a memory stick is inserted, the GPIO to which the insertion status detection unit is connected is grounded; When the memory stick is disconnected, the GPIO to which the insertion status detection unit is connected presents a 3.3V level.

4. The method for booting a computer by reading a memory bar when a CPU jumps abnormally according to claim 1, wherein: The CPU platform is the CPU platform of Intel's fourth-generation server Sapphire Rapids.

5. The method for booting a computer by reading a memory bar when a CPU jumps abnormally according to claim 4, characterized in that: The memory stick is a DDR5 memory stick in the same memory controller.

6. A boot system for reading memory bars by CPU jumping abnormal memory bars, characterized in that: A method for booting a computer to read a memory bar when a CPU jumps abnormally as described in any one of claims 1 to 5, comprising a CPU platform, a baseboard controller integrated on the CPU platform, an insertion status detection unit connected to the baseboard controller in communication, and a reading program and an execution program parasitic on the baseboard controller; wherein, The insertion status detection unit is used to detect the insertion status of the baseboard controller that is powered on. When a memory stick is inserted, the insertion status detection unit displays the insertion level. Two groups of power inputs are provided on the inserted memory stick, one group is a power supply voltage for powering the PMIC chip on the memory stick, and the other group is an internal voltage used as a DCDC input voltage of a voltage regulator inside the PMIC chip. The reading program is used to open the data channel of the inserted memory bar inserted on the baseboard controller when the insertion level is displayed, so that the baseboard controller obtains the inserted memory bar for information reading to try to obtain SPD information; wherein, if the SPD information of the inserted memory bar cannot be obtained, the inserted memory is determined to be an abnormal memory bar, the power supply of the abnormal memory bar is turned off through a preset load switch, and the information of the next inserted memory bar inserted on the baseboard controller is read in sequence; if the SPD information of the inserted memory bar is successfully read, the information of the next inserted memory bar inserted on the baseboard controller is read in sequence; wherein, turning off the power supply of the abnormal memory bar through a preset load switch includes: turning off the power supply voltage through a preset load switch; wherein the enable pin of the load switch is connected to the GPIO of the baseboard controller so that the baseboard controller controls the load switch; the power supply voltage is 3.3V, and the internal voltage is 12V; The execution program is used to send a command to the CPU board of the CPU platform to complete the startup after information has been read from all the inserted memory sticks on the baseboard controller.

7. The booting system for reading memory bars by CPU jumping abnormal memory bars as claimed in claim 6, characterized in that: The enable pin of the load switch is connected to the GPIO of the substrate controller.

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