ATE-based signal wiring compensation impedance control method

Abstract

The present application relates to the technical field of signal wiring, and especially relates to a signal wiring compensation impedance control method based on ATE, which comprises the following steps: obtaining upper and lower adjacent pins of a signal wiring to be drawn in a wiring layer of a chip to be tested; obtaining a center point of the signal wiring of the adjacent pins according to a pin inner distance of the adjacent pins and a width of the signal wiring; connecting the center points of the signal wiring of all the adjacent pins to draw a wavy signal wiring; performing copper foil compensation and avoidance on the signal wiring of the wiring layer of the chip to be tested; and performing copper foil hollowing on adjacent layers of the chip to be tested. The present application solves the problem that the existing signal line design does not consider compensation, which affects the performance of the signal line and the efficiency of the chip test.

Description

Technical Field

[0001] This invention relates to the field of signal cabling technology, and in particular to a signal cabling impedance compensation control method based on ATE. Background Technology

[0002] Test substrate (ATE) testing is a sub-field of chip R&D that tests chip performance.

[0003] Impedance matching control of signal transmission channels is a key factor determining signal transmission quality during interconnection, and it is especially important for high-speed signals. With the increasing miniaturization of BGA packages, maintaining a stable impedance value in the signal transmission channel during interconnection with other devices (including between the chip and test equipment, and between chips) can reduce signal reflection, crosstalk, and loss during transmission, thereby reducing signal distortion and providing interference immunity. Impedance matching of signal transmission channels is a critical factor in the design of signal interconnection channels.

[0004] Signal transmission rates are gradually increasing. High-speed signals, such as 112Gbps, represent the current ultra-high-speed signal transmission method. ATE is specifically used for performance testing of high-speed signal chips. ATE is an indispensable key carrier in the chip testing process and serves as the medium connecting the chip under test and the testing equipment. Poor design of the high-speed signal transmission channel on the ATE test board can seriously affect the reliability of chip test results, leading to test failure.

[0005] Problems faced in ATE design:

[0006] 1. ATE boards are characterized by their numerous layers and large thickness. The circuit design, circuit board design, signal simulation and optimization, and manufacturing of ATE boards differ from those of conventional PCB boards. When facing the chip testing requirements of 112Gbps signals, the following problems will be encountered: a significant increase in the total number of chip pins, a significant decrease in the spacing between chip pins, a significant decrease in the wiring space between chip pins, a significant increase in the number of high-speed chip pins, a significant increase in the performance indicators of high-speed chip pins, the multi-layer and high thickness of the ATE test board having a significant impact on circuit design and performance, and the fiber optic effect having a significant impact on high-speed signals. All of these problems greatly increase the difficulty of designing and testing 112Gbps signal circuits for chips. Poor signal circuit design leading to poor performance will result in low chip testing efficiency or even test failure. Summary of the Invention

[0007] To address the shortcomings of existing methods, this invention solves the problem that existing signal line designs do not consider compensation, which affects the performance of signal lines and the efficiency of chip testing.

[0008] The technical solution adopted in this invention is: a signal wiring compensation impedance control method based on ATE, comprising the following steps:

[0009] Step 1: Obtain the positions of the upper and lower adjacent pins of the signal routing to be drawn in the wiring layer of the chip under test; obtain the center point of the signal routing of the adjacent pins based on the pin spacing and the width of the signal routing.

[0010] In a preferred embodiment of the present invention, the formula for the pin inner distance is:

[0011] d1=(A-2r1) / 2 (1)

[0012] Where A is the pin pitch and r1 is the pad radius of the pin.

[0013] In a preferred embodiment of the present invention, the formula for the pin inner distance is:

[0014] d1=(A-2r2) / 2 (2)

[0015] Where A is the pin spacing and r2 is the via radius of the pin.

[0016] In a preferred embodiment of the present invention, the pin spacing is greater than a safety distance threshold.

[0017] Step 2: Connect the center points of all adjacent pin signal routing lines to draw a wavy signal routing line.

[0018] In a preferred embodiment of the present invention, the pin spacing is set in the rule setting tool of Allegro PCB Designer, and a wavy signal routing is generated using the routing tool.

[0019] Step 3: Perform copper foil compensation on the signal routing of the chip under test's routing layer; then project the signal routing of the chip under test's routing layer onto the adjacent layer of the chip under test, and cut out the copper foil in the adjacent layer of the chip under test according to the projected signal routing.

[0020] In a preferred embodiment of the present invention, copper foil compensation for the signal wiring of the wiring layer of the chip under test includes:

[0021] Step 31: Set the upper and lower compensation values ​​for the signal wiring;

[0022] Step 32: Starting from the vertical point of the signal wiring, set up upper compensation points along the length of the upper compensation amount in the direction of the vertical line on the via. Connect several upper compensation points to obtain the upper compensation line.

[0023] Step 33: Starting from the vertical point on the signal wiring, set the lower compensation point along the length of the lower compensation amount in the direction of the vertical line below the via. Connect the lower compensation points to obtain the lower compensation line.

[0024] Step 34: Cover the area between the upper compensation line and the lower compensation line with copper foil, and set it as an upper and lower compensation rectangular copper foil.

[0025] In a preferred embodiment of the present invention, copper foil avoidance of the signal wiring in the wiring layer of the chip under test includes:

[0026] Using the center point of the via as the center and the radius of the cutout as the circle, draw a circle and remove the copper foil that intersects with the upper and lower compensation rectangular copper foil to obtain the avoidance copper foil signal routing.

[0027] In a preferred embodiment of the present invention, the copper foil cut-out of the adjacent layer of the chip under test according to the projected signal wiring includes:

[0028] Using the center point of the via in the adjacent layer of the chip under test as the center, draw a circle with the radius of the cutout, and remove the copper foil around the via.

[0029] As a preferred embodiment of the present invention, a signal wiring compensation impedance control system based on ATE includes: a memory for storing instructions executable by a processor; and a processor for executing the instructions to implement the signal wiring compensation impedance control method based on ATE.

[0030] As a preferred embodiment of the present invention, a computer-readable medium storing computer program code implements an ATE-based signal wiring compensation impedance control method when executed by a processor.

[0031] The beneficial effects of this invention are:

[0032] 1. Apply copper foil compensation around the signal wiring to effectively improve the problem of high impedance caused by using thinner signal wiring due to insufficient space;

[0033] 2. By calculating the pin spacing and comparing it with the safe distance threshold, interference from signal lines on via pads can be avoided in signal routing.

[0034] 3. Using wavy signal wiring ensures a smoother path, which suppresses reflections generated during high-speed signal transmission. Attached Figure Description

[0035] Figure 1 This is a flowchart of the signal wiring compensation impedance control method based on ATE of the present invention;

[0036] Figure 2 This is a schematic diagram of the wiring layer structure of the chip under test;

[0037] Figure 3(a) and (b) are schematic diagrams of the pins and signal routing of the chip under test with and without pads, respectively.

[0038] Figure 4 This is a schematic diagram of the adjacent layer structure of the chip under test;

[0039] Figure 5 This is a schematic diagram of copper foil compensation for the wiring layer of the chip under test;

[0040] Figure 6 This is an impedance comparison curve between the method of this invention and existing methods;

[0041] Figure 7 This is a side view of the S-parameters of the chip under test using existing methods for eight signals.

[0042] Figure 8 This is a side view of the S-parameters of the eight signals of the chip under test according to the method of the present invention.

[0043] Figure 9 This is an image showing the effect of removing copper foil around vias in adjacent layers of the chip under test. Detailed Implementation

[0044] The present invention will be further described below with reference to the accompanying drawings and embodiments. The drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0045] like Figure 1 As shown, a signal wiring compensation impedance control method based on ATE includes the following steps:

[0046] Vias are used to connect the chip under test (DUT) to the internal layers of the PCB. Compared to controlling the impedance of transmission lines, the impedance of signal vias is more difficult to control, which is a challenge in high-speed circuit board design. Figure 2 As shown, the chip under test has several pins evenly distributed on the wiring layer, arranged in a diamond pattern. This invention mainly focuses on via design for diamond-patterned BGA packages. Compared with conventional rectangular arrangements, diamond-patterned arrangements have higher pin density, smaller chip size, and larger wiring channels, and are typically used for high-speed signal chips.

[0047] The pin pitch of a BGA package is an important indicator of its size. The smaller the pin pitch, the closer the pins of two BGA packages are, and the more difficult the via design becomes. In this embodiment, via design is performed for a pin pitch of 0.4-0.45mm for the chip under test. The same applies to BGA packages with pin pitches greater than 0.45mm.

[0048] The thickness of the chip under test is a crucial factor limiting via design. The greater the thickness of the chip under test and the more layers it has, the more difficult the via design becomes. This invention is designed for via design of a 60-layer chip under test with a thickness of 6mm. Designs with a thickness and number of layers not exceeding this are also applicable.

[0049] Step 1: Obtain the positions of the upper and lower adjacent pins of the signal routing to be drawn in the wiring layer of the chip under test; obtain the center point of the signal routing of the adjacent pins based on the pin spacing and the width of the signal routing.

[0050] like Figure 2 The chip under test (DUT) has several pins evenly spaced in its wiring layer. The wiring layer has no copper foil. The following explanation uses the adjacent pins 1 to 6 above and below the signal trace as an example. Figure 3 (a) Taking horizontal signal routing as an example, the pin spacing is the distance between the center points of the vias of two adjacent pins; the pin spacing of vertical signal routing is the distance between two adjacent pins.

[0051] For example, if the pin spacing A = 0.6mm; the pin pad radius r1 is 0.15mm; the pin via radius r2 is 0.075mm; and the signal trace width d is 0.076mm; then the distance between the center point of the signal trace of an adjacent pin and the inner edge of the adjacent pin is the pin inner distance d1, and the formula is:

[0052] d1=(A-2r1) / 2 (1)

[0053] or

[0054] d1=(A-2r2) / 2 (2)

[0055] The pin spacing must be greater than the safety distance. The safety distance is set to meet production requirements while ensuring signal impedance. If the safety distance is not met, the signal routing will interfere with the signal lines of the via pads, which will not meet the chip design specifications.

[0056] Taking a safety distance threshold of 0.1mm as an example, with pin spacing A = 0.6mm, the safety distance formula is = d1 - d / 2 = (0.6 - 2 * 0.15) / 2 - (0.076 / 2) = 0.112mm. 0.112 > 0.1, thus meeting the safety distance requirement. When the pin spacing is small, pads exist, and the safety distance is insufficient, it is necessary to first remove the pads, such as... Figure 3As shown in (b), the pin spacing A = 0.45 mm, the safety distance = (0.45 - 2 * 0.15) / 2 - (0.076 / 2) = 0.037, 0.037 < 0.1, which does not meet the safety distance requirement. Therefore, the pads are removed first. The safety distance after removing the pads = (0.45 - 2 * 0.075) / 2 - (0.076 / 2) = 0.112 mm, 0.112 > 0.1, which meets the safety distance requirement.

[0057] Step 2: Connect the center points of all adjacent pin signal routing lines to draw a wavy signal routing line.

[0058] Drawing signal routing involves using Allegro PCB Designer software, setting pin spacing in the rule setting tool, and automatically generating wavy signal routing using the routing tool.

[0059] Using wavy signal wiring ensures a smoother path, which suppresses reflections during high-speed signal transmission.

[0060] Step 3: Perform copper foil compensation and avoidance on the signal routing of the chip under test; remove copper foil from adjacent layers of the chip under test;

[0061] like Figure 4 The adjacent layers of the chip under test (DUT) are located above and below the wiring layer of the DUT. The wiring layer of the DUT and the two adjacent layers of the chip under test together form a pair of DUTs. Several pairs of DUTs constitute a board under test. For example, a 60-layer board under test consists of 20 pairs of DUTs. The adjacent layers of the DUTs are composed of vias and copper foil that penetrate the wiring layer of the DUTs. The copper foil covers the entire adjacent layer of the DUTs. It is necessary to remove the copper foil around the vias of the adjacent layers of the DUTs and not cover the projected signal wiring. The projected signal wiring is the orthographic projection of the signal wiring of the wiring layer of the DUTs onto the adjacent layers of the DUTs.

[0062] like Figure 5 As shown, the upper and lower compensation values ​​of the signal wiring are set. The lengths of the upper and lower compensation values ​​can be set to the same value, and the lengths of the upper and lower compensation values ​​are greater than the width of the signal wiring.

[0063] The vertical direction of the upper and lower edges of the chip under test is defined by starting from the center point of the via and ending at the upper edge of the chip under test. Conversely, the vertical direction of the lower edge of the chip under test is defined by ending at the lower edge of the chip under test.

[0064] The intersection of the vertical line on the via and the bottom edge of the signal routing is set as the lower vertical point of the signal routing. Starting from the lower vertical point of the signal routing, the upper compensation point is set along the length of the upper compensation amount in the direction of the vertical line on the via.

[0065] Connect the several compensation points to obtain the compensation line;

[0066] Similarly, the intersection of the lower vertical line of the via and the upper edge of the signal routing is set as the upper vertical point of the signal routing. Starting from the upper vertical point of the signal routing, the lower compensation point is set along the length of the lower compensation amount in the direction of the lower vertical line of the via.

[0067] Connect the several lower compensation points to obtain the lower compensation line;

[0068] Cover the area between the upper and lower compensation lines of the wiring layer of the chip under test with copper foil, and set it as an upper and lower compensation rectangular copper foil.

[0069] The cutout radius is the distance between the center point of the via and the lower vertical point of the signal wiring, or the distance between the center point of the via and the upper vertical point of the signal wiring.

[0070] Using the center point of the via as the center and the radius of the cutout as the circle, draw a circle and remove the copper foil that intersects with the upper and lower compensation rectangular copper foils to obtain the copper foil avoidance signal routing; such as Figure 5 As shown, these are two avoidance copper foil signal traces on the wiring layer of the chip under test.

[0071] Due to the limited space between vias, the width of signal traces cannot fully meet the impedance requirements. Overly thin traces will lead to increased impedance, which in turn will increase signal insertion loss. Applying copper foil compensation around the signal traces can effectively improve the problem of high impedance caused by using thinner traces due to insufficient space.

[0072] In addition, the adjacent layers of the chip under test are covered with copper foil except for the vias. Using the center point of the via of the adjacent layer of the chip under test as the center, draw a circle with the radius of the cutout and remove the copper foil around the via.

[0073] like Figure 9The image shows the effect of removing the copper foil around vias in the adjacent layer of the chip under test (DUT). High-speed signal transmission differs from basic electrical transmission in physics. In basic electrical transmission, the "electricity" flows in a signal line, forming a current. High-speed signal transmission can be simply understood as the signal line, the adjacent layer of the DUT, and the medium between them forming a structure that can accommodate energy. Therefore, to ensure excellent transmission quality of high-speed signals, the signal routing must first be designed, and the adjacent layer of the signal routing should be designed as a reference plane layer. Typically, the entire reference plane layer is made of copper foil and grounded. The position of the signal routing projected onto the reference plane must be a complete copper foil without any cut-outs. Otherwise, the energy transmission structure will be incomplete, affecting the signal transmission quality. In actual design, there may be many vias around the signal routing. These vias are not necessarily grounded. The positions of these vias on the reference plane layer need to be cut out. Otherwise, these ungrounded vias will short-circuit to ground. In this case, cut-out processing is required, but the position of the signal routing projected onto the reference plane should not be cut out. If it is, the transmission performance will definitely be affected.

[0074] Experimental procedure:

[0075] Using the compensated copper foil signal wiring method of the present invention, interconnection of high-speed signals transmitting 112Gbps can be achieved in the case of a small size of 0.45mm for a diamond-arranged BGA package.

[0076] like Figure 6 Green represents the impedance performance curve of the chip under test before compensation, and blue represents the impedance performance curve of the chip under test after compensation. By optimizing the design of signal vias, the vias can still maintain high impedance performance on ATE test boards with high board thickness and multiple layers. This achieves the effect of improving the internal signal impedance of BGA packages with minimal impact on existing design methods and processing capabilities.

[0077] like Figure 7 and 8 The comparison of the S-parameter performance of the chip under test outputting eight signals between the existing method and the method of the present invention shows that the method of the present invention can adjust the position of the resonant point, thereby improving the linearity of the signal insertion loss curve at the fundamental frequency of 112Gbps and the position of 28GHz.

[0078] This invention provides a 112Gbps signal routing design method applicable to ATE test boards with high layer counts and high thickness. While meeting the requirements for high-performance 112Gbps signal testing, it significantly improves signal impedance, signal insertion loss, and signal consistency. It also significantly enhances chip testing speed and efficiency, further reducing chip testing time and single-chip testing costs. This has a significant impact on reducing chip R&D costs and accelerating chip time-to-market, and has high economic value.

[0079] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. An ATE-based signal wiring compensation impedance control method, characterized by, The method comprises the following steps: Step 1: obtaining the upper and lower adjacent pin positions of the signal wiring to be drawn in the wiring layer of the chip to be tested; obtaining the center points of the signal wiring of the adjacent pins according to the pin inner distance and the width of the signal wiring; Step 2: connecting the center points of the signal wiring of all adjacent pins to draw a wavy signal wiring; Step 3: performing copper foil compensation and avoidance on the signal wiring of the wiring layer of the chip to be tested; Performing copper foil hollowing on the adjacent layers of the chip to be tested; The copper foil compensation on the signal wiring of the wiring layer of the chip to be tested comprises: Step 31: setting the upper compensation amount and the lower compensation amount of the signal wiring; Step 32: setting the upper compensation points along the length of the upper compensation amount in the direction of the upper vertical line of the via from the lower vertical point of the signal wiring as the starting point, connecting the upper compensation points to obtain the upper compensation line; Step 33: setting the lower compensation points along the length of the lower compensation amount in the direction of the lower vertical line of the via from the upper vertical point of the signal wiring as the starting point, connecting the lower compensation points to obtain the lower compensation line; Step 34: covering the area between the upper compensation line and the lower compensation line with copper foil to set the upper and lower compensation rectangular copper foil; The copper foil avoidance on the signal wiring of the wiring layer of the chip to be tested comprises: Taking the via center point as the center of a circle and drawing a circle with the hollowing radius, removing the copper foil intersecting with the upper and lower compensation rectangular copper foil to obtain the avoidance copper foil signal wiring; The copper foil hollowing on the adjacent layers of the chip to be tested according to the projected signal wiring comprises: Taking the via center point of the adjacent layers of the chip to be tested as the center of a circle and drawing a circle with the hollowing radius, removing the copper foil around the via.

2. The ATE-based signal-wiring-compensated impedance control method of claim 1, wherein, The formula of the pin inner distance is: d1= (A-2r1) / 2 (1) Wherein, A is the pin pitch, and r1 is the pad radius of the pin.

3. The ATE-based signal-wiring-compensated impedance control method of claim 1, wherein, The formula of the pin inner distance is: d1= (A-2r2) / 2 (2) Wherein, A is the pin pitch, and r2 is the via radius of the pin.

4. The ATE-based signal-wiring compensation impedance control method according to claim 2 or 3, characterized by, The pin inner distance is greater than the threshold value of the safety distance.

5. The ATE-based signal-wiring-compensated impedance control method of claim 1, wherein, The pin inner distance is set in the rule setting tool of allegro pcb designer, and the wavy signal wiring is generated by using the wiring tool.

6. An ATE-based signal routing compensation impedance control system, characterized by, The method comprises: a memory for storing instructions executable by a processor; a processor for executing the instructions to implement the ATE-based signal wiring compensation impedance control method according to any one of claims 1-5.

7. A computer readable medium having stored thereon a computer program code, characterized in that, The computer program code implements the ATE-based signal wiring compensation impedance control method according to any one of claims 1-5 when executed by a processor. The computer program code implements the ATE-based signal wiring compensation impedance control method according to any one of claims 1-5 when executed by a processor.

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