Semiconductor structure, method for manufacturing semiconductor structure and image sensor

Abstract

The embodiment of the present application provides a semiconductor structure, a method for manufacturing the semiconductor structure, and an image sensor, wherein the semiconductor structure includes: a substrate and an optoelectronic functional layer; the optoelectronic functional layer includes a plurality of N-type doping regions and a P-type doping region; the P-type doping region is located in an isolation groove formed between adjacent N-type doping regions; the N-type doping region includes a first N-type doping layer, a second N-type doping layer, and a third N-type doping layer; the second N-type doping layer is located between the first N-type doping layer and the third N-type doping layer, and the relative atomic mass of the impurity element doped in the second N-type doping layer is the largest; the P-type doping region has a first P-type doping layer, a second P-type doping layer, and a third P-type doping layer corresponding to the three N-type doping layers respectively; the isolation groove has a groove extension direction and a width direction perpendicular to the groove extension direction, and the width of the second P-type doping layer along the width direction is the smallest. Through the embodiment of the present application, the imaging quality of the image sensor is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and specifically to a semiconductor structure, a method for manufacturing a semiconductor structure, and an image sensor. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) image sensors are widely used in consumer electronics, security monitoring, assisted driving, medical equipment and other fields due to their low cost, anti-blurring, and flexible access. Among them, the BackSide Illumination (BSI) CMOS image sensor changes the incident direction of light, allowing light to directly illuminate the photodiode, improving the device sensitivity and light utilization, and is often used in fields that require high pixel performance of image sensors.

[0003] However, in the existing BSI CMOS image sensor process, photodiodes (PDs) are usually formed using high-energy ion implantation. As the process size shrinks, high-energy ion implantation may damage the BSI CMOS image sensor and cause cross talk between pixels, reducing the device's imaging quality and reliability. Summary of the invention

[0004] In view of this, multiple embodiments of the present application provide a semiconductor structure, a method for manufacturing the semiconductor structure, and an image sensor to improve the imaging quality and reliability of a BSI CMOS image sensor.

[0005] In one aspect, an embodiment of the present application provides a semiconductor structure, comprising: a substrate; a photoelectric functional layer for realizing photoelectric signal conversion based on the photoelectric effect; the photoelectric functional layer comprises a plurality of N-type doping regions and P-type doping regions; an isolation groove is formed between adjacent N-type doping regions, and the P-type doping region is located in the isolation groove; wherein the N-type doping region comprises a first N-type doping layer, a second N-type doping layer and a third N-type doping layer arranged in a stacked manner; the second N-type doping layer is located between the first N-type doping layer and the third N-type doping layer, and Among the two N-type doping layers and the third N-type doping layer, the relative atomic mass of the impurity elements doped in the second N-type doping layer is the largest; the P-type doping region comprises a first P-type doping layer corresponding to the first N-type doping layer, a second P-type doping layer corresponding to the second N-type doping layer, and a third P-type doping layer corresponding to the third N-type doping layer; the isolation groove comprises a groove extension direction and a width direction perpendicular to the groove extension direction, and among the first P-type doping layer, the second P-type doping layer and the third P-type doping layer, the width of the second P-type doping layer along the width direction is the smallest.

[0006] Optionally, the impurity element doped into the second N-type doping layer is antimony.

[0007] Optionally, the impurity element doped into the first N-type doping layer is arsenic, and the impurity element doped into the third N-type doping layer is phosphorus.

[0008] Optionally, the impurity element doped into the first P-type doping layer is indium, the impurity element doped into the second P-type doping layer is gallium, and the impurity element doped into the third P-type doping layer is boron.

[0009] Optionally, the width of the first P-type doped layer along the width direction is 1.5 to 2.5 times the width of the second P-type doped layer along the width direction; the width of the third P-type doped layer along the width direction is 1.5 to 2.5 times the width of the second P-type doped layer along the width direction.

[0010] Optionally, the width of the photoelectric functional layer along the width direction is 4 to 5 times the width of the P-type doping region along the width direction.

[0011] Optionally, a grid structure for separating filter structures of different colors is provided on a surface of the P-type doped region away from the substrate; and a width of the grid structure along the width direction is smaller than a width of the third P-type doped layer along the width direction.

[0012] Optionally, the width of the grid structure decreases in a direction away from the substrate.

[0013] Optionally, the grid structure includes a first grid layer, a second grid layer and a third grid layer which are stacked, wherein the material of the first grid layer is tantalum oxide, the material of the second grid layer is aluminum, and the material of the third grid layer is titanium nitride.

[0014] In another aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method comprising: providing a substrate; preparing a photoelectric functional layer on the substrate; wherein the photoelectric functional layer comprises a plurality of N-type doping regions and a P-type doping region; an isolation groove is formed between adjacent N-type doping regions, and the P-type doping region is located in the isolation groove; the N-type doping region comprises a first N-type doping layer, a second N-type doping layer and a third N-type doping layer arranged in a stacked manner; the second N-type doping layer is located between the first N-type doping layer and the third N-type doping layer, and the impurity element doped in the second N-type doping layer The relative atomic mass of the impurity elements doped in the first N-type doping layer and the third N-type doping layer is greater than the relative atomic mass of the impurity elements doped in the first N-type doping layer and the third N-type doping layer; the P-type doping region comprises a first P-type doping layer corresponding to the first N-type doping layer, a second P-type doping layer corresponding to the second N-type doping layer, and a third P-type doping layer corresponding to the third N-type doping layer; wherein the isolation groove has a groove extension direction and a width direction perpendicular to the groove extension direction, and among the first P-type doping layer, the second P-type doping layer has the smallest width along the width direction.

[0015] Optionally, the step of preparing the optoelectronic functional layer on the substrate includes: forming a first N-type doping layer on the substrate; etching the first N-type doping layer to form a first isolation groove; forming a first P-type doping layer in the first isolation groove; forming a second N-type doping layer on the first N-type doping layer; wherein the relative atomic mass of the impurity element doped in the second N-type doping layer is greater than the relative atomic mass of the impurity element doped in the first N-type doping layer; etching the second N-type doping layer corresponding to the position of the first isolation groove to form a second isolation groove; wherein the second isolation groove has a groove extension direction, and the second isolation groove is parallel to the groove extension direction. The width in the width direction perpendicular to the extension direction is smaller than the width of the first isolation groove along the width direction; a second P-type doping layer is formed in the second isolation groove; a third N-type doping layer is formed on the second N-type doping layer; wherein the relative atomic mass of the impurity element doped in the third N-type doping layer is smaller than the relative atomic mass of the impurity element doped in the second N-type doping layer; the third N-type doping layer is etched at a position corresponding to the second isolation groove to form a third isolation groove; wherein the width of the third isolation groove along the width direction is greater than the width of the second isolation groove along the width direction; a third P-type doping layer is formed in the third isolation groove.

[0016] Optionally, the method further includes: forming a first grid layer, a second grid layer and a third grid layer in sequence above the third N-type doped layer; wherein the material of the first grid layer is tantalum oxide, the material of the second grid layer is aluminum, and the material of the third grid layer is titanium nitride; etching the first grid layer, the second grid layer and the third grid layer to obtain a plurality of grid structures; wherein the position of the grid structure corresponds to the third P-type doped layer, the width of the grid structure along the width direction is smaller than the width of the third P-type doped layer along the width direction, and the width of the grid structure decreases in a direction away from the substrate.

[0017] In another aspect, an embodiment of the present application provides an image sensor, which includes the semiconductor structure described in the above embodiment or a semiconductor structure manufactured by the method for manufacturing the semiconductor structure described in the above embodiment.

[0018] In multiple embodiments provided in the present application, a multi-layer photoelectric functional layer is formed on a substrate, and the photoelectric functional layer includes multiple N-type doping regions and P-type doping regions, and isolation grooves are set between adjacent N-type doping regions to enhance the isolation between pixels. The structure of the P-type doping region is set as follows: among the multiple P-type doping layers corresponding to the multiple N-type doping layers, the width of the P-type doping layer corresponding to the N-type doping layer with the largest relative atomic mass of the impurity element doped is the narrowest. The unexpected effect is that on the one hand, the damage to the device caused by ion implantation is reduced, thereby improving the reliability of the image sensor; on the other hand, crosstalk and dark current between adjacent pixels are reduced, while the photoelectric effect of the photodiode is improved, thereby improving the imaging quality of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor structure provided for one embodiment of the present application.

[0021] Figure 2 A schematic diagram of a semiconductor substrate prepared by a front end of line (FEOL) process according to an embodiment of the present application.

[0022] Figure 3 For Figure 2 Schematic diagram of the specific structure of the protective layer and the dielectric layer.

[0023] Figure 4 A schematic flow chart of the steps of providing a substrate is provided for one embodiment of the present application.

[0024] Figure 5 A schematic diagram of forming an isolation layer in a semiconductor substrate is provided according to an embodiment of the present application.

[0025] Figure 6 A schematic diagram of a substrate provided for one embodiment of the present application.

[0026] Figure 7 A schematic flow chart of the steps of preparing a photovoltaic functional layer on a substrate is provided for one embodiment of the present application.

[0027] Figure 8 A schematic diagram of forming a first N-type doping layer on a substrate is provided for one embodiment of the present application.

[0028] Fig. 9 A schematic diagram of etching a first N-type doped layer to form a first isolation trench is provided for one embodiment of the present application.

[0029] Fig.10 A schematic diagram of forming a first P-type doping layer in a first isolation trench is provided for one embodiment of the present application.

[0030] Fig.11 A schematic diagram of forming a second N-type doping layer on a first N-type doping layer is provided for one embodiment of the present application.

[0031] Fig.12 A schematic diagram of etching the second N-type doped layer to form a second isolation trench at a position corresponding to the first isolation trench provided in one embodiment of the present application.

[0032] Fig.13 A schematic diagram of forming a second P-type doping layer in a second isolation trench is provided for one embodiment of the present application.

[0033] Fig.14 A schematic diagram of forming a third N-type doping layer on a second N-type doping layer is provided for one embodiment of the present application.

[0034] Fig.15 A schematic diagram of etching the third N-type doped layer to form a third isolation trench at a position corresponding to the second isolation trench provided in one embodiment of the present application.

[0035] Fig.16 A schematic diagram of forming a third P-type doping layer in a third isolation trench is provided for one embodiment of the present application.

[0036] Fig.17A schematic diagram of sequentially forming a first grid layer, a second grid layer, and a third grid layer on a third N-type doped layer is provided for one embodiment of the present application.

[0037] Fig.18 A schematic diagram of etching a first grid layer, a second grid layer, and a third grid layer to obtain multiple grid structures is provided for one embodiment of the present application.

[0038] Fig.19 A schematic diagram of forming a filter structure between adjacent grid structures is provided for one embodiment of the present application.

[0039] Structure number description

[0040] 100, base; 101, substrate; 1011, first surface; 1012, second surface; 102, isolation layer; 103, protection layer; 1031, gate dielectric layer; 1032, etch stop layer; 104, dielectric layer; 105, shallow trench isolation structure; 106, gate structure; 107, metal connection structure; 1071, connection column; 1072, metal layer; 110, first N-type doping layer; 111, first isolation layer Groove; 112, first P-type doped layer; 120, second N-type doped layer; 121, second isolation groove; 122, second P-type doped layer; 130, third N-type doped layer; 131, third isolation groove; 132, third P-type doped layer; 140, grid structure; 141, first grid layer; 142, second grid layer; 143, third grid layer; 150, filter structure; 160, N-type doped region; 170, P-type doped region. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0042] The drawings provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complicated.

[0043] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features.

[0044] In the related art, in the process of manufacturing BSI CMOS image sensors, a high-energy ion implantation process is usually used in the front-end process to prepare photodiodes. During the ion implantation process, a large number of high-speed moving ions collide with the semiconductor lattice, resulting in a large number of point defects, dislocations and other lattice damages in the area near the surface of the semiconductor substrate. These lattice damages may affect the transport of photogenerated carriers, reduce the carrier mobility and quantum efficiency of the photodiode, increase dark current, and lead to enhanced crosstalk between pixels, resulting in blurred imaging of the image sensor.

[0045] In addition, the lattice damage effect is related to the ion implantation parameters such as the dose and energy of the ion implantation. The degree of lattice damage will increase with the increase of dose and ion energy. In fact, when the energy of ion implantation is too large, the lattice structure close to the surface of the semiconductor substrate within the ion range will be completely destroyed and become amorphous, resulting in the degradation of photodiode performance or even failure, and the reliability of image sensors will be reduced.

[0046] Therefore, it is necessary to provide a semiconductor structure, by forming a multi-layer photoelectric functional layer on a substrate, and the photoelectric functional layer includes multiple N-type doping regions and P-type doping regions, and setting isolation grooves between adjacent N-type doping regions to enhance the isolation between pixels, and setting the structure of the P-type doping region as follows: among the multiple P-type doping layers corresponding to the multiple N-type doping layers, the width of the P-type doping layer corresponding to the N-type doping layer with the largest relative atomic mass of the impurity element doped is the narrowest, thereby reducing the damage to the device caused by ion implantation to improve the reliability of the image sensor, and reducing the crosstalk and dark current between adjacent pixels on the other hand, while improving the photoelectric effect of the photodiode to improve the imaging quality of the image sensor.

[0047] See also Figure 1 An embodiment of the present application provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure may include the following steps.

[0048] S110: providing a substrate.

[0049] See also Figure 2 and Figure 3 In this embodiment, the substrate 100 can be obtained by further processing a semiconductor substrate prepared by a previous process.

[0050] The semiconductor substrate prepared by FEOL may include a substrate 101, a protective layer 103, a dielectric layer 104, and a plurality of shallow trench isolation structures 105. Among them, a plurality of gate structures 106 are arranged at intervals in the protective layer 103, and a plurality of metal connection structures 107 are arranged at intervals in the dielectric layer 104. The specific structures are as follows:

[0051] The substrate 101 may be made of semiconductor material, insulating material, conductive material or any combination thereof. For example, the substrate 101 may be made of materials such as silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), etc. The substrate 101 may be a single-layer structure or a multi-layer structure. In this embodiment, a silicon wafer is used as the substrate 101. Specifically, the thickness of the substrate 101 may be 2.5um to 3.5um, for example, 2.6um, 2.8um, 3um, 3.3um, etc. The substrate 101 has a first surface 1011 and a second surface 1012 opposite to each other.

[0052] A plurality of shallow trench isolation structures 105 are formed in the substrate 101. The shallow trench isolation structure 105 may extend from the second surface 1012 to the first surface 1011. The distance between the shallow trench isolation structure 105 and the first surface 1011 is less than the thickness of the substrate 101. The dielectric material filled in the shallow trench isolation structure 105 may be an oxide to isolate electrical crosstalk between different active regions and improve the imaging quality of the image sensor. The shallow trench isolation structure 105 may be formed by any method in the relevant technology, such as wet etching, dry etching or ion implantation, which will not be described in detail here.

[0053] After the plurality of shallow trench isolation structures 105 are formed, a protective layer 103, a plurality of gate structures 106, a dielectric layer 104 and a plurality of metal connection structures 107 may be formed on the second surface 1012, wherein the protective layer 103 may include a gate dielectric layer 1031 and an etch stop layer 1032. The specific formation process is as follows:

[0054] After the multiple shallow trench isolation structures 105 are formed, a gate dielectric layer 1031 for isolation and threshold voltage adjustment may be formed on the second surface 1012. Specifically, the gate dielectric layer 1031 may be formed on the second surface 1012 by thermal oxidation or chemical vapor deposition (CVD). The gate dielectric layer 1031 may be made of silicon dioxide or a low dielectric constant material.

[0055] After the gate dielectric layer 1031 is formed, a plurality of gate structures 106 distributed at intervals may be formed on the surface of the gate dielectric layer 1031. Specifically, the plurality of gate structures 106 may be formed by depositing polysilicon using methods such as CVD.

[0056] After the multiple gate structures 106 are formed, an etch stop layer 1032 may be formed between the surface of the gate dielectric layer 1031 and the multiple gate structures 106. Specifically, the etch stop layer 1032 may be multiple layers, for example, two layers. To reduce the risk of cracks in the etch stop layer 1032 causing failure of the metal connection structure, the etch stop layer 1032 may be made of materials such as silicon oxide, silicon carbonitride or silicon nitride. The etch stop layer 1032 may be formed by methods such as CVD or physical vapor deposition (PVD).

[0057] After forming the etch stop layer 1032, a dielectric layer 104 is formed on the etch stop layer 1032. Specifically, the dielectric layer 104 may be a silicon oxide layer or other low dielectric constant material layer, and may be formed by CVD or PVD to improve the reliability of the metal connection structure.

[0058] Subsequently, the dielectric layer 104 is etched to form a plurality of openings, and a conductive material is deposited in the openings, such as titanium / titanium nitride and metal tungsten, to form a plurality of connecting pillars 1071. Next, a metal layer 1072 is formed on the dielectric layer 104, and the metal layer 1072 and the connecting pillars 1071 form a metal connection structure 107. In some embodiments, two or more metal layers 1072 may be provided, and adjacent metal layers 1072 are isolated by the dielectric layer 104 and connected by the connecting pillars 1071.

[0059] The present application does not limit the specific thickness of the gate dielectric layer 1031, the etch stop layer 1032 and the dielectric layer 104, nor does it limit the specific size of the gate structure 106 and the metal connection structure 107. During the manufacturing process, the above structural parameters can be selected according to the process requirements.

[0060] After forming a dielectric layer 104 and a plurality of metal connection structures 107 on the second surface 1012 of the substrate 101 , a carrier wafer is bonded, and the bonded wafer is flipped and the substrate 101 is thinned to the first surface 1011 of the substrate 101 to form a semiconductor base.

[0061] See also Figures 4 to 6 In this embodiment, the base 100 may include a substrate 101, an isolation layer 102, a protection layer 103, a dielectric layer 104, a plurality of shallow trench isolation structures 105, a plurality of gate structures 106, and a plurality of metal connection structures 107. Specifically, the step of providing the base 100 may include the following steps.

[0062] S111: forming an isolation layer in the substrate of the semiconductor substrate. Specifically, the isolation layer 102 may be formed at one end of the shallow trench isolation structure 105 away from the protective layer 103. Accordingly, the shallow trench isolation structure 105 extends from the surface of the substrate 101 close to the protective layer 103 to the isolation layer 102. For example, ionized metal plasma (IMP) may be used to implant to form the isolation layer 102, and the implanted ions may be boron ions.

[0063] S112: After the isolation layer is formed, the substrate on the side of the isolation layer away from the protective layer is removed to expose the surface of the isolation layer away from the protective layer. Specifically, a planarization process such as chemical mechanical polishing (CMP) can be used to remove the substrate 101 that does not include the shallow trench isolation structure 105.

[0064] S120: preparing a photoelectric functional layer on a substrate.

[0065] In order to reduce the damage to the device caused by ion implantation, a photoelectric functional layer for realizing photoelectric signal conversion based on the photoelectric effect can be directly formed on the surface of the substrate 100. At the same time, in order to reduce the crosstalk between pixels, the photoelectric functional layer can be set as a multilayer structure with different materials in each layer to cover a wider spectral range, reduce the propagation distance of light when passing through the element, and thus reduce the light leakage between adjacent pixels.

[0066] In this example, see Figures 7 to 15 The step of preparing the optoelectronic functional layer on the substrate 100 may include the following steps.

[0067] S121: forming a first N-type doping layer on the substrate.

[0068] In order to reduce the lateral movement of carriers between adjacent pixels, an N-type doping region 160 and a P-type doping region 170 can be formed in the optoelectronic functional layer, thereby utilizing the built-in electric field between the PN junctions to control the movement of carriers and reduce the adverse effects of crosstalk between pixels on the imaging quality of the image sensor.

[0069] See also Figure 8 . In this embodiment, a first N-type doping layer 110 may be formed on the surface exposed by the isolation layer 102. Specifically, to form N-type doping, the impurity element doped in the first N-type doping layer 110 may be one of the elements of Group V, for example, arsenic (As). Accordingly, the material of the first N-type doping layer 110 may be silicon doped with arsenic. The process that may be used to form the first N-type doping layer 110 may be selective epitaxial deposition. The thickness of the first N-type doping layer 110 may range from 90nm to 110nm. In this embodiment, the thickness of the first N-type doping layer 110 may be 92nm, 95nm, 98nm, 100nm or 104nm, etc.

[0070] S122: Etching the first N-type doping layer to form a first isolation trench.

[0071] See also Fig. 9 . After the first N-type doping layer 110 is formed, the position of the first isolation groove 111 can be defined in the first N-type doping layer 110 and the first isolation groove 111 can be etched to form the first isolation groove 111, thereby forming physical isolation between adjacent pixels. Specifically, the position of the first isolation groove 111 can be defined according to the position of the shallow trench isolation structure 105, that is, the first isolation groove 111 and the projection center line of the shallow trench isolation structure 105 on the first N-type doping layer 110 can coincide. After the position of the first isolation groove 111 is determined, the first isolation groove 111 can be formed by photolithography and dry etching. Specifically, the position of the first isolation groove 111 can be defined by using a patterned photoresist layer as a mask, or by using a mask plate, and then the first isolation groove 111 is formed by using dry etching, wet etching, or a combination of dry etching and wet etching. In this embodiment, dry etching is used to accurately control the formation of the first isolation groove 111.

[0072] S123: forming a first P-type doping layer in the first isolation trench.

[0073] See also Fig.10. In order to fill the first isolation groove 111 with material to form P-type doping, the impurity element doped in the first P-type doping layer 112 may be one of the elements of Group III, for example, indium. Accordingly, the material of the first P-type doping layer 112 may be silicon doped with indium. The process that may be used to form the first P-type doping layer 112 is similar to the process that may be used to form the first N-type doping layer 110 as described above. In this embodiment, after depositing the first P-type doping layer 112, a planarization process such as CMP is used to perform a planarization treatment so that the height of the first P-type doping layer 112 protruding from the isolation layer 102 away from the surface of the isolation layer 102 is equal to the height of the first N-type doping layer 110 protruding from the surface of the isolation layer 102 away from the isolation layer 102.

[0074] S124: forming a second N-type doping layer on the first N-type doping layer.

[0075] See also Fig.11 . The relative atomic mass of the impurity element doped in the second N-type doping layer 120 is greater than the relative atomic mass of the impurity element doped in the first N-type doping layer 110. The impurity element doped in the second N-type doping layer 120 may be one of the elements of Group V, for example, antimony. Accordingly, the material of the second N-type doping layer 120 may be silicon doped with antimony. Since the relative atomic mass of the antimony element is relatively large, the second N-type doping layer 120 formed by it can provide more electrons, and the electron diffusion movement is relatively strong, so that the electric field strength of the built-in electric field in the correspondingly formed PN junction is stronger, so that the free carrier movement can be better controlled, the crosstalk between pixels can be reduced, and the photoelectric effect of the PD can be improved. To further enhance the photoelectric effect of the PD, the thickness of the second N-type doping layer 120 in a direction away from the first N-type doping layer 110 may be greater than the thickness of the first N-type doping layer 110 in a direction away from the substrate 100. Specifically, the thickness of the second N-type doping layer 120 may range from 500 nm to 600 nm. In the present embodiment, the thickness of the second N-type doping layer 120 may be 510 nm, 515 nm, 530 nm, 550 nm or 580 nm, etc.

[0076] S125: etching the second N-type doping layer at a position corresponding to the first isolation groove to form a second isolation groove.

[0077] See also Fig.12 The second isolation trench 121 has a trench extending direction.

[0078] S126: forming a second P-type doping layer in the second isolation trench.

[0079] See also Fig.13 The impurity element doped in the second P-type doping layer 122 may be one of the elements of Group III, for example, gallium. Accordingly, the material of the second P-type doping layer 122 may be silicon doped with gallium.

[0080] In order to reduce the weakening effect that the hole diffusion in the second P-type doping layer 122 may have on the electron diffusion in the second N-type doping layer 120, maintain the intensity of the electron diffusion movement in the second N-type doping layer 120, reduce the crosstalk between pixels, and enhance the photoelectric effect of the PD, in this embodiment, the width of the second isolation groove 121 along the width direction perpendicular to the groove extension direction is smaller than the width of the first isolation groove 111 along the width direction, so as to reduce the volume of the area occupied by the second P-type doping layer 122 and reduce the concentration of P-type doping in the PN junction formed by the second P-type doping layer 122 and the second N-type doping layer 120. Accordingly, the width of the formed second P-type doping layer along the width direction is smaller than the width of the first P-type doping layer along the width direction, and the width of the first P-type doping layer along the width direction can be 1.5 to 2.5 times the width of the second P-type doping layer along the width direction. In this embodiment, the width of the first P-type doping layer along the width direction can be twice the width of the second P-type doping layer along the width direction. At the same time, an element with a relatively large atomic mass in the group III elements can be selected as the impurity element doped into the second P-type doping layer 122 to increase the difficulty of hole diffusion in the second P-type doping layer 122 .

[0081] S127: forming a third N-type doping layer on the second N-type doping layer.

[0082] See also Fig.14 . The relative atomic mass of the impurity element doped in the third N-type doping layer 130 is less than the relative atomic mass of the impurity element doped in the second N-type doping layer 120. The impurity element doped in the third N-type doping layer 130 may be one of the elements of Group V, for example, phosphorus. Accordingly, the material of the third N-type doping layer 130 may be silicon doped with phosphorus. The thickness of the third N-type doping layer 130 in a direction away from the second N-type doping layer 120 may range from 90 nm to 110 nm. In the present embodiment, the thickness of the third N-type doping layer 130 may be 92 nm, 95 nm, 98 nm, 100 nm or 104 nm, etc.

[0083] S128: etching the third N-type doping layer at a position corresponding to the second isolation groove to form a third isolation groove.

[0084] See also Fig.15 The width of the third isolation trench 131 along the width direction is greater than the width of the second isolation trench 121 along the width direction.

[0085] S129: forming a third P-type doping layer in the third isolation trench.

[0086] See also Fig.16. The impurity element doped in the third P-type doping layer 132 may be one of the elements of Group III, for example, boron. Accordingly, the material of the third P-type doping layer 132 may be silicon doped with boron. The width of the third P-type doping layer 132 along the width direction may be 1.5 to 2.5 times the width of the second P-type doping layer 122 along the width direction. In this embodiment, the width of the third P-type doping layer 132 along the width direction may be twice the width of the second P-type doping layer 122 along the width direction.

[0087] In this embodiment, the first P-type doping layer 112, the second P-type doping layer 122, and the third P-type doping layer 132 may constitute a P-type doping region 170. The width of the photoelectric functional layer along the width direction may be 4 to 5 times the width of the P-type doping region 170 along the width direction. For example, the width of the photoelectric functional layer along the width direction may be 4.5 times the width of the P-type doping region 170 along the width direction.

[0088] The process of forming the second N-type doping layer 120 on the first N-type doping layer 110 and the process of forming the third N-type doping layer 130 on the second N-type doping layer 120 are similar to the process of forming the first N-type doping layer 110 on the substrate 100. The process of etching the second N-type doping layer 120 to form the second isolation groove 121 at the position corresponding to the first isolation groove 111 and the process of etching the third N-type doping layer 130 to form the third isolation groove 131 at the position corresponding to the second isolation groove 121 are similar to the process of etching the first N-type doping layer 110 to form the first isolation groove 111. The process of forming the second P-type doping layer 122 in the second isolation groove 121 and the process of forming the third P-type doping layer 132 in the third isolation groove 131 are similar to the process of forming the first P-type doping layer 112 in the first isolation groove 111, and they are not repeated here.

[0089] In this embodiment, after the photoelectric functional layer is formed, the semiconductor structure can be subjected to a rapid annealing treatment to activate the doped ions, reduce the generation of dark current, and improve the photoelectric performance of the PD, so as to improve the yield and imaging quality of the image sensor. Specifically, laser pulse annealing can be selected for rapid annealing. For example, laser annealing can be performed in an oxygen-containing environment, and the specific process parameters are as follows: the pulse energy can be 700mj~800mj, for example, 701mj, 720mj, 740mj, 750mj or 790mj, etc. The overall time of laser pulse annealing can be 28s~32s, for example, 29s, 30s or 31s, and the peak temperature of laser pulse annealing can be 430℃~470℃, for example, 435℃, 440℃, 450℃ or 460℃, etc. Laser pulse annealing can shorten the annealing time, reduce the area of ​​lateral diffusion, and make the boundary of the photosensitive area clear.

[0090] See also Figures 17 to 19 In some embodiments, the semiconductor manufacturing method further includes: sequentially forming a first grid layer 141 , a second grid layer 142 , and a third grid layer 143 on the third N-type doped layer 130 ; and etching the first grid layer 141 , the second grid layer 142 , and the third grid layer 143 to obtain a plurality of grid structures 140 .

[0091] See also Fig.17 In this embodiment, the material of the first grid layer 141 may be tantalum oxide, the material of the second grid layer 142 may be aluminum, and the material of the third grid layer 143 may be titanium nitride. Titanium nitride may be used as a stabilizing layer to reduce crosstalk between pixels.

[0092] See also Fig.18 After forming the three-layer grid layer, the position of the grid structure 140 can be defined, and the three-layer grid layer can be etched to form the grid structure 140 for separating the filter structures 150 of different colors. Specifically, the position of the grid structure 140 can correspond to the third P-type doped layer 132, and the process of etching the three-layer grid layer to form the grid structure 140 is similar to the process of etching the N-type doped layer to form the isolation groove, which will not be repeated here.

[0093] In this embodiment, the width of the grid structure 140 along the width direction is smaller than the width of the third P-type doped layer 132 along the width direction, and the width of the grid structure 140 decreases in the direction away from the substrate 100 to increase the light flux between the grids, so that more light is received by the photoelectric functional layer, increasing the number of electron-hole pairs in the photoelectric functional layer, and at the same time reducing crosstalk between pixels, thereby enhancing the photoelectric effect of PD.

[0094] See also Fig.19 In some embodiments, after the grid structure 140 is formed, a filter structure 150 (color filter) may be provided between adjacent grid structures 140. Specifically, the filter structure 150 is formed on a surface of the optoelectronic functional layer away from the substrate 100. The filter structure 150 may include a plurality of color filters, and the plurality of color filters form a color filter array.

[0095] In this embodiment, the filter structure 150 may include at least three primary color color filters, and the color filters may be arranged in any appropriate combination.

[0096] In some embodiments, a transparent filter may be provided, and the blue filter, the green filter, the red filter and the transparent filter are arranged alternately. The color filter may be a polymer material, such as a negative photoresist with an acrylic polymer as a substrate, and may contain a color dye. When light passes through the color filter, the color may change, maintaining a high transmittance in a certain wavelength band, thereby enhancing the effect of photoelectric conversion.

[0097] In this embodiment, the top of the filter structure 150 may be in the shape of an arc protruding outward, so as to focus the incident light on the optoelectronic functional layer. The curvature of the surface of the filter structure 150 may be changed according to the light focusing requirements to improve the photosensitivity efficiency.

[0098] In some embodiments, after forming the filter structure 150, a microlens structure can be further formed on the filter structure 150. The microlens structure can be formed by any method of forming the microlens structure, and the embodiment of the present application does not make specific restrictions. The number of filter structures 150 can be set according to actual needs, and the drawings of this embodiment are only used as examples.

[0099] See also Fig.16 An embodiment of the present application provides a semiconductor structure, which may include: a substrate 100; a photoelectric functional layer, which is disposed on the substrate 100 and is used to realize photoelectric signal conversion based on the photoelectric effect; the photoelectric functional layer includes a plurality of N-type doping regions 160 and a P-type doping region 170; an isolation groove is formed between adjacent N-type doping regions 160, and the P-type doping region 170 is located in the isolation groove; wherein the N-type doping region 160 includes a first N-type doping layer 110, a second N-type doping layer 120 and a third N-type doping layer 130 which are stacked; the second N-type doping layer 120 is located between the first N-type doping layer 110 and the third N-type doping layer 130, and the second N-type doping layer 120 is located between the first N-type doping layer 110 and the third N-type doping layer 130, and the second N-type doping layer 120 is located between the first N-type doping layer 110 and the third N-type doping layer 130. Among the impurity layer 110, the second N-type doping layer 120 and the third N-type doping layer 130, the relative atomic mass of the impurity element doped in the second N-type doping layer 120 is the largest; the P-type doping region 170 has a first P-type doping layer 112 corresponding to the first N-type doping layer 110, a second P-type doping layer 122 corresponding to the second N-type doping layer 120 and a third P-type doping layer 132 corresponding to the third N-type doping layer 130; the isolation groove has a groove extension direction and a width direction perpendicular to the groove extension direction, and among the first P-type doping layer 112, the second P-type doping layer 122 and the third P-type doping layer 132, the width of the second P-type doping layer 122 along the width direction is the smallest.

[0100] In an embodiment of the present application, a multi-layer optoelectronic functional layer is formed on a substrate, and the optoelectronic functional layer includes multiple N-type doping regions and P-type doping regions, and an isolation groove is set between adjacent N-type doping regions to enhance the isolation between pixels, and the structure of the P-type doping region is set as follows: among the multiple P-type doping layers corresponding to the multiple N-type doping layers, the width of the P-type doping layer corresponding to the N-type doping layer with the largest relative atomic mass of the impurity element doped is the narrowest. The unexpected effect is that on the one hand, the damage to the device caused by ion implantation is reduced to improve the reliability of the image sensor, and on the other hand, the crosstalk and dark current between adjacent pixels are reduced, and at the same time, the photoelectric effect of the photodiode is improved to improve the imaging quality of the image sensor.

[0101] An embodiment of the present application provides an image sensor, which may include the semiconductor structure described in the above embodiment, or may include a semiconductor structure manufactured by the method for manufacturing the semiconductor structure described in the above embodiment.

[0102] Regarding the technical effects of the image sensor described in the above embodiment, reference can be made to other embodiments of the present application for comparative explanation and no further details will be given here.

[0103] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of this application.

[0104] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0105] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0106] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application are the same as the meanings generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include majority forms, unless the context clearly indicates other meanings.

[0107] In several embodiments provided in this application, it should be understood that the disclosed semiconductor structure or image sensor can be implemented in other ways. For example, the embodiments of the semiconductor structure or image sensor described above are merely illustrative.

[0108] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A photoelectric functional layer is arranged on the substrate and is used to realize photoelectric signal conversion based on the photoelectric effect; the photoelectric functional layer includes a plurality of N-type doping regions and P-type doping regions; an isolation groove is formed between adjacent N-type doping regions, and the P-type doping region is located in the isolation groove; wherein the N-type doping region includes a first N-type doping layer, a second N-type doping layer and a third N-type doping layer arranged in a stacked manner; the second N-type doping layer is located between the first N-type doping layer and the third N-type doping layer, and the first N-type doping layer, the second N-type doping layer and the third Among the N-type doping layers, the relative atomic mass of the impurity elements doped in the second N-type doping layer is the largest; the P-type doping region has a first P-type doping layer corresponding to the first N-type doping layer, a second P-type doping layer corresponding to the second N-type doping layer, and a third P-type doping layer corresponding to the third N-type doping layer; the isolation groove has a groove extension direction and a width direction perpendicular to the groove extension direction, and among the first P-type doping layer, the second P-type doping layer has the smallest width along the width direction.

2. The semiconductor structure according to claim 1, characterized in that: The impurity element doped into the second N-type doping layer is antimony; the impurity element doped into the first N-type doping layer is arsenic; and the impurity element doped into the third N-type doping layer is phosphorus.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The impurity element doped into the first P-type doping layer is indium, the impurity element doped into the second P-type doping layer is gallium, and the impurity element doped into the third P-type doping layer is boron.

4. The semiconductor structure according to claim 1, characterized in that: The width of the first P-type doped layer along the width direction is 1.5 to 2.5 times the width of the second P-type doped layer along the width direction; the width of the third P-type doped layer along the width direction is 1.5 to 2.5 times the width of the second P-type doped layer along the width direction.

5. The semiconductor structure according to claim 1, characterized in that: A grid structure for separating filter structures of different colors is arranged on a surface of the P-type doping region away from the substrate; a width of the grid structure along the width direction is smaller than a width of the third P-type doping layer along the width direction.

6. The semiconductor structure according to claim 5, characterized in that: The grid structure comprises a first grid layer, a second grid layer and a third grid layer which are stacked, wherein the material of the first grid layer is tantalum oxide, the material of the second grid layer is aluminum, and the material of the third grid layer is titanium nitride.

7. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: providing a substrate; A photoelectric functional layer is prepared on the substrate; wherein the photoelectric functional layer includes a plurality of N-type doping regions and a P-type doping region; an isolation groove is formed between adjacent N-type doping regions, and the P-type doping region is located in the isolation groove; the N-type doping region includes a first N-type doping layer, a second N-type doping layer and a third N-type doping layer which are stacked; the second N-type doping layer is located between the first N-type doping layer and the third N-type doping layer, and the relative atomic mass of the impurity element doped in the second N-type doping layer is greater than the relative atomic mass of the impurity element doped in the first N-type doping layer and the third N-type doping layer; the P-type doping region has a first P-type doping layer corresponding to the first N-type doping layer, a second P-type doping layer corresponding to the second N-type doping layer, and a third P-type doping layer corresponding to the third N-type doping layer; wherein the isolation groove has a groove extension direction and a width direction perpendicular to the groove extension direction, and among the first P-type doping layer, the second P-type doping layer and the third P-type doping layer, the width of the second P-type doping layer along the width direction is the smallest.

8. The method according to claim 7, characterized in that The step of preparing the photoelectric functional layer on the substrate comprises: forming a first N-type doped layer on the substrate; Etching the first N-type doped layer to form a first isolation trench; forming a first P-type doping layer in the first isolation trench; forming a second N-type doping layer on the first N-type doping layer; wherein the relative atomic mass of the impurity element doped in the second N-type doping layer is greater than the relative atomic mass of the impurity element doped in the first N-type doping layer; Etching the second N-type doped layer at a position corresponding to the first isolation groove to form a second isolation groove; wherein the second isolation groove has a groove extension direction, and a width of the second isolation groove along a width direction perpendicular to the groove extension direction is smaller than a width of the first isolation groove along the width direction; forming a second P-type doped layer in the second isolation trench; forming a third N-type doping layer on the second N-type doping layer; wherein the relative atomic mass of the impurity element doped in the third N-type doping layer is less than the relative atomic mass of the impurity element doped in the second N-type doping layer; Etching the third N-type doped layer at a position corresponding to the second isolation groove to form a third isolation groove; wherein the width of the third isolation groove along the width direction is greater than the width of the second isolation groove along the width direction; A third P-type doping layer is formed in the third isolation trench.

9. The method according to claim 7, characterized in that: The method further comprises: forming a first grid layer, a second grid layer and a third grid layer in sequence on the third N-type doped layer; wherein the material of the first grid layer is tantalum oxide, the material of the second grid layer is aluminum, and the material of the third grid layer is titanium nitride; The first grid layer, the second grid layer and the third grid layer are etched to obtain a plurality of grid structures; wherein the position of the grid structure corresponds to the third P-type doped layer, the width of the grid structure along the width direction is smaller than the width of the third P-type doped layer along the width direction, and the width of the grid structure decreases in a direction away from the substrate.

10. An image sensor, characterized in that: The image sensor comprises the semiconductor structure according to any one of claims 1 to 6 or a semiconductor structure manufactured by the method for manufacturing the semiconductor structure according to any one of claims 7 to 9.

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