A gallium nitride device with improved linearity and a method for preparing the same

Abstract

The present invention discloses a gallium nitride device with improved linearity, which comprises, from top to bottom, an electrode extension portion, a V-shaped structure, and a substrate structure. The present invention provides a gallium nitride device with improved linearity, which utilizes the different properties of the mobility and two-dimensional electron gas concentration in the dual crystal orientation to achieve transconductance flatness modulation of the device, thereby achieving higher linearity; specifically, the present invention directly epitaxies conventional Al on an m-plane GaN epitaxial wafer. x Ga 1‑x High linearity can be achieved by fabricating N / GaN heterojunctions and then preparing bi-directional channel GaN devices without the need for special epitaxial structures, thereby reducing the cost of epitaxial design.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a gallium nitride device with improved linearity and a preparation method thereof. Background Art

[0002] With the continuous development of the wireless communications market and advancements in the military and defense sectors, the performance requirements for microwave power devices are increasing, driving their rapid development. Third-generation semiconductor materials, such as gallium nitride (GaN) and silicon carbide (SiC), play a key role in this progress, demonstrating excellent characteristics for high-power applications. Gallium nitride (GaN) possesses outstanding physical properties, including a wide bandgap, high electron saturation velocity, high voltage and high temperature resistance, and excellent thermal stability. It is considered an ideal material for applications in high-voltage, high-frequency, high-temperature, and radiation-resistant fields. GaN holds broad prospects in optoelectronics, high-temperature, high-power devices, and radio frequency microwave devices.

[0003] The transconductance (G m ) with gate voltage (V gs ) The change curve is as shown in the attached Figure 1 As shown, with V gs Increase, G m It will rise first and then fall. m ) represents the relationship between changes in output current and input voltage. The nonlinear nature of power amplifiers (PAs) leads to a range of issues, such as spectral leakage, premature output power saturation, and signal distortion. These issues not only impact system performance but also complicate system design. Furthermore, in wireless communications, PA nonlinearity can lead to distortion of audio and video information during audio and video file transmission. To achieve superior signal transmission fidelity, GaN devices require high linearity.

[0004] Improving the linearity of GaN devices typically involves designing more complex epitaxial structures or implementing specialized device structures through processes such as etching. The former approach places higher demands on the epitaxial structure and increases costs, while the latter approach uses etching to achieve the structure, which can introduce more problems such as etching damage, thus affecting device reliability and yield, and also complicating the manufacturing process.

[0005] Patent document CN111969046A discloses a high-linearity enhancement-mode gallium nitride high-electron-mobility transistor and its fabrication method. This method utilizes a nanochannel strip structure beneath the gate electrode to deplete the two-dimensional electron gas of the III-nitride heterojunction by a p-type III-nitride region, thereby improving the flatness and linearity of the transistor's transconductance curve. However, this method relies on an inductively coupled plasma (ICP) process to etch the barrier layer, which can cause extensive etching damage in the barrier layer, degrading device performance.

[0006] Patent document CN101488457A discloses a method for improving the linearity of gallium nitride high electron mobility transistors by x Ga 1-x An Al layer is inserted between the N / GaN heterojunction y Ga 1-y N insertion layer, forming AlxGa 1-x N / AlyGa 1-y N / GaN. By optimizing the barrier layer Al x Ga 1-x The thickness of N and the value of Al component x can make Al x Ga 1-x N / A y Ga 1-y The lateral electric field ET in the 2DEG formed between N is reduced to a moderate value, thereby obtaining the maximum linearity of the device; this method requires the design of a more complex epitaxial structure, so the quality requirements for the device epitaxial structure are higher and the manufacturing cost is higher.

[0007] Therefore, there is an urgent need to develop a gallium nitride device to solve the above problems. Summary of the Invention

[0008] Based on the defects and deficiencies in the prior art, the present invention provides a gallium nitride device with improved linearity. By utilizing the different properties of the mobility of the dual crystal orientation and the two-dimensional electron gas (2DEG) concentration, the transconductance flatness modulation of the device can be achieved, thereby achieving higher linearity while avoiding the etching damage introduced by the barrier layer etching. Specifically, the present invention directly epitaxies conventional Al on the m-plane GaN. x Ga 1-x High linearity can be achieved by fabricating N / GaN heterojunctions and then preparing bi-directional channel GaN devices without the need for special epitaxial structures, thereby reducing the cost of epitaxial design.

[0009] In the present invention, linearity refers to the degree of change in the output signal of a device when the input signal changes.

[0010] An object of the present invention is to provide a gallium nitride device with improved linearity, wherein the gallium nitride device with improved linearity comprises the following structures from top to bottom: an electrode extension portion, a V-shaped structure, and a substrate structure;

[0011] in

[0012] Base structure: The base structure includes a buffer layer and a substrate from top to bottom;

[0013] The buffer layer includes a second buffer layer and a first buffer layer from top to bottom;

[0014] V-shaped structure: the V-shaped structure is arranged on the first buffer layer. The V-shaped structure is a multi-layer structure with a V-shaped cross-section. The V-shaped structure comprises an electrode layer, a barrier layer, and a second buffer layer from top to bottom.

[0015] The second buffer layer is an extension of the first buffer layer on the V-shaped structure;

[0016] The entire surface of the V-shaped electrode layer and the outer side of the second buffer layer are covered by a passivation layer formed of Si3N4;

[0017] The electrode layer consists of a source electrode, a drain electrode and a gate electrode, wherein

[0018] The gate is deposited at the center of the V-shaped structure, and the source and drain are deposited at both ends of the V-shaped structure, with gaps left between the source and drain and the gate.

[0019] Electrode extension portion: The source, drain and gate are partially extended upwards from the device to form electrode extension portions of the source, drain and gate, respectively.

[0020] Furthermore, the materials of the first buffer layer and the second buffer layer are both m-plane GaN materials.

[0021] Furthermore, the length of the source-gate gap between the source electrode and one end of the adjacent gate electrode is 1-3 μm.

[0022] Furthermore, the length of the drain-gate gap between the drain electrode and one end of the adjacent gate electrode is 3-6 μm.

[0023] Furthermore, the length of the drain-gate gap is greater than the length of the source-gate gap.

[0024] Furthermore, the material of the substrate is selected from one or more of silicon, sapphire, silicon carbide, and diamond.

[0025] Furthermore, the gate, source and drain are independently multi-layer metal electrodes, and the material of each layer of the multi-layer metal electrode is independently selected from one or more of gold, aluminum, titanium, silver, copper, platinum and nickel.

[0026] Furthermore, the barrier layer material is Al x Ga 1-x N material, wherein the value range of X is 0.2-0.34.

[0027] The present invention also provides a method for preparing the gallium nitride device with improved linearity, and the method for preparing the gallium nitride device with improved linearity comprises the following steps:

[0028] S1. Preparing a multilayer substrate, wherein the multilayer substrate comprises a barrier layer, a buffer layer, and a substrate from top to bottom;

[0029] S2. Etching the substrate to etch a portion of the barrier layer and the buffer layer into a V-shaped structure, so that the buffer layer is etched into a first buffer layer located in the substrate structure and a second buffer layer located in the V-shaped structure;

[0030] S3, depositing a gate, a source, and a drain on the V-shaped barrier layer to form an electrode layer;

[0031] S4, performing Si3N4 passivation treatment on the outer surface of the electrode layer and a portion of the first buffer layer, and controlling the thickness of the Si3N4 to form a passivation layer;

[0032] S5. Etching the passivation layer to form interconnected through holes with the source, drain and gate, and completing the preparation of electrode extension parts of the source, drain and gate.

[0033] Furthermore, the thickness of the passivation layer is 100-300 nm.

[0034] Furthermore, in the V-shaped structure, the angle between the two sides is 60-80°.

[0035] Furthermore, the passivation layer is prepared by a CVD process.

[0036] Furthermore, the gate, source, drain and the barrier layer form ohmic contacts.

[0037] The beneficial effects of the present invention are as follows:

[0038] 1. This structure enables GaN devices to achieve better transconductance flatness, thereby achieving higher linearity. Improved linearity in GaN RF devices means that within their operating range, the device's response more closely resembles the linear relationship of the input signal. Higher linearity generally means that when processing complex RF signals, the device can more accurately and reliably preserve the original signal shape without introducing nonlinear distortion.

[0039] 2. Surprisingly, the present method requires the fabrication of GaN devices with a specific crystal orientation angle on an m-plane GaN epitaxial wafer. However, the two-dimensional electron gas density and electron mobility on GaN epitaxial wafers with other polar planes, such as the Ga plane, do not vary significantly with crystal orientation. Therefore, dual-orientation channel devices on polar-plane GaN cannot achieve improved linearity. However, the present invention, by providing a barrier layer and a second buffer layer with a V-shaped structure on the m-plane GaN epitaxial wafer, can improve the transconductance flatness of the GaN device, thereby achieving higher linearity. Moreover, when the angle of the V-shaped structure is 60°, the difference in two-dimensional electron gas density and electron mobility between the two crystal orientations is the largest, and the preparation of GaN devices with dual-orientation channels can achieve maximum device linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 In the background technology, the transconductance (G m ) with gate voltage (V gs ) Schematic diagram of the change curve;

[0041] Figures 2(a)-(f) are schematic flow diagrams of a method for preparing a gallium nitride device with improved linearity in Examples 1-3;

[0042] Figure 3 This is a schematic diagram of a gallium nitride device proposed in Comparative Example 1;

[0043] In the figure: 1. Source; 2. Drain; 3. Gate; 4. Passivation layer (covering the surface); 5. Barrier layer; 6. Buffer layer; 61. First buffer layer; 62. Second buffer layer; 7. Substrate. DETAILED DESCRIPTION

[0044] In order to more clearly illustrate the technical solutions of the present invention, the following examples are given. Unless otherwise stated, the raw materials, reactions and post-processing methods mentioned in the examples are common raw materials on the market and technical methods well known to those skilled in the art.

[0045] The terms "preferred," "preferably," "more preferred," and the like, used herein, refer to embodiments of the invention that may provide certain benefits under certain circumstances. However, other embodiments may also be preferred under the same or other circumstances. Furthermore, the recitation of one or more preferred embodiments does not imply that other embodiments are not useful, nor is it intended to exclude other embodiments from the scope of the invention.

[0046] It should be understood that, except in any operating examples, or where otherwise indicated, all numbers expressing, for example, quantities of ingredients used in the specification and claims are to be understood as being modified in all instances by the term "about." Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and appended claims are approximations that may vary depending upon the desired properties to be obtained by the present invention.

[0047] The m-plane is a type of specific crystal plane in the hexagonal system. For details, please refer to "Nitride Wide Bandgap Semiconductor Materials and Electronic Devices", author: Hao Yue, publisher: Science Press, page 20.

[0048] Example 1

[0049] A gallium nitride device with improved linearity, the structure of the gallium nitride device with improved linearity is shown in Figures 2(a)-(f), including an electrode extension portion, a V-shaped structure, and a substrate structure;

[0050] in

[0051] Substrate structure: The substrate structure comprises, from top to bottom, an m-plane GaN buffer layer 6 (1000 nm) and a sapphire substrate 7 (650 μm);

[0052] The buffer layer 6 includes, from top to bottom, a second buffer layer 62 (100 nm) and a first buffer layer 61 (900 nm);

[0053] V-shaped structure: The V-shaped structure is arranged on the first buffer layer 61. The V-shaped structure is a multi-layer structure with a V-shaped cross-section (the angle is 60 degrees). The V-shaped structure is composed of an electrode layer, an Al 0.25 Ga 0.75 N barrier layer 5 (20 nm) and second buffer layer 62 (100 nm);

[0054] The second buffer layer 62 is an extension of the first buffer layer 61 on the V-shaped structure. This special shape is achieved by etching below.

[0055] The entire surface of the V-shaped electrode layer and the outer side of the second buffer layer 62 are covered by a passivation layer 4 formed of Si3N4 (100 nm);

[0056] The electrode layer consists of a source electrode 1, a drain electrode 2 and a gate electrode 3, wherein

[0057] The gate 3 is deposited at the center of the V-shaped structure, and the source 1 and drain 2 are deposited at both ends of the V-shaped structure, with gaps left between the source 1 and drain 2 and the gate 3. The gaps are filled with a passivation layer 4 formed of Si3N4.

[0058] Electrode extensions: The source 1, drain 2, and gate 3 all partially extend upward from the device, forming electrode extensions for the source 1, drain 2, and gate 3, respectively. These electrode extensions are divided into two parts: a supporting columnar structure (100 nm in height) extending upward from the electrode layer, and a planar metal plate (80 μm x 80 μm in area) extending horizontally from each columnar structure.

[0059] The method for preparing the gallium nitride device with improved linearity is as follows, and the related drawings are as follows: Figures 2(a)-2(f) shown.

[0060] S1, prepare a multi-layer structure substrate, the multi-layer structure epitaxial wafer is Al 0.25 Ga 0.75 N barrier layer 5 (20 nm), m-plane GaN buffer layer 6 (1000 nm) and sapphire substrate 7 (650 μm), as shown in Figure 2(a);

[0061] S2. Etching the upper portion of the barrier layer 5 and the buffer layer 6 using an ICP process to form a columnar V-shaped structure (including the etched barrier layer 5 and the second buffer layer 62); in this V-shaped structure, an active region of a dual-crystal channel can be formed. It should be noted that in order to ensure device isolation, the two-dimensional electron gas in the non-active region of the device needs to be completely cut off. Because the barrier layer 5 in the non-active region needs to be completely etched, the upper portion of the buffer layer 6 is etched to form the second buffer layer 62 (100 nm). The unetched portion forms the first buffer layer 61 (900 nm), as shown in FIG2(b);

[0062] S3. Deposit Ti / Al / Ti / Au (20nm / 110nm / 40nm / 50nm) as the source electrode 1 on one end of the V-shaped barrier layer 5, and deposit Ti / Al / Ti / Au (20nm / 110nm / 40nm / 50nm) as the drain electrode 2 on the other end using an electron beam evaporation device. Then, perform rapid thermal annealing at 830°C for 45s to form an ohmic contact, thereby obtaining the source electrode 1 and the drain electrode 2, as shown in FIG2(c).

[0063] S4. At the center of the V-shape, the gate length is designed to be 250nm. Then, Ni / Au (20nm / 130nm) is deposited as the gate 3 metal using electron beam evaporation equipment to obtain the gate 3. The gate 3 has a small V-shape with an angle of 60° between the two sides. There is a gap between the source 1 and the drain 2, as shown in Figure 2(d).

[0064] The length of the source-gate gap between the source electrode 1 and one end of the adjacent gate electrode 3 is 2 μm; the length of the drain-gate gap between the drain electrode 2 and one end of the adjacent gate electrode 3 is 4 μm.

[0065] S5, using CVD process to grow a passivation layer 4 of Si3N4 on the barrier layer 5, filling the gaps and wrapping the electrode layer on the surface, and controlling the surface thickness to be 100 nm;

[0066] A passivation layer 4 of Si3N4 is grown on the first buffer layer 61, and its surface thickness is controlled to be 100 nm, so that the outer side of the second buffer layer 62 is covered by the passivation layer 4 formed of Si3N4, as shown in FIG2(e);

[0067] S6. Use a photolithography machine and ICP process to etch the gate-source-drain electrode interconnection through-holes on the passivation layer 4 on the surface of the barrier layer 5. The etching depth of the through-holes is 100 nm. Then use electron beam evaporation equipment to deposit Ni / Au (20 nm / 180 nm) to form a columnar structure with a height of 100 nm, and form a Ni / Au (20 nm / 180 nm) metal plate (area of ​​80 μm*80 μm) to obtain the gallium nitride device with improved linearity, as shown in Figure 2(f).

[0068] Example 2

[0069] A gallium nitride device with improved linearity, the structure of the gallium nitride device with improved linearity is shown in Figures 2(a)-(f), including an electrode extension portion, a V-shaped structure, and a substrate structure;

[0070] in

[0071] Substrate structure: The substrate structure comprises, from top to bottom, an m-plane GaN buffer layer 6 (1000 nm) and a sapphire substrate 7 (650 μm);

[0072] The buffer layer 6 includes, from top to bottom, a second buffer layer 62 (100 nm) and a first buffer layer 61 (900 nm);

[0073] V-shaped structure: The V-shaped structure is arranged on the first buffer layer 61. The V-shaped structure is a multi-layer structure with a V-shaped cross-section (the angle is 60 degrees). The V-shaped structure is composed of an electrode layer, an Al 0.25 Ga 0.75 N barrier layer 5 (10 nm) and second buffer layer 62 (100 nm);

[0074] The second buffer layer 62 is an extension of the first buffer layer 61 on the V-shaped structure. This special shape is achieved by etching below.

[0075] The entire surface of the V-shaped electrode layer and the outer side of the second buffer layer 62 are covered by a passivation layer 4 formed of Si3N4 (100 nm);

[0076] The electrode layer consists of a source electrode 1, a drain electrode 2 and a gate electrode 3, wherein

[0077] The gate 3 is deposited at the center of the V-shaped structure, and the source 1 and drain 2 are deposited at both ends of the V-shaped structure, with gaps left between the source 1 and drain 2 and the gate 3. The gaps are filled with a passivation layer 4 formed of Si3N4.

[0078] Electrode extensions: The source 1, drain 2, and gate 3 all partially extend upward from the device, forming electrode extensions for the source 1, drain 2, and gate 3, respectively. These electrode extensions are divided into two parts: a supporting columnar structure (100 nm in height) extending upward from the electrode layer, and a planar metal plate (80 μm x 80 μm in area) extending horizontally from each columnar structure.

[0079] The method for preparing the gallium nitride device with improved linearity is as follows, and the related drawings are as follows: Figures 2(a)-2(f) shown.

[0080] S1, prepare a multi-layer structure substrate, the multi-layer structure epitaxial wafer is Al 0.25 Ga 0.75 N barrier layer 5 (10 nm), m-plane GaN buffer layer 6 (1000 nm) and sapphire substrate 7 (650 μm), as shown in Figure 2(a);

[0081] S2. Etching the upper portion of the barrier layer 5 and the buffer layer 6 using an ICP process to form a columnar V-shaped structure (including the etched barrier layer 5 and the second buffer layer 62); in this V-shaped structure, an active region of a dual-crystal channel can be formed. It should be noted that in order to ensure device isolation, the two-dimensional electron gas in the non-active region of the device needs to be completely cut off. Because the barrier layer 5 in the non-active region needs to be completely etched, the upper portion of the buffer layer 6 is etched to form the second buffer layer 62 (100 nm). The unetched portion forms the first buffer layer 61 (900 nm), as shown in FIG2(b);

[0082] S3. Deposit Ti / Al / Ti / Au (20nm / 110nm / 40nm / 50nm) as the source electrode 1 on one end of the V-shaped barrier layer 5, and deposit Ti / Al / Ti / Au (20nm / 110nm / 40nm / 50nm) as the drain electrode 2 on the other end using an electron beam evaporation device. Then, perform rapid thermal annealing at 830°C for 45s to form an ohmic contact, thereby obtaining the source electrode 1 and the drain electrode 2, as shown in FIG2(c).

[0083] S4. At the center of the V-shape, the gate length is designed to be 250nm. Then, Ni / Au (20nm / 130nm) is deposited as the gate 3 metal using electron beam evaporation equipment to obtain the gate 3. The gate 3 has a small V-shape with an angle of 60° between the two sides. There is a gap between the source 1 and the drain 2, as shown in Figure 2(d).

[0084] The length of the source-gate gap between the source electrode 1 and one end of the adjacent gate electrode 3 is 2 μm; the length of the drain-gate gap between the drain electrode 2 and one end of the adjacent gate electrode 3 is 4 μm.

[0085] S5, using CVD process to grow a passivation layer 4 of Si3N4 on the barrier layer 5, filling the gaps and wrapping the electrode layer on the surface, and controlling the surface thickness to be 100 nm;

[0086] A passivation layer 4 of Si3N4 is grown on the first buffer layer 61, and its surface thickness is controlled to be 100 nm, so that the outer side of the second buffer layer 62 is covered by the passivation layer 4 formed of Si3N4, as shown in FIG2(e);

[0087] S6. Use a photolithography machine and ICP process to etch the gate-source-drain electrode interconnection through-holes on the passivation layer 4 on the surface of the barrier layer 5. The etching depth of the through-holes is 100 nm. Then use electron beam evaporation equipment to deposit Ni / Au (20 nm / 180 nm) to form a columnar structure with a height of 100 nm, and form a Ni / Au (20 nm / 180 nm) metal plate (area of ​​80 μm*80 μm) to obtain the gallium nitride device with improved linearity, as shown in Figure 2(f).

[0088] Example 3

[0089] A gallium nitride device with improved linearity, the structure of the gallium nitride device with improved linearity is shown in Figures 2(a)-(f), including an electrode extension portion, a V-shaped structure, and a substrate structure;

[0090] in

[0091] Substrate structure: The substrate structure comprises, from top to bottom, an m-plane GaN buffer layer 6 (1000 nm) and a sapphire substrate 7 (650 μm);

[0092] The buffer layer 6 includes, from top to bottom, a second buffer layer 62 (100 nm) and a first buffer layer 61 (900 nm);

[0093] V-shaped structure: The V-shaped structure is arranged on the first buffer layer 61 of the base structure. The V-shaped structure is a multi-layer structure with a V-shaped cross-section (the angle is 60 degrees). The V-shaped structure is composed of an electrode layer, an Al 0.2 Ga 0.8 N barrier layer 5 (20 nm) and second buffer layer 62 (100 nm);

[0094] The second buffer layer 62 is an extension of the first buffer layer 61 on the V-shaped structure. This special shape is achieved by etching below.

[0095] The entire surface of the V-shaped electrode layer and the outer side of the second buffer layer 62 are covered by a passivation layer 4 formed of Si3N4 (100 nm);

[0096] The electrode layer consists of a source electrode 1, a drain electrode 2 and a gate electrode 3, wherein

[0097] The gate 3 is deposited at the center of the V-shaped structure, and the source 1 and drain 2 are deposited at both ends of the V-shaped structure, with gaps left between the source 1 and drain 2 and the gate 3. The gaps are filled with a passivation layer 4 formed of Si3N4.

[0098] Electrode extensions: The source 1, drain 2, and gate 3 all partially extend upward from the device, forming electrode extensions for the source 1, drain 2, and gate 3, respectively. These electrode extensions are divided into two parts: a supporting columnar structure (100 nm in height) extending upward from the electrode layer, and a planar metal plate (80 μm x 80 μm in area) extending horizontally from each columnar structure.

[0099] The method for preparing the gallium nitride device with improved linearity is as follows, and the related drawings are as follows: Figures 2(a)-2(f) shown.

[0100] S1, prepare a multi-layer structure substrate, the multi-layer structure epitaxial wafer is Al 0.2 Ga 0.8 N barrier layer 5 (20 nm), buffer layer 6 (1000 nm) and sapphire substrate 7 (650 μm), as shown in Figure 2(a);

[0101] S2. Etching the upper portion of the barrier layer 5 and the buffer layer 6 using an ICP process to form a columnar V-shaped structure (including the etched barrier layer 5 and the second buffer layer 62); in this V-shaped structure, an active region of a dual-crystal channel can be formed. It should be noted that in order to ensure device isolation, the two-dimensional electron gas in the non-active region of the device needs to be completely cut off. Because the barrier layer 5 in the non-active region needs to be completely etched, the upper portion of the buffer layer 6 is etched to form the second buffer layer 62 (100 nm). The unetched portion forms the first buffer layer 61 (900 nm), as shown in FIG2(b);

[0102] S3. Deposit Ti / Al / Ti / Au (20nm / 110nm / 40nm / 50nm) as the source electrode 1 on one end of the V-shaped barrier layer 5, and deposit Ti / Al / Ti / Au (20nm / 110nm / 40nm / 50nm) as the drain electrode 2 on the other end using an electron beam evaporation device. Then, perform rapid thermal annealing at 830°C for 45s to form an ohmic contact, thereby obtaining the source electrode 1 and the drain electrode 2, as shown in FIG2(c).

[0103] S4. At the center of the V-shape, the gate length is designed to be 250nm. Then, Ni / Au (20nm / 130nm) is deposited as the gate 3 metal using electron beam evaporation equipment to obtain the gate 3. The gate 3 has a small V-shape with an angle of 60° between the two sides. There is a gap between the source 1 and the drain 2, as shown in Figure 2(d).

[0104] The length of the source-gate gap between the source electrode 1 and one end of the adjacent gate electrode 3 is 2 μm; the length of the drain-gate gap between the drain electrode 2 and one end of the adjacent gate electrode 3 is 4 μm.

[0105] S5, using CVD process to grow a passivation layer 4 of Si3N4 on the barrier layer 5, filling the gaps and wrapping the electrode layer on the surface, and controlling the surface thickness to be 100 nm;

[0106] A passivation layer 4 of Si3N4 is grown on the first buffer layer 61, and its surface thickness is controlled to be 100 nm, so that the outer side of the second buffer layer 62 is covered by the passivation layer 4 formed of Si3N4, as shown in FIG2(e);

[0107] S6. Use a photolithography machine and ICP process to etch the gate-source-drain electrode interconnection through-holes on the passivation layer 4 on the surface of the barrier layer 5. The etching depth of the through-holes is 100 nm. Then use electron beam evaporation equipment to deposit Ni / Au (20 nm / 180 nm) to form a columnar structure with a height of 100 nm, and form a Ni / Au (20 nm / 180 nm) metal plate (area of ​​80 μm*80 μm) to obtain the gallium nitride device with improved linearity, as shown in Figure 2(f).

[0108] Comparative Example 1

[0109] A gallium nitride device, the structure of the gallium nitride device is as follows Figure 3 As shown, the conventional gallium nitride device includes the following structures from top to bottom: an electrode extension portion, a substrate structure;

[0110] in

[0111] Base structure: The base structure includes, from top to bottom, a passivation layer 4 (100 nm), an electrode layer, a barrier layer 5 (20 nm), a buffer layer 6 (1000 nm); and a substrate 7 (650 μm);

[0112] The buffer layer 6 includes a second buffer layer 62 (100 nm) and a first buffer layer 61 (900 nm) from top to bottom;

[0113] The electrode layer is composed of a source electrode 1, a drain electrode 2 and a gate electrode 3;

[0114] Electrode extension portion: The source 1 , drain 2 and gate 3 are partially extended upward from the device to form electrode extension portions of the source 1 , drain 2 and gate 3 , respectively.

[0115] The substrate 7 is Si; the passivation layer 4 is Si3N4 material; the barrier layer 5 is Al 0.25 Ga 0.75 N; the materials of the first buffer layer 61 and the second buffer layer 62 are GaN.

[0116] The conventional method for preparing the gallium nitride device is as follows:

[0117] S1. Soak the GaN epitaxial wafer in acetone for 10 minutes, then remove it and soak it in isopropanol solution for 5 minutes, then rinse it in deionized water for 3 minutes, and finally blow it dry with a nitrogen gun to obtain a clean GaN epitaxial wafer, completing the process preparation work;

[0118] S1. Using ICP process, grooves are etched on both sides of the GaN epitaxial wafer to form a second buffer layer 62 and a barrier layer 5 of the columnar body to achieve electrical isolation between devices. The etching depth is 120nm.

[0119] S2. Ti / Al / Ti / Au (20 nm / 110 nm / 40 nm / 50 nm) was deposited on the barrier layer 5 using an electron beam evaporation device as the source 1 and drain 2 materials, and then rapid thermal annealing was performed at 830°C for 45 seconds to form ohmic contacts, thereby obtaining the source 1 and drain 2;

[0120] S3. Expose the gate region using an electron beam lithography (EBL) process, designing a gate length of 250 nm. Then, use electron beam evaporation equipment to deposit gate metal Ni / Au (20 nm / 130 nm) between source 1 and drain 2 to form gate 3.

[0121] S4 using a CVD process on the first buffer layer 61 of the surface Si3N4 passivation layer 4 growth, controlling the surface thickness of 100nm;

[0122] A passivation layer 4 of Si3N4 is grown on the barrier layer 5 to fill the gaps and wrap the electrode layer on the surface, and the surface thickness is controlled to be 100 nm;

[0123] S5. Use a photolithography machine and ICP process to etch the interconnection through holes of the source, drain and gate electrodes in the passivation layer 4 on the surface of the barrier layer 5, and then use electron beam evaporation equipment to deposit Ni / Au (20nm / 150nm) to form the electrode extension parts of the source, drain and gate electrodes to obtain the conventional gallium nitride device.

[0124] Test Example 1

[0125] Transfer characteristic curve tests were performed on the gallium nitride devices of Example 1 and Comparative Example 1.

[0126] Test method: Set the source-drain voltage V ds =1V, and the transfer characteristic curves of the gallium nitride devices of Example 1 and Comparative Example 1 were tested.

[0127] Among them, the gate-voltage-swing (GVS) figure of merit is a physical quantity that characterizes linearity. It is specifically defined as the gate voltage swing range in the transfer characteristic curve that maintains the transconductance at 80% of the transconductance peak. The larger the GVS, the higher the transconductance flatness, that is, the better the device linearity.

[0128] The test results are shown in Table 1.

[0129] Table 1 Performance test results of gallium nitride devices of Example 1 and Comparative Example 1

[0130] Threshold voltage (V) Maximum transconductance (mS / mm) Gate voltage swing figure of merit (V) Example 1 -4.12 391 5.9 Comparative Example 1 -5.86 445 3.8

[0131] According to the test results in Table 1, the gate voltage swing of the gallium nitride device of Example 1 is significantly higher than that of the device of Comparative Example 1, and the linearity of the device of Example 1 is better.

[0132] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations that come within the meaning and range of equivalents of the claims be embraced therein.

[0133] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A gallium nitride device with improved linearity, characterized in that: The gallium nitride device with improved linearity comprises the following structures from top to bottom: an electrode extension portion, a V-shaped structure, and a substrate structure; in Base structure: The base structure includes a buffer layer and a substrate from top to bottom; The buffer layer includes a second buffer layer and a first buffer layer from top to bottom; V-shaped structure: the V-shaped structure is arranged on the first buffer layer. The V-shaped structure is a multi-layer structure with a V-shaped cross-section. The V-shaped structure comprises an electrode layer, a barrier layer, and a second buffer layer from top to bottom. The second buffer layer is an extension of the first buffer layer on the V-shaped structure; The entire surface of the V-shaped electrode layer and the outer side of the second buffer layer are covered by a passivation layer formed of Si3N4; The electrode layer consists of a source electrode, a drain electrode and a gate electrode, wherein The gate is deposited at the center of the V-shaped structure, and the source and drain are deposited at both ends of the V-shaped structure, with gaps left between the source and drain and the gate. Electrode extension portion: the source, drain and gate are partially extended upwards from the device to form the electrode extension portions of the source, drain and gate respectively; The materials of the first buffer layer and the second buffer layer are both m-plane GaN materials.

2. The gallium nitride device with improved linearity according to claim 1, characterized in that: The length of the source-gate gap between the source electrode and one end of the adjacent gate electrode is 1-3 μm.

3. The gallium nitride device with improved linearity according to claim 2, characterized in that: The length of the drain-gate gap between the drain electrode and one end of the adjacent gate is 3-6 μm.

4. The gallium nitride device with improved linearity according to claim 3, characterized in that: The length of the drain-gate gap is greater than the length of the source-gate gap.

5. The gallium nitride device with improved linearity according to claim 1, characterized in that: The barrier layer material is Al x Ga 1-x N material, wherein the value range of X is 0.2-0.

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6. The method for preparing a gallium nitride device with improved linearity according to any one of claims 1 to 5, characterized in that: The method for preparing the gallium nitride device with improved linearity comprises the following steps: S1. Preparing a multilayer substrate, wherein the multilayer substrate comprises a barrier layer, a buffer layer, and a substrate from top to bottom; S2. Etching the substrate to etch a portion of the barrier layer and the buffer layer into a V-shaped structure, so that the buffer layer is etched into a first buffer layer located in the substrate structure and a second buffer layer located in the V-shaped structure; S3, depositing a gate, a source, and a drain on the V-shaped barrier layer to form an electrode layer; S4, performing Si3N4 passivation treatment on the outer surface of the electrode layer and a portion of the first buffer layer, and controlling the thickness of the Si3N4 to form a passivation layer; S5. Etching the passivation layer to form interconnected through holes with the source, drain and gate, and completing the preparation of electrode extension parts of the source, drain and gate.

7. The method for preparing a gallium nitride device with improved linearity according to claim 6, characterized in that: The thickness of the passivation layer is 100-300 nm.

8. The method for preparing a gallium nitride device with improved linearity according to claim 6, wherein: In the V-shaped structure, the angle between the two sides is 60-80°.

9. The method for preparing a gallium nitride device with improved linearity according to claim 6, wherein: The passivation layer is prepared by a CVD process.

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