Tunneling field effect transistor, preparation method thereof and photodetector

Abstract

The present invention proposes a tunneling field effect transistor, a preparation method thereof and a photodetector, which relate to the field of photoelectric devices. The tunneling field effect transistor includes a substrate and an insulating layer, and a conductive layer, a dielectric layer and a heterostructure layer stacked on the insulating layer in sequence, the heterostructure layer includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is stacked on the dielectric layer, a part of the second semiconductor layer is stacked on the first semiconductor layer, and the other part of the second semiconductor layer is stacked on the dielectric layer, the first semiconductor layer includes a tin disulfide layer, and the second semiconductor layer includes a tin diselenide layer. The technical solution of the present invention effectively suppresses carrier recombination at the interface by forming a depletion region on tin disulfide; the device has a depletion region of about 10 7 The on / off ratio is 240 nm, and it exhibits an ultra-high responsivity of 37.5 A / W and a wide spectrum detection feature from ultraviolet to visible light, and is expected to become the next generation of high-efficiency optoelectronic devices.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic devices, and in particular to a tunneling field effect transistor, a preparation method thereof and a photoelectric detector. Background Art

[0002] In traditional semiconductor photodetector technology, heterojunctions are usually used to enhance device performance, such as reducing dark current and increasing response speed. In order to form a heterojunction with excellent performance, it is very important to match the lattice constants of the two materials. Lattice mismatch will produce crystal defects such as dislocations, which will affect the electronic and optical properties of the device. In addition, traditional semiconductors still face problems such as high preparation costs and environmental unfriendliness.

[0003] At present, the response speed of a single two-dimensional atomic crystal photoconductive detector can only reach the microsecond level or even the millisecond level, and the single material determines that the detection band is limited, which seriously restricts the application of two-dimensional materials in the field of photoelectric detection. Summary of the invention

[0004] The main purpose of the present invention is to provide a tunneling field effect transistor, a preparation method thereof and a photodetector, and to provide an important approach for future electronic and optoelectronic applications.

[0005] To achieve the above-mentioned purpose, the present invention proposes a field effect transistor with tunneling performance, comprising a substrate and an insulating layer, and a conductive layer, a dielectric layer and a heterostructure layer stacked in sequence on the insulating layer, the heterostructure layer comprising a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is stacked on the dielectric layer, a portion of the second semiconductor layer is stacked on the first semiconductor layer, and the other portion of the second semiconductor is stacked on the dielectric layer, the first semiconductor layer comprises a tin disulfide layer, and the second semiconductor layer comprises a tin diselenide layer.

[0006] In one embodiment, the tunneling field effect transistor further includes a source electrode, a drain electrode and a gate electrode, the source electrode is disposed on the first semiconductor layer, the drain electrode is disposed on the second semiconductor layer, and the gate electrode is disposed on the conductive layer.

[0007] In one embodiment, the source electrode, the drain electrode and the gate electrode are made of a composite layer of a titanium layer and a gold layer.

[0008] In one embodiment, the thickness of the titanium layer is 5 nm;

[0009] The thickness of the gold layer is 50 nm.

[0010] In one embodiment, the substrate comprises a silicon substrate;

[0011] The insulating layer comprises a silicon dioxide layer;

[0012] The conductive layer includes a graphene layer;

[0013] The dielectric layer includes a hexagonal boron nitride layer.

[0014] In one embodiment, the thickness of the silicon dioxide layer is 285 nm to 300 nm;

[0015] The thickness of the graphene layer is 8 nm to 15 nm;

[0016] The thickness of the hexagonal boron nitride layer is 10 nm to 20 nm.

[0017] The present invention also provides a method for preparing a tunneling field effect transistor, comprising the following steps:

[0018] S10. Providing a substrate covered with an insulating layer;

[0019] S20. Disposing a conductive layer on one side of the substrate covered with an insulating layer;

[0020] S30. Disposing a dielectric layer on the conductive layer;

[0021] S40. Arranging a first semiconductor layer and a second semiconductor layer on the dielectric layer, a portion of the first semiconductor layer and a portion of the second semiconductor layer are stacked, and the rest of the second semiconductor layer is arranged on the dielectric layer to obtain a stacked body, wherein the first semiconductor layer includes a tin disulfide layer, and the second semiconductor layer includes a tin diselenide layer;

[0022] S50. After vacuum annealing the stacked body, a source electrode is disposed on the first semiconductor layer, a drain electrode is disposed on the second semiconductor layer, and a gate electrode is disposed on the conductive layer to obtain a tunneling field effect transistor.

[0023] In one embodiment, step S20 includes: after mechanically peeling off the graphene layer from the graphene crystal, transferring the graphene layer to the substrate, the graphene layer forming the conductive layer;

[0024] Step S30 includes: preparing a hexagonal boron nitride layer on polydimethylsiloxane by a mechanical stripping method, transferring the hexagonal boron nitride layer to a portion of the conductive layer by a dry transfer method, and the hexagonal boron nitride layer forms the dielectric layer;

[0025] Step S40 includes: disposing a first semiconductor layer on the dielectric layer, and disposing a second semiconductor layer on the first semiconductor layer and the dielectric layer;

[0026] In step S50, the vacuum annealing temperature is 100°C to 150°C, the heating time is 20 min to 30 min, and the heat preservation time is 30 min to 1 h;

[0027] The source electrode, the drain electrode, and the gate electrode are respectively disposed on the first semiconductor layer, the second semiconductor layer, and the conductive layer by evaporation.

[0028] The present invention further provides a photodetector, which includes the tunneling field effect transistor as described above, or a tunneling field effect transistor prepared by the method for preparing the tunneling field effect transistor as described above.

[0029] The technical solution of the present invention adopts a high-efficiency optoelectronic device based on a tin diselenide / tin disulfide cross-type van der Waals heterostructure to form a depletion region on the tin disulfide, effectively suppressing carrier recombination at the interface, and at the same time using a hexagonal boron nitride layer as a dielectric layer to obtain an atomic-level interface. The device has about 10 7 The on / off ratio is 240 nm and the ultra-high responsivity of 37.5 A / W is demonstrated, as well as the wide spectrum detection characteristics from ultraviolet to visible light, which is expected to become the next generation of high-efficiency optoelectronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 It is a schematic structural diagram of an embodiment of a tunneling field effect transistor in the present invention;

[0032] Figure 2 A schematic diagram of the device structure of graphene / hexagonal boron nitride / tin diselenide / tin disulfide in the tunneling field effect transistor provided in Example 1 of the present invention;

[0033] Figure 3 An optical microscope image of a graphene / hexagonal boron nitride / tin diselenide / tin disulfide device in a tunneling field effect transistor provided in Example 1 of the present invention;

[0034] Figure 4 An atomic force microscope image of a graphene / hexagonal boron nitride / tin diselenide / tin disulfide device in a tunneling field effect transistor provided in Example 1 of the present invention;

[0035] Figure 5The Raman spectra of tin diselenide, tin disulfide and tin diselenide / tin disulfide heterojunction in the tunneling field effect transistor provided in Example 1 of the present invention;

[0036] Figure 6 A transfer curve diagram of a graphene / hexagonal boron nitride / tin diselenide / tin disulfide device in a tunneling field effect transistor provided in Example 1 of the present invention;

[0037] Figure 7 An optical microscope image of a tin diselenide / tin disulfide device in a tunneling field effect transistor provided in Example 1 of the present invention;

[0038] Figure 8 A transfer curve diagram of a tin diselenide / tin disulfide device in a tunneling field effect transistor provided in Example 1 of the present invention at different bias voltages;

[0039] Fig. 9 A direct tunneling diagram of a graphene / hexagonal boron nitride / tin diselenide / tin disulfide device in a tunneling field effect transistor provided in Example 1 of the present invention;

[0040] Fig.10 This is a time response diagram of the graphene / hexagonal boron nitride / tin diselenide / tin disulfide device in the tunneling field effect transistor provided in Example 1 of the present invention at different wavelengths.

[0041] Description of Figure Numbers:

[0042] 100. Tunneling field effect transistor; 1. substrate; 2. insulating layer; 3. conductive layer; 4. dielectric layer; 5. heterostructure layer; 51. first semiconductor layer; 52. second semiconductor layer; 61. source electrode; 62. drain electrode; 63. gate electrode.

[0043] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0044] To make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them.

[0045] It should be noted that, in the embodiments, those without specifying specific conditions are carried out according to conventional conditions or conditions recommended by the manufacturer. Those without specifying the manufacturer of reagents or instruments used are conventional products that can be purchased commercially. In addition, the technical schemes between the various embodiments can be combined with each other, but must be based on the ability of ordinary technicians in the field to achieve. When the combination of the technical schemes is mutually contradictory or cannot be achieved, it should be considered that the combination of such technical schemes does not exist, and is not within the scope of protection required by the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present invention.

[0046] At present, the response speed of a single two-dimensional atomic crystal photoconductive detector can only reach the microsecond level or even the millisecond level, and the single material determines that the detection band is limited, which seriously restricts the application of two-dimensional materials in the field of photoelectric detection.

[0047] Two-dimensional materials have excellent properties such as atomic-level thickness, high surface area, and adjustable band gap related to thickness, which makes them show great application potential in fields such as nanoelectronics and optoelectronic devices. The van der Waals heterostructure layer formed by stacking different two-dimensional materials has three different band arrangements, which are divided into leaping type, staggered type and broken type. The leaping structure means that the conduction band and valence band of one material in the heterostructure layer are completely located within the conduction band and valence band of another material. In the leaping band structure, electrons and holes are confined in the same material, thereby reducing the possibility of their recombination at the interface, which is conducive to their efficient generation and collection under light or electromagnetic radiation. This efficient carrier collection mechanism can improve the response speed and sensitivity of the detector. At the same time, tin diselenide is an environmentally friendly material with n-type electronic characteristics and an electron concentration of about 10 18 cm -3 , and is heavily doped. Since tin and selenium are abundant on Earth and are inexpensive to obtain, and are extremely stable in the air, tin diselenide is expected to gain an important competitive advantage in the future electronics field. In addition, the carrier mobility in a single-layer tin disulfide device is about 50 cm 2 / V·s ~ 230 cm 2 / V·s, and it increases with the increase of channel thickness in SnS2 FETs. At the same time, its on / off current ratio can be as high as 10 6 ~ 10 8. Therefore, the heterojunction composed of tin diselenide and tin disulfide can obtain high carrier mobility and high current switching ratio. For the tin diselenide / tin disulfide heterojunction composed of a leaping band arrangement, electrons and holes can be spatially separated due to the band offset at the interface, which leads to the formation of interlayer excitons and thus the quenching of photoluminescence in its constituent layers, providing an opportunity to study vertical carrier diffusion. In short, the leaping band structure brings a series of performance advantages to photodetectors through its unique electron and hole confinement mechanism, including improved sensitivity, wider response range and improved stability, which makes it have broad application prospects in the field of high-performance photodetection.

[0048] The technical solution of the present invention adopts a high-efficiency optoelectronic device based on a tin diselenide / tin disulfide cross-type van der Waals heterojunction to form a depletion region on the tin disulfide, effectively suppressing the carrier recombination at the interface, and at the same time using hexagonal boron nitride as a dielectric layer to obtain an atomic-level interface. The device has about 10 7 The on / off ratio is 240 nm, and it exhibits an ultra-high responsivity of 37.5 A / W and a wide spectrum detection feature from ultraviolet to visible light, and is expected to become the next generation of high-efficiency optoelectronic devices.

[0049] In view of this, see Figure 1 The present invention provides a tunneling field effect transistor, comprising a substrate 1 and an insulating layer 2, and a conductive layer 3, a dielectric layer 4 and a heterostructure layer 5 stacked in sequence on the insulating layer 2, wherein the heterostructure layer 5 comprises a first semiconductor layer 51 and a second semiconductor layer 52, wherein the first semiconductor layer 51 is stacked on the dielectric layer 4, a portion of the second semiconductor layer 52 is stacked on the first semiconductor layer 51, and the other portion of the second semiconductor layer 52 is stacked on the dielectric layer 4, the first semiconductor layer 51 comprises a tin disulfide layer, and the second semiconductor layer 52 comprises a tin diselenide layer.

[0050] In one embodiment, the tunneling field effect transistor further includes a source electrode 61 , a drain electrode 62 and a gate electrode 63 , wherein the source electrode 61 is disposed on the first semiconductor layer 51 , the drain electrode 62 is disposed on the second semiconductor layer 52 , and the gate electrode 63 is disposed on the conductive layer 3 .

[0051] In one embodiment, the source electrode 61 , the drain electrode 62 , and the gate electrode 63 are made of a composite layer of a titanium layer and a gold layer.

[0052] The technical solution of the present invention adopts titanium and gold as electrode materials, wherein titanium has good adhesion and can improve the contact quality between the electrode and the semiconductor layer, and gold has excellent conductivity and chemical stability, which helps to reduce contact resistance and improve the conductivity of the electrode; the titanium and gold composite material electrode helps to optimize the carrier transmission path and reduce the energy loss during the carrier transmission process, thereby improving the response speed of the device; both metals have good thermal stability, can maintain good performance in a wider temperature range, and help to broaden the operating temperature range of the device.

[0053] In one embodiment, the thickness of the titanium layer is 5 nm; the thickness of the gold layer is 50 nm.

[0054] The technical solution of the present invention can provide sufficient adhesion without increasing excessive resistance by adopting titanium with a thickness of 5 nm; can ensure good conductivity while maintaining low contact resistance by adopting gold with a thickness of 50 nm; and can reduce costs while ensuring performance by precisely controlling the thickness of titanium and gold.

[0055] In one embodiment, the substrate 1 includes a silicon substrate 1; the insulating layer 2 includes a silicon dioxide layer; the conductive layer 3 includes a graphene layer; and the dielectric layer 4 includes a hexagonal boron nitride layer.

[0056] The technical solution of the present invention adopts a hexagonal boron nitride layer as the dielectric layer 4. Hexagonal boron nitride is a high-quality insulating material with excellent dielectric properties. It can effectively isolate the conductive layer 3 from the heterostructure layer 5, reduce unnecessary carrier recombination, and further improve the photoelectric conversion efficiency. By adopting a graphene layer as the conductive layer 3, graphene has extremely high electron mobility and good conductivity, which helps to accelerate the carrier transmission process and reduce energy loss during the transmission process. In addition, both hexagonal boron nitride and graphene have good stability and can withstand high mechanical stress, which helps to improve the reliability and durability of the tunneling field effect transistor.

[0057] In one embodiment, the thickness of the silicon dioxide layer is 285 nm to 300 nm; the thickness of the graphene layer is 8 nm to 15 nm; and the thickness of the hexagonal boron nitride layer is 10 nm to 20 nm.

[0058] The technical solution of the present invention uses a 10 nm to 20 nm thick hexagonal boron nitride layer as a high-quality insulating layer 2 to effectively isolate each layer, reduce unnecessary carrier recombination, and improve the photoelectric conversion efficiency; by using an 8 nm to 15 nm graphene layer, the graphene itself has extremely high electron mobility and good conductivity, which helps to accelerate the carrier transmission process and reduce energy loss during the transmission process; and by using 8 nm to 15 nm multilayer graphene to provide sufficient conductivity while maintaining low resistance. Compared with single-layer graphene, multilayer graphene can better disperse current and reduce local thermoelectric effects, thereby improving the overall photoelectric conversion efficiency; multilayer graphene can provide higher electron mobility, which helps to accelerate the carrier transmission process and reduce energy loss during the transmission process; multilayer graphene has better mechanical stability than single-layer graphene, can withstand higher mechanical stress, and helps to improve the reliability and durability of tunneling field effect transistors.

[0059] The present invention provides a method for preparing a tunneling field effect transistor, comprising the following steps:

[0060] S10. Providing a substrate 1 covered with an insulating layer 2;

[0061] S20. A conductive layer 3 is provided on one side of the substrate 1 covered with the insulating layer 2;

[0062] S30. Disposing a dielectric layer 4 on the conductive layer 3;

[0063] S40. A first semiconductor layer 51 and a second semiconductor layer 52 are disposed on the dielectric layer 4, wherein a portion of the first semiconductor layer 51 and a portion of the second semiconductor layer 52 are stacked, and the other portions are disposed on the dielectric layer 4 to obtain a stack, wherein the first semiconductor layer 51 includes a tin disulfide layer, and the second semiconductor layer 52 includes a tin diselenide layer;

[0064] S50. After vacuum annealing the stacked body, a source electrode 61 is disposed on the first semiconductor layer 51, a drain electrode 62 is disposed on the second semiconductor layer 52, and a gate electrode 63 is disposed on the conductive layer 3, thereby obtaining a tunneling field effect transistor.

[0065] The technical solution of the present invention forms a heterostructure layer 5 by stacking, and then deposits an electrode after annealing the heterostructure layer 5 to obtain a tunneling field effect transistor. Vacuum annealing can remove defects and impurities introduced in the manufacturing process, which helps to improve the quality of the material and the stability of the device. By designing different heterostructure layers 5, the operating wavelength range of the photodetector can be adjusted. Specifically, the operating wavelength range of the photodetector prepared according to the technical solution of the present invention is 365 nm~740 nm. By arranging the source electrode 61 on the tin disulfide layer, the drain electrode 62 on the tin diselenide layer, and the gate electrode 63 on the conductive layer 3, this layout can optimize the transmission path of the carrier and further accelerate the response speed.

[0066] In one embodiment, step S20 comprises: after mechanically peeling off the graphene layer from the graphene crystal, transferring the graphene layer to the substrate 1, the graphene layer forming the conductive layer 3;

[0067] Step S30 includes: preparing a hexagonal boron nitride layer on polydimethylsiloxane by mechanical stripping, transferring the hexagonal boron nitride layer onto a portion of the conductive layer 3 by dry transfer, and the hexagonal boron nitride layer forms the dielectric layer 4;

[0068] Step S40 includes: disposing the first semiconductor layer 51 on the dielectric layer 4, and disposing the second semiconductor layer 52 on the first semiconductor layer 51 and the dielectric layer 4;

[0069] In step S50, the vacuum annealing temperature is 100°C to 150°C, the heating time is 20 min to 30 min, and the heat preservation time is 30 min to 1 h;

[0070] The source electrode 61 , the drain electrode 62 , and the gate electrode 63 are respectively disposed on the first semiconductor layer 51 , the second semiconductor layer 52 , and the conductive layer 3 by evaporation.

[0071] The technical solution of the present invention can effectively remove defects and impurities introduced in the manufacturing process by adopting an annealing temperature of 100°C to 150°C; and can ensure uniform heating of the material by adopting reasonable heating time and holding time, which helps to release the internal stress of the material and improve the integrity of the material.

[0072] The present invention further provides a photodetector, which includes the tunneling field effect transistor as described above, or a tunneling field effect transistor prepared by the method for preparing the tunneling field effect transistor as described above.

[0073] Since the photoelectric detector adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0074] The technical solution of the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the following embodiments are only used to explain the present invention, and are not used to limit the present invention.

[0075] Example 1

[0076] This embodiment provides a tunneling field effect transistor, whose structure is as follows Figures 2 to 4 As shown, SnS 2 Refers to tin disulfide, SnSe 2 refers to tin diselenide, h-BN refers to hexagonal boron nitride, and graphene refers to graphene. The method for preparing the tunneling field effect transistor comprises the following steps:

[0077] 1. Mechanically peel off 8 nm~15 nm graphene onto a p-type doped silicon substrate with a 285 nm~300 nm thick silicon dioxide insulating layer on the surface, peel off a 10 nm~20 nm hexagonal boron nitride layer onto polydimethylsiloxane, transfer the hexagonal boron nitride onto part of the graphene by dry transfer, then transfer 10 nm~20 nm tin disulfide onto the hexagonal boron nitride, and then transfer 60 nm~80 nm tin diselenide onto part of the tin disulfide and hexagonal boron nitride, stacking to form a graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction;

[0078] 2. Place the stacked graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction in a vacuum annealing furnace for annealing. Control the vacuum annealing temperature to 100°C, the heating time to 30 mins, the holding time to 1 h, and cool to room temperature with the furnace.

[0079] 3. An electrode is constructed on the annealed graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction by first evaporating a titanium layer with a thickness range of 5 nm and then continuing to evaporate a gold layer with a thickness range of 50 nm.

[0080] Performance Testing

[0081] Using the tunneling field effect transistor provided in Example 1, Raman spectroscopy analysis was performed on tin diselenide, tin disulfide, and tin diselenide / tin disulfide heterojunction, respectively, to obtain Raman spectra of the tin diselenide / tin disulfide heterojunction and individual tin diselenide and tin disulfide. Figure 5 shown.

[0082] See also Figure 5 For tin diselenide, two main peaks can be observed; as for tin disulfide, its Raman spectrum shows one main peak; in the tin diselenide / tin disulfide heterojunction, due to interface coupling, all Raman peaks in the overlapping area have an obvious quenching effect.

[0083] The transfer curve of the tunneling field effect transistor provided in Example 1 is characterized by using a Keithley 2636B semiconductor parameter analyzer to perform IV testing, and the transfer curve of the tunneling field effect transistor is as shown in FIG. Figure 6 shown.

[0084] according to Figure 6 It can be seen that in the present invention, the switching ratio of the graphene / hexagonal boron nitride / tin diselenide / tin disulfide heterostructure layer is as high as 10 7 At a source-drain voltage of 1 volt, the source-drain current I ds Reach 0.1 μA (the position indicated by the gray ball in the figure).

[0085] In the present invention, the optical microscope image of the tin diselenide / tin disulfide device is as follows: Figure 7 As shown, the dielectric layer is silicon dioxide, the conductive substrate is silicon, and the transfer curve is Figure 8 As shown, at a bias of 50 V, the current only reaches 10 -7 A, and Figure 6 It shows that when the bias voltage is 4 V, the current has reached 10 -5 A, showing that the hexagonal boron nitride dielectric layer and graphene electrode significantly improve the device performance.

[0086] Fig. 9 The tunneling behavior of the graphene / hexagonal boron nitride / tin diselenide / tin disulfide device is shown. In general, at lower voltages, direct tunneling is dominant, while at higher voltages, Fowler-Nordheim tunneling becomes the dominant mechanism. According to the fitting diagram, ln(I / V 2 ) is linearly correlated with ln(1 / V), indicating that direct tunneling is the dominant mechanism.

[0087] like Fig.10 As shown in the figure, the photoelectric performance of the device was characterized and the time-dependent photoresponse performance was evaluated. As the wavelength of light decreased from 740 nm to 365 nm, the photocurrent increased significantly from 27 nA to 62 nA. Due to the light-induced band alignment regulation, the tin diselenide / tin disulfide device exhibited broadband detection characteristics and reached a maximum value at 365 nm.

[0088] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A tunneling field effect transistor, characterized in that: The invention comprises a substrate and an insulating layer, and a conductive layer, a dielectric layer and a heterogeneous structure layer stacked on the insulating layer in sequence, wherein the heterogeneous structure layer comprises a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer is stacked on the dielectric layer, a part of the second semiconductor layer is stacked on the first semiconductor layer, and the other part of the second semiconductor layer is stacked on the dielectric layer, wherein the first semiconductor layer comprises a tin disulfide layer, and the second semiconductor layer comprises a tin diselenide layer; The tunneling field effect transistor further comprises a source electrode, a drain electrode and a gate electrode, wherein the source electrode is disposed on the first semiconductor layer, the drain electrode is disposed on the second semiconductor layer, and the gate electrode is disposed on the conductive layer; Wherein, the conductive layer includes a graphene layer, and the dielectric layer includes a hexagonal boron nitride layer.

2. The tunneling field effect transistor according to claim 1, characterized in that: The source electrode, the drain electrode and the gate electrode are made of a composite layer of a titanium layer and a gold layer.

3. The tunneling field effect transistor according to claim 2, characterized in that: The thickness of the titanium layer is 5 nm; The thickness of the gold layer is 50 nm.

4. The tunneling field effect transistor according to claim 1, characterized in that: The substrate comprises a silicon substrate; The insulating layer includes a silicon dioxide layer.

5. The tunneling field effect transistor according to claim 4, characterized in that: The thickness of the silicon dioxide layer is 285 nm to 300 nm; The thickness of the graphene layer is 8 nm to 15 nm; The thickness of the hexagonal boron nitride layer is 10 nm to 20 nm.

6. A method for preparing a tunneling field effect transistor according to any one of claims 1 to 5, characterized in that: The following steps are involved: S10. Providing a substrate covered with an insulating layer; S20. Disposing a conductive layer on one side of the substrate covered with an insulating layer; S30. Disposing a dielectric layer on the conductive layer; S40. Arranging a first semiconductor layer and a second semiconductor layer on the dielectric layer, a portion of the first semiconductor layer and a portion of the second semiconductor layer are stacked, and the rest of the second semiconductor layer is arranged on the dielectric layer to obtain a stacked body, wherein the first semiconductor layer includes a tin disulfide layer, and the second semiconductor layer includes a tin diselenide layer; S50. After vacuum annealing the stacked body, a source electrode is disposed on the first semiconductor layer, a drain electrode is disposed on the second semiconductor layer, and a gate electrode is disposed on the conductive layer to obtain a tunneling field effect transistor.

7. The method for preparing a tunneling field effect transistor according to claim 6, characterized in that: Step S20 includes: after mechanically peeling off the graphene layer from the graphene crystal, transferring the graphene layer to the insulating layer, the graphene layer forming the conductive layer; Step S30 includes: preparing a hexagonal boron nitride layer on polydimethylsiloxane by a mechanical stripping method, transferring the hexagonal boron nitride layer to a portion of the conductive layer by a dry transfer method, and the hexagonal boron nitride layer forms the dielectric layer; Step S40 includes: disposing a first semiconductor layer on the dielectric layer, and disposing a second semiconductor layer on the first semiconductor layer and the dielectric layer; In step S50, the vacuum annealing temperature is 100°C~150°C, the heating time is 20 min~30 min, and the holding time is 30 min~1 h; the source electrode, the drain electrode and the gate electrode are respectively arranged on the first semiconductor layer, the second semiconductor layer and the conductive layer by evaporation.

8. A photoelectric detector, characterized in that: The photodetector comprises a tunneling field effect transistor as claimed in any one of claims 1 to 5, or a tunneling field effect transistor prepared by the method for preparing a tunneling field effect transistor as claimed in any one of claims 6 to 7.

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