A high voltage bandgap reference circuit for wide input voltage range LDO

Abstract

The application discloses a high-voltage bandgap reference circuit for a wide input voltage range LDO, and relates to the technical field of integrated circuits.The high-voltage bandgap reference circuit comprises a starting circuit, a bandgap core circuit and a feedback circuit.The starting circuit comprises PMOS tubes PM3, PM4 and PM5, NMOS tubes NM1, NM2, NM3 and NM4 and resistors R7, R8, R9 and R10.The bandgap core circuit comprises PMOS tubes PM1 and PM2, NPN tubes Q1 and Q2 and resistors R1, R2, R3 and R4.The feedback circuit comprises PMOS tubes PM6, PM7, PM8, PM9 and PM10, NMOS tubes NM5, NM6, NM7 and NM8 and resistors R5 and R6.The high-voltage bandgap reference circuit for the wide input voltage range LDO has the advantages of low power consumption, high precision and small layout area, and can provide a high-precision reference voltage and a stable low-voltage power supply rail for the wide input voltage range LDO.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to a high-voltage bandgap reference circuit for LDOs with a wide input voltage range. Background Technology

[0002] Low dropout regulators (LDOs) are an important type of power management circuit, widely used in consumer electronics, medical electronics, and automotive electronics. The input range of an LDO determines its different application areas; a wider input voltage range means broader applications and a larger market. With the continuous development of consumer electronics and automotive electronics, the demand for LDOs with wide input ranges is increasing. The bandgap reference circuit, as one of the key modules of an LDO, provides a high-precision reference voltage for the internal circuitry. The specifications of the bandgap reference circuit largely determine the performance of the entire LDO chip. Therefore, designing a high-voltage-resistant, high-performance bandgap reference is of great significance for applications requiring wide input voltage range LDOs.

[0003] Wide input voltage range LDOs can withstand input voltages up to tens of volts, therefore the bandgap reference module needs to be able to withstand input voltages of tens of volts and still provide an accurate reference voltage under high input voltages. The core circuit of a traditional high-voltage bandgap reference is as follows: Figure 2 As shown, this is mainly achieved by using high-voltage LDMOS transistors in each branch of the bandgap reference circuit. M1 and M2 are LDMOS transistors, and this circuit can withstand high input voltages. However, high-voltage LDMOS transistors have poor matching, which causes unequal currents flowing through transistors Q1 and Q2, resulting in a large deviation in the bandgap reference output voltage and affecting the accuracy of the reference voltage. In addition, LDMOS transistors are much larger than ordinary MOS transistors and consume more power, which significantly increases the circuit area and power consumption.

[0004] Another traditional high-voltage bandgap reference circuit topology is as follows: Figure 3 As shown, the high input voltage V is first regulated by a pre-regulator circuit. IN Converted to an internally stable low-voltage power rail V O1The low-voltage power rail serves as the power supply voltage for the bandgap reference circuit, allowing for a low-voltage circuit structure. In this structure, the pre-regulator module can be implemented in two ways: The first method uses a Zener diode operating in reverse breakdown to generate a stable low-voltage power rail. In this state, the Zener diode generates a stable voltage reference source through a large reverse breakdown current. This approach is difficult and costly to fabricate in semiconductor technology, and consumes a significant amount of power, greatly increasing the overall chip power consumption and making it unsuitable for current low-power requirements. The second method uses a coarse reference and a first-stage LDO to generate a stable low-voltage power rail to power the bandgap reference and second-stage LDO modules. This method significantly increases the complexity of the circuit design, as well as the overall chip layout area and power consumption. Therefore, a high-voltage bandgap reference circuit for LDOs with a wide input voltage range is proposed. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a high-voltage bandgap reference circuit for LDOs with a wide input voltage range, solving the problems mentioned in the background section.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a high-voltage bandgap reference circuit for LDOs with a wide input voltage range, comprising a startup circuit, a bandgap core circuit, and a feedback circuit; the startup circuit comprises PMOS transistors PM3, PM4, and PM5, NMOS transistors NM1, NM2, NM3, and NM4, and resistors R7, R8, R9, and R10; the bandgap core circuit comprises PMOS transistors PM1 and PM2, NPN transistors Q1 and Q2, and resistors R1, R2, R3, and R4; the feedback circuit comprises PMOS transistors PM6, PM7, PM8, PM9, and PM10, NMOS transistors NM5, NM6, NM7, and NM8, and resistors R5 and R6.

[0007] Optionally, NM1 is electrically connected to R8, R8 is electrically connected to NM2, NM2 is electrically connected to R9, R9 is electrically connected to PM3, PM8 is electrically connected to R7, R7 is electrically connected to NM1, PM3 is electrically connected to PM4, PM4 is electrically connected to PM5, PM5 is electrically connected to NM3, and NM3 is electrically connected to Q3.

[0008] Optionally, PM6 is electrically connected to PM4, PM6 is electrically connected to PM8, PM8 is electrically connected to NM5, NM5 is electrically connected to NM7, NM5 is electrically connected to NM6, PM6 is electrically connected to PM7, PM7 is electrically connected to PM9, NM7 is electrically connected to NM8, NM8 is electrically connected to PM10, PM10 is electrically connected to R10, R10 is electrically connected to NM4, NM7 is electrically connected to VREV, R10 is electrically connected to VOI, and VOI and VREV are electrically connected via R6.

[0009] Optionally, PM9 is electrically connected to R3, R3 is electrically connected to PM1, PM1 is electrically connected to PM2, PM2 is electrically connected to Q2, PM1 is electrically connected to Q1, Q1 is electrically connected to R1, R1 is electrically connected to R2, R2 is electrically connected to Q2, and PM10 is electrically connected to both Q2 and PM2.

[0010] Optionally, the startup circuit operates at an input voltage V. IN Upon power-up, the bandgap core circuit is removed from its degeneracy point. The specific process is as follows: The bias circuit composed of R7, R8, NM1, and NM2 can generate a bias current independent of the power supply voltage. :

[0011] (1)

[0012] Current is measured using a current mirror. The circuit is copied to the branch containing PM4 and PM5. When PM4 and PM5 are turned on, they pull up the gate voltage of NM3, which in turn pulls up the gate voltage of NM4. NM4 is turned on, and current flows through R5, generating a voltage drop across R5. This voltage allows the bandgap core circuit to escape the zero-current state and begin normal operation. Rise to At this time, NM4 shuts down, completing the startup process.

[0013] Optionally, the bandgap core circuit adopts an op-amp-less structure. This structure not only reduces the impact of the operational amplifier's offset voltage on the circuit output but also reduces the current consumed by the bandgap reference module. Assuming the width-to-length ratio of PMOS transistors PM1 and PM2 is 1:1, the current mirror formed by PM1 and PM2 ensures that the currents flowing through Q1 and Q2 are equal, i.e., I... C1 =I C2 If the area ratio of bipolar transistors Q1 and Q2 is 8:1, then the ratio of their reverse saturation currents is also 8:1, i.e., I0. S1 = 8I S2 .but As shown below:

[0014] (2)

[0015] The collector current flowing through transistor Q1 is shown below:

[0016] (3)

[0017] Since the collector currents flowing through Q1 and Q2 are equal, the current flowing through resistor R2 is twice the collector current of Q1. Bandgap reference voltage V REF for:

[0018] (4)

[0019] in, It is a voltage with a negative temperature coefficient. Since it is a voltage with a positive temperature coefficient, a suitable... By calculating the ratio, we can obtain an output reference voltage with zero temperature coefficient.

[0020] Optionally, the feedback circuit includes PMOS transistors PM6-PM10, NMOS transistors NM5-NM8, and resistors R5 and R6. The feedback circuit can improve the accuracy of the bandgap reference output voltage and increase the power supply rejection ratio. The size ratio of PM10 to PM1 is M:1. A suitable bias current is set so that I... PM10 :I PM1 =M:1, when the resistances of R3 and R4 are very small, the voltage drop across them can be ignored. This makes the potentials at points X and Y equal, meaning the drain potentials of the PMOS current mirror are equal, improving the matching of the current mirror and ensuring that the collector currents flowing through transistors Q1 and Q2 are equal, further improving the accuracy of the bandgap reference output voltage.

[0021] This invention provides a high-voltage bandgap reference circuit for LDOs with a wide input voltage range, which has the following advantages:

[0022] This high-voltage bandgap reference circuit for wide-input-voltage-range LDOs can operate directly within a wide input voltage range. It generates a stable internal low-voltage power rail through a feedback circuit, replacing the pre-regulator circuit in traditional solutions. It offers advantages such as simple circuit structure and low power consumption. The core bandgap circuit operates on the internal low-voltage power rail and uses a low-voltage current mirror instead of the high-voltage LDMOS current mirror in traditional solutions. This provides advantages such as high matching accuracy, low power consumption, and small layout area. Source degradation technology is introduced to reduce the offset voltage of the current mirror in the core bandgap circuit, and a feedback circuit improves the matching of the current mirror, ensuring that the collector currents flowing through transistors Q1 and Q2 are equal, further improving the accuracy of the bandgap reference output voltage. Furthermore, the feedback structure effectively improves the power supply rejection performance of the bandgap reference circuit, offering advantages such as low power consumption, high accuracy, and small layout area. It can provide a high-precision reference voltage and a stable low-voltage power rail for wide-input-voltage-range LDOs. Attached Figure Description

[0023] Figure 1 This is a high-voltage bandgap reference circuit diagram of the present invention;

[0024] Figure 2 This is a core structural diagram of a traditional high-voltage bandgap reference according to the present invention;

[0025] Figure 3 This is a circuit topology diagram of another conventional high-voltage bandgap reference according to the present invention;

[0026] Figure 4 The internal power rail V of this invention O1 With input voltage V IN The change graph;

[0027] Figure 5 For different input voltages of this invention, the reference voltage V REF Temperature coefficient diagram. Detailed Implementation

[0028] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0029] Please see Figures 1 to 5This invention provides a technical solution: a high-voltage bandgap reference circuit for LDOs with a wide input voltage range, comprising a startup circuit, a bandgap core circuit, and a feedback circuit; the startup circuit includes PMOS transistors PM3, PM4, and PM5, NMOS transistors NM1, NM2, NM3, and NM4, and resistors R7, R8, R9, and R10; the bandgap core circuit includes PMOS transistors PM1 and PM2, NPN transistors Q1 and Q2, and resistors R1, R2, R3, and R4; the feedback circuit includes PMOS transistors PM6, PM7, PM8, PM9, and PM10, NMOS transistors NM5, NM6, NM7, and NM8, and resistors R5 and R6.

[0030] NM1 is electrically connected to R8, R8 is electrically connected to NM2, NM2 is electrically connected to R9, R9 is electrically connected to PM3, PM8 is electrically connected to R7, R7 is electrically connected to NM1, PM3 is electrically connected to PM4, PM4 is electrically connected to PM5, PM5 is electrically connected to NM3, and NM3 is electrically connected to Q3.

[0031] PM6 is electrically connected to PM4, PM6 is electrically connected to PM8, PM8 is electrically connected to NM5, NM5 is electrically connected to NM7, NM5 is electrically connected to NM6, PM6 is electrically connected to PM7, PM7 is electrically connected to PM9, NM7 is electrically connected to NM8, NM8 is electrically connected to PM10, PM10 is electrically connected to R10, R10 is electrically connected to NM4, NM7 is electrically connected to VREV, R10 is electrically connected to VOI, and VOI and VREV are electrically connected via R6.

[0032] PM9 is electrically connected to R3, R3 is electrically connected to PM1, PM1 is electrically connected to PM2, PM2 is electrically connected to Q2, PM1 is electrically connected to Q1, Q1 is electrically connected to R1, R1 is electrically connected to R2, R2 is electrically connected to Q2, and PM10 is electrically connected to both Q2 and PM2.

[0033] The startup circuit operates at an input voltage V. IN Upon power-up, the bandgap core circuit is removed from its degeneracy point. The specific process is as follows: The bias circuit composed of R7, R8, NM1, and NM2 can generate a bias current independent of the power supply voltage. :

[0034] (1)

[0035] Current is measured using a current mirror. The circuit is copied to the branch containing PM4 and PM5. When PM4 and PM5 are turned on, they pull up the gate voltage of NM3, which in turn pulls up the gate voltage of NM4. NM4 is turned on, and current flows through R5, generating a voltage drop across R5. This voltage allows the bandgap core circuit to escape the zero-current state and begin normal operation. Rise to At this time, NM4 shuts down, completing the startup process.

[0036] The bandgap core circuit employs an op-amp-less structure. This structure not only reduces the impact of the operational amplifier's offset voltage on the circuit output but also reduces the current consumed by the bandgap reference module. Assuming the width-to-length ratio of PMOS transistors PM1 and PM2 is 1:1, the current mirror formed by PM1 and PM2 ensures that the currents flowing through Q1 and Q2 are equal, i.e., I... C1 =I C2 If the area ratio of bipolar transistors Q1 and Q2 is 8:1, then the ratio of their reverse saturation currents is also 8:1, i.e., I0. S1 = 8I S2 .but As shown below:

[0037] (2)

[0038] The collector current flowing through transistor Q1 is shown below:

[0039] (3)

[0040] Since the collector currents flowing through Q1 and Q2 are equal, the current flowing through resistor R2 is twice the collector current of Q1. Bandgap reference voltage V REF for:

[0041] (4)

[0042] in, It is a voltage with a negative temperature coefficient. Since it is a voltage with a positive temperature coefficient, a suitable... By calculating the ratio, we can obtain an output reference voltage with zero temperature coefficient.

[0043] The current mirror composed of PM1 and PM2 introduces source degradation technology, which is achieved by adding resistors R3 and R4 in series with the source of the MOS device. Resistors R3 and R4 have equal values, and they increase the power supply rejection ratio by reducing the channel length modulation effect and noise interference. In addition, they improve the accuracy of the bandgap reference voltage by reducing the offset voltage of MP1 and MP2.

[0044] The feedback circuit includes PMOS transistors PM6-PM10, NMOS transistors NM5-NM8, and resistors R5 and R6. The feedback circuit improves the accuracy of the bandgap reference output voltage and increases the power supply rejection ratio. The size ratio of PM10 to PM1 is M:1. A suitable bias current is set so that I... PM10 :I PM1 =M:1, when the resistances of R3 and R4 are very small, the voltage drop across them can be ignored. This makes the potentials at points X and Y equal, meaning the drain potentials of the PMOS current mirror are equal, improving the matching of the current mirror and ensuring that the collector currents flowing through transistors Q1 and Q2 are equal, further improving the accuracy of the bandgap reference output voltage.

[0045] Resistors R5 and R6 are related to V O1 The voltage is clamped, causing V O1 The voltage is:

[0046] (5)

[0047] It can be seen that after the bandgap core circuit stabilizes, it will generate a voltage that does not change with the input voltage V. IN Varying low-voltage power rail V O1 This provides power to the bandgap core circuit, allowing the current mirror composed of PM1 and PM2 to use low-voltage MOSFETs, resulting in higher matching performance. This solves the problem of poor matching performance in current mirrors composed of high-voltage LDMOS transistors. Furthermore, the low-voltage power rail V... O1 It can also power the main error amplifier of the subsequent LDO.

[0048] right Figure 1 The circuit was modeled using Virtuoso on the Cadence platform and verified using Spectre simulation. Figure 4 The internal power rail V generated for this invention O1 With input voltage V IN The relationship between the input voltage V and the input voltage V. IN The simulation was set to scan from 5V to 36V, with GND set to 0V. The simulation results show that V IN When the voltage is 5-36V, V O1 The change was only 259.2 uV, V O1 Almost unaffected by input voltage V IN Change, V O1 It can be used as an internally stable low-voltage power rail for power supply.

[0049] Figure 5 The output reference voltage V of this invention REF The temperature coefficient, where the input voltage V INWith 32 different voltage combinations ranging from 5V to 36V and GND set to 0V, the circuit was scanned within a temperature range of -40℃ to 85℃. The simulation results show that, across the entire temperature range, the fluctuation range of the reference voltage under different input voltages is 1.15 mV to 1.19 mV, and the temperature coefficient is 7.59 ppm / ℃ to 7.85 ppm / ℃. The temperature coefficient is very small, meeting the design specifications of the bandgap reference circuit.

[0050] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A high voltage bandgap reference circuit for a wide input voltage range LDO, characterized by: The application relates to a bandgap voltage reference circuit, which comprises a starting circuit, a bandgap core circuit and a feedback circuit; the starting circuit comprises PMOS tubes PM3, PM4 and PM5, NMOS tubes NM1, NM2, NM3 and NM4 and resistors R7, R8, R9 and R10; the bandgap core circuit comprises PMOS tubes PM1 and PM2, NPN tubes Q1 and Q2 and resistors R1, R2, R3 and R4; and the feedback circuit comprises PMOS tubes PM6, PM7, PM8, PM9 and PM10, NMOS tubes NM5, NM6, NM7 and NM8 and resistors R5 and R6. The NM1 is electrically connected with the R8, the R8 is electrically connected with the NM2, the NM2 is electrically connected with the R9, the R9 is electrically connected with the PM3, the PM8 is electrically connected with the R7, the R7 is electrically connected with the NM1, the PM3 is electrically connected with the PM4, the PM4 is electrically connected with the PM5, the PM5 is electrically connected with the NM3, and the NM3 is electrically connected with the Q3. The PM6 is electrically connected with the PM4, the PM6 is electrically connected with the PM8, the PM8 is electrically connected with the NM5, the NM5 is electrically connected with the NM7, the NM5 is electrically connected with the NM6, the PM6 is electrically connected with the PM7, the PM7 is electrically connected with the PM9, the NM7 is electrically connected with the NM8, the NM8 is electrically connected with the PM10, the PM10 is electrically connected with the R10, the R10 is electrically connected with the NM4, the NM7 is electrically connected with the VREV, the R10 is electrically connected with the VOI, and the VOI and the VREV are electrically connected through the R6. The PM9 is electrically connected with the R3, the R3 is electrically connected with the PM1, the PM1 is electrically connected with the PM2, the PM2 is electrically connected with the Q2, the PM1 is electrically connected with the Q1, the Q1 is electrically connected with the R1, the R1 is electrically connected with the R2, the R2 is electrically connected with the Q2, the PM10 is electrically connected with the Q2 and the PM2.

2. The high voltage bandgap reference circuit for wide input voltage range LDO according to claim 1, wherein: The starting circuit is in input voltage V IN The degenerate point is removed from the band gap core circuit at power-up, and the specific process is as follows: the bias circuit composed of R7, R8, NM1 and NM2 can generate a bias current independent of the power supply voltage : （1） Current is copied to the branch where PM4, PM5 are located by current mirror PM4, PM5 are turned on, NM3 gate voltage is pulled up, NM4 gate voltage is pulled up, NM4 is turned on, current flows through R5, voltage drop is generated on R5, the voltage makes the bandgap core circuit get out of zero current state and start normal work, when NM4 is turned off, the starting process is completed. ​ 3. The high voltage bandgap reference circuit for wide input voltage range LDO according to claim 1, wherein: The bandgap core circuit adopts a non-operational amplifier structure, which not only reduces the influence of the offset voltage of the operational amplifier on the circuit output, but also reduces the current consumed by the bandgap reference module. Assuming that the width-length ratio of the PMOS tubes PM1 and PM2 is 1:1, the current mirror formed by PM1 and PM2 makes the currents flowing through Q1 and Q2 equal, that is, I C1 =I C2 , the area ratio of the bipolar transistors Q1 and Q2 is 8:1, and the reverse saturation current ratio of Q1 and Q2 is 8:1, that is, I S1 = 8I S2 , so As follows: （2） The collector current flowing through the triode Q1 is shown as follows: （3） Since the collector currents through Ql and Q2 are equal, the current through resistor R2 is twice the collector current of Ql, and the bandgap reference voltage V REF is: （4） where is a negative temperature coefficient voltage, is a positive temperature coefficient voltage, so by choosing the proper ratio, a zero temperature coefficient output reference voltage is obtained.

4. The high voltage bandgap reference circuit for wide input voltage range LDO according to claim 1, wherein: The feedback circuit comprises PMOS tubes PM6-PM10, NMOS tubes NM5-NM8 and resistors R5 and R6, can improve the precision of the band gap reference output voltage and the power supply rejection ratio, the size ratio of PM10 to PM1 is M:1, a proper bias current is set, and I PM10 : PM1 =M:1, the voltage drops on R3 and R4 can be ignored when the resistance values of R3 and R4 are very small, then , the potential at X point is equal to that at Y point, i.e. the drain potentials of the PMOS current mirror are equal, the matching of the current mirror is improved, the collector currents flowing through the triodes Q1 and Q2 are equal, and the precision of the band gap reference output voltage is further improved.

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