Chip damage determination method, device, electronic device, storage medium and product

Abstract

The present invention discloses a chip damage judgment method, device, electronic device, storage medium and product, which are applied to the hardware field and are used to solve the problem of inaccurate chip damage judgment in traditional technologies. The method is applied to a baseboard management controller, the baseboard management controller is connected to a programmable logic device, the programmable logic device is connected to a preset pin of a main controller, and the main controller is connected to a basic input and output system storage chip. The method comprises: when a power-on signal is received, the pin state of the preset pin in the main controller is obtained through the programmable logic device; whether the pin state is a preset state, the preset state is set by the basic input and output system storage chip when the power-on signal is received; if it is the preset state, the chip is not damaged; if it is not the preset state, whether the chip information of the basic input and output system storage chip can be read; if the chip information can be read, the chip is not damaged; if the chip information cannot be read, the chip is damaged.

Description

Technical Field

[0001] The present invention relates to the field of hardware technology, and in particular to a chip damage determination method, and also to a chip damage determination device, electronic equipment, computer-readable storage medium, and computer program product. Background Art

[0002] The BIOS Flash chip (Basic Input Output System Flash) is a high-speed non-volatile memory used to store firmware programs, namely BIOS code. If there is a problem with the BIOS code, the device will not be able to start normally. Therefore, major manufacturers will conduct full-function tests on the BIOS before leaving the factory to ensure the stability and security of the BIOS software. However, since the server needs to go through multiple steps such as packaging, loading, transportation, unloading, loading, and power-on deployment from the factory to the user's laboratory, hardware damage often occurs. When the BIOS Flash chip hardware is damaged, the server will not be able to enter the system and work normally because the BIOS software code cannot run normally, which brings immeasurable losses to both users and server manufacturers.

[0003] In the related art, in order to identify whether the BIOS Flash chip is damaged, it is mainly determined whether the device enters the system normally within the specified time. If the device still fails to enter the system after the preset time, the BIOS Flash chip is considered damaged. However, this implementation scheme is simple and crude, and cannot distinguish whether the hardware circuit of the BIOS Flash chip is really damaged. If the hardware circuit is not damaged, but the server cannot be turned on due to a BIOS software code failure, the BIOS Flash chip is wasted and the cost is increased. At the same time, the bug of the BIOS software code is concealed, which poses a hidden danger to the stability of the server.

[0004] Therefore, how to achieve more accurate chip damage determination is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] An object of the present invention is to provide a chip damage determination method, which can achieve more accurate chip damage determination; another object of the present invention is to provide a chip damage determination device, an electronic device, a computer-readable storage medium and a computer program product, all of which have the above-mentioned beneficial effects.

[0006] In a first aspect, the present invention provides a chip damage determination method, which is applied to a baseboard management controller, wherein the baseboard management controller is connected to a programmable logic device, wherein the programmable logic device is connected to a preset pin of a main controller, and wherein the main controller is connected to a basic input and output system storage chip, wherein the method comprises:

[0007] When a power-on signal is received, obtaining the pin state of the preset pin in the main controller through the programmable logic device;

[0008] Determining whether the pin state is a preset state, wherein the preset state is set by the basic input and output system storage chip when receiving the power-on signal;

[0009] If the pin state is the preset state, it is determined that the basic input and output system storage chip is not damaged;

[0010] If the pin state is not the preset state, determining whether the chip information of the basic input and output system storage chip can be read;

[0011] If the chip information can be read, it is determined that the basic input and output system storage chip is not damaged;

[0012] If the chip information cannot be read, it is determined that the basic input and output system storage chip is damaged.

[0013] Wherein, obtaining the pin status of the preset pin in the main controller through the programmable logic device includes:

[0014] Acquiring a power signal of the main controller;

[0015] Determining whether the power signal is valid;

[0016] When the power signal is valid, obtaining the pin state of the preset pin in the main controller through the programmable logic device;

[0017] When the power signal is invalid, an alarm prompt is output.

[0018] Among them, the output alarm prompts include:

[0019] Determine whether the current power-on duration reaches a first preset duration;

[0020] If the current power-on duration does not reach the first preset duration, returning to execute obtaining the power signal of the main controller;

[0021] If the current power-on duration reaches the first preset duration, the alarm prompt is output.

[0022] Wherein, when the power signal is valid, the step of acquiring the pin state of the preset pin in the main controller through the programmable logic device includes:

[0023] When the power signal is valid, the timer starts timing;

[0024] When the timing time of the timer reaches a second preset time length, the step of acquiring the pin state of the preset pin in the main controller through the programmable logic device is executed.

[0025] Wherein, judging whether the power signal is valid includes:

[0026] Determining whether the power signal is at a high level;

[0027] If the power signal is at a high level, determining that the power signal is valid;

[0028] If the power signal is not at a high level, it is determined that the power signal is invalid.

[0029] The baseboard management controller is connected to the programmable logic device via an I2C bus, and obtaining the pin status of the preset pin in the main controller via the programmable logic device includes:

[0030] The pin status of the preset pin in the main controller is obtained by reading the register of the programmable logic device through the I2C bus; the pin status of the preset pin is obtained in real time by the programmable logic device and written into the register.

[0031] The step of determining whether the pin state is a preset state, wherein the preset state is set by the basic input / output system storage chip when receiving the power-on signal, includes:

[0032] Determine whether the pin state is in a low level state; wherein the initial state of the preset pin is a high level state, and the low level state is obtained by the basic input and output system storage chip inverting the initial state of the preset pin when receiving the power-on signal;

[0033] If the pin state is in a low level state, determining that the pin state is the preset state;

[0034] If the pin state is not in a low level state, it is determined that the pin state is not the preset state.

[0035] The step of determining whether the chip information of the basic input / output system storage chip can be read includes:

[0036] Controlling the current device to enter a shutdown state, so as to disconnect the basic input and output system storage chip from the main controller and connect the basic input and output system storage chip to the baseboard management controller;

[0037] It is determined whether the chip information of the basic input and output system storage chip can be read through the connection relationship between the basic input and output system storage chip and the baseboard management controller.

[0038] The basic input / output system storage chip is connected to the main controller via a serial peripheral interface bus, and the current device is controlled to enter a shutdown state to disconnect the basic input / output system storage chip from the main controller, and the basic input / output system storage chip is connected to the baseboard management controller, including:

[0039] The current device is controlled to enter a shutdown state, so as to switch the serial peripheral interface bus of the basic input / output system storage chip from being connected to the main controller to being connected to the baseboard management controller.

[0040] Wherein, when it is determined that the basic input and output system storage chip is damaged, the method further includes:

[0041] A chip switching command is sent to the programmable logic device, so that the programmable logic device switches the basic input and output system storage chip to a spare basic input and output system storage chip.

[0042] Wherein, after sending a chip switching command to the programmable logic device so that the programmable logic device switches the basic input and output system storage chip to the spare basic input and output system storage chip, the method further includes:

[0043] The standby BIOS storage chip is controlled to start up, so that the standby BIOS storage chip acquires the file data in the BIOS storage chip and synchronizes the file data to a local device.

[0044] In a second aspect, the present invention further discloses a chip damage determination device, which is applied to a baseboard management controller, wherein the baseboard management controller is connected to a programmable logic device, wherein the programmable logic device is connected to a preset pin of a main controller, and wherein the main controller is connected to a basic input and output system storage chip, wherein the device comprises:

[0045] An acquisition module, configured to acquire the pin state of the preset pin in the main controller through the programmable logic device when a power-on signal is received;

[0046] A first determination module, used for determining whether the pin state is a preset state, wherein the preset state is set by the basic input and output system storage chip when receiving the power-on signal;

[0047] A first determination module, configured to determine that the basic input / output system storage chip is not damaged if the pin state is the preset state;

[0048] A second judgment module, used for judging whether the chip information of the basic input and output system storage chip can be read if the pin state is not the preset state;

[0049] A second determination module, configured to determine that the basic input and output system storage chip is not damaged if the chip information can be read;

[0050] The third determination module is used to determine that the basic input and output system storage chip is damaged if the chip information cannot be read.

[0051] In a third aspect, the present invention further discloses an electronic device, comprising:

[0052] Memory for storing computer programs;

[0053] A processor is used to implement the steps of any one of the chip damage determination methods described above when executing the computer program.

[0054] In a fourth aspect, the present invention further discloses a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any one of the chip damage determination methods described above are implemented.

[0055] In a fifth aspect, the present invention further discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of any one of the chip damage determination methods described above.

[0056] The present invention provides a chip damage judgment method, which is applied to a baseboard management controller, wherein the baseboard management controller is connected to a programmable logic device, which is connected to a preset pin of a main controller, and the main controller is connected to a basic input / output system storage chip. The method comprises: when a power-on signal is received, obtaining the pin state of the preset pin in the main controller through the programmable logic device; judging whether the pin state is a preset state, wherein the preset state is set by the basic input / output system storage chip when the power-on signal is received; if the pin state is the preset state, determining that the basic input / output system storage chip is not damaged; if the pin state is not the preset state, judging whether the chip information of the basic input / output system storage chip can be read; if the chip information can be read, determining that the basic input / output system storage chip is not damaged; if the chip information cannot be read, determining that the basic input / output system storage chip is damaged.

[0057] By applying the technical solution provided by the present invention, a programmable logic device is added between the baseboard management controller and the main controller, and the damage judgment of the basic input and output system storage chip is realized through the baseboard management controller. When the basic input and output system storage chip can be powered on normally, it will set the connection pin between the main controller and the programmable logic device to a preset state. Therefore, the baseboard management controller can determine the quality of the basic input and output system storage chip by identifying whether the pin state of the connection pin is the preset state; and when the pin state is not the preset state, it can be determined whether the basic input and output system storage chip is damaged by judging whether the chip information of the basic input and output system storage chip can be read. Obviously, if the chip information can be read, it can be determined that the basic input and output system storage chip itself is not damaged, but the basic input and output system software code stored therein is damaged, otherwise it is considered that the basic input and output system storage chip is damaged. It can be seen that the technical solution realizes a more accurate chip damage judgment, and is simple and easy to implement.

[0058] The chip damage determination device, electronic device, computer-readable storage medium and computer program product provided by the present invention also have the above-mentioned technical effects, and the present invention will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present invention, the following briefly introduces the drawings required for describing the prior art and the embodiments of the present invention. Of course, the drawings related to the embodiments of the present invention described below are only part of the embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without creative work, and the obtained other drawings also belong to the protection scope of the present invention.

[0060] Figure 1 A schematic diagram of the structure of a chip damage determination system provided by an embodiment of the present invention;

[0061] Figure 2 A schematic diagram of a process flow of a chip damage determination method provided by an embodiment of the present invention;

[0062] Figure 3 A schematic flow chart of another chip damage determination method provided by an embodiment of the present invention;

[0063] Figure 4 A schematic diagram of the structure of a chip damage determination device provided by an embodiment of the present invention;

[0064] Figure 5 The present invention is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0065] The core of the present invention is to provide a chip damage judgment method, which can achieve more accurate chip damage judgment; another core of the present invention is to provide a chip damage judgment device, electronic device, computer-readable storage medium and computer program product, all of which have the above-mentioned beneficial effects.

[0066] In order to describe the technical solutions in the embodiments of the present invention more clearly and completely, the technical solutions in the embodiments of the present invention will be introduced below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0067] An embodiment of the present invention provides a chip damage determination method.

[0068] First, please refer to Figure 1 , Figure 1The present invention provides a schematic diagram of the structure of a chip damage determination system provided by an embodiment of the present invention. The chip damage determination system includes a baseboard management controller (BMC), a programmable logic device (CPLD), a main controller (CPU, Central Processing Unit / Processor) and a basic input and output system storage chip (BIOS Flash, Basic Input Output System Flash), wherein the baseboard management controller is connected to the programmable logic device, the programmable logic device is connected to the preset pin of the main controller, and the main controller is connected to the basic input and output system storage chip. The chip damage determination method provided by an embodiment of the present invention is implemented based on the chip damage determination system, and is intended to determine whether the basic input and output system storage chip is damaged through the baseboard management controller.

[0069] For further information, please refer to Figure 2 , Figure 2 A schematic diagram of a chip damage determination method provided by an embodiment of the present invention, wherein the chip damage determination method is applied to Figure 1 The baseboard management controller shown may include the following S101 to S106.

[0070] S101: When a power-on signal is received, a pin state of a preset pin in a main controller is obtained through a programmable logic device.

[0071] This step aims to obtain the pin status of the preset pin in the main controller. The preset pin is essentially a connection pin between the programmable logic device and the main controller. The programmable logic device is connected to the baseboard management controller and the main controller respectively. Therefore, the baseboard management controller can obtain the pin status of the preset pin through the programmable logic device. It can be understood that the determination of whether the basic input and output system storage chip is damaged should be performed before the normal operation of the equipment. Therefore, for the baseboard management controller, it can perform this operation after receiving the power-on signal. On this basis, the baseboard management controller can identify the quality of the basic input and output system storage chip according to the pin status of the preset pin.

[0072] In one embodiment of the present invention, the baseboard management controller and the programmable logic device are connected via an I2C (Inter-Integrated Circuit) bus, and the above-mentioned obtaining the pin status of the preset pin in the main controller via the programmable logic device may include:

[0073] The pin state of the preset pin in the main controller is obtained by reading in the register of the programmable logic device through the I2C bus; the pin state of the preset pin is obtained in real time by the programmable logic device and written into the register.

[0074] The embodiment of the present invention provides a method for obtaining the pin status of a preset pin. Specifically, a baseboard management controller and a programmable logic device can be connected via an I2C bus, and a register is provided in the programmable logic device, which can obtain the pin status of the connection pin (preset pin) between itself and the main controller in real time after receiving a power-on signal, and store it in a local register, so that the baseboard management controller can access the register in the programmable logic device through the I2C bus to obtain the pin status of the preset pin.

[0075] S102: Determine whether the pin state is a preset state, which is set by the basic input and output system storage chip when receiving a power-on signal; if so, execute S103, if not, execute S104.

[0076] S103: Determine whether the basic input and output system storage chip is damaged.

[0077] This step is intended to achieve the identification and determination of the pin state, that is, to determine whether the pin state of the preset pin is the preset state. It is understandable that before the system is powered on, the preset pin maintains the default state. After the system is powered on, if the basic input and output system storage chip is not damaged, it will respond to the power-on signal to set the default state of the preset pin to the preset state. If the basic input and output system storage chip is damaged, it will not respond to the power-on signal, and will not set the default state of the preset pin to the preset state. Therefore, the baseboard management controller can determine whether the basic input and output system storage chip is damaged by identifying whether the pin state of the preset pin is the preset state.

[0078] On this basis, when the pin state of the preset pin is indeed the preset state, it can be determined that the BIOS storage chip is not damaged. On the contrary, when the pin state of the preset pin is not the preset state, it can be considered that abnormal damage does exist. However, this abnormal damage may be caused by hardware damage of the BIOS storage chip itself, or by damage to the BIOS software code stored in the BIOS storage chip. Therefore, S104 can be further executed to determine the specific damage situation.

[0079] In one embodiment of the present invention, the above-mentioned determination of whether the pin state is a preset state, the preset state being set by the basic input and output system storage chip when receiving a power-on signal, may include:

[0080] Determine whether the pin state is in a low level state; wherein the initial state of the preset pin is a high level state, and the low level state is obtained by the basic input and output system storage chip inverting the initial state of the preset pin when receiving a power-on signal;

[0081] If the pin state is in a low level state, the pin state is determined to be a preset state;

[0082] If the pin state is not in a low level state, it is determined that the pin state is not a preset state.

[0083] The embodiment of the present invention provides a method for determining the state of a pin, wherein the pin state of a preset pin may include a high level state and a low level state. Specifically, the preset pin can be connected using an external pull-up resistor, and its initial default state is a high level state before the system is powered on. After the system is powered on, if the basic input-output system storage chip is not damaged, it will respond to the power-on signal and reverse the level state of the preset pin during initialization, so that it changes from a high level state to a low level state; if the basic input-output system storage chip is damaged, the level state of the preset pin will not be switched from a high level to a low level. On this basis, the baseboard management controller can realize pin state recognition by determining whether the pin state of the preset pin is a low level state, and then determine whether the basic input-output system storage chip is damaged.

[0084] S104: Determine whether the chip information of the basic input and output system storage chip can be read; if so, execute S103, if not, execute S105.

[0085] S105: Determine whether the basic input / output system storage chip is damaged.

[0086] This step determines whether the BIOS storage chip is damaged by judging whether the chip information of the BIOS storage chip can be read. It should be noted that the damage of the BIOS storage chip here specifically refers to the damage of the hardware of the BIOS storage chip itself, that is, hardware damage. Obviously, if the chip information of the BIOS storage chip can be directly read, it can be determined that the BIOS storage chip is not damaged. If the chip information of the BIOS storage chip cannot be read, it can be determined that the BIOS storage chip is damaged. Among them, the chip information of the BIOS storage chip can specifically be a chip ID.

[0087] In addition, when the chip information of the basic input and output system storage chip can be read, although it can be determined that the basic input and output system storage chip itself is not damaged, since the pin state of the preset pin is not the preset state in S103, it means that there is still an abnormality. At this time, it can be determined that there is an abnormality in the basic input and output system software code stored in the basic input and output system storage chip, that is, the software is damaged. Further, a corresponding prompt message can be output.

[0088] In one embodiment of the present invention, the above-mentioned determination of whether the chip information of the basic input and output system storage chip can be read may include:

[0089] Control the current device to enter a shutdown state, so as to disconnect the basic input and output system storage chip from the main controller, and connect the basic input and output system storage chip to the baseboard management controller;

[0090] It is determined whether the chip information of the basic input and output system storage chip can be read through the connection relationship between the basic input and output system storage chip and the baseboard management controller.

[0091] The embodiment of the present invention provides a method for determining whether the chip information of the basic input and output system storage chip can be read. Figure 1 From the chip damage judgment system shown, it can be seen that there is no connection relationship between the baseboard management controller and the basic input and output system storage chip. Therefore, in order to realize the baseboard management controller to read the chip information of the basic input and output system storage chip, before judging whether the chip information of the basic input and output system storage chip can be read, the current device can be controlled to enter the shutdown state. Through this operation, the connection between the basic input and output system storage chip and the main controller can be disconnected, and the connection between the basic input and output system storage chip and the baseboard management controller can be established. Therefore, the baseboard management controller can try to read the chip information of the basic input and output system storage chip through the connection relationship, thereby realizing this judgment operation.

[0092] Among them, the basic input and output system storage chip and the main controller are connected through a serial peripheral interface (SPI) bus. The above-mentioned control of the current device to enter a shutdown state to disconnect the basic input and output system storage chip from the main controller and establish a connection between the basic input and output system storage chip and the baseboard management controller may include: controlling the current device to enter a shutdown state to switch the serial peripheral interface bus of the basic input and output system storage chip from connecting to the main controller to connecting to the baseboard management controller.

[0093] Specifically, the basic input / output system storage chip and the main controller can be connected via an SPI bus. The baseboard management controller can switch the SPI bus connected to the main controller on the basic input / output system storage chip to the baseboard management controller by controlling the current device to enter a shutdown state, thereby disconnecting the basic input / output system storage chip from the main controller and establishing a connection between the basic input / output system storage chip and the baseboard management controller.

[0094] It can be seen that the chip damage judgment method provided by the embodiment of the present invention adds a programmable logic device between the baseboard management controller and the main controller, and realizes the damage judgment of the basic input and output system storage chip through the baseboard management controller. When the basic input and output system storage chip can be powered on normally, it will set the connection pin between the main controller and the programmable logic device to a preset state. Therefore, the baseboard management controller can determine the quality of the basic input and output system storage chip by identifying whether the pin state of the connection pin is the preset state; and when the pin state is not the preset state, it can be determined whether the basic input and output system storage chip is damaged by judging whether the chip information of the basic input and output system storage chip can be read. Obviously, if the chip information can be read, it can be determined that the basic input and output system storage chip itself is not damaged, but the basic input and output system software code stored therein is damaged, otherwise it is considered that the basic input and output system storage chip is damaged. It can be seen that the technical solution realizes more accurate chip damage judgment and is simple and easy to implement.

[0095] Based on the above embodiments:

[0096] In one embodiment of the present invention, the above-mentioned obtaining the pin status of a preset pin in the main controller through a programmable logic device may include:

[0097] Get the power signal of the main controller;

[0098] Determine whether the power signal is valid;

[0099] When the power signal is valid, the pin state of the preset pin in the main controller is obtained through the programmable logic device;

[0100] When the power signal is invalid, an alarm is output.

[0101] The chip damage determination method provided in the embodiment of the present invention can further realize the validity judgment of the power supply signal of the main controller. It can be understood that the normal operation of the equipment depends on the normal power-on process. Only when the power supply is normal and effective can the normal progress of the subsequent steps be effectively guaranteed. Based on this, after receiving the power-on signal, before obtaining the pin status of the preset pin in the main controller through the programmable logic device, the power supply signal of the main controller can be obtained and judged whether it is valid. The power supply signal can specifically be a PWROK signal. Obviously, if the power supply signal is valid, the subsequent operations can be continued; if the power supply signal is invalid, the subsequent operations cannot be continued, and an alarm prompt can be output at this time.

[0102] It can be seen that the embodiment of the present invention realizes the validity judgment of the power signal immediately after power-on, and effectively avoids the waste of resources caused by continuing to perform subsequent operations when the power signal is invalid.

[0103] The output warning prompts may include:

[0104] Determine whether the current power-on duration reaches a first preset duration;

[0105] If the current power-on duration does not reach the first preset duration, returning to execute obtaining the power signal of the main controller;

[0106] If the current power-on duration reaches the first preset duration, an alarm prompt is output.

[0107] It is understandable that the system power-on process also takes a certain amount of time. If a valid power signal is not detected after power-on, in addition to the abnormality of the power supply itself, it may also be caused by the fact that the power-on process has not been completed. Based on this, in order to avoid misjudgment, a detection duration can be set in advance, that is, the above-mentioned first preset duration. In other words, it is possible to cyclically determine whether the power signal of the main controller is valid within the first preset duration. If a valid power signal is still not detected after exceeding the first preset duration, it can be considered that there is indeed a power abnormality problem, and an alarm can be issued at this time. Of course, the value of the above-mentioned first preset duration does not affect the implementation of the present technical solution. It can be set according to the actual performance of the equipment, such as the conventional power-on time, and this application does not limit this.

[0108] Wherein, when the power signal is valid, obtaining the pin state of a preset pin in the main controller through the programmable logic device may include:

[0109] When it is determined that the power signal is valid, the timing starts;

[0110] When the timing time reaches a second preset time length, a step of acquiring a pin state of a preset pin in the main controller through a programmable logic device is executed.

[0111] It is understandable that the system will first perform initialization operations after power-on, such as initializing various system components, configurations, etc. Obviously, this process will inevitably take a certain amount of time. Based on this, when the baseboard management controller determines that the power signal of the main controller is valid, before obtaining the pin status of the preset pin in the main controller through the programmable logic device, it can start timing first, until its timing time reaches a certain duration, that is, the above-mentioned second preset duration, and then obtain the pin status of the preset pin in the main controller through the programmable logic device. Similarly, the value of the second preset duration does not affect the implementation of the present technical solution, and can be specifically set according to the actual performance of the equipment, such as the conventional initialization time, and this application does not limit this. Among them, the timing function can be implemented by setting a timer in the baseboard management controller.

[0112] The above-mentioned determining whether the power signal is valid may include:

[0113] Determine whether the power signal is at a high level;

[0114] If the power signal is at a high level, it is determined that the power signal is valid;

[0115] If the power signal is not at a high level, it is determined that the power signal is invalid.

[0116] The embodiment of the present invention provides a method for implementing the validity judgment of a power supply signal. It can be understood that when the power supply is at a high level, the power supply is normally supplied, and when the power supply is at a low level, the power supply cannot be normally supplied. Based on this, the validity judgment of the power supply signal can be implemented according to the level state of the power supply signal, that is, if the power supply signal is at a high level, it is determined that the power supply signal is valid; if the power supply signal is not at a high level, it is determined that the power supply signal is invalid.

[0117] In one embodiment of the present invention, when it is determined that the basic input and output system storage chip is damaged, the chip damage determination method may also include: sending a chip switching command to the programmable logic device so that the programmable logic device switches the basic input and output system storage chip to a spare basic input and output system storage chip.

[0118] The chip damage determination method provided in the embodiment of the present invention can further implement the main and standby chip switching function to ensure the normal use of the device. Figure 1 The chip damage determination system shown may also include a spare basic input and output system storage chip. When it is finally determined that the basic input and output system storage chip is indeed damaged, a chip switching operation can be performed through a programmable logic device, so that the spare basic input and output system storage chip can be used to provide BIOS services for the current device. Therefore, by performing a chip switching operation when the main basic input and output system storage chip is damaged, the normal operation of the current device can be effectively guaranteed.

[0119] It is conceivable that, in order to ensure the normal operation of the current device, the spare BIOS storage chip can also be judged to be damaged by executing the above steps S101 to S105, that is, the damage judgment of the spare BIOS storage chip is realized. This embodiment will not be described in detail.

[0120] Among them, after sending the chip switching command to the programmable logic device so that the programmable logic device switches the basic input and output system storage chip to the spare basic input and output system storage chip, it can also include: controlling the standby basic input and output system storage chip to start up so that the standby basic input and output system storage chip obtains the file data in the basic input and output system storage chip and synchronizes it to the local.

[0121] The chip damage determination method provided in the embodiment of the present application is intended to realize the data synchronization operation after the chip is switched, so as to effectively ensure the normal operation of the device. It is understandable that when using the device, the user may adjust the configuration items of the basic input and output system in the basic input and output system storage chip for their own actual needs. Obviously, the adjustment here is only for the main basic input and output system storage chip, and the standby basic input and output system storage chip will not be adjusted synchronously. The content in the standby basic input and output system storage chip is still the default setting at the factory. Based on this, after controlling the standby basic input and output system storage chip to start, the file data in the main basic input and output system storage chip can be obtained first and synchronized to the local, so that the standby basic input and output system storage chip can enter a normal operating state based on the file data, thereby meeting the actual use needs of the user.

[0122] In one embodiment of the present invention, the chip damage determination method may further include:

[0123] When it is determined that the basic input and output system storage chip is damaged, a first fault code is generated and recorded in a log file;

[0124] When it is determined that the pin state of the preset pin is not the preset state and the chip information of the basic input and output system storage chip can be read, a second fault code is generated and recorded in the log file.

[0125] The chip damage determination method provided by the embodiment of the present invention can further realize the log recording function. As described above, when the chip information of the basic input and output system storage chip can be read, but the pin state of the preset pin is not the preset state, it means that the basic input and output system software code stored in the basic input and output system storage chip is abnormal, that is, the software is damaged; and the basic input and output system storage chip damage finally determined means that the hardware circuit of the basic input and output system storage chip is damaged, that is, the hardware is damaged. On this basis, whether it is software damage or hardware damage, corresponding log records can be generated. Specifically, in order to distinguish the types of damage, different fault codes can be set for different damage situations. Thus, the technician can determine the specific damage situation according to the fault code recorded in the log file, so that the technician can trace the problem more conveniently and quickly. Furthermore, for different damage situations, different alarm methods can also be used to inform the technician of the current abnormal situation in a timely manner.

[0126] In one embodiment of the present invention, the chip damage determination method may further include:

[0127] Upload log files to the cloud server so that the cloud server can manage log files for all devices in the current environment domain.

[0128] The chip damage determination method provided in the embodiment of the present invention can further realize the log management function within a specific environmental domain. Specifically, the baseboard management controller can be connected to the cloud server through the device network to which it belongs, so that the log files recorded by itself can be uploaded to the cloud server for storage and management. Among them, the cloud server is used to realize the log file management of all devices in a specific environmental domain. For example, log file management for all servers in a certain computer room can be realized. Through the cloud server, technicians can clearly understand the damage status of all basic input and output system storage chips on all servers in a certain computer room, the switching status of spare basic input and output system storage chips, the damage status of spare basic input and output system storage chips, etc., so as to carry out batch repairs and replacements in time.

[0129] An embodiment of the present invention provides another chip damage determination method.

[0130] Please refer to Figure 3 , Figure 3 This is a flow chart of another chip damage determination method provided by an embodiment of the present invention, and its implementation process is as follows:

[0131] Step 1. When designing the hardware motherboard, two BIOS chips need to be reserved, which are used as the main BIOS and the backup BIOS respectively, to provide physical conditions for dual Flash switching. On the hardware motherboard, it is also necessary to reserve the CPU pin GPIO-X (preset pin) that can be driven by the BIOS and connected to the CPLD as an indication signal for the startup of the BIOS code. This pin is connected using an external pull-up resistor. When the device is powered on and no other program operates on it, the default state of GPIO-X is high level, that is, 1. In addition, the CPLD can write the real-time level status value of GPIO-X into the CPLD register, which is convenient for the BMC to query through the I2C bus, and can ensure that the queried state of GPIO-X is the current state value.

[0132] Step 2. After the device is powered on, according to step 1, the default level state of GPIO-X is high, that is, 1, due to the external pull-up resistor. When the Power Button is pressed, the CPU jumps to the entry execution of the BIOS code. When the BIOS performs the EFI (Extensible Firmware Interface) pre-initialization in the PEI (Pre-EFI Initialization) stage, the CPU is initialized. At this time, the level state of GPIO-X is reversed and pulled down to 0. After the PEI stage, the BIOS no longer operates GPIO-X and keeps the low level state until it is shut down to restore the default high level state.

[0133] Step 3: Based on step 2, BMC starts up after the device is powered on. After BMC starts up, it detects whether the PWROK signal (power signal) of the CPU is valid. The PWROK signal is a sign that the hardware device has completed powering on, that is, when the device is in the off state, the PWROK signal is at a low level; when the device is in the on state, the PWROK signal is at a high level. When the PWROK signal is detected to be valid at a high level, the BMC starts the timer. After a certain time T is reached, the BMC can obtain the level status FlagX of GPIO-X from the CPLD through the I2C bus. Among them, by detecting the PWROK signal, it is possible to detect whether the BIOS chip and hardware circuit are normal every time the device is turned on, thereby improving the stability of the device.

[0134] Step 4. When the level state FlagX of GPIO-X detected in step 3 is 0, that is, low level, it means that the code of BIOS operating the level state of GPIO-X in step 2 is operating normally, which means that the BIOS Flash chip and peripheral circuits are normal. At this time, you can start the computer normally without special processing. However, when the level state FlagX of GPIO-X detected in step 3 is 1, that is, high level, it means that the BIOS code in step 2 is not operating normally. At this time, it is necessary to further distinguish whether the problem is caused by a soft fault in the BIOS code or a hardware fault in the BIOS chip and peripheral circuits.

[0135] Step 5: When further determination is required, the BMC controls the device to enter shutdown state, with the purpose of switching the SPI bus of the BIOS chip from the CPU end to the BMC end to ensure that the BMC can read the device ID (chip information) of the BIOS Flash. It is understandable that since step 4 has confirmed that the BIOS code is not working and the device cannot be started normally at this time, the BMC performs the power-off shutdown action at this time, which has no negative impact on the server status. When the BMC can obtain the device ID from the BIOS Flash, it indicates that the BIOS Flash chip and the surrounding hardware circuits are normal. At this time, it can be determined that the problem is caused by a soft fault in the BIOS code, and there is no need to switch to the backup BIOS chip, and the problem can be handed over to the BIOS R&D personnel for analysis. In addition, a SEL log can be recorded in the BMC event log to inform the maintenance personnel of the situation, which is convenient for subsequent problem tracing.

[0136] Step 6: When the BMC cannot obtain the device ID from the BIOS Flash, it indicates that there is an abnormality in the BIOS chip and the peripheral circuits. At this time, the BMC gives a command to the CPLD to switch the main BIOS chip to the backup BIOS chip, complete the switching of the backup BIOS, and start the computer normally after the switching is completed. Similarly, a SEL log can also be recorded in the BMC event log to inform maintenance personnel of the situation, facilitate after-sales maintenance, and improve the maintainability of the product. Among them, the log records of software failures and hardware damage can be implemented using different fault codes for easy distinction.

[0137] Step 7. Since the device has been running the main BIOS chip before, the user's various option configurations are also in the main BIOS program. Therefore, when the backup BIOS chip is started, it is the first startup, and there are no settings before the user's machine becomes abnormal. In this regard, when the backup BIOS is started for the first time, the variable data of the main BIOS can be obtained from the BMC and synchronized to the local variable area of ​​the backup BIOS to ensure the integrity and consistency of the main and backup BIOS data, thereby improving the reliability and stability of the switch.

[0138] Obviously, this solution can cover the scenarios where the BIOS chip is missing, the BIOS chip itself is damaged, resulting in inability to access Flash, and the BIOS chip peripheral circuit or clock problems result in inability to access Flash. It realizes the function of 100% accurate identification of physical damage scenarios such as BIOS chips, peripheral circuits, and clock circuits. It has the advantages of clear development logic, simple development, high stability, high reliability, and high maintainability.

[0139] It can be seen that the chip damage judgment method provided by the embodiment of the present invention adds a programmable logic device between the baseboard management controller and the main controller, and realizes the damage judgment of the basic input and output system storage chip through the baseboard management controller. When the basic input and output system storage chip can be powered on normally, it will set the connection pin between the main controller and the programmable logic device to a preset state. Therefore, the baseboard management controller can determine the quality of the basic input and output system storage chip by identifying whether the pin state of the connection pin is the preset state; and when the pin state is not the preset state, it can be determined whether the basic input and output system storage chip is damaged by judging whether the chip information of the basic input and output system storage chip can be read. Obviously, if the chip information can be read, it can be determined that the basic input and output system storage chip itself is not damaged, but the basic input and output system software code stored therein is damaged, otherwise it is considered that the basic input and output system storage chip is damaged. It can be seen that the technical solution realizes more accurate chip damage judgment and is simple and easy to implement.

[0140] An embodiment of the present invention provides a chip damage determination device.

[0141] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of a chip damage determination device provided by the present invention. The chip damage determination device is applied to a baseboard management controller, the baseboard management controller is connected to a programmable logic device, the programmable logic device is connected to a preset pin of a main controller, and the main controller is connected to a basic input and output system storage chip. The chip damage determination device may include:

[0142] An acquisition module 1 is used to acquire the pin status of a preset pin in the main controller through a programmable logic device when a power-on signal is received;

[0143] A first determination module 2 is used to determine whether the pin state is a preset state, the preset state being set by the basic input and output system storage chip when receiving a power-on signal;

[0144] A first determination module 3, for determining that the basic input and output system storage chip is not damaged if the pin state is a preset state;

[0145] The second judgment module 4 is used to judge whether the chip information of the basic input and output system storage chip can be read if the pin state is not the preset state;

[0146] The second determination module 5 is used to determine that the basic input and output system storage chip is not damaged if the chip information can be read;

[0147] The third determination module 6 is used to determine that the basic input and output system storage chip is damaged if the chip information cannot be read.

[0148] It can be seen that the chip damage judgment device provided by the embodiment of the present invention adds a programmable logic device between the baseboard management controller and the main controller, and realizes the damage judgment of the basic input and output system storage chip through the baseboard management controller. When the basic input and output system storage chip can be powered on normally, it will set the connection pin between the main controller and the programmable logic device to a preset state. Therefore, the baseboard management controller can determine the quality of the basic input and output system storage chip by identifying whether the pin state of the connection pin is the preset state; and when the pin state is not the preset state, it can be determined whether the basic input and output system storage chip is damaged by judging whether the chip information of the basic input and output system storage chip can be read. Obviously, if the chip information can be read, it can be determined that the basic input and output system storage chip itself is not damaged, but the basic input and output system software code stored therein is damaged, otherwise it is considered that the basic input and output system storage chip is damaged. It can be seen that the technical solution realizes more accurate chip damage judgment and is simple and easy to implement.

[0149] In one embodiment of the present invention, the acquisition module 1 may include:

[0150] A first acquisition unit, used for acquiring a power signal of a main controller;

[0151] A first judging unit, used to judge whether the power signal is valid;

[0152] A second acquisition unit, used for acquiring a pin state of a preset pin in the main controller through a programmable logic device when the power signal is valid;

[0153] The alarm unit is used to output an alarm prompt when the power signal is invalid.

[0154] In one embodiment of the present invention, the above-mentioned alarm unit can be specifically used to determine whether the current power-on duration reaches a first preset duration; if the current power-on duration does not reach the first preset duration, it returns to execute to obtain the power signal of the main controller; if the current power-on duration reaches the first preset duration, an alarm prompt is output.

[0155] In one embodiment of the present invention, the second acquisition unit can be specifically used to start timing when it is determined that the power signal is valid; when the timing time reaches a second preset time, the pin state of a preset pin in the main controller is acquired through the programmable logic device.

[0156] In one embodiment of the present invention, the above-mentioned judgment unit can be specifically used to judge whether the power signal is at a high level; if the power signal is at a high level, the power signal is determined to be valid; if the power signal is not at a high level, the power signal is determined to be invalid.

[0157] In one embodiment of the present invention, the baseboard management controller and the programmable logic device are connected via an I2C bus, and the above-mentioned acquisition module 1 can be specifically used to read the pin status of the preset pin in the main controller in the register of the programmable logic device via the I2C bus; the pin status of the preset pin is acquired in real time by the programmable logic device and written into the register.

[0158] In one embodiment of the present invention, the above-mentioned first judgment module 2 can be specifically used to determine whether the pin state is in a low level state; wherein, the initial state of the preset pin is a high level state, and the low level state is obtained by the basic input and output system storage chip inverting the initial state of the preset pin when receiving a power-on signal; if the pin state is in a low level state, it is determined that the pin state is the preset state; if the pin state is not in a low level state, it is determined that the pin state is not the preset state.

[0159] In one embodiment of the present invention, the second determination module 4 may include:

[0160] A shutdown unit, used to control the current device to enter a shutdown state, so as to disconnect the basic input and output system storage chip from the main controller and connect the basic input and output system storage chip to the baseboard management controller;

[0161] The second determination unit is used to determine whether the chip information of the basic input / output system storage chip can be obtained by reading the connection relationship between the basic input / output system storage chip and the baseboard management controller.

[0162] In one embodiment of the present invention, the basic input / output system storage chip is connected to the main controller via a serial peripheral interface bus, and the second judgment unit can be specifically used to control the current device to enter a shutdown state, so as to switch the serial peripheral interface bus of the basic input / output system storage chip from connecting to the main controller to connecting to the baseboard management controller.

[0163] In one embodiment of the present invention, the chip damage determination device may further include a switching module for sending a chip switching command to the programmable logic device when it is determined that the basic input and output system storage chip is damaged, so that the programmable logic device switches the basic input and output system storage chip to a spare basic input and output system storage chip.

[0164] In one embodiment of the present invention, the chip damage determination device may further include a synchronization module for controlling the startup of the spare basic input-output system storage chip after sending the chip switching command to the programmable logic device so that the programmable logic device switches the basic input-output system storage chip to the spare basic input-output system storage chip, so that the spare basic input-output system storage chip obtains the file data in the basic input-output system storage chip and synchronizes it to the local.

[0165] For an introduction to the device provided in the embodiment of the present invention, please refer to the above method embodiment, and the present invention will not be elaborated here.

[0166] An embodiment of the present invention provides an electronic device.

[0167] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device provided by the present invention, and the electronic device may include:

[0168] A memory 11, used for storing computer programs;

[0169] The processor 10 can implement the steps of any one of the above-mentioned chip damage determination methods when executing a computer program.

[0170] like Figure 5 , which is a schematic diagram of the composition structure of an electronic device, the electronic device may include: a processor 10, a memory 11, a communication interface 12 and a communication bus 13. The processor 10, the memory 11 and the communication interface 12 all communicate with each other through the communication bus 13.

[0171] In the embodiment of the present invention, the processor 10 may be a central processing unit (CPU), an application specific integrated circuit, a digital signal processor, a field programmable gate array or other programmable logic devices.

[0172] The processor 10 may call a program stored in the memory 11. Specifically, the processor 10 may execute operations in the embodiment of the chip damage determination method.

[0173] The memory 11 is used to store one or more programs, which may include program codes, and the program codes include computer operation instructions. In the embodiment of the present invention, the memory 11 at least stores programs for implementing the following functions:

[0174] When a power-on signal is received, the pin state of a preset pin in the main controller is obtained through the programmable logic device;

[0175] Determine whether the pin state is a preset state, the preset state is set by the basic input and output system storage chip when receiving a power-on signal;

[0176] If the pin status is the default status, it is determined that the basic input and output system storage chip is not damaged;

[0177] If the pin state is not the preset state, determining whether the chip information of the basic input and output system storage chip can be read;

[0178] If the chip information can be read, it is confirmed that the basic input and output system storage chip is not damaged;

[0179] If the chip information cannot be read, it is determined that the basic input and output system storage chip is damaged.

[0180] In a possible implementation, the memory 11 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function, etc.; the data storage area may store data created during use.

[0181] In addition, the memory 11 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device or other volatile solid-state storage device.

[0182] The communication interface 12 may be an interface of a communication module, and is used to connect to other devices or systems.

[0183] Of course, it should be noted that Figure 5 The structure shown does not constitute a limitation on the electronic device in the embodiment of the present invention. In actual applications, the electronic device may include Figure 5 More or fewer components than shown, or combinations of certain components.

[0184] An embodiment of the present invention provides a computer-readable storage medium.

[0185] The computer-readable storage medium provided in the embodiment of the present invention stores a computer program, and when the computer program is executed by a processor, the steps of any one of the above-mentioned chip damage determination methods can be implemented.

[0186] Among them, the computer-readable storage medium can be any available medium that can be stored in a computer or a data storage device such as a server or data center that includes one or more available media integrated. For example, it can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape, etc.), an optical medium (such as a DVD) or a semiconductor medium (such as a solid-state hard disk) and other media that can store computer program codes.

[0187] For an introduction to the computer-readable storage medium provided in an embodiment of the present invention, please refer to the above method embodiment, and the present invention will not elaborate on it here.

[0188] An embodiment of the present invention provides a computer program product.

[0189] The computer program product provided in the embodiment of the present invention includes a computer program / instruction. When the computer program / instruction is executed by a processor, the steps of any one of the above-mentioned chip damage determination methods can be implemented.

[0190] Specifically, in the above embodiments, all or part of them can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of them can be implemented in the form of a computer program product.

[0191] Among them, the computer program product may include one or more computer programs / instructions, and when the computer program / instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention may be generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line, etc.) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0192] For an introduction to the computer program product provided by the embodiment of the present invention, please refer to the above method embodiment, and the present invention will not be elaborated here.

[0193] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0194] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0195] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0196] The technical solution provided by the present invention is described in detail above. Specific examples are used herein to illustrate the principle and implementation of the present invention, and the description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A chip damage determination method, characterized in that: Applied to a baseboard management controller, the baseboard management controller is connected to a programmable logic device, the programmable logic device is connected to a preset pin of a main controller, and the main controller is connected to a basic input and output system storage chip, the method includes: When a power-on signal is received, obtaining the pin state of the preset pin in the main controller through the programmable logic device; Determining whether the pin state is a preset state, wherein the preset state is set by the basic input and output system storage chip when receiving the power-on signal; If the pin state is the preset state, it is determined that the basic input and output system storage chip is not damaged; If the pin state is not the preset state, determining whether the chip information of the basic input and output system storage chip can be read; If the chip information can be read, it is determined that the basic input and output system storage chip is not damaged, and it is determined that the basic input and output system software code stored in the basic input and output system storage chip is abnormal; If the chip information cannot be read, it is determined that the basic input and output system storage chip is damaged; Determining whether the pin state is a preset state, the preset state is set by the basic input and output system storage chip when receiving the power-on signal, including: determining whether the pin state is in a low level state; wherein the initial state of the preset pin is a high level state, and the low level state is obtained by inverting the initial state of the preset pin by the basic input and output system storage chip when receiving the power-on signal; if the pin state is in a low level state, determining that the pin state is the preset state; if the pin state is not in a low level state, determining that the pin state is not the preset state.

2. The chip damage determination method according to claim 1, characterized in that: Acquiring the pin state of the preset pin in the main controller through the programmable logic device includes: Acquiring a power signal of the main controller; Determining whether the power signal is valid; When the power signal is valid, obtaining the pin state of the preset pin in the main controller through the programmable logic device; When the power signal is invalid, an alarm prompt is output.

3. The chip damage determination method according to claim 2, characterized in that: Output alarm prompts, including: Determine whether the current power-on duration reaches a first preset duration; If the current power-on duration does not reach the first preset duration, returning to execute obtaining the power signal of the main controller; If the current power-on duration reaches the first preset duration, the alarm prompt is output.

4. The chip damage determination method according to claim 2, characterized in that: When the power signal is valid, obtaining the pin state of the preset pin in the main controller through the programmable logic device includes: When it is determined that the power signal is valid, start timing; When the timing time reaches a second preset time length, the pin state of the preset pin in the main controller is obtained through the programmable logic device.

5. The chip damage determination method according to claim 2, characterized in that: Determining whether the power signal is valid includes: Determining whether the power signal is at a high level; If the power signal is at a high level, determining that the power signal is valid; If the power signal is not at a high level, it is determined that the power signal is invalid.

6. The chip damage determination method according to claim 1, characterized in that: The baseboard management controller is connected to the programmable logic device via an I2C bus, and obtaining the pin status of the preset pin in the main controller via the programmable logic device includes: The pin status of the preset pin in the main controller is obtained by reading the register of the programmable logic device through the I2C bus; the pin status of the preset pin is obtained in real time by the programmable logic device and written into the register.

7. The chip damage determination method according to claim 1, characterized in that: Determining whether the chip information of the basic input and output system storage chip can be read includes: Controlling the current device to enter a shutdown state, so as to disconnect the basic input and output system storage chip from the main controller and connect the basic input and output system storage chip to the baseboard management controller; It is determined whether the chip information of the basic input and output system storage chip can be read through the connection relationship between the basic input and output system storage chip and the baseboard management controller.

8. The chip damage determination method according to claim 7, characterized in that: The basic input-output system storage chip is connected to the main controller via a serial peripheral interface bus, and the current device is controlled to enter a shutdown state to disconnect the basic input-output system storage chip from the main controller, and the basic input-output system storage chip is connected to the baseboard management controller, including: The current device is controlled to enter a shutdown state, so as to switch the serial peripheral interface bus of the basic input / output system storage chip from being connected to the main controller to being connected to the baseboard management controller.

9. The chip damage determination method according to any one of claims 1 to 8, characterized in that: When it is determined that the basic input and output system storage chip is damaged, the method further includes: A chip switching command is sent to the programmable logic device, so that the programmable logic device switches the basic input and output system storage chip to a spare basic input and output system storage chip.

10. The chip damage determination method according to claim 9, characterized in that: After sending a chip switching command to the programmable logic device so that the programmable logic device switches the basic input and output system storage chip to a spare basic input and output system storage chip, the method further includes: The standby BIOS storage chip is controlled to start up, so that the standby BIOS storage chip acquires the file data in the BIOS storage chip and synchronizes the file data to a local device.

11. A chip damage determination device, characterized in that: Applied to a baseboard management controller, the baseboard management controller is connected to a programmable logic device, the programmable logic device is connected to a preset pin of a main controller, the main controller is connected to a basic input and output system storage chip, and the device includes: An acquisition module, configured to acquire the pin state of the preset pin in the main controller through the programmable logic device when a power-on signal is received; A first determination module, used for determining whether the pin state is a preset state, wherein the preset state is set by the basic input and output system storage chip when receiving the power-on signal; A first determination module, configured to determine that the basic input / output system storage chip is not damaged if the pin state is the preset state; A second judgment module, used for judging whether the chip information of the basic input and output system storage chip can be read if the pin state is not the preset state; a second determination module, configured to determine that the BIOS storage chip is not damaged if the chip information can be read, and to determine that an abnormality exists in the BIOS software code stored in the BIOS storage chip; A third determination module, configured to determine that the basic input and output system storage chip is damaged if the chip information cannot be read; The first judgment module is specifically used to judge whether the pin state is in a low level state; wherein, the initial state of the preset pin is a high level state, and the low level state is obtained by the basic input and output system storage chip inverting the initial state of the preset pin when receiving the power-on signal; if the pin state is in a low level state, it is determined that the pin state is the preset state; if the pin state is not in a low level state, it is determined that the pin state is not the preset state.

12. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the chip damage determination method according to any one of claims 1 to 10 when executing the computer program.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip damage determination method according to any one of claims 1 to 10 are implemented.

14. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the chip damage determination method according to any one of claims 1 to 10 are implemented.

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