Intelligent optimization method for reliability of 2.5D storage and computing integrated chip packaging based on MOPSO

Abstract

The present invention discloses a MOPSO-based intelligent optimization method for the reliability of a 2.5D package of a storage-computing integrated core particle, comprising the following steps: S1. Determine the key bump parameters of the 2.5D package structure; S2. Establish an equivalent finite element model of the 2.5D package structure according to the level combination divided by the Taguchi orthogonal experiment; S3. Adopt a percentage-based weighted evaluation method and a signal-to-noise ratio range analysis method to determine the parameter ranking; S4. Implement a multi-objective comprehensive evaluation through a signal-to-noise ratio range analysis method, perform percentage-based weighting according to the calculated weight proportion, obtain a comprehensive score of different level combinations, and determine the optimal 2.5D package structure parameter solution; S5. Use the least squares method to fit the functions of stress, warpage, and comprehensive score; S6. Use the MOPSO model to optimize multiple target variables. The present invention can avoid the risk of product reliability failure due to warpage and excessive stress in advance.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit packaging, and more specifically, to a MOPSO-based intelligent optimization method for reliability of a 2.5D storage and computing integrated core particle packaging. Background Art

[0002] Electronic devices are subjected to repeated thermal loads during production and service. The mismatch in thermal expansion coefficients of various structures leads to the generation of internal stresses. Although these stresses are far less than the strength to destroy the device, under the repeated action of external thermal cycle loads, stresses can cause damage at key locations.

[0003] In large-size chip packaging, unreasonable material combination or structural design will lead to structural warping, directly affecting the coplanarity of the package, causing chip breakage, delamination and other problems, thereby affecting product performance and service life.

[0004] Therefore, a new MOPSO-based intelligent optimization method for the reliability of 2.5D packaging of integrated storage and computing chips is urgently needed. Summary of the invention

[0005] The purpose of the present invention is to find the best material combination and structural parameters through the Taguchi method and the MOPSO algorithm, so as to reduce the warping and stress of 2.5D packaging products and avoid the risk of product reliability failure due to warping and excessive stress in advance.

[0006] In order to solve at least one of the above technical problems, according to one aspect of the present invention, a reliability intelligent optimization method for 2.5D packaging of integrated storage and computing core particles based on MOPSO is provided, comprising the following steps: S1. Determine the key bump parameters of the 2.5D packaging structure; the key bump parameters include the C2 bump diameter on the lower surface of the integrated chip, the C2 bump height, the C4 bump height where the silicon adapter plate is connected to the substrate, the C4 bump radius, and the C4 bump material, divide them into different level combinations according to the Taguchi orthogonal method, and design an orthogonal experimental table;

[0007] S2. Establish an equivalent finite element model of the 2.5D packaging structure according to the level combination divided by the Taguchi orthogonal experiment, set the thermal cycle temperature curve for the equivalent finite element model, simulate and obtain the quality indicators, and count them into the orthogonal experiment table;

[0008] S3. For multi-target quality indicators, the percentage-based weighted evaluation method and the signal-to-noise ratio range analysis method are used to determine the ranking of the comprehensive influence of C2 bump diameter, C2 bump height, C4 bump height of the connection between the silicon adapter and the substrate, C4 bump radius, and C4 bump material;

[0009] S4. Implement multi-objective comprehensive evaluation through signal-to-noise ratio range analysis, weight the results according to the calculated weight ratio, obtain comprehensive scores for different level combinations, analyze the orthogonal test design results, and determine the optimal 2.5D packaging structure parameter solution;

[0010] S5. Based on the orthogonal experimental results in steps S2 and S4, the functions of stress, warpage and comprehensive score are fitted using the least squares method;

[0011] S6. Use the MOPSO model to optimize multiple objective variables, modify the finite element model, simulate to obtain the optimized quality indicators, and verify the optimization results by comparing them with the simulation results of the corresponding structural parameters.

[0012] Furthermore, in S1, the C2 bump diameter on the lower surface of the integrated chip, the C2 bump height, the C4 bump height connecting the silicon adapter plate and the substrate, the C4 bump radius, and the C4 bump material are divided into different level combinations; the Taguchi orthogonal design experimental table is used, and the factors and their respective level values ​​are input into the software for experimental design.

[0013] Furthermore, in S2, the quality indicators in the bump test table are set as the maximum warpage value, average stress value, maximum warpage value of the ASIC integrated chip, and maximum stress value of the C4 bump connecting the silicon adapter and the substrate; a finite element model of a 2.5D packaging product is established according to the combined parameters listed in the Taguchi method, and then the finite element software is used to simulate the product model to obtain the quality indicators.

[0014] Furthermore, in S3, based on the range analysis method of signal-to-noise ratio, the ranking of the influence of C2 bump diameter, C2 bump height, C4 bump height connecting the silicon adapter plate and the substrate, C4 bump radius and C4 bump material on different quality indicators is determined;

[0015] The signal-to-noise ratio range analysis method is used to obtain the influence weight of each factor on the quality index, and the weight ratio is determined.

[0016] Furthermore, in S4, the percentage-based weighted evaluation method and the range analysis method are used to obtain the comprehensive score of the impact of each factor on the quality index according to the weight ratio. The smaller the score, the better the parameter combination. The orthogonal test design results are analyzed, and the optimal parameter scheme is determined based on the comprehensive impact ranking and the signal-to-noise ratio. The percentage-based weighted evaluation formula is: ,in, i Indicates the test number, k Indicates the quality indicator number, Indicates i The overall score of the group test, Indicates the weight ratio, Represents quality indicator data results.

[0017] Furthermore, in S5, based on the orthogonal experimental table, the C2 bump diameter, C2 bump height, C4 bump height connecting the silicon adapter and the substrate, C4 bump radius, and C4 bump material are used as design variables, and the quality indicators ASIC integrated chip maximum warpage value and silicon adapter average stress value and comprehensive score function are fitted by the least squares method.

[0018] Furthermore, in S6, based on the fitted function, the MOPSO model is used to optimize multiple target variables, and the optimization range is the horizontal division range determined in step S1. The optimization results are compared with the corresponding structural parameter simulation results for verification.

[0019] According to another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the steps of the nonlinear geometric phase liquid crystal element, preparation method and application thereof of the present invention are implemented.

[0020] According to another aspect of the present invention, there is provided a computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the nonlinear geometric phase liquid crystal element, the preparation method and the application thereof of the present invention are implemented.

[0021] Compared with the prior art, the above method of the present invention has the following beneficial effects:

[0022] In the present invention, the weights of bump parameters and material types for a single quality index are determined by Taguchi orthogonal experiment and signal-to-noise ratio range analysis, and then the optimal bump parameter and material type combination is determined by a percentage-weighted comprehensive score, and then the bump structural parameters and material types are used as design variables, and the function is fitted by the least squares method, and finally the MOPSO model is used to optimize the variables to obtain the optimal bump structural parameters and material types, and compared with the optimal bump parameter combination and material type obtained by the percentage-weighted comprehensive score, the optimal 2.5D package structural parameters are finally obtained. The invention can improve the efficiency and accuracy of obtaining the optimal 2.5D package structural parameter combination, reduce the warping and stress of 2.5D package products, and avoid the risk of product reliability failure due to warping and excessive stress in advance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0024] Figure 1 This is a schematic diagram of the process of Example 1 of the present invention;

[0025] Figure 2 It is a finite element model structure diagram of embodiment 1 of the present invention;

[0026] Figure 3 This is a flow chart of the MOPSO algorithm in Example 1 of the present invention;

[0027] Figure 4 The spatial distribution of the Pareto solution in Example 1 of the present invention;

[0028] Figure 5 This is a warpage simulation comparison diagram before and after optimization of Example 1 of the present invention;

[0029] Figure 6 This is a comparison chart of the results before and after optimization of Example 1 of the present invention. DETAILED DESCRIPTION

[0030] To make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them.

[0031] Unless otherwise defined, technical or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs.

[0032] Example 1: Figure 2 As shown, the 2.5D packaging structure used in this example includes: a substrate 1, a reinforcing rib 2, a C4 solder ball 3 connecting the silicon adapter board and the substrate, a silicon adapter board 4, a C2 bump 5 connecting the ASIC chip and the silicon adapter board, an ASIC chip 6, a C4 solder ball 7 on the lower surface of the HBM chip, a DRAM stacked chip 8 in the HBM, and a DRAM interconnection C2 bump 9.

[0033] This example provides a reliability intelligent optimization method for 2.5D integrated chip packaging based on machine learning (MOPSO). Figure 1 As shown, the following steps are included:

[0034] S1. Select the structural parameters of the 2.5D packaging structure required for simulation. The structural parameters include the C2 bump diameter on the lower surface of the integrated chip, the C2 bump height, the C4 bump height connecting the silicon adapter plate and the substrate, the C4 bump radius, and the C4 bump material. Combined with the sample data actually produced by the enterprise, the structural parameters are divided into different level combinations, and the Taguchi method orthogonal table is designed using Minitab software. The structural parameters and their respective level values ​​are selected and input into the software for experimental design.

[0035] Table 1 below shows the selection of structural parameters, and the selection criteria are determined based on the sample data actually produced by the enterprise. Table 2 shows 27 combinations of different bump parameters.

[0036] Table 1 Structural parameters and levels

[0037]

[0038] Table 2 Combinations of different bump parameters and material types

[0039]

[0040] S2. Establish 2.5D packaging structure finite element models with different structural parameters, use ANSYS finite element analysis software to simulate the thermal cycle of the model, set the temperature curve according to the GJB 150.5A-2009 temperature cycle test loading standard, and a single temperature cycle experience: 0s to 600s from room temperature 20℃ to 125℃, the heating rate is 0.2℃ / s, high temperature is maintained for 15min (600s-1500s), 1500s to 2400s from high temperature 125℃ to -55℃, the cooling rate is 0.2℃ / s, and low temperature is maintained for 15min (2400s-3300s), the next temperature cycle starts from -55℃, and the heating, insulation and cooling time stages are all 900s. This simulation loads three temperature cycles in total. The quality indicators are simulated, and the quality indicators in the experimental table are set as the maximum warpage value of ASIC, the average value of ASIC stress, the maximum warpage value of DRAM chip, the maximum warpage value of silicon adapter board, the average value of silicon adapter board stress, and the maximum stress value of C4 bump.

[0041] As shown in Table 3, they are orthogonal design tables. Since there are many data as quality indicators and their dimensions are different, the data need to be normalized to obtain the comprehensive score of each group.

[0042] Table 3 Orthogonal design table

[0043]

[0044] S3. Calculate the signal-to-noise ratio of each quality index and put it into the signal-to-noise ratio experimental table. Table 4 shows the signal-to-noise ratio experimental table. The signal-to-noise ratio can truly reflect the influence of different structural parameter combinations on the quality index data. The signal-to-noise ratio can be analyzed based on the three characteristics of large, small and large. The warpage and stress value are small characteristics. The signal-to-noise ratio calculation formulas for different characteristics are different:

[0045] Features: ;

[0046] in, is the signal-to-noise ratio result, n is the number of sample data, For the i The actual calculated value of the experimental result;

[0047] Features: ;

[0048] in, is the signal-to-noise ratio result, n is the number of sample data, For the i The actual calculated value of the experimental result;

[0049] Features: ; ;

[0050] in, is the signal-to-noise ratio result, is the sample variance, n is the number of sample data, is the mean, For the i The actual calculated value of the experimental results.

[0051] The signal-to-noise ratio range analysis method is used to obtain the ranking of the influence of each bump parameter on the comprehensive quality index, and then determine the weight R value of the influence of each bump parameter and material type on the quality index. The larger the R value, the greater the influence. Table 5 is a signal-to-noise ratio response table.

[0052] Table 4 Signal-to-noise ratio experimental table

[0053]

[0054] Table 5 Signal-to-noise ratio response table

[0055]

[0056] S4. Multi-objective comprehensive evaluation is achieved through the signal-to-noise ratio range analysis method. The weight of each quality indicator is calculated. All signal-to-noise ratios are added up to obtain their dimensionless mean, thereby calculating the weight of each quality indicator. According to the weight of each quality indicator, the comprehensive score of each different structural combination is calculated. The quality indicator weights are shown in Table 6.

[0057] The percentage-based weighted evaluation formula is: ;

[0058] in, i Indicates the test number, k Indicates the quality indicator number, Indicates i The overall score of the group test, Indicates the weight ratio, Represents quality indicator data results.

[0059] Table 7 shows the experimental table after statistical comprehensive scoring.

[0060] Table 6 Quality index weights

[0061]

[0062] Table 7 Signal-to-noise ratio experimental table

[0063]

[0064] S5. Using the data in Table 3 as sample data, the quality index results are fitted using the least squares method, and the maximum warpage value of ASIC with higher fitting degree is selected. Y 1. Average stress value of silicon adapter board Y 5. Overall rating Y 7. Get quality indicators Y 1, Y 5. Y 7 and the functional relationship between the structural parameters A, B, C, D, E, the fitting results are as follows:

[0065]

[0066]

[0067]

[0068] right Y 1, Y 5. Y 7 The variance analysis was performed on the fitting function, as shown in Tables 8 to 10, which are the fitting functions Y 1, Y 5. Y The variance analysis results of 7 have determination coefficients of 0.883146, 0.880799, and 0.850556, respectively, all greater than 0.85, indicating that the parameters have a high degree of explanation for the objective function and the relationship between the variables is significant. The P values ​​of the regression analysis of the two fitting functions are both less than 0.01, indicating that the model is highly significant, the degree of fit is high, and the statistical significance is obvious.

[0069] Table 8 Y 1. Functional ANOVA

[0070]

[0071] Table 9 Y 5-function ANOVA

[0072]

[0073] Table 10 Y7-function ANOVA

[0074]

[0075] S6. Based on the fitted function, the MOPSO model is used to optimize the three target variables. The MOPSO flow chart is as follows: Figure 3 As shown in the figure, the algorithm steps are: (1) initialization of population particles, including initialization of particle speed and position; (2) calculation of particle fitness, and calculation of non-dominated solution set according to the dominance relationship; (3) updating the solutions of the external archive set and deleting some solutions with poor quality; (4) updating Pbest particles and updating particles according to the Pareto dominance relationship; (5) selecting a part of particles in the external archive set as Gbest; (6) updating the properties of particles, namely position and speed; (7) iteration and termination.

[0076] According to the MOPSO algorithm, the number of particles is set to 200, the number of iterations is set to 50, the optimization range is the horizontal division range determined in step S1, and the optimization target is Y 1, Y 5. Y 7 are the smallest, and the algorithm optimization results are as follows Figure 4 As shown. The Pareto solution space is screened and the parameters A=0.3mm, B=0.15mm, C=0.36mm, D=0.42mm, E=1 are selected. The optimal parameter combination screened by the MOPSO algorithm is re-modeled and finite element simulation is performed, as shown in Figure 5 The figure shows the warpage simulation comparison before and after optimization. After optimization by the MOPSO algorithm, the maximum warpage value of the ASIC is reduced by 14.6%, the maximum warpage value of the DRAM chip is reduced by 61.7%, the average stress value of the silicon transfer board is reduced by 21.2%, and the maximum stress value of the C4 bump is reduced by 6.2%. Figure 6 The figure shows the comparison of the results before and after optimization. It can be seen that the present invention can efficiently screen out the optimal parameter combination from a variety of different bump parameters and material types, so as to reduce the warpage and stress generated by the storage and computing integrated heterogeneous integrated core particle 2.5D packaging product in a thermal service environment, and avoid the risk of product reliability failure due to warpage and excessive stress in advance.

[0077] Embodiment 2: The computer-readable storage medium of this embodiment stores a computer program thereon, which, when executed by a processor, implements the steps in the MOPSO-based intelligent optimization method for reliability of 2.5D integrated chip packaging of embodiment 1.

[0078] The computer-readable storage medium of this embodiment may be an internal storage unit of the terminal, such as a hard disk or memory of the terminal; the computer-readable storage medium of this embodiment may also be an external storage device of the terminal, such as a plug-in hard disk, a smart memory card, a secure digital card, a flash memory card, etc. equipped on the terminal; further, the computer-readable storage medium may also include both an internal storage unit of the terminal and an external storage device.

[0079] The computer-readable storage medium of this embodiment is used to store computer programs and other programs and data required by the terminal. The computer-readable storage medium can also be used to temporarily store data that has been output or is to be output.

[0080] Embodiment 3: The computer device of this embodiment includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps in the MOPSO-based intelligent optimization method for reliability of 2.5D integrated chip packaging are implemented in Embodiment 1.

[0081] In this embodiment, the processor may be a central processing unit, or other general-purpose processors, digital signal processors, application-specific integrated circuits, readily available programmable gate arrays or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. A portion of the memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0082] Those skilled in the art will appreciate that the contents disclosed in the embodiments may be provided as methods, systems, or computer program products. Therefore, the present solution may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware. Moreover, the present solution may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program codes.

[0083] The present solution is described with reference to the flowchart and / or block diagram of the method and computer program product according to the embodiment of the present solution. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions; these computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0084] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0085] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0086] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0087] The examples described in the present invention are merely descriptions of the preferred implementation modes of the present invention, and are not intended to limit the concept and scope of the present invention. Without departing from the design concept of the present invention, various modifications and improvements made to the technical solutions of the present invention by engineers and technicians in this field should all fall within the protection scope of the present invention.

Claims

1. A MOPSO-based intelligent optimization method for 2.5D packaging reliability of integrated storage and computing core particles, characterized in that: The steps include: S1. Determine the key bump parameters of the 2.5D packaging structure; the key bump parameters include the C2 bump diameter on the lower surface of the integrated chip, the C2 bump height, the C4 bump height of the silicon adapter board connected to the substrate, the C4 bump radius, and the C4 bump material. Divide them into different level combinations according to the Taguchi orthogonal method, and design an orthogonal experimental table; S2. Establish an equivalent finite element model of the 2.5D packaging structure according to the level combination divided by the Taguchi orthogonal experiment, set the thermal cycle temperature curve for the equivalent finite element model, simulate and obtain the quality indicators, and count them into the orthogonal experiment table; S3. For multi-target quality indicators, the percentage-based weighted evaluation method and the signal-to-noise ratio range analysis method are used to determine the ranking of the comprehensive influence of C2 bump diameter, C2 bump height, C4 bump height of the connection between the silicon adapter and the substrate, C4 bump radius, and C4 bump material; S4. Implement multi-objective comprehensive evaluation through signal-to-noise ratio range analysis, weight the results according to the calculated weight ratio, obtain comprehensive scores for different level combinations, analyze the orthogonal test design results, and determine the optimal 2.5D packaging structure parameter solution; S5. Based on the orthogonal experimental results in steps S2 and S4, the functions of stress, warpage and comprehensive score are fitted using the least squares method; S6. Use the MOPSO model to optimize multiple objective variables, modify the finite element model, simulate to obtain the optimized quality indicators, and verify the optimization results by comparing them with the simulation results of the corresponding structural parameters.

2. The method according to claim 1, characterized in that In S1, the C2 bump diameter on the lower surface of the integrated chip, the C2 bump height, the C4 bump height connecting the silicon adapter plate and the substrate, the C4 bump radius, and the C4 bump material are divided into different level combinations; the Taguchi orthogonal design experimental table is used to select the factors and their respective level values ​​and input them into the software for experimental design.

3. The method according to claim 2, characterized in that In S2, the quality indicators in the orthogonal experiment table are set as the maximum warpage value, average stress value, maximum warpage value of the ASIC integrated chip, and maximum stress value of the C4 bump connecting the silicon adapter and the substrate; a 2.5D packaging product finite element model is established based on the combined parameters listed in the Taguchi method, and then the product model is simulated using finite element software to obtain the quality indicators.

4. The method according to claim 1, characterized in that In S3, based on the range analysis method of signal-to-noise ratio, the influence ranking of C2 bump diameter, C2 bump height, C4 bump height of the connection between silicon adapter and substrate, C4 bump radius and C4 bump material on different quality indicators is determined; The signal-to-noise ratio range analysis method is used to obtain the influence weight of each factor on the quality index, and the weight ratio is determined.

5. The method according to claim 4, characterized in that In S4, the percentage-based weighted evaluation method and the range analysis method are used to obtain the comprehensive score of the impact of each factor on the quality index according to the weight ratio. The smaller the score, the better the parameter combination. The orthogonal test design results are analyzed, and the optimal parameter scheme is determined based on the comprehensive impact ranking and the signal-to-noise ratio. The percentage-based weighted evaluation formula is: ,in, i Indicates the test number, k Indicates the quality indicator number, Indicates i The overall score of the group test, Indicates the weight ratio, Represents quality indicator data results.

6. The method according to claim 5, characterized in that In S5, based on the orthogonal experimental table, the C2 bump diameter, C2 bump height, C4 bump height connecting the silicon adapter and the substrate, C4 bump radius, and C4 bump material are used as design variables, and the quality indicators ASIC integrated chip maximum warpage value and silicon adapter average stress value and comprehensive score function are fitted by the least squares method.

7. The method according to claim 6, characterized in that In S6, based on the fitted function, the MOPSO model is used to optimize multiple target variables. The optimization range is the horizontal division range determined in step S1, and the optimization results are compared with the corresponding structural parameter simulation results for verification.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps in the MOPSO-based intelligent optimization method for reliability of 2.5D integrated chip packaging are implemented as described in any one of claims 1 to 7.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps in the MOPSO-based intelligent optimization method for reliability of 2.5D integrated chip packaging are implemented as described in any one of claims 1 to 7.

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