Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof. The preparation method comprises: providing a substrate, the substrate comprising an active region; forming a gate structure and a dummy gate structure on the substrate, the gate structure overlapping the active region, the gate structure comprising a gate dielectric layer on the substrate and a gate conductive layer on the gate dielectric layer, the gate dielectric layer comprising a high dielectric constant layer, the gate conductive layer comprising a first conductive layer, the dummy gate structure comprising a second conductive layer on the substrate, the second conductive layer being of the same material as the first conductive layer; doping the active region to form a first doped region between the gate structure and the dummy gate structure; and forming a first contact plug on the first doped region, the first contact plug being electrically connected to the first doped region and the second conductive layer respectively.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As transistor sizes continue to shrink, high-k metal gate (HKMG) technology has become a near-essential technology for processes below 45nm. HKMG transistors have the same structure as planar transistors, replacing the traditional SiO2 layer with a high-k insulating layer and replacing the polysilicon gate with a metal gate. This improves transistor switching speeds and reduces gate leakage current.

[0003] In some semiconductor structures, dummy gate structures are often formed to meet gate pattern requirements. These dummy gate structures do not need to function as gates. However, in the manufacturing process of semiconductor structures using a high-k metal gate as a dummy gate structure, the high-k metal gate is exposed to the reaction chamber. Metal particles within the high-k metal gate can diffuse into the reaction chamber, causing contamination of the reaction chamber and affecting other processes performed there.

[0004] Therefore, how to effectively utilize these pseudo-gate structures while preventing metal particles in the High-K insulating layer from contaminating the reaction chamber has become the focus of current research. Summary of the Invention

[0005] The technical problem to be solved by the embodiments of the present disclosure is to provide a semiconductor structure and a preparation method thereof, which can effectively utilize the pseudo gate structure and at the same time avoid the problem of metal particles in the high dielectric constant metal gate causing contamination to the reaction chamber.

[0006] An embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate, wherein the substrate includes an active area; forming a gate structure and a dummy gate structure on the substrate, wherein the gate structure overlaps with the active area, the gate structure includes a gate dielectric layer located on the substrate and a gate conductive layer located on the gate dielectric layer, the gate dielectric layer includes a high dielectric constant layer, the gate conductive layer includes a first conductive layer, and the dummy gate structure includes a second conductive layer located on the substrate, the second conductive layer being made of the same material as the first conductive layer; doping the active area to form a first doped area located between the gate structure and the dummy gate structure; forming a first contact plug on the first doped area, wherein the first contact plug is electrically connected to the first doped area and the second conductive layer, respectively.

[0007] In one embodiment, the gate structure and the dummy gate structure are formed on the substrate, including: forming a first stacked structure on the substrate, the first stacked structure including a high dielectric constant material layer; removing the first stacked structure in the area corresponding to the dummy gate structure; forming a second stacked structure on the substrate, wherein the second stacked structure includes a first conductive material layer, and the second stacked structure covers the first stacked structure in the area corresponding to the gate structure; patterning the second stacked structure and the first stacked structure to form the gate dielectric layer and the gate conductive layer in the area corresponding to the gate structure, and forming the second conductive layer in the area corresponding to the dummy gate structure.

[0008] In one embodiment, the gate conductive layer also includes a third conductive layer, which is arranged between the gate dielectric layer and the first conductive layer, and the third conductive layer is made of a different material from the first conductive layer; forming the gate structure and the dummy gate structure on the substrate includes: the first stacked structure also includes a third conductive material layer, and the third conductive material layer covers the high dielectric constant material layer; patterning the second stacked structure and the first stacked structure includes: forming the third conductive layer.

[0009] In one embodiment, the gate dielectric layer also includes an interface layer, and the interface layer is arranged on the surface of the active area. The preparation method also includes: before the step of forming the first stacked structure on the substrate, forming an interface material layer in the active area of ​​the substrate; after removing the first stacked structure in the area corresponding to the pseudo gate structure, removing the interface material layer in the area corresponding to the pseudo gate structure; patterning the second stacked structure and the first stacked structure, including: patterning the interface material layer to form the interface layer in the area corresponding to the gate structure.

[0010] In one embodiment, forming the gate structure and the dummy gate structure on the substrate further includes: forming a first isolation layer covering sidewalls of the gate dielectric layer and the gate conductive layer, and a second isolation layer covering sidewalls of the second conductive layer.

[0011] In one embodiment, a first contact plug is formed on the first doped region, including: forming a planarization layer, the planarization layer filling between the gate structure and the dummy gate structure, and covering the gate structure, the dummy gate structure and the surface of the substrate; forming a contact hole, the contact hole penetrating the planarization layer to the first doped region, and the sidewall of the contact hole exposing the second conductive layer; filling the contact hole with a conductive material to form the first contact plug.

[0012] In one embodiment, in the step of forming the contact hole, the contact hole also exposes a portion of the top surface of the second conductive layer; in the step of forming the first contact plug, the first contact plug also covers a portion of the top surface of the second conductive layer.

[0013] In one embodiment, doping the active area further includes: forming a second doping area located on a side of the gate structure away from the dummy gate structure; the preparation method further includes: forming a first contact plug on the first doping area and forming a second contact plug on the second doping area at the same time.

[0014] An embodiment of the present disclosure also provides a semiconductor structure, comprising: a substrate, comprising an active area; a gate structure located on the substrate, overlapping with the active area, wherein the gate structure comprises a gate dielectric layer located on the substrate and a gate conductive layer located on the gate dielectric layer, the gate dielectric layer comprises a high dielectric constant layer, and the gate conductive layer comprises a first conductive layer; a dummy gate structure located on the substrate, wherein the dummy gate structure comprises a second conductive layer located on the substrate, the second conductive layer is made of the same material as the first conductive layer, and the active area comprises a first doped region located between the gate structure and the dummy gate structure; a first contact plug located on the first doped region, wherein the first contact plug is electrically connected to the first doped region and the second conductive layer, respectively.

[0015] In one embodiment, the gate conductive layer further includes a third conductive layer, which is disposed between the gate dielectric layer and the first conductive layer, and the third conductive layer and the first conductive layer are made of different materials.

[0016] In one embodiment, the gate dielectric layer further includes an interface layer, and the interface layer is located between the substrate and the high dielectric constant layer.

[0017] In one embodiment, the present invention further includes: a first isolation layer, at least covering the sidewalls of the gate dielectric layer and the gate conductive layer; and a second isolation layer, at least covering the sidewalls of the second conductive layer.

[0018] In one embodiment, a shallow trench isolation structure is provided in the substrate, the shallow trench isolation structure divides the substrate into a plurality of active areas, and the second conductive layer covers the active areas and the shallow trench isolation structure.

[0019] In one embodiment, a planarization layer is further included, which is filled between the gate structure and the dummy gate structure and covers the gate structure, the dummy gate structure and the surface of the substrate. The first contact plug passes through the planarization layer and is electrically connected to the first doped region.

[0020] In one embodiment, the first contact plug covers the sidewalls of the second conductive layer to be electrically connected to the second conductive layer, or the first contact plug covers the sidewalls and a portion of the top surface of the second conductive layer.

[0021] In one embodiment, the active region further includes a second doped region located on a side of the gate structure away from the dummy gate structure, and the semiconductor structure further includes a second contact plug located on the second doped region, and the second contact plug is electrically connected to the second doped region.

[0022] The method for fabricating a semiconductor structure provided by the embodiments of the present disclosure can form a dummy gate structure on a substrate that does not include a high-k dielectric layer, thereby preventing particles in the high-k dielectric layer from diffusing into the reaction chamber and thereby preventing contamination of the reaction chamber. Furthermore, a first contact plug is electrically connected to the dummy gate structure, and the dummy gate structure is used to provide a potential to the first contact plug, eliminating the need for forming a metal trace connected to the first contact plug. This reduces the area of ​​the metal traces, provides more area for metal traces of other devices, and reduces the difficulty of trace routing for the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 1 is a schematic diagram of the steps of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0024] Figures 2A-2P It is a process flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The specific implementation of the semiconductor structure and the preparation method thereof provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0026] Figure 1 This is a schematic diagram of the steps of the method for preparing a semiconductor structure according to an embodiment of the present disclosure. Figure 1 The preparation method includes: step S10, providing a substrate, wherein the substrate includes an active area; step S11, forming a gate structure and a dummy gate structure on the substrate, wherein the gate structure overlaps with the active area, the gate structure includes a gate dielectric layer located on the substrate and a gate conductive layer located on the gate dielectric layer, the gate dielectric layer includes a high dielectric constant layer, the gate conductive layer includes a first conductive layer, and the dummy gate structure includes a second conductive layer located on the substrate, and the second conductive layer is made of the same material as the first conductive layer; step S12, doping the active area to form a first doped region located between the gate structure and the dummy gate structure; step S13, forming a first contact plug on the first doped region, wherein the first contact plug is electrically connected to the first doped region and the second conductive layer, respectively.

[0027] The method for fabricating a semiconductor structure provided by the embodiments of the present disclosure can form a dummy gate structure on a substrate that does not include a high-k dielectric layer, thereby preventing particles in the high-k dielectric layer from diffusing into the reaction chamber and thereby preventing contamination of the reaction chamber. Furthermore, the first contact plug is electrically connected to the dummy gate structure, and the dummy gate structure is used to provide a potential to the first contact plug, eliminating the need for forming a metal trace connected to the first contact plug. This reduces the area of ​​the metal traces, provides more area for metal traces of other devices, and reduces the difficulty of trace routing for the semiconductor structure.

[0028] Figures 2A-2P It is a process flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure.

[0029] See also Figure 1 、 Figure 2A and Figure 2B ,in, Figure 2A For top view, Figure 2B For the Figure 2A In the cross-sectional view along line A-A1, step S10 is to provide a substrate 200 , wherein the substrate 200 includes an active area 201 .

[0030] The substrate 200 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc.; the substrate 200 may also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The substrate 200 may also be a stacked structure, such as a silicon / silicon germanium stack, etc.; in addition, the substrate 200 may be an ion-doped substrate, which may be P-type doped or N-type doped; a plurality of peripheral devices may also be formed in the substrate 200, such as field-effect transistors, capacitors, inductors, and / or diodes, etc. In this embodiment, the substrate 200 is a silicon substrate, which may also include other device structures, such as transistor structures, metal wiring structures, etc., but since they are not related to the embodiments of the present disclosure, they are not shown.

[0031] In some embodiments, a shallow trench isolation (STI) structure 202 is provided within the substrate 200. The STI structure 202 divides the substrate 200 into multiple active regions 201. The STI structure 202 includes, but is not limited to, an oxide isolation structure or a composite isolation structure of an oxide layer and a nitride layer. In this embodiment, the STI structure 202 is an oxide isolation structure. The figure schematically illustrates two active regions 201, which are separated by the STI structure 202.

[0032] See also Figure 1 、 2I andFigure 2J ,in, Figure 2I For top view, Figure 2J For the Figure 2I In the cross-sectional view along the A-A1 line, step S11, a gate structure 210 and a dummy gate structure 220 are formed on the substrate 200, wherein the gate structure 210 overlaps with the active area 201, the gate structure 210 includes a gate dielectric layer 211 located on the substrate 200 and a gate conductive layer 212 located on the gate dielectric layer 211, the gate dielectric layer 211 includes a high dielectric constant layer 2111, the gate conductive layer 212 includes a first conductive layer 2121, and the dummy gate structure 220 includes a second conductive layer 221 located on the substrate 200, and the second conductive layer 221 is made of the same material as the first conductive layer 2121.

[0033] The gate structure 210 is a high-k metal gate. The gate dielectric layer 211 includes a high-k layer 2111, and the gate dielectric layer 211 is disposed between the first conductive layer 2121 and the substrate 200. The gate dielectric layer 211 covers the surface of the active area 201. The dummy gate structure 220 does not include a high-k layer, and no gate dielectric layer is disposed between it and the substrate 200. A second conductive layer 221 is disposed on the surface of the substrate 200, with a portion of the second conductive layer 221 covering the surface of the active area 201 and another portion covering the surface of the shallow trench isolation structure 202.

[0034] The gate structure 210 and the dummy gate structure 220 both extend in a direction parallel to the surface of the substrate 200 (such as the X direction in the figure), and in another direction parallel to the surface of the substrate 200 (such as the Y direction in the figure), the gate structure 210 and the dummy gate structure 220 are arranged at intervals. In some embodiments, a plurality of gate structures 210 are formed on the substrate 200, and the plurality of gate structures 210 and the dummy gate structures 220 are arranged at intervals in a direction parallel to the surface of the substrate 200. For example, Figure 2C Two gate structures 210 and one dummy gate structure 220 are schematically shown. The two gate structures 210 and the one dummy gate structure 220 extend along the X direction and are spaced apart along the Y direction.

[0035] As an example, an embodiment of the present disclosure provides a method for forming a gate structure 210 and a dummy gate structure 220 on a substrate 200. The method includes:

[0036] See also Figure 2C and Figure 2D ,in, Figure 2C For top view, Figure 2D For the Figure 2C In the cross-sectional view along line A-A1, a first stacked structure 230 is formed on the substrate 200 . The first stacked structure 230 includes a high dielectric constant material layer 231 .

[0037] The high dielectric constant material layer 231 uses a high dielectric constant material, and the high dielectric constant material includes but is not limited to one or more of hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0038] In some embodiments, an interface material layer 240 is provided on the surface of the active region 201, and the first stacked structure 230 covers the interface material layer 240. Specifically, the high-k dielectric material layer 231 covers the interface material layer 240. The interface material layer 240 can be formed by an ISSG (In Situ Steam Generation) process. The interface material layer 240 includes, but is not limited to, a silicon oxide or silicon oxynitride layer.

[0039] In some embodiments, the first stacked structure 230 further includes a third conductive material layer 232, and the third conductive material layer 232 covers the high dielectric constant material layer 231. The third conductive material layer 232 includes but is not limited to a polysilicon layer.

[0040] In some embodiments, the first stacked structure 230 further includes a work function material layer 233 and a metal TiN material layer 234 with a higher melting point, the work function material layer 233 covers the high dielectric constant material layer 231, the metal TiN material layer 234 covers the work function material layer 233, and the third conductive material layer 232 covers the metal TiN material layer 234.

[0041] The process of forming the high-k material layer 231 , the work function material layer 233 , the metal TiN material layer 234 and the third conductive material layer 232 on the substrate 200 is a high-k metal gate process, which will not be described in detail here.

[0042] See also Figure 2E and Figure 2F ,in, Figure 2E For top view, Figure 2F For the Figure 2E In the cross-sectional view taken along line A-A1, the first stacked structure 230 in the region B1 corresponding to the dummy gate structure 220 is removed, and the substrate 200 is exposed in the region B1 corresponding to the dummy gate structure 220.

[0043] In some embodiments, a patterned first mask layer 290 is formed on the first stacked structure 230. The first mask layer 290 shields the first stacked structure 230 in the region B2 corresponding to the gate structure 210, between the region B2 corresponding to the gate structure 210 and the region B1 corresponding to the dummy gate structure 220, and between the regions B2 corresponding to the gate structure 210, and exposes the first stacked structure 230 in the region B1 corresponding to the dummy gate structure 220. The first mask layer 290 includes, but is not limited to, a photoresist layer, which covers the third conductive material layer 232.

[0044] In some embodiments, if the active region 201 has an interface material layer 240 on its surface, the high-k dielectric material layer 231 may diffuse or react with the interface material layer 240 at the interface. Therefore, after removing the first stacked structure 230, there may be residues of the high-k dielectric material on the surface of the interface material layer 240. Therefore, after removing the first stacked structure 230, the interface material layer 240 in the region B1 corresponding to the dummy gate structure 220 is removed to remove the residues of the high-k dielectric material. The interface material layer 240 in the region B2 corresponding to the gate structure 210 is retained.

[0045] See also Figure 2G and Figure 2H ,in, Figure 2G For top view, Figure 2H For the Figure 2G In the cross-sectional view along line A-A1, a second stacked structure 250 is formed on the substrate 200, wherein the second stacked structure 250 includes a first conductive material layer 251, and in the region B2 corresponding to the gate structure 210, the second stacked structure 250 covers the first stacked structure 230, and in the region B1 corresponding to the dummy gate structure 220, the second stacked structure 250 covers the surface of the substrate 200.

[0046] Before forming the second stacked structure 250 on the substrate 200 , the first mask layer 290 is removed to expose the first stacked structure 230 in the region B2 corresponding to the gate structure 210 , so as to facilitate connection between the second stacked structure 250 and the first stacked structure 230 .

[0047] The first conductive material layer 251 includes, but is not limited to, a metal tungsten layer, a metal TiN layer, and a composite thereof. In some embodiments, the second stacked structure 250 further includes a gate capping material layer 252, which covers the first conductive material layer 251 to protect it. The gate capping material layer 252 includes, but is not limited to, a SiN layer. In some embodiments, in a direction perpendicular to the surface of the substrate 200 (e.g., the Z direction in the figure), the surface of the gate capping material layer 252 in the region B2 corresponding to the gate structure 210 is flush with the surface of the region B1 corresponding to the dummy gate structure 220.

[0048] See also Figure 2I and Figure 2J ,in, Figure 2I For top view, Figure 2J For the Figure 2I In the cross-sectional view along the A-A1 line, the second stacked structure 250 and the first stacked structure 230 are patterned to form a gate dielectric layer 211 and a gate conductive layer 212 in the region B2 corresponding to the gate structure 210, and to form a second conductive layer 221 in the region B1 corresponding to the dummy gate structure 220.

[0049] In some embodiments, the method of patterning the second stacked structure 250 and the first stacked structure 230 includes: forming a patterned hard mask layer on the second stacked structure 250 using photolithography and etching processes; and dry etching the second stacked structure 250 and the first stacked structure 230 using the hard mask layer as a shield.

[0050] In region B2 corresponding to the gate structure 210, the gate cap material layer 252 is patterned to form a first gate cap layer 213, the first conductive material layer 251 is patterned to form a first conductive layer 2121, the third conductive material layer 232 is patterned to form a third conductive layer 2122, the metal TiN material layer 234 is patterned to form a metal TiN layer 2123, the work function material layer 233 is patterned to form a work function layer 2124, the high dielectric constant material layer 231 is patterned to form a high dielectric constant layer 2111, and the interface material layer 240 is patterned to form an interface layer 2112. The first conductive layer 2121, the third conductive layer 2122, the metal TiN layer 2123, and the work function layer 2124 collectively serve as the gate conductive layer 212, and the high dielectric constant layer 2111 and the interface layer 2112 collectively serve as the gate dielectric layer 211. In the region B1 corresponding to the dummy gate structure 220 , the gate cover material layer 252 is patterned to form a second gate cover layer 222 , and the first conductive material layer 251 is patterned to form a second conductive layer 221 . The first conductive layer 2121 and the second conductive layer 221 are made of the same material.

[0051] In region B2 corresponding to gate structure 210, metallic TiN layer 2123 can address polysilicon gate depletion. Work function layer 2124 can address Fermi level pinning to adjust the transistor's threshold voltage. For NMOS transistors, work function layer 2124 can be La2O3, and for PMOS transistors, work function layer 2124 can be Al2O3. Interface layer 2112 is used to enhance the bonding strength between high-k dielectric layer 2111 and substrate 200, repair defects at the interface between high-k dielectric layer 2111 and substrate 200, and improve the interface state between high-k dielectric layer 2111 and substrate 200.

[0052] Please continue reading Figure 2I and Figure 2J After patterning the second stacked structure 250 and the first stacked structure 230, the fabrication method further includes forming a first isolation layer 214 covering the sidewalls of the gate dielectric layer 211 and the gate conductive layer 212, and a second isolation layer 223 covering the sidewalls of the second conductive layer 221. The first isolation layer 214 is used to protect the gate dielectric layer 211 and the gate conductive layer 212 during the subsequent doping process, and the second isolation layer 223 is used to protect the second conductive layer 221 during the subsequent doping process, thereby preventing the gate dielectric layer 211, the gate conductive layer 212, and the second conductive layer 221 from being affected by the doping process. In some embodiments, the first isolation layer 214 also covers the first gate cap layer 213, and the second isolation layer 223 also covers the second gate cap layer 222.

[0053] In some embodiments, the first isolation layer 214 and the second isolation layer 223 may be made of the same material, including but not limited to SiN. The method for forming the first isolation layer 214 and the second isolation layer 223 includes: forming an isolation material layer on the sidewalls and surface of the gate structure 210 and the dummy gate structure 220 using a chemical vapor deposition process or an atomic layer deposition process; and removing the isolation material layer on the top surface of the gate structure 210 and the dummy gate structure 220 to form the first isolation layer 214 and the second isolation layer 223.

[0054] The above steps can form the gate structure 210 and the dummy gate structure 220 on the substrate 200 .

[0055] See also Figure 1 and Figure 2K and Figure 2L ,in, Figure 2K For top view, Figure 2L For the Figure 2K In the cross-sectional view along line A-A1, in step S12, the active region 201 is doped to form a first doped region 203 located between the gate structure 210 and the dummy gate structure 220.

[0056] In this step, the active area 201 is doped with the gate structure 210, the dummy gate structure 220, the first isolation layer 214 and the second isolation layer 223 as shielding to form a first doped area 203, wherein the type of doping particles can be determined according to the type of transistor. For example, in the area B2 corresponding to the gate structure 210, if an NMOS transistor needs to be formed, the active area 201 is doped with N-type particles, and if a PMOS transistor needs to be formed, the active area 201 is doped with P-type particles.

[0057] In some embodiments, doping the active area 201 also includes: forming a second doping region 204 located on the side of the gate structure 210 away from the dummy gate structure 220 in a direction parallel to the surface of the substrate 200 (such as the Y direction in the figure), and the second doping region 204 has the same doping type as the first doping region 203.

[0058] After forming the first doping region 203 and the second doping region 204 , an annealing process is further performed. After the annealing, the doping ions in the active region diffuse to below the first isolation layer 214 and the second isolation layer 223 .

[0059] See also Figure 1 and Figure 2O and Figure 2P ,in, Figure 2O For top view, Figure 2P For the Figure 2O In the cross-sectional view along line A-A1, step S13, a first contact plug 260 is formed on the first doping region 203, wherein the first contact plug 260 is electrically connected to the first doping region 203 and the second conductive layer 221 respectively. Figure 2O The gate structure 210 , the dummy gate structure 220 and the active region 201 are schematically depicted using dotted lines.

[0060] The first doped region 203 and the second conductive layer 221 are electrically connected via a first contact plug 260. The second conductive layer 221 provides a potential to the first contact plug, thereby electrically leading the first doped region 203 through the second conductive layer 221. This eliminates the need for metal traces connected to the first contact plug 260, reduces the area of ​​metal traces, provides more area for metal traces in other structures, and reduces the difficulty of trace routing in the semiconductor structure. The first contact plug 260 includes, but is not limited to, a polysilicon plug.

[0061] In some embodiments, the preparation method further includes: forming a first contact plug 260 on the first doping region 203 and forming a second contact plug 261 on the second doping region 204 at the same time, wherein the second contact plug 261 is electrically connected to the second doping region 204 to electrically lead out the second doping region 204.

[0062] As an example, the embodiment of the present disclosure further provides a method for forming the first contact plug 260 and the second contact plug 261. The method includes:

[0063] See also Figure 1 and Figure 2M and Figure 2N ,in, Figure 2M For top view, Figure 2N For the Figure 2M Cross-section along line A-A1.

[0064] A planarization layer 270 is formed between the gate structure 210 and the dummy gate structure 220, and covers the gate structure 210, the dummy gate structure 220, and the surface of the substrate 200. The planarization layer 270 includes, but is not limited to, a silicon nitride layer. In some embodiments, the planarization layer 270 also covers the surfaces of the first isolation layer 214 and the second isolation layer 223. The surface of the substrate 200 includes the exposed surface of the active area 201 and the exposed surface of the shallow trench isolation structure 202.

[0065] A contact hole 280 is formed, which penetrates the planarization layer 270 to the first doped region 203 , and the sidewall of the contact hole 280 exposes the second conductive layer 221 . In this step, the contact hole 280 also exposes the sidewall of the second gate cap layer 222 .

[0066] In this step, a hard mask layer can be formed on the surface of the planarization layer 270; the hard mask layer is patterned using photolithography and etching processes to form an opening corresponding to the contact hole 280 area; and the planarization layer 270 is etched using the hard mask layer as a barrier to form the contact hole 280.

[0067] In this step, the second isolation layer 223 corresponding to the contact hole 280 region is also removed.

[0068] In some embodiments, a contact hole 280 is also formed on a side of the gate structure 210 away from the dummy gate structure 220 . The contact hole 280 penetrates the planarization layer 270 to the second doped region 204 . In this region, the contact hole 280 does not expose the gate structure 210 .

[0069] In some embodiments, the first doped region 203 and the second doped region 204 are over-etched so that the bottom surface of the contact hole 280 is lower than the surface of the active region 201, thereby increasing the contact area between the subsequently formed first contact plug 260 and the first doped region 203, and the contact area between the second contact plug 261 and the second doped region 204, thereby reducing the contact resistance.

[0070] In some embodiments, the second gate capping layer 222 is also partially removed, and the contact hole 280 further exposes a portion of the top surface of the second conductive layer 221 to increase the opening area of ​​the top of the contact hole 280 .

[0071] See also Figure 1 and Figure 2O and Figure 2P ,in, Figure 2O For top view, Figure 2P For the Figure 2O In the cross-sectional view taken along line A-A1, a conductive material is filled into the contact hole 280 to form a first contact plug 260 and a second contact plug 261. The conductive material includes but is not limited to polysilicon.

[0072] In some embodiments, the first contact plug 260 also covers a portion of the top surface of the second conductive layer 221, thereby increasing the area of ​​the top of the first contact plug 260 and increasing the reliability of the subsequent electrical connection between the first contact plug 260 and the external device; and also increasing the contact area between the first contact plug 260 and the second conductive layer 221, thereby reducing the contact resistance between the first contact plug 260 and the second conductive layer 221.

[0073] The method for preparing a semiconductor structure provided by an embodiment of the present disclosure forms a dummy gate structure 220 on a substrate 200 as an electrical lead for an active area 201. The dummy gate structure 220 does not include a high dielectric constant layer 2111, which can prevent particles in the high dielectric constant layer 2111 from diffusing into the reaction chamber, thereby improving the performance of the semiconductor structure and preventing the reaction chamber from being contaminated.

[0074] An embodiment of the present disclosure also provides a semiconductor structure manufactured using the above-mentioned manufacturing method. Figures 2A-2P The semiconductor structure includes a substrate 200, a gate structure 210, a dummy gate structure 220, and a first contact plug 260 located on the substrate 200. The gate structure 210 and the dummy gate structure 220 extend in a direction parallel to the surface of the substrate 200 (e.g., the X direction in the figure). In some embodiments, the semiconductor structure includes a plurality of gate structures 210, and the plurality of gate structures 210 and dummy gate structures 220 are arranged in a direction parallel to the surface of the substrate 200 (e.g., the Y direction in the figure). Two gate structures 210 are schematically illustrated in the figure.

[0075] The substrate 200 includes an active region 201. In some embodiments, a shallow trench isolation (STI) structure 202 is provided within the substrate 200. The STI structure 202 divides the substrate 200 into a plurality of active regions 201. Two active regions 201 are schematically illustrated in the figure, and the two active regions 201 are isolated by the STI structure 202.

[0076] The active region 201 includes a first doped region 203 located between the gate structure 210 and the dummy gate structure 220. That is, in a direction parallel to the surface of the substrate 200 (e.g., the Y direction in the figure), the first doped region 203 is located between the gate structure 210 and the dummy gate structure 220. The type of doping particles in the first doped region 203 can be determined according to the type of transistor. For example, in region B2 corresponding to the gate structure 210, if an NMOS transistor is to be formed, the active region 201 is doped with N-type particles, while if a PMOS transistor is to be formed, the active region 201 is doped with P-type particles.

[0077] In some embodiments, the active region 201 further includes a second doped region 204. In a direction parallel to the surface of the substrate 200 (e.g., direction Y in the figure), the second doped region 204 is located on a side of the gate structure 210 away from the dummy gate structure 220. The doping type of the second doped region 204 is the same as the doping type of the first doped region 203.

[0078] The gate structure 210 overlaps with the active area 201 , that is, in a direction perpendicular to the surface of the substrate 200 (eg, the Z direction in the figure), the gate structure 210 partially overlaps with the active area 201 , wherein the overlapping area serves as the channel region of the transistor.

[0079] The gate structure 210 is a high-k metal gate, which includes a gate dielectric layer 211 located on the substrate 200 and a gate conductive layer 212 located on the gate dielectric layer 211 .

[0080] The gate dielectric layer 211 includes a high dielectric constant layer 2111, and the material of the high dielectric constant layer 2111 includes but is not limited to one or more of hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0081] In some embodiments, the gate dielectric layer 211 further includes an interface layer 2112, which is located between the substrate 200 and the high-k dielectric layer 2111. Specifically, the interface layer 2112 covers the surface of the active region 201, and the high-k dielectric layer 2111 covers the surface of the interface layer 2112. The interface layer 2112 is used to enhance the bonding strength between the high-k dielectric layer 2111 and the substrate 200, repair defects at the interface between the high-k dielectric layer 2111 and the substrate 200, and improve the interface state between the high-k dielectric layer 2111 and the substrate 200.

[0082] The gate conductive layer 212 includes a first conductive layer 2121. In some embodiments, the gate conductive layer 212 further includes a third conductive layer 2122, which is disposed between the gate dielectric layer 211 and the first conductive layer 2121. The third conductive layer 2122 is formed of a different material than the first conductive layer 2121. For example, in some embodiments, the first conductive layer 2121 includes a composite layer of a metal tungsten layer and a metal TiN layer, and the third conductive layer 2122 is a polysilicon layer.

[0083] In some embodiments, the gate conductive layer 212 further includes a metal TiN layer 2123 and a work function layer 2124. In a direction perpendicular to the surface of the substrate 200 (such as the Z direction in the figure), the work function layer 2124 covers the high dielectric constant layer 2111, the metal TiN layer 2123 covers the work function layer 2124, the third conductive layer 2122 covers the metal TiN layer 2123, and the first conductive layer 2121 covers the third conductive layer 2122. The metal TiN layer 2123 can solve the problem of polysilicon gate depletion. The work function layer 2124 can solve the pinning phenomenon of the Fermi level to adjust the threshold voltage of the transistor. The materials of the work function layer 2124 of the NMOS transistor and the PMOS transistor are different. For example, in the two gate structures shown in the figure, one gate structure is a gate structure of an NMOS transistor, and its work function layer is La2O3, and the other gate structure is a gate structure of a PMOS transistor, and its work function layer is Al2O3. In some embodiments, the gate structure 210 further includes a first gate capping layer 213 covering the first conductive layer 2121. The first gate capping layer 213 is used to protect the first conductive layer 2121 from damage and contamination during semiconductor processing. The first gate capping layer 213 includes, but is not limited to, a SiN layer.

[0084] The dummy gate structure 220 includes a second conductive layer 221 located on the substrate 200. The second conductive layer 221 is made of the same material as the first conductive layer 2121; for example, both comprise a composite layer of a metal tungsten layer and a metal TiN layer. The second conductive layer 221 directly covers the surface of the substrate 200. For example, in some embodiments, the second conductive layer 221 directly covers the surfaces of the active area 201 and the shallow trench isolation structure 202. The absence of a high-k dielectric layer 2111 between the second conductive layer 221 and the substrate 200 prevents particles in the high-k dielectric layer 2111 from diffusing into the reaction chamber, thereby preventing contamination of the reaction chamber.

[0085] In some embodiments, the dummy gate structure 220 further includes a second gate capping layer 222. In a direction perpendicular to the surface of the substrate 200 (e.g., the Z direction in the figure), the second gate capping layer 222 covers the surface of the second conductive layer 221. In some embodiments, in a direction perpendicular to the surface of the substrate 200 (e.g., the Z direction in the figure), the first gate capping layer 213 is flush with the surface of the second gate capping layer 222.

[0086] The first contact plug 260 is located on the first doped region 203, and the first contact plug 260 is electrically connected with the first doped region 203 and the second conductive layer 221 respectively. The first doped region 203 and the second conductive layer 221 are electrically connected through the first contact plug 260, so that the first doped region 203 can be electrically led out through the second conductive layer 221. The first contact plug 260 is electrically connected with the second conductive layer 221, and the second conductive layer 221 is used to provide a potential to the first contact plug 260, so that a metal trace connected with the first contact plug 260 does not need to be formed, the area of the metal trace is reduced, a larger area is provided for the metal trace of other devices, and the difficulty of the trace of the semiconductor structure is reduced. The first contact plug 260 includes but is not limited to a polysilicon plug.

[0087] In some embodiments, the semiconductor structure includes a plurality of first contact plugs 260, and the plurality of first contact plugs 260 are electrically connected with the same dummy gate structure 220, so that a common source structure design is achieved. In some embodiments, the first doped regions 203 of two active regions 201 can be electrically connected to the dummy gate structure 220 through the same first contact plug 260, so as to further reduce the complexity of the metal trace.

[0088] The first contact plug 260 covers at least the sidewall of the second conductive layer 221 to be electrically connected with the second conductive layer 221. In some embodiments, the first contact plug 260 not only covers the sidewall of the second conductive layer 221, but also covers part of the top surface of the second conductive layer 221, so as to increase the area of the top of the first contact plug 260, increase the reliability of the subsequent electrical connection of the first contact plug 260 with an external device, and increase the contact area of the first contact plug 260 with the second conductive layer 221, and reduce the contact resistance of the first contact plug 260 with the second conductive layer 221.

[0089] In some embodiments, the semiconductor structure further includes a second contact plug 261 located on the second doped region 204, and the second contact plug 261 is electrically connected with the second doped region 204 to electrically lead out the second doped region 204. The second contact plug 261 is electrically insulated from the gate structure 210.

[0090] In some embodiments, in the direction (such as the Z direction in the figure) of the surface of the vertical substrate 200, the bottom surface of the first contact plug 260 and the second contact plug 261 is lower than the surface of the active region 201, so as to increase the contact area of the first contact plug 260 with the first doped region 203 and the contact area of the second contact plug 261 with the second doped region 204, and further reduce the contact resistance.

[0091] In some embodiments, the semiconductor structure further includes a first isolation layer 214 and a second isolation layer 223. The first isolation layer 214 covers at least the sidewalls of the gate dielectric layer 211 and the gate conductive layer 212, thereby protecting the gate dielectric layer 211 and the gate conductive layer 212. In some embodiments, the first isolation layer 214 also covers the sidewalls of the first gate capping layer 213. The second isolation layer 223 covers at least the sidewalls of the second conductive layer 221, thereby protecting the second conductive layer 221. In some embodiments, the second isolation layer 223 also covers the sidewalls of the second gate capping layer 222.

[0092] In some embodiments, the semiconductor structure further includes a planarization layer 270. The planarization layer 270 is filled between the gate structure 210 and the dummy gate structure 220 and covers the gate structure 210, the dummy gate structure 220, and the surface of the substrate 200. The first contact plug 260 penetrates the planarization layer 270 and is electrically connected to the first doped region 203. The second contact plug 261 penetrates the planarization layer 270 and is electrically connected to the second doped region 204. In some embodiments, the planarization layer 270 also covers the surfaces of the first isolation layer 214 and the second isolation layer 223. The planarization layer 270 includes, but is not limited to, a silicon nitride layer.

[0093] The semiconductor structure provided by the embodiment of the present disclosure has a dummy gate structure 220 on the substrate 200 as an electrical lead-out of the active area 201. The dummy gate structure 220 does not include a high dielectric constant layer 2111, which can prevent particles in the high dielectric constant layer 2111 from diffusing into the reaction chamber, thereby preventing the reaction chamber from being contaminated. At the same time, the second conductive layer 221 is used to provide a potential to the first contact plug 260, reducing the wiring difficulty of the semiconductor structure.

[0094] The above is only a preferred embodiment of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate, wherein the substrate comprises an active region; forming a gate structure and a dummy gate structure on the substrate, wherein the gate structure overlaps with the active area, the gate structure comprises a gate dielectric layer located on the substrate and a gate conductive layer located on the gate dielectric layer, the gate dielectric layer comprises a high dielectric constant layer, the gate conductive layer comprises a first conductive layer, and the dummy gate structure comprises a second conductive layer located on the substrate, the second conductive layer being made of the same material as the first conductive layer; doping the active region to form a first doped region located between the gate structure and the dummy gate structure; forming a first contact plug on the first doped region, wherein the first contact plug is electrically connected to the first doped region and the second conductive layer respectively; The step of forming the gate structure and the dummy gate structure on the substrate includes: forming a first stacked structure on the substrate, wherein the first stacked structure includes a high dielectric constant material layer; removing the first stacked structure in the region corresponding to the dummy gate structure; forming a second stacked structure on the substrate, wherein the second stacked structure includes a first conductive material layer, and the second stacked structure covers the first stacked structure in a region corresponding to the gate structure; The second stacked structure and the first stacked structure are patterned to form the gate dielectric layer and the gate conductive layer in a region corresponding to the gate structure, and to form the second conductive layer in a region corresponding to the dummy gate structure.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The gate conductive layer further includes a third conductive layer, which is disposed between the gate dielectric layer and the first conductive layer, and the third conductive layer and the first conductive layer are made of different materials; Forming the gate structure and the dummy gate structure on the substrate includes: The first stacked structure further includes a third conductive material layer, wherein the third conductive material layer covers the high dielectric constant material layer; Patterning the second stacked structure and the first stacked structure includes forming the third conductive layer.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The gate dielectric layer further includes an interface layer, and the interface layer is disposed on a surface of the active region. The preparation method further includes: Before the step of forming the first stacked structure on the substrate, an interface material layer is formed in the active area of ​​the substrate; After removing the first stacked structure in the area corresponding to the dummy gate structure, removing the interface material layer in the area corresponding to the dummy gate structure; Patterning the second stacked structure and the first stacked structure includes: patterning the interface material layer to form the interface layer in a region corresponding to the gate structure.

4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, wherein: forming the gate structure and the dummy gate structure on the substrate, further comprising: A first isolation layer covering the sidewalls of the gate dielectric layer and the gate conductive layer and a second isolation layer covering the sidewalls of the second conductive layer are formed.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 3, wherein: forming a first contact plug on the first doped region, comprising: forming a planarization layer, wherein the planarization layer is filled between the gate structure and the dummy gate structure and covers the gate structure, the dummy gate structure and the surface of the substrate; forming a contact hole, wherein the contact hole penetrates the planarization layer to the first doped region, and a sidewall of the contact hole exposes the second conductive layer; The contact hole is filled with a conductive material to form the first contact plug.

6. The method for preparing a semiconductor structure according to claim 5, wherein: In the step of forming the contact hole, the contact hole also exposes a portion of the top surface of the second conductive layer; in the step of forming the first contact plug, the first contact plug also covers a portion of the top surface of the second conductive layer.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 3, wherein: Doping the active region further includes: forming a second doping region located on a side of the gate structure away from the dummy gate structure; The preparation method further includes: forming a first contact plug on the first doping region and forming a second contact plug on the second doping region at the same time.

8. A semiconductor structure, characterized in that include: a substrate including an active region; a gate structure located on the substrate, overlapping the active area, wherein the gate structure comprises a gate dielectric layer located on the substrate and a gate conductive layer located on the gate dielectric layer, the gate dielectric layer comprises a high dielectric constant layer, and the gate conductive layer comprises a first conductive layer; a dummy gate structure located on the substrate, wherein the dummy gate structure comprises a second conductive layer located on the substrate, the second conductive layer is made of the same material as the first conductive layer, and the active area comprises a first doped region located between the gate structure and the dummy gate structure; a first contact plug located on the first doped region, wherein the first contact plug is electrically connected to the first doped region and the second conductive layer respectively; The first contact plug covers the sidewall of the second conductive layer to be electrically connected to the second conductive layer, or the first contact plug covers the sidewall and a portion of the top surface of the second conductive layer.

9. The semiconductor structure according to claim 8, wherein: The gate conductive layer further includes a third conductive layer, which is disposed between the gate dielectric layer and the first conductive layer. The third conductive layer and the first conductive layer are made of different materials.

10. The semiconductor structure according to claim 8, wherein: The gate dielectric layer further includes an interface layer, and the interface layer is located between the substrate and the high dielectric constant layer.

11. The semiconductor structure according to any one of claims 8 to 10, wherein: Also includes: a first isolation layer, covering at least the sidewalls of the gate dielectric layer and the gate conductive layer; The second isolation layer at least covers the sidewalls of the second conductive layer.

12. The semiconductor structure according to any one of claims 8 to 10, wherein: A shallow trench isolation structure is provided in the substrate, and the shallow trench isolation structure divides the substrate into a plurality of active areas. The second conductive layer covers the active areas and the shallow trench isolation structure.

13. The semiconductor structure according to any one of claims 8 to 10, wherein: It also includes a planarization layer, which fills between the gate structure and the dummy gate structure and covers the gate structure, the dummy gate structure and the surface of the substrate. The first contact plug passes through the planarization layer and is electrically connected to the first doped region.

14. The semiconductor structure according to any one of claims 8 to 10, wherein: The active region further includes a second doped region located on a side of the gate structure away from the dummy gate structure. The semiconductor structure further includes a second contact plug located on the second doped region. The second contact plug is electrically connected to the second doped region.

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