Nitride semiconductor device and method for manufacturing the same

Abstract

The present application relates to a nitride semiconductor device and a method for manufacturing the same. The present application designs a gate groove in the device, prepares the gate metal in the gate groove, then designs a ring-shaped source groove surrounding the gate groove on the device, and prepares the source metal in the source groove. This setting can wrap the gate in the source of the ring structure to reduce the electric field strength in the gate area, thereby reducing the risk of gate breakdown. At the same time, the design of the ring-shaped source groove helps to distribute the electric field more evenly, reduce the area where the electric field is concentrated, and further prevent premature breakdown to improve the device performance and reliability.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a nitride semiconductor device and a method for manufacturing the same. Background Art

[0002] Third-generation wide-bandgap semiconductor materials, represented by GaN (gallium nitride) and SiC (silicon carbide), offer advantages such as high breakdown electric field strength and higher electron saturation velocity. Compared to SiC, GaN offers advantages such as a wider bandgap, higher saturated electron drift velocity, lower dielectric constant, stronger corrosion resistance, and relatively easy preparation of high-quality heterojunctions, making it widely used in power semiconductor devices.

[0003] Gallium nitride Schottky barrier diodes (SBDs) have broad application prospects in mobile communications, semiconductor lighting, and consumer electronics due to their advantages such as high blocking voltage, high switching speed, and low power consumption.

[0004] However, vertically structured GaN devices usually produce uneven electric field and current distribution when integrating SBDs. In addition, since the gate is not effectively protected in the GaN device structure with integrated SBDs, the gate is prematurely broken down due to electric field concentration, thereby reducing the performance and reliability of the power device. Summary of the Invention

[0005] This application provides a nitride semiconductor device and a method for manufacturing the same, which can solve the breakdown problem existing in existing power devices. The technical solution is as follows:

[0006] A nitride semiconductor device comprises a first metal layer, an auxiliary layer, a drift layer, a channel layer, a barrier layer and a second metal layer arranged in sequence along the vertical direction of the device.

[0007] The nitride semiconductor device further includes a first trench and a second trench, wherein the first trench and the second trench both penetrate the barrier layer and the channel layer and extend into the drift layer;

[0008] The first trench is provided with a dielectric layer covering the bottom and sidewalls thereof and a third metal layer filled in the first trench; the second trench is filled with the second metal layer;

[0009] The second groove is arranged around the first groove, and the second groove is annular.

[0010] In one embodiment, a regulation layer is provided between the drift layer and the channel layer;

[0011] The first trench sequentially penetrates the barrier layer, the channel layer, and the regulation layer and then extends into the drift layer.

[0012] In one embodiment, the nitride semiconductor device further includes a third trench, wherein the third trench penetrates the regulating layer and extends into the drift layer;

[0013] The third trench is filled with a first semiconductor layer, and the first semiconductor layer is flush with the upper surface of the regulating layer.

[0014] In one embodiment, the third trench is arranged around the first trench, the projection of the second trench on the regulation layer is entirely located on the first semiconductor layer, and the second trench extends into the first semiconductor layer after passing through the barrier layer and the channel layer.

[0015] In one embodiment, the third groove is annular, and the ring width of the third groove is greater than the ring width of the second groove.

[0016] In one embodiment, the first trench extends into the drift layer to a first depth, and the third trench extends into the drift layer to a second depth, and the second depth is greater than the first depth.

[0017] In one embodiment, the second trench extends into the first semiconductor layer to a third depth, and the third depth is less than the thickness of the control layer.

[0018] In one embodiment, the first trench is further filled with a second semiconductor layer;

[0019] The first dielectric layer, the second semiconductor layer and the third metal layer are sequentially formed in the first trench along the vertical direction of the device.

[0020] In one embodiment, the first semiconductor layer and the second semiconductor layer are made of the same material.

[0021] In one embodiment, a fourth metal layer is further provided on the periphery of the third trench, and the fourth metal layer is located between the barrier layer and the second metal layer;

[0022] The fourth metal layer and the drift layer together form a Schottky diode.

[0023] In one embodiment, the third metal layer and the fourth metal layer are made of the same material.

[0024] A method for manufacturing a nitride semiconductor device comprises the following steps:

[0025] Providing a substrate, and sequentially stacking an auxiliary layer and a drift layer on the substrate;

[0026] preparing a regulating layer on the drift layer;

[0027] Etching the regulating layer to form a third trench, and depositing the first semiconductor layer in the third trench; wherein the third trench is annular;

[0028] Sequentially stacking a channel layer and a barrier layer on the regulating layer;

[0029] Etching the barrier layer to form a first trench, and depositing a dielectric layer on the bottom and sidewalls of the first trench; wherein the first trench sequentially penetrates the barrier layer, the channel layer, and the control layer from top to bottom along the vertical direction of the device, and is embedded in the drift layer;

[0030] preparing a metal layer on the barrier layer; etching the metal layer to simultaneously form a gate layer located in the first trench and a Schottky metal layer located on both sides of the third trench;

[0031] Etching the barrier layer to form a second trench; wherein the second trench sequentially penetrates the barrier layer and the channel layer from top to bottom along the vertical direction of the device and is embedded in the first semiconductor layer;

[0032] Preparing a source layer in the second trench; wherein the source layer fills the second trench and covers the Schottky metal layer and the barrier layer;

[0033] The substrate is peeled off, and a drain metal layer is formed on a side of the auxiliary layer away from the drift layer.

[0034] In one embodiment, the steps of providing a substrate and forming an auxiliary layer on the substrate include:

[0035] A nucleation layer, a first buffer layer, a second buffer layer, a planarization layer, a third buffer layer and a fourth buffer layer are sequentially stacked on the substrate; wherein

[0036] Depositing aluminum nitride with a thickness of 10 nm to 30 nm on the substrate as the nucleation layer;

[0037] Depositing aluminum gallium nitride with a thickness of 0.1 μm to 0.2 μm on the nucleation layer as the first buffer layer;

[0038] Alternately depositing several layers of aluminum nitride and gallium nitride with a thickness of 1 nm to 3 nm on the first buffer layer to form the planar layer;

[0039] Depositing a 150 nm to 300 nm thick low-temperature formed gallium nitride on the flat layer as the third buffer layer;

[0040] Gallium nitride formed at high temperature is deposited on the third buffer layer to a thickness of 500 nm to 1000 nm as the fourth buffer layer.

[0041] In one embodiment, the step of preparing a drift layer on the auxiliary layer includes at least one of the following:

[0042] Depositing undoped gallium nitride with a thickness of 1 μm to 20 μm on the auxiliary layer to form the drift layer;

[0043] Depositing a 1 μm to 20 μm thick doped gallium nitride on the auxiliary layer to form the drift layer; wherein the doping concentration range is 1×10 15 cm -3 ~1×10 16 cm -3 .

[0044] In one embodiment, the specific steps of preparing the control layer on the drift layer include:

[0045] Depositing 50nm to 500nm thick doped gallium nitride on the drift layer to form the control layer; wherein the doping concentration range is 1×10 16 cm -3 ~1×10 17 cm -3 .

[0046] In one embodiment, the specific steps of etching the regulating layer to form a third trench and depositing the first semiconductor layer in the third trench include:

[0047] Etching the control layer until it extends into the drift layer to form the third trench; wherein the total height of the third trench in the vertical direction of the device is 150nm to 500nm, and the photolithographic pattern formed by etching is in a circular ring shape;

[0048] A P-type doped gallium nitride layer with a thickness of 150 nm to 500 nm is deposited in the third trench to form the first semiconductor layer.

[0049] In one embodiment, the specific steps of sequentially stacking a channel layer and a barrier layer on the regulating layer include:

[0050] Depositing undoped gallium nitride with a thickness of 0.3 μm to 1 μm on the regulating layer to form the channel layer;

[0051] Aluminum gallium nitride with a thickness of 20 nm to 30 nm is deposited on the channel layer to form the barrier layer.

[0052] In one embodiment, the specific steps of etching the barrier layer to form a first trench and depositing a dielectric layer on the bottom and sidewalls of the first trench include:

[0053] Etching the barrier layer within the inner ring of the third trench until it extends into the drift layer to form the first trench, wherein the depth of the first trench in the drift layer is less than the depth of the third trench in the drift layer, and the formed photolithographic pattern is in the shape of an elongated strip;

[0054] Aluminum nitride is deposited on the bottom and sidewalls of the first trench to a thickness of 20 nm to 30 nm to form the dielectric layer.

[0055] In one embodiment, the second semiconductor layer is formed in the first trench, and the specific steps include:

[0056] P-type doped gallium nitride is deposited on the dielectric layer to form the second semiconductor layer; wherein the thickness of the second semiconductor is less than the height of the first trench, and the height difference between the upper surface of the second semiconductor layer and the top surface of the first trench ranges from 20nm to 30nm.

[0057] In one embodiment, a metal layer is formed on the barrier layer, and the specific steps of etching the metal layer include:

[0058] Depositing a metal layer with a thickness of 20 nm to 30 nm on the barrier layer; during the deposition process, part of the metal is directly deposited in the first trench;

[0059] The metal layer in the first trench and the metal layer around the third trench are etched away to form a gate layer in the first trench and a Schottky metal layer outside the third trench.

[0060] In one embodiment, 0.5 μm to 1.5 μm is deposited on the barrier layer, the gate layer, and the Schottky metal layer;

[0061] The passivation layer on the Schottky metal layer is etched.

[0062] In one embodiment, the specific step of etching the barrier layer to form the second trench includes:

[0063] Etching a portion of the passivation layer whose projection between the Schottky metal layer and the first trench is located above the third trench, until the portion extends into the first semiconductor layer above the third trench to form a second trench; wherein the photolithographic pattern formed by etching is in a circular ring shape;

[0064] A source layer is prepared in the second trench; wherein the source layer fills the second trench and covers the Schottky metal layer and the passivation layer.

[0065] The technical solution provided by the embodiments of the present application may include the following beneficial effects: by designing a gate trench in the device, preparing the gate metal in the gate trench, and then designing a ring-shaped source trench surrounding the gate trench in the device, and preparing the source metal in the source trench. This setting can wrap the gate in the source of the ring structure to reduce the electric field strength in the gate area, thereby reducing the risk of gate breakdown. At the same time, the design of the ring-shaped source trench helps to distribute the electric field more evenly, reduce the area where the electric field is concentrated, and further prevent premature breakdown to improve the performance and reliability of the device.

[0066] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0068] Figure 1 FIG1 is a schematic structural diagram of a nitride semiconductor device according to an embodiment of the present application at a certain viewing angle.

[0069] Figure 2-Figure 27 FIG. 1 is a structural diagram of a manufacturing process of a nitride semiconductor device according to an embodiment of the present application.

[0070] Description of reference numerals:

[0071] 10. Substrate; 101. First metal layer.

[0072] 20. Auxiliary layer; 201. Nucleation layer; 202. First buffer layer; 203. Planarization layer; 204. Third buffer layer; 205. Fourth buffer layer.

[0073] 30. Drift layer.

[0074] 40. Channel layer.

[0075] 50. Barrier layer.

[0076] 60. Second trench / source groove; 601. Second metal layer / source layer.

[0077] 70. First trench / gate trench; 700. Total metal layer; 701. Dielectric layer; 702. Third metal layer / gate layer; 703. Second semiconductor layer; 704. Fourth metal layer / Schottky metal layer.

[0078] 80. Regulatory layer.

[0079] 90. Third trench; 901. First semiconductor layer.

[0080] 100. Passivation layer.

[0081] a. First depth; b. Second depth; c. Third depth. DETAILED DESCRIPTION

[0082] Compared to first-generation semiconductor materials Si (silicon) and second-generation semiconductor materials GaAs (gallium arsenide), third-generation wide-bandgap semiconductor materials, represented by GaN (gallium nitride) and SiC (silicon carbide), offer advantages such as higher breakdown electric field strength and higher electron saturation velocity. GaN, on the other hand, has advantages over SiC such as a wider bandgap, higher saturated electron drift velocity, lower dielectric constant, stronger corrosion resistance, and relatively easy preparation of high-quality heterojunctions, making it widely used in power semiconductor devices.

[0083] Current GaN power devices can be divided into lateral power devices and vertical power devices according to the conduction direction of the current. Lateral power devices refer to a heterojunction structure formed by epitaxial barrier layers on the channel layer. With the help of the polarization effect of the GaN-based material system, a two-dimensional electron gas (2DEG) is generated at the heterojunction surface as a lateral current path. However, lateral devices have a serious current collapse problem. Vertical power devices, on the other hand, use GaN materials for conduction to form a current that penetrates up and down. This can effectively solve the problems of lateral power devices.

[0084] Gallium nitride Schottky barrier diodes (SBDs) have broad application prospects in mobile communications, semiconductor lighting, and consumer electronics due to their high blocking voltage, high switching speed, and low power consumption. Current GaN Schottky barrier diodes (SBDs) primarily utilize two structural types: vertical SBDs based on bulk GaN material and lateral SBDs based on a heterojunction two-dimensional electron gas (2DEG) formed between the barrier and channel layers.

[0085] Generally, vertical GaN devices are mostly composed of strip-shaped gates and drains. When forming vertical SBDs, the gate strips usually need to be split for preparation. This method not only leaves a large area of ​​the device empty, resulting in uneven electric field and current distribution in the device, but also because the gate is exposed, it causes premature breakdown due to electric field concentration, thereby reducing the performance and reliability of the power device.

[0086] Based on this, the present application provides a nitride semiconductor device that can effectively solve the problems of breakdown and electric field unevenness caused by the structural design of power devices.

[0087] Reference Figure 1 、 Figure 18 as well as Figure 20 The nitride semiconductor provided in this application includes a first metal layer 101, an auxiliary layer 20, a drift layer 30, a channel layer 40, a barrier layer 50, and a second metal layer 601, which are sequentially arranged along the vertical direction of the device. It also includes a first trench 70 and a second trench 60, which both penetrate the barrier layer 50 and the channel layer 40 and extend into the drift layer 30.

[0088] The first trench 70 includes a dielectric layer 701 covering the bottom and sidewalls thereof and a third metal layer 702 filled in the first trench. The second trench is filled with a second metal layer 601. The second trench 60 is arranged around the first trench 70 and is annular.

[0089] It should be noted that, in some embodiments, the first metal layer 101 forms an ohmic contact with the auxiliary layer 20, and the lead-out terminal of the first metal layer 101 serves as a drain. The lead-out terminal of the second metal layer 601 serves as a source. The third metal layer 702 forms an ohmic contact with both the drift region and the barrier layer 50, and the lead-out terminal of the third metal layer 702 serves as a gate.

[0090] Specifically, the first metal layer 101 can be understood as the drain metal. The first trench 70 can also be understood as the gate trench, and the corresponding third metal layer 702 filled in the first trench 70 can be understood as the gate metal. The second trench 60 can be understood as the source trench, and the corresponding second metal layer 601 filled in the second trench 60 can be understood as the source metal.

[0091] For ease of understanding and readability, the first trench 70 is subsequently expressed as gate trench 70. The third metal layer 702 is expressed as gate layer 702. The second trench 60 is expressed as source trench 60, and the second metal layer 601 is expressed as source layer 601.

[0092] In this application, the annular source groove 60 is designed around the gate groove 70, and then the gate layer 702 is filled in the gate groove 70 accordingly to control the flow of current in the device, and the source layer 601 is filled in the source groove 60 to control the current flowing into or out of the device.

[0093] This structure not only wraps the gate layer 702 to reduce the electric field strength in the gate region, thereby lowering the risk of gate breakdown, but also the annular source trench 60 ensures that the filled source layer 601 has the same shape, providing a larger contact area between the source layer 601 and the drift layer 30, thereby helping to reduce contact resistance. Finally, the annular source layer 601 helps to more evenly distribute the electric field, reducing areas of electric field concentration and further preventing premature device breakdown.

[0094] In some embodiments, the drift layer 30 and the channel layer 40 are both made of gallium nitride (GaN), the barrier layer 50 is made of aluminum gallium nitride (AlGaN), and the dielectric layer 701 is made of aluminum nitride (AlN).

[0095] Since the gate trench 70 sequentially penetrates the barrier layer 50 and the channel in the vertical direction of the device and then extends to the drift layer 30, the bottom of the gate layer 702 contacts the drift layer 30, and the sidewalls of the gate layer 702 contact the channel layer 40. Therefore, when the dielectric layer 701 is formed in the bottom and sidewalls, the dielectric layer 701 forms AlN / GaN heterojunctions with the drift layer 30 and the channel layer 40, respectively.

[0096] The heterostructure formed by AlN / GaN will produce a piezoelectric effect due to the lattice constant mismatch. This effect, combined with the spontaneous polarization effect of AlN, can generate a strong built-in electric field. The built-in electric field can attract electrons in GaN to the vicinity of the AlN / GaN interface, forming a high-density 2DEG, thereby reducing the channel resistance and improving the current driving capability, thereby improving the conductivity and switching speed of the device.

[0097] In some embodiments, continue with reference to Figure 18 The gate groove 70 is also filled with a second semiconductor layer 703. That is, after the dielectric layer 701 is prepared on the bottom and sidewall of the gate groove 70, the second semiconductor layer 703 and the gate layer 702 are filled in sequence.

[0098] Specifically, the material of the second semiconductor layer 703 is gallium nitride (p-GaN) doped with p-type impurities. This configuration still relies on the gate trench 70 penetrating the barrier layer 50 and the channel layer 40 and extending deep into the drift layer 30. When the gate trench 70 is filled with p-GaN (the second semiconductor layer), the band structure between the p-GaN and AlGaN (the barrier layer 50) changes, resulting in an increased potential barrier, which in turn increases the barrier height of the AlGaN. This increased barrier height can raise the potential energy at the channel beneath the gate layer 702 to above the Fermi level, thereby modulating the carrier concentration in the channel to improve the conductivity of the channel.

[0099] In some embodiments, continue with reference to Figure 1 A control layer 80 is provided between the drift layer 30 and the channel layer 40 .

[0100] Specifically, the material of the control layer 80 is doped gallium nitride. The specific doping concentration depends on the doping distribution requirements during the device manufacturing process, which will not be elaborated here.

[0101] Forming a control layer 80 on the drift layer 30 effectively regulates the electric field distribution within the drift layer 30, optimizing the breakdown voltage and current handling capability of the device. Complex doping techniques can also create a space charge region within the drift layer 30, smoothing the electric field distribution and reducing the local electric field strength, thereby increasing the device breakdown voltage.

[0102] In one embodiment, referring to Figure 1 The gate trench 70 sequentially penetrates the barrier layer 50, the channel layer 40, and the control layer 80, and then extends into the drift layer 30. The dielectric layer 701 on the inner sidewall of the gate trench 70 contacts the control layer 80, the channel layer 40, and the barrier layer 50 respectively.

[0103] In some embodiments, reference Figure 9 and Figure 11 The nitride semiconductor device further includes a third trench 90 that penetrates the control layer 80 and extends into the drift layer 30. The third trench 90 is filled with a first semiconductor layer 901 that is flush with the upper surface of the control layer 80.

[0104] Specifically, the material of the first semiconductor layer 901 is consistent with the material of the second semiconductor layer 703 , and is gallium nitride doped with p-type impurities (p-GaN).

[0105] Adding the first semiconductor layer 901 between the source and the drain can block charge penetration under high voltage conditions, thereby increasing the breakdown voltage of the device.

[0106] Furthermore, the first semiconductor layer 901 and the regulating layer 80 below the channel layer 40 work together to effectively increase the device saturation output current and reduce turn-off leakage, thereby achieving better reliability and lower power consumption.

[0107] In some embodiments, reference Figure 1 、 14 The third trench 90 is arranged around the gate trench 70 , and the projection of the source trench 60 on the control layer 80 is entirely located on the first semiconductor layer 901 . The source trench 60 penetrates the barrier layer 50 and the channel layer 40 and extends into the first semiconductor layer 901 .

[0108] It can be understood that the source groove 60 formed on the barrier layer 50 penetrates the barrier layer 50 and the channel layer 40 and its bottom is located in the third groove 90, and the lower surface of the source layer 601 filled in the source groove 60 is in contact with the first semiconductor layer 901.

[0109] In one embodiment, the source layer 601 extends into the first semiconductor layer 901 to a depth less than the thickness of the control layer 80 .

[0110] In some embodiments, the third trench 90 is annular, and the width of the third trench 90 is greater than the width of the source trench 60. This configuration can ensure that the source layer 601 can be in full contact with the first semiconductor layer 901.

[0111] The specific values ​​of the ring widths of the third trench 90 and the source trench 60 are determined based on the actual needs of device production and are not limited here. The ratio between the ring widths of the third trench 90 and the source trench 60 is also determined based on actual needs. As long as the simple size relationship between the two is met, it is within the scope of protection of this application.

[0112] In some embodiments, reference Figure 1 The gate trench 70 extends into the drift layer 30 to a first depth a, and the third trench 90 extends into the drift layer 30 to a second depth b. The second depth b is greater than the first depth a.

[0113] It can also be understood that the depth of the second semiconductor layer 703 in the drift layer 30 is less than the depth of the first semiconductor layer 901 in the drift layer 30 , which has the following beneficial effects:

[0114] First, the shallow depth of the second semiconductor layer 703 embedded in the drift layer 30 allows for more direct and effective control of the channel, helping to increase the switching speed of the device and reduce the on-resistance. It also reduces charge carrier injection between the gate and the drift layer 30, reducing the power consumption of the device in the on state.

[0115] The deeper the first semiconductor layer 901 is embedded in the drift layer 30, the better it blocks charge carrier penetration between the source and drain, thereby improving the device's withstand voltage. It also helps create a more uniform electric field distribution in the drift layer 30, reducing the risk of electric field concentration and breakdown. Furthermore, it can withstand higher reverse bias voltages without breakdown, thereby increasing the device's breakdown voltage.

[0116] In some embodiments, continue with reference to Figure 1 A fourth metal layer 704 is further provided around the third trench 90 and is located between the barrier layer 50 and the second metal layer 601. The fourth metal layer 704 and the drift layer 30 together form a Schottky diode.

[0117] A fourth metal layer 704 is formed on the outer periphery of the third trench 90 and on the barrier layer 50. The fourth metal layer 704 may also be understood and replaced by a Schottky metal layer 704.

[0118] First, setting the Schottky diode on the periphery of the third trench 90 means that the Schottky diode is also located on the periphery of the source groove 60. Under the joint action of the annular source layer 601 and the Schottky diode located at the edge of the source groove 60, the gate can be completely wrapped, further avoiding premature breakdown of the gate area, thereby improving the stability of the device.

[0119] Secondly, the Schottky diode provides a current path when it is reverse biased, which can prevent the breakdown caused by reverse voltage and protect the device from damage. At the same time, the Schottky diode has a high voltage resistance characteristic and can operate under high reverse voltage without avalanche breakdown.

[0120] The present application also provides a method for manufacturing a nitride semiconductor device, comprising the following steps. It should be noted that the photolithography or etching technology involved in the following steps includes electron beam lithography (EBL) and deep ultraviolet lithography (DUV) technology. And the etching technology is selected according to actual needs in different steps. At the same time, the specific steps of photolithography include pretreatment, coating, pre-baking, exposure and development. The operations are all conventional operations and will not be described in detail here.

[0121] Secondly, the deposition technologies involved in the following steps include metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LP-CVD), and plasma enhanced chemical vapor deposition (PECVD). Different steps can be selected based on actual needs, so we will not elaborate on them here.

[0122] Step S10 : providing a substrate 10 , and sequentially stacking an auxiliary layer 20 and a drift layer 30 on the substrate 10 .

[0123] In one embodiment, the material of the substrate 10 is single crystal diamond.

[0124] Furthermore, the specific steps of preparing the auxiliary layer 20 on the substrate 10 include:

[0125] S101, reference Figure 2 , aluminum nitride with a thickness of 10 nm to 30 nm is deposited on the substrate 10 as a nucleation layer 201 .

[0126] Nucleation layer 201 can promote crystal growth, reduce lattice defects, and improve crystal quality. Secondly, the material selection for nucleation layer 201 can influence the device's electrical and optical properties. In practical applications, device performance can be optimized by adjusting the properties of nucleation layer 201. Finally, nucleation layer 201 can alleviate the lattice mismatch between single-crystal diamond and the gallium nitride bulk, reducing lattice strain and minimizing the generation of lattice defects.

[0127] In some embodiments, the material of the nucleation layer 201 may also be gallium nitride (GaN), indium nitride (InN), etc.

[0128] S102. Reference Figure 3 Aluminum gallium nitride (AlGaN) with a thickness of 0.1 μm to 0.2 μm is deposited on the nucleation layer 201 as the first buffer layer 202 .

[0129] The first buffer layer 202 can alleviate the lattice mismatch between the substrate 10 and GaN, reduce lattice strain, thereby reducing lattice defect density and improving device performance and reliability.

[0130] Furthermore, the first buffer layer 202 includes a plurality of sub-buffer layers, and in a direction away from the substrate 10 , the AL concentration doped in each sub-buffer layer gradually increases in a gradient state.

[0131] In one embodiment, the first buffer layer 202 includes 10 sub-buffer layers, which are stacked in sequence in a direction away from the substrate 10, and the doping AL concentrations are 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, and 100%, respectively.

[0132] S103. Reference Figure 4 , several layers of AlN and GaN with a thickness of 1 nm to 3 nm are alternately deposited on the first buffer layer 202 to form a planarization layer 203 .

[0133] In the present application, the flat layer 203 reduces the dislocation density through a multi-level alternating stress field, making the subsequent epitaxial layer more flat and uniform.

[0134] In one embodiment, a layer of AlN and a layer of GaN form a pair. The thickness of each AlN / GaN pair is preferably 2 nm. The total thickness of the planar layer 203 is 40 nm.

[0135] S104. Reference Figure 5 , a 150 nm to 300 nm thick low-temperature formed GaN is deposited on the flat layer 203 as the third buffer layer 204 .

[0136] Low-temperature GaN can reduce stress caused by lattice mismatch or differences in thermal expansion coefficients. It can also improve adhesion between subsequently grown GaN and substrate 10, reducing defects. Finally, low-temperature GaN can serve as a template for subsequent growth, helping to improve growth rate and uniformity.

[0137] In one embodiment, the thickness of the third buffer layer 204 is preferably 150 nm.

[0138] S105, reference Figure 6, a 500 nm to 1000 nm thick high-temperature formed GaN is deposited on the third buffer layer 204 as the fourth buffer layer 205. Preferably, the thickness of the fourth buffer layer 205 is 1000 nm.

[0139] The high-temperature GaN buffer layer can provide a high-quality foundation, enabling the subsequent drift layer 30 to have better crystal quality and lower defect density.

[0140] S106, reference Figure 7 , a drift layer 30 is formed on the auxiliary layer 20 .

[0141] In one embodiment, undoped GaN with a thickness of 1 μm to 20 μm is deposited on the fourth buffer layer 205 to form the drift layer 30 .

[0142] In one embodiment, a doped GaN layer with a thickness of 1 μm to 20 μm is deposited on the fourth buffer layer 205 to form the drift layer 30. The doping concentration range is 1×10 15 cm -3 ~1×10 16 cm -3 This means that every cubic centimeter of semiconductor material contains 10 to the power of 15 to 10 to the power of 16 doping atoms.

[0143] The drift layer 30 provides a path for conducting the majority of the current and withstands the voltages applied during device operation. In practical applications, the thickness and doping concentration of the drift layer 30 directly affect the device's breakdown voltage and on-resistance. The thickness and doping concentration of the drift layer 30 can be tailored to meet specific requirements.

[0144] Step S200, refer to Figure 8 , a control layer 80 is prepared on the drift layer 30 .

[0145] Specifically, a 50 nm to 500 nm thick doped gallium nitride is deposited on the drift layer 30 to form the control layer 80. The doping concentration range is 1×10 16 cm -3 ~1×10 17 cm -3 This means that every cubic centimeter of semiconductor material contains 10 to the power of 16 to 10 to the power of 17 doping atoms.

[0146] The control layer 80 is used to adjust the electric field distribution in the drift layer 30 to optimize the breakdown voltage and the current carrying capacity of the device. Through complex doping engineering, a space charge region can be created in the drift layer 30 to help smooth the electric field distribution and reduce the local electric field strength, thereby increasing the breakdown voltage of the device.

[0147] Step S300, refer to Figures 9-11, etching the control layer 80 to form a third trench 90, and depositing a first semiconductor layer 901 in the third trench 90. The third trench 90 is annular.

[0148] Reference Figure 9 The control layer 80 is etched until it extends into the drift layer 30 to form a third trench 90. Preferably, the total height of the third trench 90 in the vertical direction of the device is 150nm to 500nm. It can also be understood as the depth of the third trench 90.

[0149] Reference Figure 10 The photolithographic pattern formed by etching is in the shape of a circular ring.

[0150] In one embodiment, P-type doped gallium nitride (P-GaN) is deposited in the third trench 90 to form a first semiconductor layer 901 in a circular shape.

[0151] The first semiconductor layer 901 acts as a current block, that is, as described above, the first semiconductor layer 901 can block the charge penetration between the source and the drain to prevent the device from accidentally conducting electricity under high voltage conditions, thereby improving the voltage resistance and reliability of the device.

[0152] Step S400, refer to Figure 12 and Figure 13 , a channel layer 40 and a barrier layer 50 are sequentially stacked on the regulating layer 80 .

[0153] In one embodiment, undoped GaN with a thickness of 0.3 μm to 1 μm is deposited on the regulating layer 80 to form the channel layer 40. The channel layer 40 provides current flow from the gate to the source.

[0154] In one embodiment, a barrier layer 50 is formed by depositing 20 nm to 30 nm thick AlGaN on the channel layer 40. The AlGaN / GaN heterojunction formed by the channel layer 40 and the barrier layer 50 can form a high-density 2DEG, thereby reducing channel resistance and improving current drive capability, thereby improving the conductivity and switching speed of the device.

[0155] In step S500, the barrier layer 50 is etched to form a first trench 70. As can be seen from the above description, the first trench in this step is the gate trench 70, which is also used in this embodiment.

[0156] Specifically, refer to Figure 14 The projection of the region where the gate groove 70 is formed on the control layer 80 is located in the inner ring region of the third trench 90 mentioned above. The barrier layer 50, the channel layer 40, the control layer 80 and even the drift layer 30 are etched.

[0157] In one embodiment, the photolithographic pattern on the gate groove 70 is designed to be long strip. Further, the gate groove 70 is rectangular. Preferably, the gate groove 70 is a combination of a rectangular and a circular structure, and the rectangular and circular structures have an overlapping area. Preferably, referring to Figure 15 The gate groove 70 is a combination of a rectangular and a circular structure, and the center of the circular structure coincides with the midpoint of the rectangular structure. Furthermore, the diameter of the circular structure is greater than the width of the rectangle.

[0158] In one embodiment, the distances from both sides of the gate trench 70 to the third trench 90 are equal.

[0159] In some embodiments, continue with reference to Figure 14 , the depth of the gate groove 70 in the drift layer 30 is less than the depth of the third trench 90 in the drift layer 30 .

[0160] S501 , depositing a dielectric layer 701 on the bottom and sidewalls of the gate trench 70 .

[0161] Reference Figure 16 and Figure 17 A 20 nm to 30 nm thick AlN layer is deposited on the bottom and sidewalls of the gate trench 70 to form a dielectric layer 701. The relevant contents and effects of the dielectric layer 701 are consistent with the above description of the dielectric layer 701 and will not be elaborated here.

[0162] S502 , preparing a second semiconductor layer 703 in the gate trench 70 .

[0163] Specifically, refer to Figure 18 , P-GaN is deposited on the dielectric layer 701 to form a second semiconductor layer 703. The relevant contents and effects of the second semiconductor layer 703 are consistent with the above description of the dielectric layer 701, and will not be repeated here.

[0164] In some embodiments, the thickness of the second semiconductor layer 703 is smaller than the height of the gate trench 70 , and the height difference between the upper surface of the second semiconductor layer 703 and the top surface of the first trench is in a range of 20 nm to 30 nm.

[0165] When preparing the gate layer 702, this arrangement can ensure that the gate metal above the gate trench 70 is completely deposited in the gate trench 70. Preferably, the upper surface of the gate layer 702 is flush with the top of the gate trench 70 and the upper surface of the barrier layer 50.

[0166] Step S600, refer to Figure 19 , a total metal layer 700 is prepared on the barrier layer 50 .

[0167] Specifically, a metal with a thickness of 20 nm to 30 nm is deposited on the barrier layer 50 to form a total metal layer 700. The metal layer is made of at least one of Ni (Nickel), Pt (Platinum), Mo (Molybdenum), Cr (Chromium), Al (Aluminum), Au (Gold), and the like.

[0168] During the deposition process, continue to refer to Figure 19 , the metal located above the gate trench 70 is directly deposited in the gate trench 70 . Another portion of the metal is deposited on the barrier layer 50 .

[0169] S601, reference Figure 20 The metal layer in the gate trench 70 and the total metal layer 700 around the third trench 90 are etched away to form a gate layer 702 located in the gate trench 70 and a Schottky metal layer 704 located outside the third trench 90 .

[0170] During this process, continue to refer to Figure 20 The metal in the gate trench 70 is retained to form a gate layer 702. The total metal layer 700 of the outer ring of the projection of the third trench 90 above the barrier layer 50 is retained to form a Schottky metal layer 704. The Schottky metal layer 704, the barrier layer 50, the drift layer 30, etc. constitute a Schottky barrier diode structure.

[0171] S602, depositing a passivation layer 100 on the device surface. Figure 21 A passivation layer 100 with a thickness of 0.5 μm to 1.5 μm is deposited on the upper surface of the barrier layer 50 , the gate layer 702 , the Schottky metal layer 704 and the dielectric layer 701 .

[0172] S603, reference Figure 22 , the passivation layer 100 on the Schottky metal layer 704 is etched, as well as the portion of the passivation layer 100 between the Schottky metal layer 704 and the gate layer 702, and located on the barrier layer 50 in the projection of the third trench 90 on the barrier layer 50. It can also be understood that the passivation layer 100 above the gate layer 702 is retained without being etched.

[0173] Reference Figure 22 and Figure 23 The region on the barrier layer 50 where the passivation layer 100 is not provided is the region of the source trench 60. The rounded region is in a circular ring shape.

[0174] In step S700, the barrier layer 50 is etched to form a second trench 60. As described above, the second trench 60 in this step is the source trench 60, which is also replaced by the source trench 60 in this embodiment. Therefore, this step can be understood as etching in the source trench 60 region to form the source trench 60.

[0175] Reference Figure 24 and Figure 25 The source trench 60 passes through the barrier layer 50 and the channel layer 40 in sequence from top to bottom along the vertical direction of the device and is embedded in the first semiconductor layer 901. The source trench 60 is also arranged in a circular ring around the gate trench 70.

[0176] In some embodiments, the depth of the source trench 60 embedded in the first semiconductor layer 901 is less than the thickness of the control layer 80 .

[0177] In some embodiments, the ring width of the third trench 90 is greater than the ring width of the source trench 60 .

[0178] Step S800 : preparing a source layer 601 in the source trench 60 .

[0179] The source metal is made of one of Pt (Platinum), Mo (Molybdenum), silver (Ag), aluminum (Al), and copper (Cu).

[0180] In some embodiments, reference Figure 26 The source layer 601 fills the source trench 60 and covers the Schottky metal layer 704 and the barrier layer 50 .

[0181] Step S900, refer to Figure 27 , the substrate 10 is peeled off, and a drain layer 101 is formed on a side of the auxiliary layer 20 away from the drift layer 30 .

[0182] Specifically, the substrate 10 is peeled off using a laser lift-off technique, CMP (chemical mechanical polishing) or a shearing technique.

[0183] The drain layer 101 is made of one of Pt (Platinum), Mo (Molybdenum), silver (Ag), aluminum (Al), and copper (Cu).

[0184] The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, "plurality" or "several" means two or more. Unless otherwise indicated, terms such as "top" and / or "bottom" are used for ease of description only and are not limited to a single position or spatial orientation.

Claims

1. A nitride semiconductor device comprising a first metal layer, an auxiliary layer, a drift layer, a control layer, a channel layer, a barrier layer, and a second metal layer arranged in sequence along the vertical direction of the device, characterized in that: The nitride semiconductor device further includes a first trench and a second trench, wherein the first trench and the second trench both penetrate the barrier layer, the channel layer, and the regulating layer and extend into the drift layer; the regulating layer can effectively regulate the electric field distribution in the drift layer; The nitride semiconductor device further includes a third trench, the third trench extending through the control layer and into the drift layer, the third trench being filled with a first semiconductor layer flush with an upper surface of the control layer, and the first semiconductor layer being made of P-type doped gallium nitride; A dielectric layer covering the bottom and sidewalls of the first trench and a third metal layer filling the first trench are provided in the first trench; The second groove is filled with the second metal layer; The second groove is arranged around the first groove, and the second groove is annular.

2. The nitride semiconductor device according to claim 1, wherein The third groove is arranged around the first groove, The projection of the second trench on the regulating layer is entirely located on the first semiconductor layer, and the second trench penetrates the barrier layer and the channel layer and then extends into the first semiconductor layer.

3. The nitride semiconductor device according to claim 2, wherein: The third groove is annular, and the ring width of the third groove is greater than the ring width of the second groove.

4. The nitride semiconductor device according to claim 2, wherein: The first trench extends into the drift layer to a first depth, and the third trench extends into the drift layer to a second depth, where the second depth is greater than the first depth.

5. The nitride semiconductor device according to claim 4, wherein: The second trench extends into the first semiconductor layer to a third depth, and the third depth is less than the thickness of the regulating layer.

6. The nitride semiconductor device according to claim 1, wherein The first trench is further filled with a second semiconductor layer; The dielectric layer, the second semiconductor layer and the third metal layer are sequentially formed in the first trench along the vertical direction of the device.

7. The nitride semiconductor device according to claim 6, wherein: The first semiconductor layer and the second semiconductor layer are made of the same material.

8. The nitride semiconductor device according to any one of claims 1 to 7, characterized in that: A fourth metal layer is further provided on the periphery of the third trench, and the fourth metal layer is located between the barrier layer and the second metal layer; The fourth metal layer and the drift layer together form a Schottky diode.

9. The nitride semiconductor device according to claim 8, wherein The third metal layer and the fourth metal layer are made of the same material.

10. A method for manufacturing a nitride semiconductor device, characterized in that: The following steps are involved: Providing a substrate, and sequentially stacking an auxiliary layer and a drift layer on the substrate; preparing a regulating layer on the drift layer, wherein the regulating layer can effectively regulate the electric field distribution in the drift layer; Etching the control layer to form a third trench, and depositing a first semiconductor layer in the third trench; wherein the third trench is annular, and the first semiconductor layer is flush with the upper surface of the control layer, and the first semiconductor layer is selected to be P-type doped gallium nitride; Sequentially stacking a channel layer and a barrier layer on the regulating layer; Etching the barrier layer to form a first trench, and depositing a dielectric layer on the bottom and sidewalls of the first trench; wherein the first trench sequentially penetrates the barrier layer, the channel layer, and the control layer from top to bottom along the vertical direction of the device, and is embedded in the drift layer; preparing a metal layer on the barrier layer; Etching the metal layer to simultaneously form a gate layer located in the first trench and a Schottky metal layer located on both sides of the third trench; Etching the barrier layer to form a second trench; wherein the second trench sequentially penetrates the barrier layer and the channel layer from top to bottom along the vertical direction of the device and is embedded in the first semiconductor layer; Preparing a source layer in the second trench; wherein the source layer fills the second trench and covers the Schottky metal and the barrier layer; The substrate is peeled off, and a drain metal layer is formed on a side of the auxiliary layer away from the drift layer.

11. The method for manufacturing a nitride semiconductor device according to claim 10, wherein: The steps of providing a substrate and forming an auxiliary layer on the substrate include: A nucleation layer, a first buffer layer, a second buffer layer, a planarization layer, a third buffer layer and a fourth buffer layer are sequentially stacked on the substrate; wherein Depositing aluminum nitride with a thickness of 10 nm to 30 nm on the substrate as the nucleation layer; Depositing aluminum gallium nitride with a thickness of 0.1 μm to 0.2 μm on the nucleation layer as the first buffer layer; Alternately depositing several layers of aluminum nitride and gallium nitride with a thickness of 1 nm to 3 nm on the first buffer layer to form the planar layer; Depositing a 150 nm to 300 nm thick low-temperature formed gallium nitride on the flat layer as the third buffer layer; Gallium nitride formed at high temperature is deposited on the third buffer layer to a thickness of 500 nm to 1000 nm as the fourth buffer layer.

12. The method for manufacturing a nitride semiconductor device according to claim 11, wherein: The step of preparing a drift layer on the auxiliary layer includes at least one of the following: Depositing undoped gallium nitride with a thickness of 1 μm to 20 μm on the auxiliary layer to form the drift layer; Depositing 1 μm to 20 μm thick doped gallium nitride on the auxiliary layer to form the drift layer; wherein the doping concentration range is ~ .

13. The method for manufacturing a nitride semiconductor device according to claim 12, wherein: The specific steps of preparing the control layer on the drift layer include: Depositing 50nm~500nm thick doped gallium nitride on the drift layer to form the control layer; wherein the doping concentration range is ~ .

14. The method for manufacturing a nitride semiconductor device according to claim 13, wherein: The specific steps of etching the regulating layer to form a third trench and depositing the first semiconductor layer in the third trench include: Etching the control layer until it extends into the drift layer to form the third trench; wherein the total height of the third trench in the vertical direction of the device is 150 nm to 500 nm, and the photolithographic pattern formed by etching is in a circular ring shape; P-type doped gallium nitride is deposited in the third trench with a thickness of 150 nm to 500 nm to form the first semiconductor layer.

15. The method for manufacturing a nitride semiconductor device according to claim 14, wherein: The specific steps of sequentially stacking a channel layer and a barrier layer on the regulating layer include: Depositing undoped gallium nitride with a thickness of 0.3 μm to 1 μm on the regulating layer to form the channel layer; Aluminum gallium nitride with a thickness of 20 nm to 30 nm is deposited on the channel layer to form the barrier layer.

16. The method for manufacturing a nitride semiconductor device according to claim 15, wherein: The specific steps of etching the barrier layer to form a first trench and depositing a dielectric layer on the bottom and sidewalls of the first trench include: Etching the barrier layer within the inner ring of the third trench until it extends into the drift layer to form the first trench, wherein the depth of the first trench in the drift layer is less than the depth of the third trench in the drift layer, and the formed photolithographic pattern is in the shape of an elongated strip; Aluminum nitride is deposited on the bottom and sidewalls of the first trench to a thickness of 20 nm to 30 nm to form the dielectric layer.

17. The method for manufacturing a nitride semiconductor device according to claim 16, wherein: The second semiconductor layer is prepared in the first trench, and the specific steps include: P-type doped gallium nitride is deposited on the dielectric layer to form the second semiconductor layer; wherein the thickness of the second semiconductor is less than the height of the first trench, and the height difference between the upper surface of the second semiconductor layer and the top surface of the first trench ranges from 20nm to 30nm.

18. The method for manufacturing a nitride semiconductor device according to claim 17, wherein: The specific steps of preparing a metal layer on the barrier layer and etching the metal layer include: Depositing a metal layer with a thickness of 20 nm to 30 nm on the barrier layer; during the deposition process, part of the metal is directly deposited in the first trench; The metal layer in the first trench and the metal layer around the third trench are etched away to form a gate layer in the first trench and a Schottky metal layer outside the third trench.

19. The method for manufacturing a nitride semiconductor device according to claim 18, wherein: Depositing a passivation layer with a thickness of 0.5 μm to 1.5 μm on the barrier layer, the gate layer, and the Schottky metal layer; The passivation layer on the Schottky metal layer is etched.

20. The method for manufacturing a nitride semiconductor device according to claim 19, wherein: The specific steps of etching the barrier layer to form the second trench include: Etching a portion of the passivation layer whose projection between the Schottky metal layer and the first trench is located above the third trench, until the portion extends into the first semiconductor layer above the third trench to form a second trench; wherein the photolithographic pattern formed by etching is in a circular ring shape; A source layer is prepared in the second trench; wherein the source layer fills the second trench and covers the Schottky metal layer and the passivation layer.

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