Silicon carbide-based floating back barrier gate power device and preparation method thereof

Abstract

The present invention relates to the field of semiconductor devices and discloses a silicon carbide-based floating back-barrier gate power device and a preparation method thereof. The device comprises a back drain metal layer, an n+-type silicon carbide substrate, and an n-type drift layer, which are stacked sequentially from bottom to top; a p-type base region is provided on both sides of the top of the n-type drift layer, a p+-type floating back barrier is provided between the two p-type base regions, and a p+-type source region and an n+-type source region are enclosed in the p-type base region; a first source metal layer, an oxide layer, and a second source metal layer are provided sequentially from left to right above the n-type drift layer, a polysilicon gate is enclosed in the oxide layer, and a gate oxide layer adjacent to the polysilicon gate is provided below the oxide layer. The p+-type floating back barrier is located below the gate oxide layer and forms a floating back-barrier gate structure with the gate oxide layer. The present invention can prevent a large number of electrons from entering the gate oxide layer and causing degradation of the gate oxide layer through the floating back barrier, thereby improving the reliability of the power device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a silicon carbide-based floating back barrier gate power device and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC), a representative of third-generation semiconductors, boasts a wide bandgap, high breakdown voltage, high thermal conductivity, and a high electron saturation rate. Consequently, power electronic devices fabricated with SiC exhibit higher withstand voltage, current stability, and operating frequency. They can operate in high-frequency and high-temperature environments, offering high reliability and suitability for demanding operating environments. Consequently, SiC, as a third-generation power electronic device, has become a key development direction in power electronics technology, with significant application prospects in both military and civilian fields.

[0003] Metal oxide semiconductor field effect transistors (MOSFETs), as voltage-controlled devices, offer advantages such as fast switching speed, excellent high-frequency performance, low noise, and low drive power, making them a commonly used power switching device. Compared to comparable silicon-based MOSFETs, silicon carbide-based MOSFETs offer higher voltage resistance and higher operating temperatures due to their material properties. Without requiring complex structural design, they can achieve lower specific on-resistance than silicon-based materials at the same voltage, making them the most suitable power switching devices for operation under high-temperature and high-voltage conditions. However, reliability issues with silicon carbide-based MOSFETs have hindered their commercial development and widespread application.

[0004] However, reliability issues in silicon carbide-based MOSFET devices, particularly the gate oxide layer, including the gate oxide layer's TDDB (Time Dependent Dielectric Breakdown) and BTI (Bias Temperature Instability) effects, have restricted the device's further application and development. Because silicon carbide contains numerous interface defects in the Si / SiO2 region, electrons in the SiC easily penetrate the potential barrier and enter the gate oxide under high voltage stress, causing severe degradation of the gate oxide layer and impacting the performance of power devices. Summary of the Invention

[0005] The present invention provides a silicon carbide-based floating back-barrier gate power device and a preparation method thereof, which can prevent a large number of electrons from entering the gate oxide layer and causing degradation of the gate oxide layer by depleting the floating back barrier under a large reverse voltage, thereby improving the reliability of the power device.

[0006] To solve the above technical problems, the present invention adopts a technical solution: providing a silicon carbide-based floating back barrier gate power device, comprising a back drain metal layer, an n+ type silicon carbide substrate, and an n-type drift layer stacked in sequence from bottom to top; p-type base regions are respectively provided on both sides of the top of the n-type drift layer, a p+ type floating back barrier is provided between the two p-type base regions, the p+ type floating back barrier is spaced apart from the p-type base region, a p+ type source region and an n+ type source region are wrapped in the p-type base region, the p+ type source region and the n+ type source region are arranged side by side and contact each other on the side, The p+ type source region is arranged close to the side of the n-type drift layer; a first source metal layer, an oxide layer and a second source metal layer are arranged in sequence from left to right above the n-type drift layer, a polysilicon gate is wrapped in the oxide layer, and a gate oxide layer adjacent to the polysilicon gate is provided below the oxide layer. The p+ type floating back barrier is located below the gate oxide layer and forms a floating back barrier gate structure with the gate oxide layer; a top metal layer is provided above the first source metal layer, the oxide layer and the second source metal layer, and a passivation layer is provided above the top metal layer.

[0007] According to one embodiment of the present invention, the depth of the p+ type floating back barrier is 3.0 μm, and the doping concentration is 1e18 cm -3 ~1e19 cm -3 .

[0008] According to one embodiment of the present invention, the depth of the p-type base region is 1.5 μm, and the doping concentration is 1e17 cm -3 ~1e18 cm -3 The depth of the n+ type source region is 0.2 μm, and the doping concentration is greater than 1e19 cm -3 The depth of the p+ type source region is 3.0 μm and the doping concentration is 1e18 cm -3 ~1e19 cm -3 .

[0009] According to one embodiment of the present invention, the thickness of the gate oxide layer is 500 Å; the thickness of the polysilicon gate is 4000 Å.

[0010] According to an embodiment of the present invention, the thickness of the oxide layer is 1.0 μm.

[0011] According to one embodiment of the present invention, the passivation layer includes a plasma-enhanced tetraethyl orthosilicate layer with a thickness of 6000 Å, a plasma-enhanced silicon nitride layer with a thickness of 300 Å, and a polyimide film layer with a thickness of 7 μm.

[0012] According to one embodiment of the present invention, the thickness of the first source metal layer and the second source metal layer are both 1000 Å.

[0013] According to one embodiment of the present invention, the thickness of the top metal layer is 4 μm.

[0014] According to one embodiment of the present invention, the back drain metal layer includes a metal titanium layer with a thickness of 1000 Å, a metal nickel layer with a thickness of 2000 Å, and a metal silver layer with a thickness of 10 kA.

[0015] In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a method for preparing the silicon carbide-based floating back barrier gate power device, comprising:

[0016] Step S1: epitaxially growing an n-type drift layer on an n+ silicon carbide substrate;

[0017] Step S2: forming a p-type base region on the n-type drift layer by sequentially performing a first masking layer growth process, a high-temperature oxidation process, a photolithography process, an etching process, and an ion implantation process;

[0018] Step S3: growing a layer of low-pressure tetraethoxy silicate glass using the first masking layer, and forming an n+ type source region through a plasma dry isotropic etching process, a self-aligned process, and an ion implantation process;

[0019] Step S4: removing the first masking layer by wet method, re-depositing the second masking layer of each layer, and forming a p+ type source region and a p+ type floating back barrier by photolithography, etching and ion implantation;

[0020] Step S5: growing a gate oxide layer through a carbon film growth and high temperature activation process and a nitrogen annealing process;

[0021] Step S6: depositing saturated doped polysilicon on the gate oxide layer, and forming a polysilicon gate through photolithography and etching processes;

[0022] Step S7: depositing a layer of borophosphosilicate glass on the polysilicon gate and the gate oxide layer, and forming an oxide layer by photolithography and etching, wherein the oxide layer wraps the polysilicon gate;

[0023] Step S8: forming a first source metal layer and a second source metal layer on both sides of the oxide layer by a metal deposition process and a rapid annealing process;

[0024] Step S9: forming a top metal layer through a sputtering process and an etching process, and depositing a passivation layer on the top metal layer;

[0025] Step S10: forming a back drain metal layer on the back of the n+ type silicon carbide substrate by a metal deposition process and a laser annealing process, thereby completing the preparation of a silicon carbide-based floating back barrier gate power device.

[0026] The beneficial effect of the present invention is that the silicon carbide-based floating back barrier gate power device can prevent a large number of electrons from entering the gate oxide layer and causing degradation of the gate oxide layer by depleting the floating back barrier under a large reverse voltage, thereby improving the reliability of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 1 is a schematic structural diagram of a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0028] Figure 2 This is a schematic flow chart of a method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0029] Figure 3 Schematic diagram of the structure formed in step S1 of the method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0030] Figure 4 Schematic diagram of the structure formed in step S2 of the method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0031] Figure 5 Schematic diagram of the structure formed in step S3 of the method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0032] Figure 6 Schematic diagram of the structure formed in step S4 of the method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0033] Figure 7 Schematic diagram of the structure formed in step S5 of the method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0034] Figure 8 Schematic diagram of the structure formed in step S5 of the method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0035] Figure 9 Schematic diagram of the structure formed in step S6 of the method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0036] Figure 10 Schematic diagram of the structure formed in step S7 of the method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0037] Figure 11 Schematic diagram of the structure formed in step S8 of the method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0038] Figure 12 Schematic diagram of the structure formed in step S9 of the method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0039] Figure 13 Schematic diagram of the structure formed in step S9 of the method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention;

[0040] Figure 14 Schematic diagram of the structure formed in step S10 of the method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention.

[0041] The meanings of the reference numerals in the accompanying drawings are:

[0042] 1-back drain metal layer; 2-n+ silicon carbide substrate; 3-n-type drift layer; 4-p-type base region; 50-p+ floating back barrier; 5-p+ source region; 6-n+ source region; 7-first source metal layer; 8-oxide layer; 9-second source metal layer; 10-gate oxide layer; 11-polysilicon gate; 12-top metal layer; 13-passivation layer; 14-first masking layer; 15-second masking layer; 16-carbon film. DETAILED DESCRIPTION

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0044] The terms "first", "second" and "third" in the present invention are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first", "second" and "third" may explicitly or implicitly include at least one of such features. In the description of the present invention, "multiple" means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined. All directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0045] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0046] Figure 1 This is a schematic diagram of the structure of a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention. Figure 1The silicon carbide-based floating back barrier gate power device includes a back drain metal layer 1, an n+ type silicon carbide substrate 2, and an n-type drift layer 3 stacked in sequence from bottom to top; p-type base regions 4 are respectively provided on both sides of the top of the n-type drift layer 3, a p+ type floating back barrier 50 is provided between the two p-type base regions 4, the p+ type floating back barrier 50 is spaced apart from the p-type base region 4, and a p+ type source region 5 and an n+ type source region 6 are wrapped in the p-type base region 4. The p+ type source region 5 and the n+ type source region 6 are arranged side by side and contact each other on the side, and the p+ type source region 5 is arranged close to the side of the n-type drift layer 3; on the n-type A first source metal layer 7, an oxide layer 8 and a second source metal layer 9 are provided above the drift layer 3 from left to right. A polysilicon gate 11 is wrapped in the oxide layer 8. A gate oxide layer 10 adjacent to the polysilicon gate 11 is provided below the oxide layer 8. The gate oxide layer 10 is provided above the n-type drift layer 3. The p+ type floating back barrier 50 is located below the gate oxide layer 10 and forms a floating back barrier gate structure with the gate oxide layer 10. A top metal layer 12 is provided above the first source metal layer 7, the oxide layer 8 and the second source metal layer 9, and a passivation layer 13 is provided above the top metal layer 12.

[0047] The silicon carbide-based floating back-barrier gate power device of an embodiment of the present invention forms a floating back-barrier gate structure through a p+ type floating back barrier 50 and a gate oxide layer 10. Under a large reverse voltage, it can prevent a large number of electrons from entering the gate oxide layer 10 and causing degradation of the gate oxide layer 10 by depleting the p+ type floating back barrier 50, thereby improving the reliability of the power device.

[0048] As an embodiment, the thickness of the n+ type silicon carbide substrate 2 is 350 μm, and the doping concentration is greater than 1e19 cm -3 .

[0049] As an embodiment, the thickness of the n-type drift layer 3 is 9.5 μm to 10.5 μm, and the doping concentration is 1e15 cm -3 ~1e16 cm -3 .

[0050] As an embodiment, the depth of the p+ type floating back barrier 50 is 3.0 μm, and the doping concentration is 1e18 cm -3 ~1e19cm -3 .

[0051] As an embodiment, the depth of the p-type base region 4 is 1.5 μm, and the doping concentration is 1e17 cm -3 ~1e18 cm -3 The depth of the n+ source region 6 is 0.2 μm, and the doping concentration is greater than 1e19 cm -3 The depth of the p+ source region 5 is 3.0 μm, and the doping concentration is 1e18 cm -3~1e19 cm -3 .

[0052] As an embodiment, the thickness of the gate oxide layer 10 is 500 Å.

[0053] As an embodiment, the thickness of the polysilicon gate 11 is 4000 Å.

[0054] As an embodiment, the thickness of the oxide layer 8 is 1.0 μm.

[0055] As an embodiment, the passivation layer 13 includes a plasma enhanced tetraethyl orthosilicate layer with a thickness of 6000 Å, a plasma enhanced silicon nitride layer with a thickness of 300 Å, and a polyimide film layer with a thickness of 7 μm.

[0056] As an embodiment, the thickness of the first source metal layer 7 and the second source metal layer 9 are both 1000 Å.

[0057] As an embodiment, the thickness of the top metal layer 12 is 4 μm.

[0058] As an embodiment, the back drain metal layer 1 includes a metal titanium layer with a thickness of 1000 Å, a metal nickel layer with a thickness of 2000 Å, and a metal silver layer with a thickness of 10 kA.

[0059] Figure 2 The figure is a flow chart of a method for preparing a silicon carbide-based floating back barrier gate power device according to an embodiment of the present invention. It should be noted that the method of the present invention is not limited to the method of the present invention if substantially the same results are achieved. Figure 2 The process sequence shown is limited. Figure 2 As shown, the method includes the steps of:

[0060] Step S1: epitaxially growing an n-type drift layer on an n+ silicon carbide substrate.

[0061] In step S1, Figure 3 As shown, the thickness of the n+ type silicon carbide substrate 2 is 350 μm, and the doping concentration is greater than 1e19 cm -3 The thickness of the n-type drift layer 3 is 9.5 μm to 10.5 μm, and the doping concentration is 1e15 cm -3 ~1e16 cm -3 .

[0062] Step S2: forming a p-type base region on the n-type drift layer by sequentially performing a first masking layer growth process, a high-temperature oxidation process, a photolithography process, an etching process, and an ion implantation process.

[0063] In step S2, first, a first masking layer 14 is grown on the cleaned n-type drift layer 3. The first masking layer 14 is a sandwich structure, including a thermal oxide layer with a thickness of 500 Å, a transition layer with a thickness of 1000 Å, and a low-pressure tetraethoxy silicate glass layer with a thickness of 2 μm, which are arranged in sequence from bottom to top. The thermal oxide layer serves as a shielding layer during injection, which can effectively prevent injection channel tunneling; the transition layer can connect the thermal oxide layer and the low-pressure tetraethoxy silicate glass layer, and the endpoint detection signal is strong during etching. Then, after high-temperature densification, photolithographic patterning, photoresist coating, exposure and development are carried out. The photoresist has a thickness of 2 μm, smooth sidewalls, and a sidewall angle greater than 88±2°. Next, the etching process is carried out. The etching is carried out using an ICP (Inductive Coupled Plasma) or TCP (Transformer Coupled Plasma) dry etching machine with better anisotropy. First, 2μm of the top low-pressure tetraethoxysilicate glass layer is etched, and the end point is stopped at the transition layer. After the over-etching is completed, the etching is switched to the transition layer, and the end point is stopped at the thermal oxide layer. Finally, the photoresist is removed and cleaned to prepare for ion implantation. Aluminum is implanted at a high temperature of 500°C with high energy. The implantation is divided into multiple times. Generally, 3 to 5 implantations are required, and the implantation angle is 0°. For example, taking 5 implantations as an example, the energy of the first implantation is 30kev, and the dose is 5e15 cm -2 The second injection energy is 100keV and the dose is 5e13 cm -2 The third injection energy is 250keV and the dose is 5e13cm -2 The fourth injection energy is 350keV and the dose is 5e14 cm -2 The fifth injection energy is 500keV and the dose is 5e15cm -2 , forming a depth of about 1.5 μm and a doping concentration of 1e17 cm -3 ~1e18cm -3 The p-type base region 4, such as Figure 4 shown.

[0064] Step S3: using the first masking layer to grow a layer of low-pressure tetraethoxy silicate glass, and forming an n+ type source region through a plasma dry isotropic etching process, a self-alignment process and an ion implantation process.

[0065] In step S3, a low-pressure tetraethoxy silicate glass with a thickness of about 5 kA is grown using the first masking layer 14. A 0.5 μm conductive channel is formed by plasma dry isotropic etching and self-alignment process. Then, nitrogen is injected at a high temperature of 500°C in multiple injections, typically 3 to 5 times, with an injection angle of 0°. For example, taking 4 injections as an example, the first injection energy is 20 kev and the dose is 5e14 cm -2 The second injection energy is 40keV and the dose is 5e14 cm -2 The third injection energy is 60keV and the dose is 5e14 cm -2 The fourth injection energy is 100keV and the dose is 8e13 cm -2 , with a depth of 0.2 μm and a doping concentration greater than 1e19 cm -3 The n+ type source region 6, such as Figure 5 shown.

[0066] Step S4: removing the first masking layer by wet method, re-depositing the second masking layer of each layer, and forming the p+ type source region and the p+ type floating back barrier by photolithography, etching and ion implantation.

[0067] In step S4, the first masking layer 14 is removed by wet method, and the second masking layer 15 of each layer is re-deposited. Then, photolithography patterning, photoresist coating, exposure and development are carried out in sequence. The second masking layer is etched, and after removing the photoresist, P-type ion implantation is performed. Aluminum is implanted at high energy at a high temperature of 500°C, in multiple injections, generally 4 to 7 times, with an implantation angle of 0°. For example, taking 7 injections as an example, the first injection energy is 30keV and the dose is 5e15cm -2 The second injection energy is 100keV and the dose is 5e14 cm -2 The third injection energy is 250keV and the dose is 5e14 cm -2 The fourth injection energy is 350keV and the dose is 5e14 cm -2 The fifth injection energy is 500keV and the dose is 5e15 cm -2 The sixth injection energy is 600keV and the dose is 5e14 cm -2 The seventh injection energy is 700keV and the dose is 5e13 cm -2 , forming a depth of about 3.0 μm and a doping concentration of 1e18 cm -3 ~1e19 cm -3 The p+ type source region 5 and the p+ type floating back barrier 50 are as follows: Figure 6 shown.

[0068] Step S5: growing a gate oxide layer through a carbon film growth and high-temperature activation process and a nitrogen annealing process.

[0069] In step S5, a carbon film 16 is sputtered in a metal sputtering chamber, and then activated in a high-temperature furnace at 1650° C. for 30 minutes, and finally the carbon film 16 is removed with sulfuric acid. Figure 7 As shown. Before growing the gate oxide layer 10, a nitrogen annealing process is added. During the nitrogen annealing process, a sandwich annealing process with NO / O2 / NO gas is used. Specifically, before thermal oxidation, the sample surface is treated with a gas with a NO content of 2% for 1 hour, and then thermal oxidation is carried out in a gas with an O2 content of 5% to grow a gate oxide layer 10 with a thickness of 500A. Finally, the sample is thermally annealed with a gas with a NO content of 2% for 1 hour. The temperature is controlled at 1250℃ throughout the process, and the following is obtained: Figure 8 As shown in the gate oxide layer 10 , the p+ type floating back barrier 50 is located below the gate oxide layer 10 and forms a floating back barrier gate structure with the gate oxide layer 10 .

[0070] Step S6: depositing saturated doped polysilicon on the gate oxide layer, and forming a polysilicon gate through photolithography and etching processes.

[0071] In step S6, first, saturated doped polysilicon with a thickness of about 4000A is deposited in a low temperature furnace tube, and then a polysilicon gate 11 is formed by photolithography and etching. Figure 9 shown.

[0072] Step S7: depositing a layer of boron phosphosilicate glass on the polysilicon gate and the gate oxide layer, and forming an oxide layer through photolithography and etching processes, wherein the oxide layer wraps the polysilicon gate.

[0073] In step S7, a layer of borophosphosilicate glass with a thickness of 1 μm is first deposited as a dielectric isolation layer, and a pattern is exposed using a photomask for an ohmic contact hole. The borophosphosilicate glass is then dry-etched to form an ohmic contact hole and an oxide layer 8 is formed. The oxide layer 8 wraps around the polysilicon gate 11. Figure 10 shown.

[0074] Step S8: forming a first source metal layer and a second source metal layer on both sides of the oxide layer through a metal deposition process and a rapid annealing process.

[0075] In step S8, a nickel metal layer with a thickness of 1000A is deposited on both sides of the oxide layer 8, and a rapid annealing is performed at 500℃~700℃ for 60 seconds to form a layer of Ni x Si y The nickel without alloy layer on the dielectric SiO2 is removed by etching solution, and finally rapid annealing is performed at 980℃ for 60 seconds to make Ni x Siy The alloy layer becomes a high temperature alloy to form a good ohmic contact, that is, the first source metal layer 7 and the second source metal layer 9, such as Figure 11 shown.

[0076] Step S9: forming a top metal layer through a sputtering process and an etching process, and depositing a passivation layer on the top metal layer.

[0077] In step S9, a layer of titanium aluminum metal with a thickness of 4 μm is sputtered on the first source metal layer 7, the oxide layer 8 and the second source metal layer 9, and the gate and the source are isolated by metal etching to form a top metal layer 12, as shown in FIG. Figure 12 As shown. A passivation layer 13 is deposited on the top metal layer 12, as shown Figure 13 The passivation layer 13 includes a plasma enhanced tetraethyl orthosilicate layer with a thickness of 6000 Å, a plasma enhanced silicon nitride layer with a thickness of 300 Å, and a polyimide film layer with a thickness of 7 μm.

[0078] Step S10: forming a back drain metal layer on the back of the n+ type silicon carbide substrate by a metal deposition process and a laser annealing process, thereby completing the preparation of the silicon carbide-based floating back barrier gate power device.

[0079] In step S10, a blue film is applied to the front side of the n+ type silicon carbide substrate 2, and the back side is thinned to 100 μm. Then, the blue film is removed, cleaned, titanium is evaporated on the back side, and an ohmic contact is formed by laser annealing to form a back drain metal layer 1, thereby completing the preparation of the silicon carbide-based floating back barrier gate power device. Figure 14 The back drain metal layer 1 includes a metal titanium layer with a thickness of 1000 Å, a metal nickel layer with a thickness of 2000 Å, and a metal silver layer with a thickness of 10 kÅ.

[0080] The method for preparing a silicon carbide-based floating back-barrier gate power device in an embodiment of the present invention forms a floating back-barrier gate structure through a p+ type floating back barrier 50 and a gate oxide layer 10. Under a large reverse voltage, the p+ type floating back barrier 50 can be depleted to prevent a large number of electrons from entering the gate oxide layer 10 and causing degradation of the gate oxide layer 10, thereby improving the reliability of the power device.

[0081] The above are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A silicon carbide-based floating back barrier gate power device, characterized in that: The invention comprises a back drain metal layer, an n+ type silicon carbide substrate, and an n-type drift layer stacked in sequence from bottom to top; p-type base regions are respectively provided on both sides of the top of the n-type drift layer, a p+ type floating back barrier is provided between the two p-type base regions, the p+ type floating back barrier is spaced apart from the p-type base region, a p+ type source region and an n+ type source region are wrapped in the p-type base region, the p+ type source region and the n+ type source region are arranged side by side and contact each other on the side, and the p+ type source region is arranged close to the side of the n-type drift layer; A first source metal layer, an oxide layer, and a second source metal layer are sequentially provided above the n-type drift layer from left to right, a planar polysilicon gate is encapsulated in the oxide layer, a gate oxide layer adjacent to the planar polysilicon gate is provided below the oxide layer, and the p+ type floating back barrier is located below the gate oxide layer and contacts the gate oxide layer to form a floating back barrier gate structure; a top metal layer is provided above the first source metal layer, the oxide layer, and the second source metal layer, and a passivation layer is provided above the top metal layer; The depth of the p+ type floating back barrier is 3.0 μm and the doping concentration is 1e18 cm -3 ~1e19 cm -3 .

2. The silicon carbide-based floating back barrier gate power device according to claim 1, characterized in that: The depth of the p-type base region is 1.5 μm and the doping concentration is 1e17 cm -3 ~1e18 cm -3 The depth of the n+ type source region is 0.2 μm, and the doping concentration is greater than 1e19 cm -3 The depth of the p+ type source region is 3.0 μm and the doping concentration is 1e18 cm -3 ~1e19 cm -3 .

3. The silicon carbide-based floating back barrier gate power device according to claim 1, characterized in that: The thickness of the gate oxide layer is 500 angstroms; the thickness of the planar polysilicon gate is 4000 angstroms.

4. The silicon carbide-based floating back barrier gate power device according to claim 1, characterized in that: The thickness of the oxide layer is 1.0 μm.

5. The silicon carbide-based floating back barrier gate power device according to claim 1, characterized in that: The passivation layer includes a plasma enhanced tetraethyl orthosilicate layer with a thickness of 6000 angstroms, a plasma enhanced silicon nitride layer with a thickness of 300 angstroms, and a polyimide film layer with a thickness of 7 μm.

6. The silicon carbide-based floating back barrier gate power device according to claim 1, characterized in that: The thickness of the first source metal layer and the second source metal layer are both 1000 angstroms.

7. The silicon carbide-based floating back barrier gate power device according to claim 1, characterized in that: The thickness of the top metal layer is 4 μm.

8. The silicon carbide-based floating back barrier gate power device according to claim 1, characterized in that: The back drain metal layer includes a metal titanium layer with a thickness of 1000 angstroms, a metal nickel layer with a thickness of 2000 angstroms, and a metal silver layer with a thickness of 10 kiloangstroms.

9. A method for preparing a silicon carbide-based floating back barrier gate power device according to any one of claims 1 to 8, comprising: Step S1: epitaxially growing an n-type drift layer on an n+ silicon carbide substrate; Step S2: forming a p-type base region on the n-type drift layer by sequentially performing a first masking layer growth process, a high-temperature oxidation process, a photolithography process, an etching process, and an ion implantation process; Step S3: growing a layer of low-pressure tetraethoxy silicate glass using the first masking layer, and forming an n+ type source region through a plasma dry isotropic etching process, a self-aligned process, and an ion implantation process; Step S4: removing the first masking layer by wet method, re-depositing the second masking layer of each layer, and forming a p+ type source region and a p+ type floating back barrier by photolithography, etching and ion implantation; Step S5: growing a gate oxide layer through a carbon film growth and high temperature activation process and a nitrogen annealing process; Step S6: depositing saturated doped polysilicon on the gate oxide layer, and forming a planar polysilicon gate through photolithography and etching processes; Step S7: depositing a layer of borophosphosilicate glass on the planar polysilicon gate and the gate oxide layer, and forming an oxide layer by photolithography and etching processes, wherein the oxide layer wraps the planar polysilicon gate; Step S8: forming a first source metal layer and a second source metal layer on both sides of the oxide layer by a metal deposition process and a rapid annealing process; Step S9: forming a top metal layer through a sputtering process and an etching process, and depositing a passivation layer on the top metal layer; Step S10: forming a back drain metal layer on the back of the n+ type silicon carbide substrate by a metal deposition process and a laser annealing process, thereby completing the preparation of a silicon carbide-based floating back barrier gate power device.

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