Silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact and preparation method thereof

Abstract

The present invention relates to the field of semiconductor devices and discloses a silicon carbide MOSFET with gate-integrated Schottky and ohmic contacts and a method for preparing the same. The MOSFET comprises p-type base regions on either side of an n-type drift layer, with a first p+ source region and an n+ source region encapsulated within the p-type base region. Two second p+ source regions are spaced apart along the extension direction of the p-type base region between the two p-type base regions. A first source metal layer and a second source metal layer are disposed on either side of the n-type drift layer above the n-type drift layer, with a first gate oxide layer, an ohmic metal layer, and a second gate oxide layer arranged side by side between the first and second source metal layers. The ohmic metal layer is disposed corresponding to the second p+ source region and forms an ohmic contact with the second p+ source region. A Schottky metal layer is disposed between the two ohmic metal layers, forming a Schottky contact with the n-type drift layer. Through the above-described approach, the present invention can prevent gate oxide degradation and improve device performance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC), a representative of third-generation semiconductors, boasts a wide bandgap, high breakdown voltage, high thermal conductivity, and a high electron saturation rate. Consequently, power electronic devices fabricated with SiC exhibit higher withstand voltage, current stability, and operating frequency. They can operate in high-frequency and high-temperature environments, offering high reliability and suitability for demanding operating environments. Consequently, SiC, as a third-generation power electronic device, has become a key development direction in power electronics technology, with significant application prospects in both military and civilian fields.

[0003] Metal oxide semiconductor field effect transistors (MOSFETs), as voltage-controlled devices, offer advantages such as fast switching speed, excellent high-frequency performance, low noise, and low drive power, making them a commonly used power switching device. Compared to comparable silicon-based MOSFETs, silicon carbide-based MOSFETs offer higher voltage resistance and higher operating temperatures due to their material properties. Without requiring complex structural design, they can achieve lower specific on-resistance than silicon-based materials at the same voltage, making them the most suitable power switching devices for operation under high-temperature and high-voltage conditions. However, reliability issues with silicon carbide-based MOSFETs have hindered their commercial development and widespread application.

[0004] However, reliability issues in silicon carbide-based MOSFET devices, particularly the gate oxide layer, including the gate oxide layer's TDDB (Time Dependent Dielectric Breakdown) and BTI (Bias Temperature Instability) effects, have restricted the device's further application and development. Because silicon carbide contains numerous interface defects in the Si / SiO2 region, electrons in the SiC easily penetrate the potential barrier and enter the gate oxide under high voltage stress, causing severe degradation of the gate oxide layer and impacting the performance of power devices. Summary of the Invention

[0005] The present invention provides a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact and a preparation method thereof, which can avoid degradation of the gate oxide layer and improve device performance.

[0006] In order to solve the above technical problems, a technical solution adopted by the present invention is as follows: a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact is provided, comprising: a back drain metal layer, an n+ type silicon carbide substrate, and an n-type drift layer stacked in sequence from bottom to top; p-type base regions are respectively provided on both sides of the top of the n-type drift layer, a first p+ type source region and an n+ type source region are wrapped in the p-type base region, the first p+ type source region and the n+ type source region are arranged side by side and contact each other on the side, and the first p+ type source region is arranged close to the side of the n-type drift layer; two second p+ type source regions are provided between the two p-type base regions and are spaced apart along the extension direction of the p-type base region; a first source metal layer and a second source metal layer are respectively provided on both sides above the n-type drift layer, and a first gate oxide layer is provided side by side between the first source metal layer and the second source metal layer. , an ohmic metal layer and a second gate oxide layer; the ohmic metal layer is arranged corresponding to the second p+ type source region and forms an ohmic contact with the second p+ type source region, a Schottky metal layer is provided between the two ohmic metal layers, the Schottky metal layer and the ohmic metal layer are arranged at intervals from each other, the Schottky metal layer is located above the n-type drift layer and forms a Schottky contact with the n-type drift layer; a first oxide layer is provided above the first gate oxide layer, a second oxide layer is provided above the second gate oxide layer, a first polysilicon gate is wrapped in the first oxide layer, and a second polysilicon gate is wrapped in the second oxide layer; a top metal layer is provided above the first source metal layer, the first oxide layer, the Schottky metal layer, the ohmic metal layer, the second oxide layer and the second source metal layer, and a passivation layer is provided above the top metal layer.

[0007] According to one embodiment of the present invention, the depth of the p-type base region is 1.5 μm, and the doping concentration is 1e17 cm -3 ~1e18cm -3 The depth of the n+ type source region is 0.2 μm, and the doping concentration is greater than 1e19 cm -3 The depth of the first p+ type source region and the second p+ type source region is 3.0 μm, and the doping concentration is 1e18 cm -3 ~1e19cm -3 .

[0008] According to one embodiment of the present invention, the thickness of the Schottky metal layer and the ohmic metal layer are both 1000 Å.

[0009] According to one embodiment of the present invention, the thickness of the first gate oxide layer and the second gate oxide layer is 500 Å; the thickness of the first polysilicon gate and the second polysilicon gate is 4000 Å.

[0010] According to an embodiment of the present invention, the thickness of the first oxide layer and the second oxide layer are both 1.0 μm.

[0011] According to one embodiment of the present invention, the passivation layer includes a plasma-enhanced tetraethyl orthosilicate layer with a thickness of 6000 Å, a plasma-enhanced silicon nitride layer with a thickness of 300 Å, and a polyimide film layer with a thickness of 7 μm.

[0012] According to one embodiment of the present invention, the thickness of the first source metal layer and the second source metal layer are both 1000 Å.

[0013] According to one embodiment of the present invention, the thickness of the top metal layer is 4 μm.

[0014] According to one embodiment of the present invention, the back drain metal layer includes a metal titanium layer with a thickness of 1000 Å, a metal nickel layer with a thickness of 2000 Å, and a metal silver layer with a thickness of 10 kA.

[0015] To solve the above technical problems, another technical solution adopted by the present invention is to provide a method for preparing the silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact, comprising:

[0016] Step S1: epitaxially growing an n-type drift layer on an n+ silicon carbide substrate;

[0017] Step S2: forming a p-type base region on the n-type drift layer by sequentially performing a first masking layer growth process, a high-temperature oxidation process, a photolithography process, an etching process, and an ion implantation process;

[0018] Step S3: growing a layer of low-pressure tetraethoxy silicate glass using the first masking layer, and forming an n+ type source region through a plasma dry isotropic etching process, a self-aligned process, and an ion implantation process;

[0019] Step S4: removing the first masking layer by wet process, re-depositing the second masking layer of each layer, and forming a first p+ type source region and a second p+ type source region by photolithography, etching and ion implantation, wherein two second p+ type source regions are provided, and the two second p+ type source regions are spaced apart along the extension direction of the p-type base region;

[0020] Step S5: growing a gate oxide layer through a carbon film growth and high temperature activation process and a nitrogen annealing process;

[0021] Step S6: depositing saturated doped polysilicon on the gate oxide layer, and forming two mutually separated first polysilicon gates and second polysilicon gates through photolithography and etching processes;

[0022] Step S7: depositing a layer of borophosphosilicate glass on the first polysilicon gate, the second polysilicon gate, and the gate oxide layer; and forming a first oxide layer, a second oxide layer, and an ohmic filling region between the first oxide layer and the second oxide layer corresponding to the position of the second p+ type source region, and forming an oxide region corresponding to the position between the two second p+ type source regions through photolithography and etching processes.

[0023] Step S8: forming a first source metal layer, a second source metal layer and an ohmic metal layer on both sides of the oxide region and the oxide layer by a metal deposition process and a rapid annealing process;

[0024] Step S9: forming the first oxide layer, the second oxide layer and a Schottky filling region between the first oxide layer and the second oxide layer, which are separated from each other, in the oxide region by a dry etching process, depositing a layer of metal titanium in the Schottky filling region, and forming a Schottky metal layer by an annealing process;

[0025] Step S10: forming a top metal layer over the first source metal layer, the first oxide layer, the Schottky metal layer, the ohmic metal layer, the second oxide layer, and the second source metal layer by sputtering and etching, and depositing a passivation layer on the top metal layer;

[0026] Step S11: forming a back drain metal layer on the back of the n+ type silicon carbide substrate by a metal deposition process and a laser annealing process, thereby completing the preparation of a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact.

[0027] The beneficial effects of the present invention are as follows: the silicon carbide MOSFET is ohmic conduction during forward conduction and has a low on-voltage; when reversely cut off, the Schottky is reverse biased; a Schottky contact is formed between the Schottky metal layer and the n-type drift layer, and the layer can be depleted together with the p-type base region and the ohmic metal layer to form a P-type depletion layer; compared with the traditional gate oxide layer, two depletion layers are added, which can better protect the gate from being broken down by a large drain pulse and avoid degradation of the gate oxide layer; in addition, the polysilicon gate with a separated structure can reduce the gate capacitance and reduce the high-frequency power consumption of the device, thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 1 is a schematic cross-sectional structural diagram of a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0029] Figure 2 1 is another schematic cross-sectional structure diagram of a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0030] Figure 3 This is a schematic flow chart of a method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0031] Figure 4 Schematic diagram of the structure formed in step S1 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0032] Figure 5 Schematic diagram of the structure formed in step S2 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0033] Figure 6 Schematic diagram of the structure formed in step S3 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0034] Figure 7 1 is a schematic cross-sectional view of a structure formed in step S4 of a method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0035] Figure 8 2 is another schematic cross-sectional view of the structure formed in step S4 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0036] Figure 9 1 is a schematic cross-sectional view of a structure formed in step S5 of a method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0037] Figure 10 2 is another schematic cross-sectional view of the structure formed in step S5 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0038] Figure 11 2 is another schematic cross-sectional view of the structure formed in step S5 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0039] Figure 12 2 is another schematic cross-sectional view of the structure formed in step S5 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0040] Figure 13 1 is a schematic cross-sectional view of a structure formed in step S6 of a method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0041] Figure 14 2 is another schematic cross-sectional view of the structure formed in step S6 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0042] Figure 15 1 is a schematic cross-sectional view of a structure formed in step S7 of a method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0043] Figure 16 2 is another schematic cross-sectional view of the structure formed in step S7 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0044] Figure 17 Schematic diagram of the structure formed in step S8 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0045] Figure 18 1 is a partial schematic diagram of the structure formed in step S9 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0046] Figure 19 1 is a schematic cross-sectional view of a structure formed in step S9 of a method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0047] Figure 20 Schematic diagram of the structure formed in step S10 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0048] Figure 21 Schematic diagram of the structure formed in step S10 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention;

[0049] Figure 22 Schematic diagram of the structure formed in step S11 of the method for preparing a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact according to an embodiment of the present invention.

[0050] The meanings of the reference numerals in the accompanying drawings are:

[0051] 1-back drain metal layer; 2-n+ type silicon carbide substrate; 3-n-type drift layer; 4-p-type base region; 5-first p+ type source region; 6-n+ type source region; 7-second p+ type source region; 80-gate oxide layer; 81-first gate oxide layer; 82-second gate oxide layer; 91-first polysilicon gate; 92-second polysilicon gate; 10-first oxide layer; 11-second oxide layer; 12-first source metal layer; 13-second source metal layer; 14-Schottky metal layer; 15-ohmic metal layer; 16-top metal layer; 17-passivation layer; 18-first masking layer; 19-second masking layer; 20-carbon film; 100-oxide region. DETAILED DESCRIPTION

[0052] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0053] The terms "first", "second" and "third" in the present invention are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first", "second" and "third" may explicitly or implicitly include at least one of such features. In the description of the present invention, "multiple" means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined. All directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0054] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0055] Figure 1 、 Figure 2 Schematic diagram of the structure of a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact at different positions according to an embodiment of the present invention. Figure 1 and Figure 2 The silicon carbide MOSFET with integrated Schottky contact and ohmic contact includes: a back drain metal layer 1, an n+ type silicon carbide substrate 2, and an n-type drift layer 3 stacked in sequence from bottom to top; a p-type base region 4 is provided on both sides of the top of the n-type drift layer 3, and a first p+ type source region 5 and an n+ type source region 6 are wrapped in the p-type base region 4. The first p+ type source region 5 and the n+ type source region 6 are arranged side by side and contact each other on the side. The first p+ type source region 5 is arranged close to the side of the n-type drift layer 3; two second p+ type source regions 7 are provided between the two p-type base regions 4 and are spaced apart along the extension direction of the p-type base region 4; a first source metal layer 12 and a second source metal layer 13 are provided on both sides above the n-type drift layer 3, and a first gate oxide layer 81, an ohmic metal layer 15, and a second gate oxide layer 82 are provided side by side between the first source metal layer 12 and the second source metal layer 13. ; The ohmic metal layer 15 is arranged corresponding to the second p+ type source region 7 and forms an ohmic contact with the second p+ type source region 7. A Schottky metal layer 14 is provided between the two ohmic metal layers 15. The Schottky metal layer 14 and the ohmic metal layer 15 are arranged at intervals from each other. The Schottky metal layer 14 is located above the n-type drift layer 3 and forms a Schottky contact with the n-type drift layer 3; a first oxide layer 10 is provided above the first gate oxide layer 81, and a second oxide layer 11 is provided above the second gate oxide layer 82. The first oxide layer 10 is wrapped with a first polysilicon gate 91, and the second oxide layer 11 is wrapped with a second polysilicon gate 92; a top metal layer 16 is provided above the first source metal layer 12, the first oxide layer 10, the Schottky metal layer 14, the ohmic metal layer 15, the second oxide layer 11 and the second source metal layer 13, and a passivation layer 17 is provided above the top metal layer 16.

[0056] The silicon carbide MOSFET with integrated Schottky contact and ohmic contact of the gate in the embodiment of the present invention is ohmic conduction during forward conduction and has a low turn-on voltage. During reverse cutoff, the Schottky is reverse biased, and a Schottky contact is formed between the Schottky metal layer 14 and the n-type drift layer 3. It can be depleted together with the p-type base region 4 and the ohmic metal layer 15 to form a P-type depletion layer. Compared with the traditional gate oxide layer, two depletion layers are added, which can better protect the gate from being broken down by a large drain pulse and avoid degradation of the gate oxide layer. In addition, the polysilicon gate with a separated structure can reduce the gate capacitance and reduce the high-frequency power consumption of the device, thereby improving the performance of the device.

[0057] As an embodiment, the thickness of the n+ type silicon carbide substrate 2 is 350 μm, and the doping concentration is greater than 1e19 cm -3 .

[0058] As an embodiment, the thickness of the n-type drift layer 3 is 9.5 μm to 10.5 μm, and the doping concentration is 1e15 cm -3 ~1e16cm -3 .

[0059] As an embodiment, the depth of the p-type base region 4 is 1.5 μm, and the doping concentration is 1e17 cm -3 ~1e18cm -3 The depth of the n+ source region 6 is 0.2 μm, and the doping concentration is greater than 1e19 cm -3 The depth of the first p+ type source region 5 and the second p+ type source region 7 is 3.0 μm, and the doping concentration is 1e18 cm -3 ~1e19cm -3 .

[0060] As an embodiment, the thickness of the Schottky metal layer 14 and the ohmic metal layer 15 are both 1000 Å.

[0061] As an embodiment, the thickness of the first gate oxide layer 81 and the second gate oxide layer 82 is 500 Å.

[0062] As an embodiment, the thickness of the first polysilicon gate 91 and the second polysilicon gate 92 is 4000 Å.

[0063] As an embodiment, the thickness of the first oxide layer 10 and the second oxide layer 11 are both 1.0 μm.

[0064] As an embodiment, the passivation layer 17 includes a plasma enhanced tetraethyl orthosilicate layer with a thickness of 6000 Å, a plasma enhanced silicon nitride layer with a thickness of 300 Å, and a polyimide film layer with a thickness of 7 μm.

[0065] As an embodiment, the thickness of the first source metal layer 12 and the second source metal layer 13 are both 1000 Å.

[0066] As an embodiment, the thickness of the top metal layer 16 is 4 μm.

[0067] As an embodiment, the back drain metal layer 1 includes a metal titanium layer with a thickness of 1000 Å, a metal nickel layer with a thickness of 2000 Å, and a metal silver layer with a thickness of 10 kA.

[0068] Figure 3 The figure is a flow chart of a method for preparing a silicon carbide MOSFET with gate-integrated Schottky contacts and ohmic contacts according to an embodiment of the present invention. It should be noted that the method of the present invention is not limited to the method of the present invention if substantially the same results are achieved. Figure 3 The process sequence shown is limited. Figure 3 As shown, the method includes the steps of:

[0069] Step S1: epitaxially growing an n-type drift layer on an n+ silicon carbide substrate.

[0070] In step S1, Figure 4 As shown, the thickness of the n+ type silicon carbide substrate 2 is 350 μm, and the doping concentration is greater than 1e19 cm -3 The thickness of the n-type drift layer 3 is 9.5 μm to 10.5 μm, and the doping concentration is 1e15 cm -3 ~1e16cm -3 .

[0071] Step S2: forming a p-type base region on the n-type drift layer by sequentially performing a first masking layer growth process, a high-temperature oxidation process, a photolithography process, an etching process, and an ion implantation process.

[0072] In step S2, first, a first masking layer 18 is grown on the cleaned n-type drift layer 3. The first masking layer 18 is a sandwich structure, including a thermal oxide layer with a thickness of 500 Å, a transition layer with a thickness of 1000 Å, and a low-pressure tetraethoxy silicate glass layer with a thickness of 2 μm, which are arranged in sequence from bottom to top. The thermal oxide layer serves as a shielding layer during injection, which can effectively prevent injection channel tunneling; the transition layer can connect the thermal oxide layer and the low-pressure tetraethoxy silicate glass layer, and the endpoint detection signal is strong during etching. Then, after high-temperature densification, photolithographic patterning, photoresist coating, exposure and development are carried out. The photoresist has a thickness of 2 μm, smooth sidewalls, and a sidewall angle greater than 88±2°. Next, the etching process is carried out. The etching is carried out using an ICP (Inductive Coupled Plasma) or TCP (Transformer Coupled Plasma) dry etching machine with better anisotropy. First, the top low-pressure tetraethoxysilicate glass layer is etched to 2μm, and the end point is stopped at the transition layer. After the over-etching is completed, the etching is switched to the transition layer, and the end point is stopped at the thermal oxide layer. Finally, the photoresist is removed and cleaned to prepare for ion implantation. Aluminum is injected at high energy at a high temperature of 500°C, and the injection is divided into multiple times. Generally, 3 to 5 injections are required, and the injection angle is 0°. For example, taking 5 injections as an example, the energy of the first injection is 30kev, and the dose is 5e15cm -2 The second injection energy is 100keV and the dose is 5e13cm -2 The third injection energy is 250keV and the dose is 5e13cm -2 The fourth injection energy is 350keV and the dose is 5e14cm -2 The fifth injection energy is 500keV and the dose is 5e15cm -2, forming a depth of about 1.5μm and a doping concentration of 1e17cm -3 ~1e18cm -3 The p-type base region 4, such as Figure 5 shown.

[0073] Step S3: using the first masking layer to grow a layer of low-pressure tetraethoxy silicate glass, and forming an n+ type source region through a plasma dry isotropic etching process, a self-alignment process and an ion implantation process.

[0074] In step S3, a low-pressure tetraethoxy silicate glass with a thickness of about 5 kA is grown using the first masking layer 18. A 0.5 μm conductive channel is formed by plasma dry isotropic etching and self-alignment process. Then, nitrogen is injected at a high temperature of 500°C in multiple injections, typically 3 to 5 times, with an injection angle of 0°. For example, taking 4 injections as an example, the first injection energy is 20 kev and the dose is 5e14 cm -2 The second injection energy is 40keV and the dose is 5e14cm -2 The third injection energy is 60keV and the dose is 5e14cm -2 The fourth injection energy is 100keV and the dose is 8e13cm -2 , with a depth of 0.2 μm and a doping concentration greater than 1e19 cm -3 The n+ type source region 6, such as Figure 6 shown.

[0075] Step S4: Use a wet method to remove the first masking layer, re-deposit the second masking layer of each layer, and form a first p+ type source region and a second p+ type source region through photolithography, etching and ion implantation processes. Two second p+ type source regions are set, and the two second p+ type source regions are spaced apart along the extension direction of the p-type base region.

[0076] In step S4, the first masking layer 18 is removed by wet method, and the second masking layer 19 of each layer is re-deposited. Then, photolithography patterning, photoresist coating, exposure and development are carried out in sequence. The second masking layer is etched, and after removing the photoresist, P-type ion implantation is performed. Aluminum is implanted at high energy at a high temperature of 500°C, in multiple injections, generally 4 to 7 times, with an implantation angle of 0°. For example, taking 7 injections as an example, the first injection energy is 30keV and the dose is 5e15cm -2 The second injection energy is 100keV and the dose is 5e14cm -2 The third injection energy is 250keV and the dose is 5e14cm -2 The fourth injection energy is 350keV and the dose is 5e14cm -2The fifth injection energy is 500keV and the dose is 5e15cm -2 The sixth injection energy is 600keV and the dose is 5e14cm -2 The seventh injection energy is 700keV and the dose is 5e13cm -2 , forming a depth of about 3.0μm and a doping concentration of 1e18cm -3 ~1e19cm -3 The first p+ type source region 5 (such as Figure 7 As shown) and the second p+ type source region 7 (as Figure 8 shown).

[0077] Step S5: growing a gate oxide layer through a carbon film growth and high-temperature activation process and a nitrogen annealing process.

[0078] In step S5, a carbon film 20 is sputtered in a metal sputtering chamber, and then activated in a high-temperature furnace at 1650° C. for 30 minutes, and finally the carbon film 20 is removed with sulfuric acid. Figure 9-10 As shown. Before growing the gate oxide layer 80, a nitrogen annealing process is added. During the nitrogen annealing process, a sandwich annealing process with NO / O2 / NO gas is used. Specifically, before thermal oxidation, the sample surface is treated with a gas with a NO content of 2% for 1 hour, and then thermal oxidation is carried out in a gas with an O2 content of 5% to grow a gate oxide layer 80 with a thickness of 500A. Finally, the sample is thermally annealed with a gas with a NO content of 2% for 1 hour. The temperature is controlled at 1250℃ throughout the process, and the following is obtained: Figure 11-12 A gate oxide layer 80 is shown.

[0079] Step S6: depositing saturated doped polysilicon on the gate oxide layer, and forming a first polysilicon gate and a second polysilicon gate separated from each other through photolithography and etching processes.

[0080] In step S6, first, saturated doped polysilicon with a thickness of about 4000A is deposited in a low-temperature furnace tube, and the polysilicon is photoetched to form a first polysilicon gate 91 and a second polysilicon gate 92 separated from each other. Figure 13-14 shown.

[0081] Step S7: depositing a layer of borophosphosilicate glass on the first polysilicon gate, the second polysilicon gate and the gate oxide layer; and forming a first oxide layer, a second oxide layer and an ohmic filling region between the first oxide layer and the second oxide layer at the position corresponding to the second p+ type source region through photolithography and etching processes; and forming an oxide region at the position corresponding to the position between the two second p+ type source regions.

[0082] In step S7, a layer of borophosphosilicate glass with a thickness of 1 μm is first deposited as a dielectric isolation layer, and a pattern is exposed using a photomask for an ohmic contact hole. The borophosphosilicate glass is then dry-etched to form an ohmic contact hole. Due to different etching positions, different profiles are formed, such as Figure 15 The oxidation region 100 shown, and Figure 16 The first oxide layer 10 and the second oxide layer 11 are shown, and an ohmic filling region is provided between the first oxide layer 10 and the second oxide layer 11 .

[0083] Step S8: forming a first source metal layer, a second source metal layer and an ohmic metal layer on both sides of the oxide region and the oxide layer by a metal deposition process and a rapid annealing process.

[0084] In step S8, a nickel metal layer with a thickness of 1000A is deposited on both sides of the oxidation region 100, the first oxide layer 10 and the second oxide layer 11, and a rapid annealing is performed at 500℃~700℃ for 60 seconds to form a layer of Ni x Si y The nickel without alloy layer on the dielectric SiO2 is removed by etching solution, and finally rapid annealing is performed at 980℃ for 60 seconds to make Ni x Si y The alloy layer becomes a high temperature alloy, forming a good ohmic contact, and obtaining a first source metal layer 12, a second source metal layer 13 and an ohmic metal layer 15, such as Figure 17 shown.

[0085] Step S9: forming a first oxide layer, a second oxide layer and a Schottky filling region between the first oxide layer and the second oxide layer in the oxide region by dry etching, depositing a layer of metal titanium in the Schottky filling region, and forming a Schottky metal layer by annealing.

[0086] In step S9, in step S7 Figure 15 On the basis of, a Schottky metal layer is formed by dry etching process and annealing process, the annealing temperature is 500 ° C, the annealing time is 1 minute, and the thickness of the Schottky metal layer 14 is 1000A. Figure 18 and Figure 19 shown.

[0087] Step S10: forming a top metal layer by sputtering and etching above the first source metal layer, the first oxide layer, the Schottky metal layer, the ohmic metal layer, the second oxide layer and the second source metal layer, and depositing a passivation layer on the top metal layer.

[0088] In step S10, a layer of titanium aluminum metal with a thickness of 4 μm is sputtered on the first source metal layer 12, the first oxide layer 10, the Schottky metal layer 14, the ohmic metal layer 15, the second oxide layer 11 and the second source metal layer 13, and the gate and the source are isolated by metal etching to form a top metal layer 16, as shown in FIG. Figure 20 A passivation layer 17 is deposited on the top metal layer 16, as shown. Figure 21 The passivation layer 17 includes a plasma enhanced tetraethyl orthosilicate layer with a thickness of 6000 Å, a plasma enhanced silicon nitride layer with a thickness of 300 Å, and a polyimide film layer with a thickness of 7 μm.

[0089] Step S11: forming a back drain metal layer on the back of the n+ type silicon carbide substrate by a metal deposition process and a laser annealing process, thereby completing the preparation of a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact.

[0090] In step S11, a blue film is applied to the front surface of the n+ type silicon carbide substrate 2, and the back surface is thinned to 100 μm. Then, the blue film is removed, cleaned, titanium is evaporated on the back surface, and an ohmic contact is formed by laser annealing to form a back drain metal layer 1, thereby completing the preparation of a silicon carbide MOSFET with gate integrated Schottky contact and ohmic contact. Figure 22 The back drain metal layer 1 includes a metal titanium layer with a thickness of 1000 Å, a metal nickel layer with a thickness of 2000 Å, and a metal silver layer with a thickness of 10 kÅ.

[0091] The method for preparing a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact in an embodiment of the present invention forms a Schottky contact between the Schottky metal layer 14 and the n-type drift layer 3, and forms an ohmic contact with the second p+ type source region 7 through the ohmic metal layer 15; the silicon carbide MOSFET is ohmic conduction in forward conduction and has a low turn-on voltage, and the Schottky is reverse biased in reverse cutoff. The Schottky contact is formed between the Schottky metal layer 14 and the n-type drift layer 3, and can be depleted together with the p-type base region 4 and the ohmic metal layer 15 to form a P-type depletion layer. Compared with the traditional gate oxide layer, two depletion layers are added, which can better protect the gate from being broken down by a large drain pulse and avoid degradation of the gate oxide layer; in addition, the polysilicon gate with a separated structure can reduce the gate capacitance, reduce the high-frequency power consumption of the device, and thus improve the performance of the device.

[0092] The above are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for preparing a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact, characterized in that: The silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact comprises a back drain metal layer, an n+ type silicon carbide substrate, and an n-type drift layer stacked in sequence from bottom to top; p-type base regions are respectively provided on both sides of the top of the n-type drift layer, a first p+ type source region and an n+ type source region are wrapped in the p-type base region, the first p+ type source region and the n+ type source region are arranged side by side and contact each other on the side, and the first p+ type source region is arranged close to the side of the n-type drift layer; two second p+ type source regions spaced apart along the extension direction of the p-type base region are provided between the two p-type base regions; a first source metal layer and a second source metal layer are respectively provided on both sides above the n-type drift layer, a first gate oxide layer, an ohmic metal layer and a second gate oxide layer are respectively provided side by side between the first source metal layer and the second source metal layer; the ohmic A metal layer is provided corresponding to the second p+ type source region and forms an ohmic contact with the second p+ type source region, a Schottky metal layer is provided between the two ohmic metal layers, the Schottky metal layer and the ohmic metal layer are provided at intervals, the Schottky metal layer is located above the n-type drift layer and forms a Schottky contact with the n-type drift layer; a first oxide layer is provided above the first gate oxide layer, a second oxide layer is provided above the second gate oxide layer, a first polysilicon gate is wrapped in the first oxide layer, and a second polysilicon gate is wrapped in the second oxide layer; a top metal layer is provided above the first source metal layer, the first oxide layer, the Schottky metal layer, the ohmic metal layer, the second oxide layer and the second source metal layer, and a passivation layer is provided above the top metal layer; the preparation method comprises: Step S1: epitaxially growing the n-type drift layer on the n+ type silicon carbide substrate; Step S2: forming the p-type base region on the n-type drift layer by sequentially performing a first masking layer growth process, a high-temperature oxidation process, a photolithography process, an etching process, and an ion implantation process; Step S3: growing a layer of low-pressure tetraethoxy silicate glass using the first masking layer, and forming the n+ type source region through a plasma dry isotropic etching process, a self-aligned process, and an ion implantation process; Step S4: removing the first masking layer by wet process, re-depositing the second masking layer of each layer, and forming a first p+ type source region and a second p+ type source region by photolithography, etching and ion implantation, wherein two second p+ type source regions are provided, and the two second p+ type source regions are spaced apart along the extension direction of the p-type base region; Step S5: growing the gate oxide layer through a carbon film growth and high temperature activation process and a nitrogen annealing process; Step S6: depositing saturated doped polysilicon on the gate oxide layer, and forming the first polysilicon gate and the second polysilicon gate separated from each other through photolithography and etching processes; Step S7: depositing a layer of borophosphosilicate glass on the first polysilicon gate, the second polysilicon gate, and the gate oxide layer; and forming the first oxide layer, the second oxide layer, and an ohmic filling region between the first oxide layer and the second oxide layer at positions corresponding to the second p+ type source regions, and forming an oxide region at positions corresponding to the positions between the two second p+ type source regions, through photolithography and etching processes. Step S8: forming the first source metal layer, the second source metal layer and the ohmic metal layer on both sides of the oxide region and the oxide layer by a metal deposition process and a rapid annealing process; Step S9: forming the first oxide layer, the second oxide layer and a Schottky filling region between the first oxide layer and the second oxide layer, which are separated from each other, in the oxide region by a dry etching process, depositing a layer of metal titanium in the Schottky filling region, and performing an annealing process to form the Schottky metal layer; Step S10: forming the top metal layer on the first source metal layer, the first oxide layer, the Schottky metal layer, the ohmic metal layer, the second oxide layer, and the second source metal layer by sputtering and etching, and depositing the passivation layer on the top metal layer; Step S11: forming the back drain metal layer on the back of the n+ type silicon carbide substrate by a metal deposition process and a laser annealing process, thereby completing the preparation of the silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact.

2. The method for preparing a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact according to claim 1, wherein: The depth of the p-type base region is 1.5 μm and the doping concentration is 1e17 cm -3 ~1e18 cm -3 The depth of the n+ type source region is 0.2 μm, and the doping concentration is greater than 1e19 cm -3 The depth of the first p+ type source region and the second p+ type source region is 3.0 μm, and the doping concentration is 1e18 cm -3 ~1e19 cm -3 .

3. The method for preparing a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact according to claim 1, characterized in that: The thickness of the Schottky metal layer and the ohmic metal layer are both 1000 angstroms.

4. The method for preparing a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact according to claim 1, characterized in that: The thickness of the first gate oxide layer and the second gate oxide layer is 500 angstroms; the thickness of the first polysilicon gate and the second polysilicon gate is 4000 angstroms.

5. The method for preparing a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact according to claim 1, wherein: The thickness of the first oxide layer and the second oxide layer are both 1.0 μm.

6. The method for preparing a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact according to claim 1, characterized in that: The passivation layer includes a plasma enhanced tetraethyl orthosilicate layer with a thickness of 6000 angstroms, a plasma enhanced silicon nitride layer with a thickness of 300 angstroms, and a polyimide film layer with a thickness of 7 μm.

7. The method for preparing a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact according to claim 1, characterized in that: The thickness of the first source metal layer and the second source metal layer are both 1000 angstroms.

8. The method for preparing a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact according to claim 1, characterized in that: The thickness of the top metal layer is 4 μm.

9. The method for preparing a silicon carbide MOSFET with gate-integrated Schottky contact and ohmic contact according to claim 1, characterized in that: The back drain metal layer includes a metal titanium layer with a thickness of 1000 angstroms, a metal nickel layer with a thickness of 2000 angstroms, and a metal silver layer with a thickness of 10 kiloangstroms.

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