A multi-time programmable device and a manufacturing method thereof

Abstract

The present application discloses a multi-time programmable device and a manufacturing method thereof, wherein the multi-time programmable device comprises: a semiconductor layer; a first active region located in the semiconductor layer, the first active region comprising a source region, a channel region and a drain region arranged in a first axis direction; an isolation structure located in the semiconductor layer; a floating gate, comprising a first floating gate and a second floating gate connected together, the first floating gate being located above the channel region and extending to above the isolation structure in a second axis direction, the second floating gate being located inside the isolation structure and arranged with the channel region in the second axis direction; a gate dielectric layer; a control gate; and an inter-gate dielectric layer located between the control gate and the first floating gate; the control gate is opposite to the first floating gate and the second floating gate, the control gate, the inter-gate dielectric layer between the control gate and the first floating gate and the first floating gate constitute a first capacitor, and the control gate, the isolation structure between the control gate and the second floating gate and the second floating gate constitute a second capacitor.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a multi-time programmable device and a manufacturing method thereof. Background Art

[0002] A Multi Time Programming (MTP) device is a type of storage device. Compared with a One Time Programming (OTP) device, its programming process is reversible and it can be programmed multiple times. It is suitable for use in a variety of occasions and has therefore been widely used.

[0003] In the related art, a multi-time programmable device can be implemented using a Flash structure. The Flash structure is to set a control gate on a floating gate, apply a forward voltage to the control gate to store electrons in the floating gate, and apply a reverse voltage to the control gate to erase the electrons in the floating gate, thereby realizing binary conversion between 0 and 1. However, the use of a Flash structure to implement a multi-time programmable device will result in a larger size of the multi-time programmable device, thereby limiting the use scenarios of the multi-time programmable device. Summary of the invention

[0004] In view of the above problems, the purpose of the present application is to provide a multi-time programmable device and a manufacturing method thereof, by setting a first floating gate and a second floating gate, the coupling coefficient between the control gate and the floating gate is increased without changing the size of the device.

[0005] According to one aspect of the present invention, there is provided a multi-time programmable device, comprising: a semiconductor layer; a first active region in the semiconductor layer, the first active region comprising a source region, a channel region and a drain region arranged in a first axis direction; an isolation structure in the semiconductor layer, adjacent to the first active region in the semiconductor layer; a floating gate, comprising a first floating gate and a second floating gate connected together, the first floating gate being located above the channel region and extending to above the isolation structure in a second axis direction, the second floating gate being located inside the isolation structure and arranged with the channel region in the second axis direction, the first axis direction and the second axis direction intersecting; a gate dielectric layer being located between the floating gate and the channel region; a control gate being located on the isolation structure and arranged with the floating gate in the second axis direction; and an inter-gate dielectric layer being located between the control gate and the first floating gate; the control gate being opposite to the first floating gate and the second floating gate respectively, the inter-gate dielectric layer between the control gate and the first floating gate and the first floating gate forming a first capacitor, and the isolation structure between the control gate and the second floating gate and the second floating gate forming a second capacitor.

[0006] Optionally, the gate dielectric layer is located above the channel region, and in the direction of the second axis, at least one side of the gate dielectric layer extends to above the isolation structure adjacent to the channel region, and the portion extending to above the isolation structure extends downward into the interior of the isolation structure; in the direction of the second axis, the width of the gate dielectric layer is greater than the width of the channel region; the isolation structure is formed in a trench, a lining dielectric layer is formed on the bottom and inner wall of the trench, a filling dielectric layer is formed inside the trench, and the filling dielectric layer and the lining dielectric layer together constitute the isolation dielectric of the isolation structure; the floating gate is isolated from the channel region via the gate dielectric layer and the lining dielectric layer.

[0007] Optionally, the isolation structure is formed in a trench, the gate dielectric layer covers the bottom, inner wall and surface of the channel region of the trench, a filling dielectric layer is formed inside the trench, the filling dielectric layer and the gate dielectric layer at the bottom and inner wall of the trench together constitute the isolation dielectric of the isolation structure; in the direction of the second axis, the width of the gate dielectric layer is greater than the width of the channel region; the floating gate is isolated from the channel region via the gate dielectric layer.

[0008] Optionally, there is a certain concentration gradient between the first floating gate and the second floating gate.

[0009] According to another aspect of the present invention, a method for manufacturing a multi-time programmable device is provided, comprising: forming a first active region, an isolation structure, a second floating gate and a gate dielectric layer; the first active region and the isolation structure are located in a semiconductor layer and are adjacent to each other, the first active region comprises a source formation region, a channel region and a drain formation region arranged in a first axis direction; the second floating gate is located inside the isolation structure and is arranged with the channel region in a second axis direction; the gate dielectric layer is located between the second floating gate and the channel region; forming a control gate and a first floating gate separated from each other, the control gate is located on the isolation structure, the first floating gate is located above the channel region, and The device extends in the second direction to above the isolation structure and is connected to the second floating gate located inside the isolation structure. The second floating gate and the first floating gate together constitute a floating gate. The gate dielectric layer is also located between the first floating gate and the channel region. An inter-gate dielectric layer is formed between the control gate and the first floating gate. A source region and a drain region are formed in the source formation region and the drain formation region, respectively. The control gate is respectively opposite to the first floating gate and the second floating gate. The inter-gate dielectric layer between the control gate and the first floating gate and the first floating gate constitute a first capacitor. The isolation structure between the control gate and the second floating gate and the second floating gate constitute a second capacitor.

[0010] Optionally, the step of forming the first active region, the isolation structure, the second floating gate and the gate dielectric layer includes: forming a first hard mask layer on the semiconductor layer, and etching the semiconductor layer through the first hard mask layer to form a trench in the semiconductor layer; forming a lining dielectric layer at the bottom and sidewalls of the trench, and forming a first filling dielectric layer in the trench; removing part of the first hard mask layer, and performing ion implantation on the semiconductor layer through the remaining first hard mask layer to form a first active region in the semiconductor layer, wherein the first filling dielectric layer defines the position of the first active region; the first active region includes a source formation region, a trench region and a gate dielectric layer arranged in the direction of the first axis; A channel region and a drain formation region are formed; a gate dielectric layer is formed, the gate dielectric layer is located on the channel region, extends to above the trench in the second direction, and the portion extending above the trench extends downward to the inside of the trench; the first filling dielectric layer in the trench is removed, the lining dielectric layer in the trench is retained, and a second floating gate is formed in the trench, the second floating gate is arranged with the channel region in the second axial direction, and the second floating gate is isolated from the channel region via the gate dielectric layer and the lining dielectric layer; a second filling dielectric layer is formed in the trench to form an isolation structure, the second filling dielectric layer and the lining dielectric layer together constitute the isolation dielectric of the isolation structure.

[0011] Optionally, the method for forming the gate dielectric layer includes: forming a first photoresist on the surface of the first filling dielectric layer and the remaining surface of the first hard mask layer; placing a mask on the first photoresist, patterning the first photoresist through the mask, the first photoresist exposing the first hard mask layer and a portion of the first filling dielectric layer adjacent to the first hard mask layer in the second axis direction; removing the exposed first hard mask layer and a portion of the first filling dielectric layer adjacent to the first hard mask layer in the second axis direction through the patterned first photoresist to form an opening; filling the opening with a dielectric layer to form a gate dielectric layer in the opening; the method for forming the second floating gate includes: removing the first filling dielectric layer in the trench, Retain the lining dielectric layer in the groove; fill the gate conductor layer in the groove; form a second hard mask layer on the surface of the gate dielectric layer and the gate conductor layer; form a second photoresist on the second hard mask layer; also place a mask on the second photoresist, and pattern the second photoresist through the mask, wherein the second photoresist is patterned using the mask for patterning the first photoresist, and during the process of patterning the second photoresist, an OVL adjustment is made in the second axis direction so that the formed second photoresist is located above the gate dielectric layer and extends to part of the gate conductor layer in the second direction; pattern the second hard mask layer through the second photoresist; and etch the gate conductor layer through the patterned second hard mask layer to form a second floating gate.

[0012] Optionally, the steps of forming a first active area, an isolation structure, a second floating gate and a gate dielectric layer include: forming a trench in a semiconductor layer; forming a gate dielectric layer at the bottom, sidewalls and surface of the trench; forming a second floating gate in the trench, the second floating gate and the channel area are arranged in the second axis direction; forming a filling dielectric layer in the trench to form an isolation structure, the filling dielectric layer and the gate dielectric layer in the trench together constitute an isolation dielectric of the isolation structure; forming a first active area adjacent to the trench in the semiconductor layer, the first active area including a source formation area, a channel area and a drain formation area arranged in the first axis direction, wherein the isolation structure defines the position of the first active area.

[0013] Optionally, the method for forming the second floating gate includes: forming a gate conductor layer in the groove, the top of the gate conductor layer is flush with the top of the gate dielectric layer; forming a patterned hard mask layer on the surfaces of the gate conductor layer and the gate dielectric layer, the patterned hard mask layer is located on the surface of the gate dielectric layer above the channel region, and extends in the second axis direction to the surface of the portion of the gate conductor layer adjacent to the channel region; etching the gate conductor layer through the patterned hard mask layer of the mask layer to form a second floating gate, the second floating gate is located in the groove and is arranged with the channel region in the second axis direction.

[0014] Optionally, ion implantation is performed on the semiconductor layer to form a first active area. During the process of forming the first active area, a first type of dopant is implanted into the semiconductor layer and the first floating gate. The first type of dopant and the second type of dopant in the second floating gate have a certain concentration gradient.

[0015] The unexpected technical effects of this application are:

[0016] The multi-time programmable device of the present application forms a floating gate transistor in the first axis direction and forms a control gate opposite to the floating gate in the second axis direction. Electrons are coupled to the floating gate by applying voltage to the control gate for MTP compilation. There is no need for voltage coupling through another MOS capacitor, thereby simplifying the device structure.

[0017] The floating gate of the present application includes a first floating gate and a second floating gate respectively opposite to the control gate, the intergate dielectric layer between the control gate and the first floating gate and the first floating gate constitute a first capacitor, and the isolation structure between the control gate and the second floating gate and the second floating gate constitute a second capacitor. By adding a second floating gate located inside the isolation structure, the coupling coefficient between the control gate and the floating gate is increased without changing the size of the device.

[0018] The control gate and the floating gate of the floating gate transistor in the multi-time programmable device are arranged in the horizontal direction. Compared with the arrangement in the vertical direction, the thickness of the multi-time programmable device of the present application is smaller, and the first floating gate and the control gate can be formed through the same process, thereby reducing the manufacturing cost of the multi-time programmable device; in addition, the multi-time programmable device of the present application forms a floating gate transistor in the first axis direction and forms a control gate opposite to the floating gate in the second axis direction. By reasonably arranging the positional relationship between the floating gate transistor and the control gate, the control gate and the floating gate transistor are relatively compact, so that the structure of the storage unit in the multi-time programmable device can be further reduced as the process platform is reduced, thereby realizing the miniaturization of the multi-time programmable device.

[0019] Furthermore, in the direction of the second axis, control gates are provided on both sides of the floating gate. The increase in the number of control gates enables the threshold voltage of the floating gate transistor to shift over a larger range, thereby allowing the multi-time programmable device to achieve different operating voltages within a larger range, which is conducive to realizing the multifunctional use of the product.

[0020] Furthermore, in the multi-time programmable device of the present application, the width of the gate dielectric layer of the floating gate transistor in the second axis direction is greater than the width of the channel region in the second axis direction, and the gate dielectric layer includes a portion extending into the interior of the isolation structure, so that the contact area between the floating gate and the gate dielectric layer is larger, and the writing speed of the multi-time programmable device is faster.

[0021] There is a certain concentration gradient between the first floating gate and the second floating gate of the present application to effectively prevent the floating gate from leaking electricity.

[0022] According to the method for manufacturing a multi-time programmable device of an embodiment of the present application, a second floating gate is formed simultaneously in the process of forming an isolation structure, and by adding a second floating gate located inside the isolation structure, the coupling coefficient between the control gate and the floating gate is increased without changing the size of the device. Furthermore, the present application forms the first floating gate and the control gate through the same process, so that the manufacturing cost of the multi-time programmable device is reduced.

[0023] In a preferred embodiment, since a second floating gate is provided, a liner dielectric layer is formed first and then a gate dielectric layer is formed. The liner dielectric layer and the gate dielectric layer together isolate the floating gate and the channel region to ensure that the second floating gate can be completely isolated from the channel region.

[0024] In a preferred embodiment, the gate dielectric layer and the second floating gate are formed using the same mask, thereby avoiding re-masking.

[0025] In a preferred embodiment, a gate dielectric layer is formed at the bottom, sidewalls and surface of the channel region of the trench through one process, thereby ensuring that the second floating gate is completely isolated from the channel region and simplifying the process steps.

[0026] In a preferred embodiment, a dopant of a first doping type is injected into the semiconductor layer to form a first active region, and the first active region has a first doping type. In the process of forming the first active region, a dopant of the first doping type is injected into the second floating gate at the same time, and the dopant of the first doping type and the dopant of the second doping type in the second floating gate are reduced to reduce the doping concentration of the second floating gate, so that the second floating gate and the first floating gate formed subsequently have a certain concentration gradient, which effectively prevents leakage of the floating gate without adding additional steps.

[0027] Furthermore, the manufacturing method of the above-mentioned multi-time programmable device also includes: growing an oxide film layer included in the inter-gate dielectric layer on the side walls of the formed floating gate and the control gate, and there is a gap between the oxide film layer grown on the side walls of the floating gate and the oxide film layer grown on the side walls of the control gate, and then filling nitride in the gap to form a nitride film layer included in the inter-gate dielectric layer, so that by reasonably controlling the thickness of the oxide film layer grown on the side walls of the floating gate and the oxide film layer grown on the side walls of the control gate and using existing processes, an oxide-nitride-oxide structure serving as an inter-gate dielectric layer between the floating gate and the control gate can be manufactured, without the need for additional masks and related processes, thereby reducing the manufacturing cost of the multi-time programmable device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0029] Figure 1a A schematic top view of a multi-time programmable device provided by the first embodiment of the present application is shown;

[0030] Figure 1b A schematic three-dimensional diagram of a multi-time programmable device provided by the first embodiment of the present application is shown;

[0031] Figure 1c Shows Figure 1a Cross-sectional view along AA direction;

[0032] Figure 1d Shows Figure 1a Cross-section along direction BB;

[0033] Figure 2a to Figure 2z 1 is a schematic diagram of the steps of an exemplary method for manufacturing a multi-time programmable device provided in the first embodiment of the present application, wherein:

[0034] Figure 2a A schematic diagram showing a first embodiment of the present application in which a pad oxide layer is formed on a substrate and a deep well region is formed in the substrate;

[0035] Figure 2bA schematic diagram showing a first embodiment of the present application in which a nitride layer is formed on the surface of the pad oxide layer;

[0036] Figure 2c A schematic diagram showing the formation of a groove in the first embodiment of the present application is shown;

[0037] Figure 2d A schematic diagram showing a first embodiment of the present application for forming a lining dielectric layer;

[0038] Figure 2e A schematic diagram showing a first filling dielectric layer formed in a trench in a first embodiment of the present application is shown;

[0039] Figure 2f A schematic diagram showing a first hard mask layer in which a portion is removed in the first embodiment of the present application;

[0040] Figure 2g A schematic diagram showing a first active region and a second active region formed in a semiconductor layer according to a first embodiment of the present application;

[0041] Figure 2h A schematic diagram showing a first photoresist patterned in the first embodiment of the present application is shown;

[0042] Figure 2i A schematic diagram showing a first embodiment of the present application for forming an opening that exposes a channel region and a portion of a sidewall of a trench adjacent to the channel region;

[0043] Figure 2j A schematic diagram showing the formation of a gate dielectric layer in the first embodiment of the present application is shown;

[0044] Figure 2k A schematic diagram showing a first embodiment of the present application in which a third hard mask layer is formed on the surfaces of the gate dielectric layer and the first filling dielectric layer;

[0045] Figure 2l A schematic diagram showing a first embodiment of the present application in which the first filling dielectric layer is removed and the lining dielectric layer is retained;

[0046] Figure 2m A schematic diagram showing the removal of the third hard mask layer in the first embodiment of the present application is shown;

[0047] Figure 2n A schematic diagram showing a first embodiment of the present application for forming a gate conductor layer in a trench;

[0048] Figure 2o A schematic diagram showing a first embodiment of the present application in which a second hard mask layer is formed on the surfaces of the gate dielectric layer and the gate conductor layer;

[0049] Figure 2p A schematic diagram showing the formation of a second floating gate in the first embodiment of the present application is shown;

[0050] Figure 2q A schematic diagram showing the removal of the second hard mask layer in the first embodiment of the present application is shown;

[0051] Figure 2r A schematic diagram showing a first embodiment of the present application to form an isolation structure;

[0052] Figure 2s A schematic diagram showing a first embodiment of the present application in which a gate conductor layer and a fourth hard mask layer are formed on the surfaces of the gate dielectric layer, the second floating gate and the isolation structure;

[0053] Figure 2t A schematic diagram showing the formation of a first floating gate and a control gate in the first embodiment of the present application is shown;

[0054] Figure 2u A schematic diagram showing the formation of an oxide film layer in the first embodiment of the present application is shown;

[0055] Figure 2v A schematic diagram showing the formation of a nitride film layer in the first embodiment of the present application is shown;

[0056] Figure 2w A schematic diagram showing the formation of a contact layer in the first embodiment of the present application is shown;

[0057] Figure 2x A schematic diagram showing the formation of a fifth hard mask layer in the first embodiment of the present application is shown;

[0058] Figure 2y A schematic diagram showing the formation of contact holes in the first embodiment of the present application is shown;

[0059] Figure 2z A schematic diagram showing the formation of a connection channel in the first embodiment of the present application is shown;

[0060] Figure 3a A schematic top view of a multi-time programmable device provided in a second embodiment of the present application is shown;

[0061] Figure 3b Shows Figure 3a Cross-sectional view along AA direction;

[0062] Figures 4a to 4k 1 is a schematic diagram of the steps of an exemplary method for manufacturing a multi-time programmable device provided in the second embodiment of the present application, wherein:

[0063] Figure 4a A schematic diagram showing a second embodiment of the present application in which a pad oxide layer is formed on a substrate and a deep well region is formed in the substrate;

[0064] Figure 4b A schematic diagram showing a second embodiment of the present application in which a nitride layer is formed on the surface of the pad oxide layer;

[0065] Figure 4cA schematic diagram showing the formation of a groove in the second embodiment of the present application is shown;

[0066] Figure 4d A schematic diagram showing the removal of the first hard mask layer according to the second embodiment of the present application is shown;

[0067] Figure 4e A schematic diagram showing a second embodiment of the present application in which a gate dielectric layer is formed in a trench at the bottom, sidewalls and surface of a semiconductor layer of the trench;

[0068] Figure 4f A schematic diagram showing the formation of a gate conductor layer in the second embodiment of the present application is shown;

[0069] Figure 4g A schematic diagram showing a second hard mask layer formed on the surfaces of the gate dielectric layer and the gate conductor layer in the second embodiment of the present application is shown;

[0070] Figure 4h A schematic diagram showing the formation of a second floating gate in the second embodiment of the present application is shown;

[0071] Figure 4i A schematic diagram showing the removal of the second hard mask layer in the second embodiment of the present application is shown;

[0072] Figure 4j A schematic diagram showing a second embodiment of the present application for forming an isolation structure;

[0073] Figure 4k A schematic diagram showing the formation of the first active region and the second active region according to the second embodiment of the present application is shown. DETAILED DESCRIPTION

[0074] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0075] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" another layer or region.

[0076] If it is intended to describe a situation where it is directly on another layer or another area, this article will use the expression “directly on…” or “on… and adjacent to…”.

[0077] Unless otherwise specified below, the various parts of the semiconductor device can be composed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as gallium arsenide (GaAs), gallium nitride (GaN), etc., IV-IV semiconductors, such as silicon carbide (SiC), etc., II-VI compound semiconductors, such as cadmium sulfide (CdS), cadmium telluride (CdTe), etc., and IV semiconductors, such as silicon (Si), germanium (Ge), etc. The gate conductor can be formed of various materials that can conduct electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric may be made of SiO2 or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. Furthermore, the gate dielectric may be formed not only of materials known to those skilled in the art, but also of materials to be developed for the gate dielectric in the future.

[0078] This application may be presented in a variety of forms, some examples of which are described below.

[0079] Figure 1a FIG. 4 shows a schematic top view of a multi-time programmable device provided by the first embodiment of the present application, Figure 1b A schematic three-dimensional diagram of a multi-time programmable device provided by the first embodiment of the present application is shown. Figure 1c Shows Figure 1a Cross-sectional view along AA direction, Figure 1d Shows Figure 1a Cross-sectional view along the BB direction. Figure 1a and Figure 1b The structural layout of the multi-time programmable device 100 on the XY plane is simply illustrated, and thus the inter-gate dielectric layer between the control gate CG and the floating gate FG is not shown.

[0080] like Figure 1a to Figure 1d As shown, the semiconductor device 100 includes a semiconductor layer 101 and a first active region 1051 and an isolation structure 103 formed in the semiconductor layer 101 .

[0081] The semiconductor layer 101 may be selected from any one of a semiconductor substrate, a doped well region, a doped epitaxial semiconductor layer or a combination thereof. In this embodiment, the semiconductor layer 101 includes a substrate 1011 and a deep well region 1012 located on the substrate 1011. The first active region 1051 and the isolation structure 103 are located in the semiconductor layer 101, specifically in the well region 1012. The first active region 1051 and the isolation structure 103 extend from the surface of the semiconductor layer 101 (deep well region 1012) to the inside thereof, respectively, and terminate inside the semiconductor layer 101 (deep well region 1012).

[0082] The substrate 111 and the first active region 1051 have a first doping type, and the deep well region 1012 has a second doping type. In one embodiment, the substrate 111 is a P-type substrate, the deep well region 1012 is a deep N-well, and the first active region 1051 is a P-well.

[0083] The first active region 1051 extends along a first direction (eg, the direction indicated by the X axis of the coordinate system in the figure), and the isolation structure 103 is adjacent to the first active region 1051. The first axis direction intersects with the second axis direction, and preferably, the first axis direction and the second axis direction are perpendicular to each other.

[0084] See also Figure 1a , Figure 1b and Figure 1d , the semiconductor device 100 includes a floating gate transistor formed in a first active region 1051, and the floating gate transistor includes a source region S, a drain region D, and a gate stack located between the source region S and the drain region D in the first active region 1051. The source region S and the drain region D are doped regions in the first active region 1051. For example, for an N-type MOSFET, the source region S and the drain region D are N-type doped; for a P-type MOSFET, the source region S and the drain region D are P-type doped. In this embodiment, the floating gate transistor is, for example, an N-type MOSFET, and the source region S and the drain region D are, for example, N-type doped. The source region S and the drain region D are arranged in a first direction (for example, the direction indicated by the X-axis of the coordinate system in the figure), and the first active region 1051 between the source region S and the drain region D forms a channel region 1051a. The gate stack of the floating gate transistor 150 includes a gate dielectric layer GOX and a floating gate FG which are stacked, wherein the gate dielectric layer GOX is sandwiched between the first active region 1051 (channel region) and the floating gate FG.

[0085] See also Figure 1cThe floating gate FG includes a first floating gate FG-1 and a second floating gate FG-2. The first floating gate FG-1 is located above the channel region 1051a and extends above the isolation structure 103 in the second axis direction (for example, the direction indicated by the Y axis of the coordinate system in the figure); the second floating gate FG-2 is located in the isolation structure 103 and is aligned with the channel region 1051a in the second axis direction. The top of the second floating gate FG-2 is connected to the bottom of the first floating gate FG-1, and the first floating gate FG-1 and the second floating gate FG-2 jointly surround the first active region 1051 (channel region).

[0086] The gate dielectric layer GOX is located between the floating gate FG and the channel region 1051a. Specifically, the gate dielectric layer GOX is located above the channel region 1051a. In the direction of the second axis (for example, the direction indicated by the Y axis of the coordinate system in the figure), the first side and / or the second side (for example, the left side and / or the right side in the figure) of the gate dielectric layer GOX extends above the isolation structure 103, and the portion extending above the isolation structure 103 extends downward into the interior of the isolation structure 103, and is adjacent to the channel region 1051a in the direction of the second axis.

[0087] The floating gate FG is isolated from the channel region 1051 a via the gate dielectric layer GOX and a portion of the isolation dielectric of the isolation structure 103 .

[0088] The semiconductor device 100 further includes a control gate CG, which is located on the isolation structure 103, and the top of the control gate CG is flush with the top of the first floating gate FG-1. The control gate CG is isolated from the first floating gate FG-1 via the inter-gate dielectric layer 110, and the control gate CG is isolated from the second floating gate FG-2 via the isolation structure 103. The control gate CG is opposite to the first floating gate FG-1 and the second floating gate FG-2, and the control gate CG, the inter-gate dielectric layer 110 and the first floating gate FG-1 constitute a first capacitor, and the control gate CG, the isolation structure 103 and the second floating gate FG-2 constitute a second capacitor. Due to the provision of the second floating gate FG-2, the relative area of ​​the control gate CG and the floating gate FG is increased, thereby increasing the coupling coefficient between the control gate and the floating gate.

[0089] The control gate CG and the floating gate FG are both gate conductor layers, for example, made of doped polysilicon. The gate dielectric layer GOX is made of silicon oxide, for example. The inter-gate dielectric layer 110 is, for example, an oxide-nitride-oxide (ONO) structure, and the inter-gate dielectric layer 110 is adjacent to the floating gate FG as one of the oxide film layers, and the inter-gate dielectric layer 110 is adjacent to the control gate CG as another of the oxide film layers.

[0090] In this embodiment, when a voltage is applied to the control gate CG, a certain coupling voltage is generated on the floating gate FG, so that the writing, reading and erasing of the multi-time programmable device 100 can be achieved by adjusting the source voltage Vs on the source region S, the drain voltage Vd on the drain region D and the control voltage Vg on the control gate CG.

[0091] The semiconductor device 100 further includes a second active region 1052 located in the semiconductor layer 101 (deep well region 1012), and the doping type of the second active region 1052 is the same as the doping type of the first active region 1051. The second active region 1052 is isolated from the first active region 1051 via an isolation structure 103. The second active region 1052 is used as a lead-out structure of the substrate for receiving a substrate voltage.

[0092] The multi-time programmable device 100 further includes the following multiple connection channels: a first connection channel electrically connected to the source region S for transmitting a source voltage Vs, a second connection channel electrically connected to the drain region D for transmitting a drain voltage Vd, a third connection channel electrically connected to the control gate CG for the control gate CG to receive a control voltage Vg, and a fourth connection channel electrically connected to the lead-out structure B for the lead-out structure B to receive a substrate voltage Vb. In this embodiment, the source voltage Vs, the drain voltage Vd, the control voltage Vg, and the substrate voltage Vb are provided to the multi-time programmable device 100 from the same side of the multi-time programmable device 100.

[0093] When the multi-time programmable device 100 is working, when a strong voltage is applied to the control gate CG and the drain region D, the floating gate FG will generate a coupling voltage to form a strong electric field, so that the floating gate FG will absorb a large number of electrons based on the hot carrier injection effect. Since there is a gate dielectric layer GOX between the floating gate FG and the channel region 1051a, the electrons are bound in the floating gate FG and cannot flow out freely, so the threshold voltage (Threshold Voltage, referred to as VT) of the floating gate transistor shifts. In this case, applying the initial turn-on voltage to the control gate CG cannot turn on the floating gate transistor, so no current will pass through the M floating gate transistor, that is, the output of binary 0 is realized at the initial turn-on voltage. When the floating gate FG does not store electrons, the threshold voltage of the floating gate transistor does not shift, the initial turn-on voltage can turn on the floating gate transistor, and the floating gate transistor has current passing through, that is, the output of binary 1 is realized at the initial turn-on voltage. Therefore, by controlling the floating gate FG to store electrons and controlling the floating gate FG to be erased, the data stored in the storage unit corresponding to the floating gate FG in the multi-time programmable device 100 can be converted between binary 1 and binary 0, thereby also realizing multiple compilations of the storage unit corresponding to the floating gate FG.

[0094] Table 1

[0095] Logo Vg Vd Vs Vb PGM 6.3V 3.7V 0V 0V Read PGM 0-10V 0.9V 0V 0V ERS -5.4V Floating 7.7V 7.7V Read ERS 0-4V 0.9V 0V 0V

[0096] Table 1 shows a plurality of exemplary operating voltage groups of the multi-time programmable device 100, wherein the MOSFET device formed in the well region of the multi-time programmable device 100 is an N-type MOSFET device. Referring to Table 1, the plurality of exemplary operating voltage groups are as follows:

[0097] (1) The operating voltage group marked as PGM is the operating voltage group when the floating gate FG stores electrons, that is, when the control voltage Vg=6.3V, the drain voltage Vd=3.7V, and the source voltage Vs and the substrate voltage Vb are each 0V, the floating gate FG will form a very strong electric field so that the floating gate FG absorbs a large number of electrons. The threshold voltage of the floating gate transistor absorbed by the floating gate FG shifts accordingly. For example, the initial turn-on voltage is 2.2V, and the threshold voltage after the shift increases to be greater than the initial turn-on voltage;

[0098] (2) The operating voltage group identified as Read PGM is an operating voltage group for reading after the operating voltage group identified as PGM causes the floating gate FG to store electrons, that is, when the drain voltage Vd=0.9V and the source voltage Vs and the substrate voltage Vb are each 0V, a control voltage Vg of 0-10V is applied to the control gate CG to scan and determine the threshold voltage of the floating gate transistor after the shift. For example, when the control voltage Vg increases from 0V to 3V, the floating gate transistor is turned on, thereby determining that the threshold voltage of the floating gate transistor after the shift is 3V;

[0099] (3) The operating voltage group marked as ERS is the operating voltage group for erasing the electrons stored in the floating gate FG, that is, by setting the control voltage Vg=-5.4V and making the drain floating (Floating) and setting the source voltage Vs and the substrate voltage Vb to 7.7V respectively, an electric field in the opposite direction to that when the floating gate FG stores electrons is formed, so that the electrons stored in the floating gate FG are separated from the floating gate FG, thereby achieving erasure of the electrons stored in the floating gate FG;

[0100] (4) The operating voltage group identified as Read ERS is an operating voltage group that is read after the operating voltage group identified as ERS performs an erase operation, that is, when the drain voltage Vd=0.9V and the source voltage Vs and the substrate voltage Vb are each 0V, a control voltage Vg of 0-4V is applied to the control gate CG for scanning to determine the turn-on voltage of the floating gate transistor at this time. For example, when the control voltage Vg increases from 0V to the initial turn-on voltage, the floating gate transistor is turned on, and the turn-on voltage of the floating gate transistor at this time is determined to be the initial turn-on voltage, thereby also determining that the threshold voltage of the floating gate transistor is restored.

[0101] It should be noted that the non-suspended and non-0V voltage values ​​in the multiple operating voltage groups in Table 1 are only exemplary voltage values ​​and do not represent limitations on the embodiments of the present application. The initial turn-on voltage as the working voltage is pre-associated with the non-suspended and non-0V voltage values ​​in the above multiple operating voltage groups. After adjusting the non-suspended and non-0V voltage values ​​in the above multiple operating voltage groups, the pre-set initial turn-on voltage should also be reset according to the requirements. For example, the control voltage Vg and the drain voltage Vd in the operating voltage group identified as PGM are both increased so that the threshold voltage of the MOSFET device is shifted to 5V, and the control voltage Vg in the operating voltage group identified as ERS is also increased so that the floating gate FG still has some electrons after the erase operation so that the threshold voltage can only be restored to 4V. In this case, the working voltage of the multi-time programmable device 100 is no longer the initial turn-on voltage of 2.2V, but a voltage greater than 4V and less than 5V. At this time, it is necessary to erase the pre-set initial turn-on voltage of 2.2V and then write a voltage value between 4V and 5V as the reset initial turn-on voltage. It should be understood that the operating voltage is determined by the operating requirements of the multi-time programmable device 100 , and the non-floating and non-0V voltage values ​​in the plurality of operating voltage groups are also determined by the operating requirements of the multi-time programmable device 100 .

[0102] In addition, the control voltage Vg shown in Table 1 is for the case where the multi-time programmable device 100 includes two control gates CG, that is, Figure 1a to Figure 1c As shown, in the direction of the second axis, the control gate CG is located on both sides of the floating gate FG, and the control gates CG on both sides of the floating gate FG are applied with a control voltage Vg, so that the threshold voltage of the MOSFET device formed in the well region is shifted to a larger range due to the floating gate FG being able to generate a larger coupling voltage and absorb more electrons, and since the threshold voltage after the shift is the upper limit of the operating voltage of the multi-time programmable device 100, the multi-time programmable device 100 allows different operating voltages to be realized in a larger range, which is conducive to realizing the multi-functional use of the product.

[0103] It should be understood that, in other embodiments, in order to meet other parameter requirements of the device (such as the size requirement of the device), the control gate CG may also be provided on one side of the floating gate FG.

[0104] The multi-time programmable device 100 provided in the embodiment of the present application can apply a substrate voltage Vb directly to the substrate, and then apply a strong voltage to the control gate CG and the drain region D, so that the floating gate FG can generate a strong coupling voltage through the inter-gate dielectric layer between the control gate CG and the floating gate FG, and does not need to be coupled through another MOS capacitor. Therefore, there is no need to add a photolithography mask to form another MOS capacitor, thereby reducing the manufacturing cost of the multi-time programmable device.

[0105] Corresponding to the multi-time programmable device provided in the above embodiments, the present application further provides a method for manufacturing the multi-time programmable device of the first embodiment, the manufacturing method comprising:

[0106] Step S110, forming a first active region, an isolation structure, a second floating gate and a gate dielectric layer; the first active region and the isolation structure are located in the semiconductor layer and are adjacent to each other, the first active region includes a source formation region, a channel region and a drain formation region arranged in a first axis direction; the second floating gate is located inside the isolation structure and is arranged with the channel region in the second axis direction; the gate dielectric layer is located between the second floating gate and the channel region;

[0107] Step S120, forming a control gate and a first floating gate separated from each other, wherein the control gate is located on the isolation structure, the first floating gate is located above the channel region and extends in a second direction to above the isolation structure, and the gate dielectric layer is also located between the first floating gate and the channel region;

[0108] Step S130, forming an inter-gate dielectric layer between the control gate and the first floating gate; and

[0109] Step S140, forming a source region and a drain region in the source formation region and the drain formation region respectively.

[0110] Figure 2a to Figure 2z 1 is a schematic diagram of each step of an exemplary method for manufacturing a multi-time programmable device provided in the first embodiment of the present application, wherein the MOSFET device formed by the well region of the exemplary multi-time programmable device is an N-type MOSFET device. In other examples, if the MOSFET device formed by the well region of the multi-time programmable device is a P-type MOSFET device, the manufacturing of the multi-time programmable device can be achieved by replacing the N-type doping in the following description with the P-type doping and replacing the P-type doping in the following description with the N-type doping.

[0111] Combine the following Figure 2a to Figure 2z The manufacturing method of the multi-time programmable device provided in the embodiment of the present application is described in detail.

[0112] See also Figure 2a to Figure 2p In step S110, a first active region, an isolation structure, a second floating gate and a gate dielectric layer are formed.

[0113] Have, such as Figure 2a and Figure 2bAs shown, a semiconductor layer 101 is formed, and a first hard mask layer 102 is formed on the semiconductor layer 101. In this embodiment, the semiconductor layer 101 includes a substrate 1011 and a deep well region 1012 located in the substrate 1011, and the first hard mask layer 102 includes a stacked pad oxide layer 1021 (Pad Oxide) and a nitride layer 1022.

[0114] Specific as Figure 2a As shown, a pad oxide is grown on the surface of the substrate 1011 to form a pad oxide layer 1021, and then a deep well region 1012 is formed by ion implantation into the substrate 1011 below the pad oxide layer 1021. The substrate 1011 has a first doping type, and the deep well region 1012 has a second doping type. The first doping type is, for example, P-type doping, and the second doping type is, for example, N-type doping. The substrate 1011 is, for example, P-type doping, and the deep well region 1012 is, for example, N-type doping.

[0115] like Figure 2b As shown, a nitride layer 1022 is formed on the surface of the pad oxide layer 1021 , and the pad oxide layer 1021 and the nitride layer 1022 constitute a first hard mask layer 102 .

[0116] Next, a photoresist PR1 is formed on the first hard mask layer 102 , and the mask PR1 layer is patterned by a photolithography process to form an opening in the photoresist PR1 , thereby forming a patterned photoresist PR1 .

[0117] like Figure 2c As shown, the first hard mask layer 102 and a portion of the semiconductor layer 101 are etched through the opening of the photoresist PR1 to form a trench 1031. After the trench 1031 is formed, the photoresist PR1 is removed, and only the portion of the first hard mask layer 102 originally covered by the patterned photoresist PR1 remains.

[0118] like Figure 2d As shown, a thinner liner dielectric layer 1032a is formed on the inner wall of the groove 1031. The liner dielectric layer 1032a is, for example, a liner oxide. For example, the liner dielectric layer 1032a is formed by an oxidation process to repair the damage on the edge surface of the groove caused by the above etching process and relieve the stress of the first filling dielectric layer 1032b formed by the subsequent deposition process, thereby improving the electrical properties and yield of the device.

[0119] like Figure 2e As shown, a first filling dielectric layer 1032 b is formed in the trench 1031 .

[0120] In this step, for example, a deposition process is used to form the first filling dielectric layer 1032 b . The first filling dielectric layer 1032 b and the liner dielectric layer 1032 a together fill the trench 1031 , and the first filling dielectric layer 1032 b covers the surface of the semiconductor layer 110 .

[0121] Next, for example, the first filling dielectric layer 1032 b is planarized by using a CMP (Chemical Mechanical Plamarization) process, so that the surface of the first filling dielectric layer 1032 b is flush with the surface of the first hard mask layer 102 (nitride layer 1022 ).

[0122] The first filling dielectric layer 1032 b is, for example, tetraethoxysilane (TEOS for short). Since tetraethoxysilane reacts with oxygen to generate silicon dioxide and volatile ethanol, the trench will be filled with silicon dioxide.

[0123] like Figure 2f As shown, part of the first hard mask layer 102 is removed, specifically, the nitride layer 1022 of the first hard mask layer 102 is removed.

[0124] In this step, the nitride layer 1022 is removed by wet etching, for example, using phosphoric acid as the etching solution. Then, the first filling dielectric layer 1032 b is planarized by CMP (Chemical Mechanical Plamarization) process, so that the surface of the first filling dielectric layer 1032 b is flush with the surface of the pad oxide layer 1021 .

[0125] like Figure 2g As shown, ion implantation is performed on the semiconductor layer 101 through the remaining first hard mask layer 102 to form a first active region 1051 and a second active region 1052 (not shown in the figure) in the semiconductor layer 101, wherein the first active region 1051 extends along a first axis direction (e.g., X-axis direction), and the second active region 1052 extends along a second axis direction (e.g., Y-axis direction), and the first active region 1051 and the second active region 1052 are separated from each other and isolated by the trench 1031.

[0126] In this step, for example, an ion implantation (IMP) process is used to implant doping ions into the semiconductor layer 101 to form the first active region 1052 and the second active region 152 in the semiconductor layer 101. The first filling dielectric layer 1032b in the trench 1031 defines the positions of the first active region 1051 and the second active region 1052.

[0127] The first active region 1051 includes a source formation region, a channel region 1051a and a drain formation region arranged in the first axis direction. The source formation region and the drain formation region form a source region S and a drain region D respectively in subsequent steps.

[0128] like Figure 2h to Figure 2j As shown, a gate dielectric layer GOX is formed.

[0129] Specifically, Figure 2h As shown, a patterned first photoresist PR2 is formed.

[0130] In this step, a first photoresist PR2 is formed on the surface of the first filling dielectric layer 1032b and the remaining first hard mask layer 102 (pad oxide layer 1021), a mask is placed on the surface of the first photoresist PR2, and the first photoresist PR2 is patterned through the mask to form an opening in the photoresist PR2. The opening exposes the remaining first hard mask layer 102 (pad oxide layer 1021) above the channel region 1051a, and a portion of the first filling dielectric layer 1032b adjacent to the first hard mask layer 102 (pad oxide layer 1021) in the second axis direction (e.g., the Y axis direction).

[0131] like Figure 2i As shown, the first filling dielectric layer 1032b and the first hard mask layer 102 (oxygen pad layer 1021) exposed by etching through the patterned first photoresist PR2 are removed to remove the first hard mask layer 102 (oxygen pad layer 1021) above the channel region 1051a and a portion of the first filling dielectric layer 1032b adjacent to the first hard mask layer 102 (oxygen pad layer 1021), thereby forming an opening 1041 exposing the channel region 1051a and a portion of the sidewall of the trench 1031 adjacent to the channel region 1051a.

[0132] After the opening 1041 is formed, the photoresist PR2 is removed.

[0133] like Figure 2j As shown, a gate dielectric layer GOX is formed.

[0134] In this step, for example, a deposition process is used to fill the dielectric layer in the opening 1041. The dielectric layer covers the surface of the channel region 1051a and covers part of the sidewall of the trench 1031 adjacent to the channel region 1051a. The dielectric layer is, for example, an oxide layer. In other embodiments, an ISSG (In Situ Steam Generation) process may be used to fill the oxide layer in the opening.

[0135] Next, for example, the oxide layer is planarized by using a CMP (Chemical Mechanical Plamarization) process so that the top of the oxide layer is flush with the top of the first filling dielectric layer 1032b, thereby forming a gate dielectric layer GOX. The gate dielectric layer GOX surrounds the channel region 1051a, specifically, the gate dielectric layer GOX covers the surface of the channel region 1051a and at least part of the sidewall of the trench 1031 adjacent to the channel region 1051a, that is, in the second axis direction, the width W1 of the gate dielectric layer GOX is greater than the width W2 of the channel region 1051a.

[0136] like Figure 2k to Figure 2p As shown, a second floating gate FG-2 is formed.

[0137] Specifically, Figure 2k As shown, a third hard mask layer 1061 is formed on the surfaces of the gate dielectric layer GOX and the first filling dielectric layer 1032 b.

[0138] In this step, for example, a deposition process is used to form a third hard mask layer 1061 on the surface of the gate dielectric layer GOX and the first filling dielectric layer 1032b. Next, a patterned photoresist PR3 is formed on the surface of the third hard mask layer 1061, for example, by a photolithography process, and the patterned photoresist PR3 is located above the gate dielectric layer GOX, and the third hard mask layer 1061 is etched through the patterned photoresist PR3 to remove part of the third hard mask layer 1061, so that only the part of the third hard mask layer 1061 located above the gate dielectric layer GOX is retained. The third hard mask layer 1061 is, for example, a nitride layer.

[0139] like Figure 2l As shown, the first filling dielectric layer 1032 b is etched through the third hard mask layer 1061 to remove the first filling dielectric layer 1032 b and retain the liner dielectric layer 1032 a. The remaining liner dielectric layer 1032 a and the oxide layer 104 a together cover the inner wall of the trench 1031 .

[0140] like Figure 2m As shown, the third hard mask layer 1061 is removed.

[0141] In this step, for example, wet etching is used to remove the third hard mask layer 1061 , and the wet etching solution is, for example, a phosphoric acid solution.

[0142] like Figure 2n As shown, a gate conductor layer 1071 is formed in the trench 1031 .

[0143] In this step, a gate conductor layer 1071 filling the trench 1031 is formed by, for example, a deposition process, and then, for example, a CMP (Chemical Mechanical Plamarization) process is used to planarize the gate conductor layer 1071 so that the top of the gate conductor layer 1071 is flush with the top of the gate dielectric layer GOX. The gate conductor layer 1071 is, for example, a polysilicon layer, preferably doped polysilicon of the second doping type.

[0144] like Figure 2o As shown, a second hard mask layer 1062 is formed on the surfaces of the gate dielectric layer GOX and the gate conductor layer 1071 .

[0145] In this step, for example, a deposition process is used to form a second hard mask layer 1062 on the surfaces of the gate dielectric layer GOX and the polysilicon layer.

[0146] A second photoresist PR4 is formed on the surface of the second hard mask layer 1062, and a mask is placed on the second photoresist PR4, and the second photoresist PR4 is patterned through the mask. In the process of patterning the second photoresist PR4, the mask for patterning the first photoresist PR3 is used, and no additional plate making is required. Specifically, in the process of patterning the second photoresist PR4, the OVL (Overlapping Value) is adjusted in the second axis direction, and the OVL is first adjusted to the left for a certain width (for example, 5nm) for exposure, and then adjusted to the right for a certain width (for example, 5nm) for exposure. The patterned photoresist PR4 is located above the gate dielectric layer GOX, and extends in the second axis direction to above a portion of the gate conductor layer 107 adjacent to the gate dielectric layer GOX.

[0147] Then, the second hard mask layer 1062 is etched through the patterned second photoresist PR4 to remove a portion of the second hard mask layer 1062 . The remaining second hard mask layer 1062 is located above the gate dielectric layer GOX and above a portion of the gate conductor layer 107 adjacent to the gate dielectric layer GOX.

[0148] like Figure 2p As shown, the gate conductor layer 1071 is etched through the second hard mask layer 1062 to remove part of the gate conductor layer 1071. The remaining gate conductor layer 1071 forms a second floating gate FG-2. The second floating gate FG-2 is adjacent to the gate dielectric layer GOX in the second axis direction, and is isolated from the sidewall of the trench 1031 through the gate dielectric layer GOX and the remaining lining dielectric layer 1032a on the sidewall of the trench 1031.

[0149] like Figure 2q As shown, the second hard mask layer 1062 is removed.

[0150] In this step, for example, wet etching is used to remove the second hard mask layer 1062 , and the wet etching solution is, for example, a phosphoric acid solution.

[0151] like Figure 2r As shown, a second filling dielectric layer 1032 c is formed in the trench 1031 to form an isolation structure 103 .

[0152] In this step, for example, a deposition process is used to form a second filling dielectric layer 1032c, the second filling dielectric layer 1032c fills the trench 1031, and covers the surface of the gate dielectric layer GOX and the second floating gate FG-2. Then, for example, a CMP (Chemical Mechanical Plamarization) process is used to flatten the second filling dielectric layer 1032c, so that the surface of the second filling dielectric layer 1032c is flush with the surface of the gate dielectric layer GOX and the second floating gate FG-2. The second filling dielectric layer 1032c is, for example, tetraethoxysilane (TEOS for short). Since tetraethoxysilane reacts with oxygen to generate silicon dioxide and volatile ethanol, silicon dioxide is filled in the trench. The second filling dielectric layer 1032c and the lining dielectric layer 1032a together constitute an isolation dielectric, and the isolation dielectric and the trench 1031 together constitute an isolation structure 103.

[0153] like Figure 2s to Figure 2t In step S120, a control gate and a first floating gate separated from each other are formed.

[0154] Specifically, Figure 2s As shown, a gate conductor layer 1072 and a fourth hard mask layer 108 are formed on the surfaces of the gate dielectric layer GOX, the second floating gate FG- 2 and the isolation structure 103 .

[0155] The gate conductor layer 1072 covers the gate dielectric layer GOX, the second floating gate FG-2 and the isolation structure 103; the fourth hard mask layer 108 covers the gate conductor layer 1072, and the fourth hard mask layer 108 can be formed by depositing a first silicon nitride layer 108a, a first oxide layer 108b, a first amorphous carbon (aC) layer 108c, a first anti-reflective coating (Anti-reflective Coating, referred to as ARC) 108d and a first bottom anti-reflective coating (Bottom Anti-Reflection Coating, referred to as BARC) 108e from bottom to top, and the anti-reflective coating 108d can also be formed by depositing a silicon oxynitride layer and an oxide layer from bottom to top. In addition, after the gate conductor layer 1072 is formed, an initial oxide layer 109 can be formed on the gate conductor layer 1072.

[0156] Next, a photoresist PR5 is formed on the surface of the mask layer 108 , and the photoresist PR5 is patterned by a photolithography process to form an opening in the photoresist PR5 .

[0157] like Figure 2t As shown, the fourth hard mask layer 108, the initial oxide layer 109 and the gate conductor layer 1072 are etched through the patterned photoresist PR5 to simultaneously form the first floating gate FG-1 and the control gate CG through one process, thereby achieving the purpose of reducing the manufacturing cost of the multi-time programmable device.

[0158] The bottom of the first floating gate FG-1 contacts the top of the second floating gate FG-2, and the first floating gate FG-1 and the second floating gate FG-2 together constitute a floating gate FG, which surrounds the channel region 1051a.

[0159] Next, the photoresist PR5, a portion of the fourth hard mask layer 108, and the remaining first silicon nitride layer 108a of the fourth hard mask layer 108 are removed. Then, phosphoric acid can be used to remove the remaining portion of the first silicon nitride layer 108a at the bottom of the fourth hard mask layer 108, and the remaining portion of the initial oxide layer 109 plays a role in protecting the formed floating gate FG and control gate CG.

[0160] like Figure 2u to Figure 2v In step S130, an inter-gate dielectric layer 110 is formed between the control gate CG and the first floating gate FG-1.

[0161] Specifically, Figure 2u As shown, an oxide film layer 1101 is formed.

[0162] In this step, an oxide film layer 1101 is grown on the sidewalls of the first floating gate FG-1 and the control gate CG, and a gap 1103 exists between the oxide film layer 1101 grown on the sidewall of the first floating gate FG-1 and the oxide film layer 1101 grown on the sidewall of the control gate CG.

[0163] like Figure 2v As shown, a nitride film layer 1102 is formed.

[0164] In this step, for example, a nitride film layer 1102 is formed by a deposition process, and the nitride film layer 1102 fills the gap 1103 and covers the initial oxide layer 109. Then, the nitride film layer 1102 and the initial oxide layer 109 can be etched back by a self-aligned etching process to remove the nitride film layer 1102 and the initial oxide layer 109 above the initial oxide layer 109, and the top of the remaining nitride film layer 1102 is flush with the top of the first floating gate FG-1 and the control gate CG. The remaining oxide film layer 1101 and the nitride film layer 1102 constitute the inter-gate dielectric layer 110.

[0165] By properly controlling the thickness of the oxide film layer 1101 grown on the side wall of the first floating gate FG-1 and the oxide film layer 1101 grown on the side wall of the control gate CG and using the existing process, an oxide-nitride-oxide structure as an inter-gate dielectric layer between the floating gate FG and the control gate CG can be manufactured without the need for additional photomasks and related processes, thereby reducing the manufacturing cost of the multi-time programmable device. The above-mentioned oxide film layer 1101 can be formed by growing oxide (Remain oxide, referred to as Rox) on the side walls of the first floating gate FG-1 and the control gate CG using a furnace tube, and the spacing between the first floating gate FG-1 and the control gate CG can be controlled to be 40-50nm to facilitate the formation of the inter-gate dielectric layer 109.

[0166] Although not shown in the above cross-sectional view, it should be known that in step S140, a source region and a drain region are formed in the source formation region and the drain formation region, respectively.

[0167] For example, by a self-aligned ion implantation process, N-type doping regions are formed in the source formation region and the drain formation region to form source regions S and drain regions D. In the first axis direction, the source region S and the drain region D are located on both sides of the floating gate FG.

[0168] In addition, if Figure 2w to Figure 2z As shown, this embodiment further includes the steps of forming a contact layer 111 , an adhesion layer 114 and a connection channel 115 .

[0169] Specifically, Figure 2w As shown, a contact layer 111 is formed.

[0170] In this step, metal silicide is grown on the surfaces of the control gate CG, the source region S, the drain region D, and the second active region 1052 to form a contact layer 111. The metal silicide, as an electrode, has the function of reducing contact resistance. Specifically, a self-aligned silicide barrier (SAB) can be formed first, that is, oxide and silicon nitride are deposited to cover the area where metal silicide does not need to be formed, and then the metal silicide is formed, including: first performing a SiCoNi pre-cleaning process to selectively remove the original material of the area where metal silicide needs to be formed with a thickness of about 60 angstroms, then depositing a nickel-platinum alloy layer with a thickness of about 120 angstroms and a titanium nitride layer with a thickness of about 50 angstroms in the area where metal silicide needs to be formed, and then performing a first rapid thermal processing (RTP) at 290°C for 30S to form a high-resistance metal silicide Ni2PtSi, and then performing a second rapid thermal processing to convert the high-resistance metal silicide Ni2PtSi into a low-resistance metal silicide NiPtSi2, and after completion, the metal in the area where the metal silicide NiPtSi2 is not formed is eliminated.

[0171] like Figure 2x As shown, a fifth hard mask layer 112 is formed.

[0172] In this step, a fifth hard mask layer 112 and a photoresist PR6 are deposited, and the photoresist PR6 is patterned.

[0173] The fifth hard mask layer 112 includes, from bottom to top, a second silicon nitride layer 112a with a thickness of 330 angstroms, a second oxide layer 112b with a thickness of 2100 angstroms, a second amorphous carbon layer 112c with a thickness of 1900 angstroms, a second anti-reflective coating layer 112d with a thickness of 370 angstroms, and a second bottom anti-reflective coating layer 112e with a thickness of 200 angstroms. The second anti-reflective coating layer 112d can be formed by depositing a 320 angstrom silicon oxynitride layer and a 50 angstrom oxide layer from bottom to top, and the thickness of the photoresist PR6 can be 1000 angstroms.

[0174] like Figure 2y As shown, a contact hole 113 is formed.

[0175] In this step, the fifth hard mask layer 112 is etched through the patterned photoresist PR6 to form a contact hole 113 reaching the contact layer 10. After the contact hole 113 is formed, the second silicon nitride layer 112a and the second oxide layer 112b are retained.

[0176] like Figure 2z As shown, a connecting channel 115 is formed.

[0177] In this step, a wet cleaning and deposition process can be used to form an adhesion layer 114 at the bottom and sidewall of the contact hole 113. The adhesion layer 114 includes, for example, titanium with a thickness of about 100 angstroms and titanium nitride with a thickness of about 50 angstroms. Next, a chemical vapor deposition (CVD) process can be used to form a conductive layer, which fills the contact hole 113 and covers the surface of the second oxide layer 112b. Next, for example, a CMP process is used to remove the conductive layer on the second oxide layer 111b, and the conductive layer inside the contact hole 113 is retained to form a connection channel 115.

[0178] Figure 3a FIG. 4 shows a schematic top view of a multi-time programmable device provided by a second embodiment of the present application, Figure 3b Shows Figure 3a Cross-sectional view along the AA direction. Figure 3a The structural layout of the multi-time programmable device 100 on the XY plane is simply illustrated, and thus the inter-gate dielectric layer between the control gate CG and the floating gate FG is not shown.

[0179] like Figure 3a and Figure 3bAs shown, different from the first embodiment, in this embodiment, the gate dielectric layer GOX covers the surface of the channel region 1051a and the bottom and side walls of the trench 1031, and a filling dielectric layer is also formed in the trench 1031. The gate dielectric layer GOX at the bottom and side walls of the trench 1031 and the filling dielectric layer in the trench 1031 together constitute the isolation dielectric of the isolation structure 103.

[0180] The floating gate FG is isolated from the channel region 1051 a via a gate dielectric layer GOX. In the second axis direction, the width of the gate dielectric layer GOX is greater than the width of the channel region 1051 a. The gate dielectric layer GOX surrounds the channel region 1051 a.

[0181] Furthermore, the second floating gate FG-2 and the first floating gate FG-1 have a certain concentration gradient.

[0182] Figures 4a to 4k It is a schematic diagram of each step of an exemplary method for manufacturing a multi-time programmable device provided in the second embodiment of the present application. The MOSFET device formed in the well region of the exemplary multi-time programmable device is an N-type MOSFET device.

[0183] Combine the following Figures 4a to 4k The manufacturing method of the multi-time programmable device provided in the embodiment of the present application is described in detail.

[0184] See also Figures 4a to 4k In step S110, a first active region, an isolation structure, a second floating gate and a gate dielectric layer are formed.

[0185] like Figure 4a and Figure 4b As shown, a semiconductor layer 201 is formed, and a first hard mask layer 202 is formed on the semiconductor layer 201. In this embodiment, the semiconductor layer 201 includes a substrate 2011 and a deep well region 2012 located in the substrate 2011, and the first hard mask layer 202 includes a stacked pad oxide layer 2021 (Pad Oxide) and a nitride layer 2022

[0186] Specific as Figure 4a As shown, a pad oxide is grown on the surface of the substrate 1011 to form a pad oxide layer 1021, and then a deep well region 1012 is formed by ion implantation into the substrate 1011 below the pad oxide layer 1021. The substrate 1011 has a first doping type, and the deep well region 1012 has a second doping type. The first doping type is, for example, P-type doping, and the second doping type is, for example, N-type doping. The substrate 1011 is, for example, P-type doping, and the deep well region 1012 is, for example, N-type doping.

[0187] like Figure 4bAs shown, a nitride layer 1022 is formed on the surface of the pad oxide layer 1021 , and the pad oxide layer 1021 and the nitride layer 1022 constitute a first hard mask layer 102 .

[0188] Next, a photoresist PR1 is formed on the first hard mask layer 102 , and the mask PR1 layer is patterned by a photolithography process to form an opening in the photoresist PR1 , thereby forming a patterned photoresist PR1 .

[0189] like Figure 4c As shown, the first hard mask layer 102 and a portion of the semiconductor layer 101 are etched through the opening of the photoresist PR1 to form a trench 1031 in the semiconductor layer 101. After the trench 1031 is formed, the photoresist PR1 is removed and only the portion of the first hard mask layer 102 originally covered by the patterned photoresist PR1 remains.

[0190] like Figure 4d As shown, for example, a wet etching process is used to remove the first hard mask layer 102 .

[0191] like Figure 4e As shown, for example, an oxidation and annealing process is used to form a gate dielectric layer GOX on the bottom and sidewall of the trench 1031 and the surface of the semiconductor layer 101 .

[0192] like Figure 4f As shown, a gate conductor layer 1071 is formed.

[0193] In this step, a gate conductor layer 1071 filling the trench 1031 is formed by, for example, a deposition process, and then, for example, a CMP (Chemical Mechanical Plamarization) process is used to planarize the gate conductor layer 1071 so that the top of the gate conductor layer 1071 is flush with the top of the gate dielectric layer GOX. The gate conductor layer 1071 is, for example, a doped polysilicon layer of the second doping type.

[0194] like Figure 4g As shown, a second hard mask layer 1062 is formed on the surfaces of the gate dielectric layer GOX and the gate conductor layer 1071 .

[0195] In this step, for example, a deposition process is used to form a second hard mask layer 1062 on the surfaces of the oxide layer 104 and the polysilicon layer.

[0196] Next, a photoresist PR4 is formed on the surface of the second hard mask layer 1062, for example, a photolithography process is used to form a patterned photoresist PR4 on the surface of the second hard mask layer 1062. The patterned photoresist PR4 is located above the gate dielectric layer GOX and extends to a portion of the gate conductor layer 1071 adjacent to the gate dielectric layer GOX.

[0197] Then, the second hard mask layer 1062 is etched through the patterned photoresist PR4 to remove a portion of the second hard mask layer 1062 . The remaining second hard mask layer 1062 is located above the gate dielectric layer GOX and above a portion of the gate conductor layer 1071 adjacent to the gate dielectric layer GOX.

[0198] like Figure 4h As shown, the gate conductor layer 1071 is etched through the second hard mask layer 1062 to remove part of the gate conductor layer 1071. The remaining gate conductor layer 1071 forms a second floating gate FG-2. The second floating gate FG-2 is adjacent to the gate dielectric layer GOX and is isolated from the sidewall of the trench 1031 through the gate dielectric layer GOX.

[0199] like Figure 4i As shown, the second hard mask layer 1062 is removed.

[0200] In this step, for example, wet etching is used to remove the second hard mask layer 1062 , and the wet etching solution is, for example, a phosphoric acid solution.

[0201] like Figure 4j As shown, a filling dielectric layer 1032 is formed in the trench 1031 to form an isolation structure 103 .

[0202] In this step, for example, a deposition process is used to form a filling dielectric layer 1032, and the filling dielectric layer 1032 and the gate dielectric layer GOX inside the trench 1031 jointly fill the trench 1031, and cover the surface of the gate dielectric layer GOX and the second floating gate FG-2. Then, for example, a CMP (Chemical Mechanical Plamarization) process is used to flatten the filling dielectric layer 1032, so that the surface of the filling dielectric layer 1032 is flush with the surface of the gate dielectric layer GOX and the second floating gate FG-2. The second filling dielectric layer 1032c is, for example, tetraethoxysilane (TEOS for short). Since tetraethoxysilane reacts with oxygen to generate silicon dioxide and volatile ethanol, silicon dioxide is filled in the trench. The gate dielectric layer GOX inside the trench 1031 and the second filling dielectric layer 1032c together constitute an isolation dielectric, and the isolation dielectric and the trench 1031 together constitute an isolation structure 103.

[0203] like Figure 4k As shown, a first active region 1051 and a second active region 1052 (not shown in the figure) are formed, wherein the first active region 1051 extends along a first axis direction (for example, an X-axis direction), and the second active region 1052 extends along a second axis direction (for example, a Y-axis direction), and the first active region 1051 and the second active region 1052 are separated from each other and isolated via an isolation structure 103.

[0204] In this step, for example, an ion implantation (IMP) process is used to implant doping ions into the semiconductor layer 101 to form a first active region 1051 and a second active region 1052 in the semiconductor layer 101 , and the filling dielectric layer 1032 defines the positions of the first active region 1052 and the second active region 1052 .

[0205] The first active region 1051 includes a source formation region, a channel region 1051a and a drain formation region arranged in the first axis direction. The source formation region and the drain formation region form a source region S and a drain region D respectively in subsequent steps.

[0206] Further, a dopant of the first doping type is injected into the semiconductor layer 101 to form a first active area 1051 and a second active area 1052, and the first active area 1051 and the second active area 1052 have the first doping type. In the process of forming the first active area 1051 and the second active area 1052, a dopant of the first doping type is injected into the second floating gate FG-2 at the same time, and the dopant of the first doping type and the dopant of the second doping type in the second floating gate FG-2 reduce the doping concentration of the second floating gate FG-2, so that the second floating gate FG-2 and the first floating gate FG-1 formed subsequently have a certain concentration gradient, which effectively prevents leakage of the floating gate.

[0207] In this embodiment, step S120: forming a control gate and a first floating gate separated from each other; step S130: forming an inter-gate dielectric layer between the control gate and the first floating gate; and step S140: forming a source region and a drain region in the source formation region and the drain formation region, respectively; and the steps of forming a contact layer 111, an adhesion layer 114 and a connecting channel 115 are the same as those in the first embodiment, and will not be repeated in this embodiment.

[0208] The unexpected technical effects of this application are:

[0209] The multi-time programmable device of the present application forms a floating gate transistor in the first axis direction and forms a control gate opposite to the floating gate in the second axis direction. Electrons are coupled to the floating gate by applying voltage to the control gate for MTP compilation. There is no need for voltage coupling through another MOS capacitor, thereby simplifying the device structure.

[0210] The floating gate of the present application includes a first floating gate and a second floating gate respectively opposite to the control gate, the intergate dielectric layer between the control gate and the first floating gate and the first floating gate constitute a first capacitor, and the isolation structure between the control gate and the second floating gate and the second floating gate constitute a second capacitor. By adding a second floating gate located inside the isolation structure, the coupling coefficient between the control gate and the floating gate is increased without changing the size of the device.

[0211] The control gate and the floating gate of the floating gate transistor in the multi-time programmable device are arranged in the horizontal direction. Compared with the arrangement in the vertical direction, the thickness of the multi-time programmable device of the present application is smaller, and the first floating gate and the control gate can be formed through the same process, thereby reducing the manufacturing cost of the multi-time programmable device; in addition, the multi-time programmable device of the present application forms a floating gate transistor in the first axis direction and forms a control gate opposite to the floating gate in the second axis direction. By reasonably arranging the positional relationship between the floating gate transistor and the control gate, the control gate and the floating gate transistor are relatively compact, so that the structure of the storage unit in the multi-time programmable device can be further reduced as the process platform is reduced, thereby realizing the miniaturization of the multi-time programmable device.

[0212] Furthermore, in the direction of the second axis, control gates are provided on both sides of the floating gate. The increase in the number of control gates enables the threshold voltage of the floating gate transistor to shift over a larger range, thereby allowing the multi-time programmable device to achieve different operating voltages within a larger range, which is conducive to realizing the multifunctional use of the product.

[0213] Furthermore, in the multi-time programmable device of the present application, the width of the gate dielectric layer of the floating gate transistor in the second axis direction is greater than the width of the channel region in the second axis direction, and the gate dielectric layer includes a portion extending into the interior of the isolation structure, so that the contact area between the floating gate and the gate dielectric layer is larger, and the writing speed of the multi-time programmable device is faster.

[0214] There is a certain concentration gradient between the first floating gate and the second floating gate of the present application to effectively prevent the floating gate from leaking electricity.

[0215] According to the method for manufacturing a multi-time programmable device of an embodiment of the present application, a second floating gate is formed simultaneously in the process of forming an isolation structure, and by adding a second floating gate located inside the isolation structure, the coupling coefficient between the control gate and the floating gate is increased without changing the size of the device. Furthermore, the present application forms the first floating gate and the control gate through the same process, so that the manufacturing cost of the multi-time programmable device is reduced.

[0216] In a preferred embodiment, since a second floating gate is provided, a liner dielectric layer is formed first and then a gate dielectric layer is formed. The liner dielectric layer and the gate dielectric layer together isolate the floating gate and the channel region to ensure that the second floating gate can be completely isolated from the channel region.

[0217] In a preferred embodiment, the gate dielectric layer and the second floating gate are formed using the same mask, thereby avoiding re-masking.

[0218] In a preferred embodiment, a gate dielectric layer is formed at the bottom, sidewalls and surface of the channel region of the trench through one process, thereby ensuring that the second floating gate is completely isolated from the channel region and simplifying the process steps.

[0219] In a preferred embodiment, a dopant of a first doping type is injected into the semiconductor layer to form a first active region, and the first active region has a first doping type. In the process of forming the first active region, a dopant of the first doping type is injected into the second floating gate at the same time, and the dopant of the first doping type and the dopant of the second doping type in the second floating gate are reduced to reduce the doping concentration of the second floating gate, so that the second floating gate and the first floating gate formed subsequently have a certain concentration gradient, which effectively prevents leakage of the floating gate without adding additional steps.

[0220] Furthermore, the manufacturing method of the above-mentioned multi-time programmable device also includes: growing an oxide film layer included in the inter-gate dielectric layer on the side walls of the formed floating gate and the control gate, and there is a gap between the oxide film layer grown on the side walls of the floating gate and the oxide film layer grown on the side walls of the control gate, and then filling nitride in the gap to form a nitride film layer included in the inter-gate dielectric layer, so that by reasonably controlling the thickness of the oxide film layer grown on the side walls of the floating gate and the oxide film layer grown on the side walls of the control gate and using existing processes, an oxide-nitride-oxide structure serving as an inter-gate dielectric layer between the floating gate and the control gate can be manufactured, without the need for additional masks and related processes, thereby reducing the manufacturing cost of the multi-time programmable device.

[0221] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A multi-time programmable device, comprising: Semiconductor layer; A first active region located in the semiconductor layer, the first active region comprising a source region, a channel region and a drain region arranged in a first axis direction; an isolation structure located in the semiconductor layer, adjacent to a first active region located in the semiconductor layer; A floating gate, comprising a first floating gate and a second floating gate connected together, wherein the first floating gate is located above the channel region and extends to above the isolation structure in the second axis direction, and the second floating gate is located inside the isolation structure and is arranged with the channel region in the second axis direction, and the first axis direction and the second axis direction intersect; A gate dielectric layer, located between the floating gate and the channel region; A control gate, located on the isolation structure and arranged with the floating gate in the direction of the second axis; as well as An inter-gate dielectric layer, located between the control gate and the first floating gate; The control gate is opposite to the first floating gate and the second floating gate respectively, the intergate dielectric layer between the control gate and the first floating gate and the first floating gate constitute a first capacitor, and the isolation structure between the control gate and the second floating gate and the second floating gate constitute a second capacitor.

2. The multi-time programmable device according to claim 1, wherein: The gate dielectric layer is located above the channel region, and in the direction of the second axis, at least one side of the gate dielectric layer extends to above the isolation structure adjacent to the channel region, and the portion extending above the isolation structure extends downward to the inside of the isolation structure; In the direction of the second axis, the width of the gate dielectric layer is greater than the width of the channel region; The isolation structure is formed in a trench, a lining dielectric layer is formed on the bottom and inner wall of the trench, a filling dielectric layer is formed inside the trench, and the filling dielectric layer and the lining dielectric layer together constitute the isolation dielectric of the isolation structure; The floating gate is isolated from the channel region via the gate dielectric layer and the liner dielectric layer.

3. The multi-time programmable device according to claim 1, wherein: The isolation structure is formed in the trench, the gate dielectric layer covers the bottom, inner wall and surface of the channel region of the trench, a filling dielectric layer is formed inside the trench, and the filling dielectric layer and the gate dielectric layer at the bottom and inner wall of the trench together constitute the isolation dielectric of the isolation structure; In the direction of the second axis, the width of the gate dielectric layer is greater than the width of the channel region; The floating gate is isolated from the channel region via the gate dielectric layer.

4. The multi-time programmable device according to claim 1, wherein: There is a certain concentration gradient between the first floating gate and the second floating gate.

5. A method for manufacturing a multi-time programmable device, comprising: A first active region, an isolation structure, a second floating gate and a gate dielectric layer are formed; the first active region and the isolation structure are located in a semiconductor layer and are adjacent to each other, the first active region includes a source formation region, a channel region and a drain formation region arranged in a first axis direction; the second floating gate is located inside the isolation structure and is arranged with the channel region in a second axis direction; the gate dielectric layer is located between the second floating gate and the channel region; forming a control gate and a first floating gate separated from each other, wherein the control gate is located on the isolation structure, the first floating gate is located above the channel region and extends to above the isolation structure in a second direction and is connected to a second floating gate located inside the isolation structure, the second floating gate and the first floating gate together constitute a floating gate, and the gate dielectric layer is also located between the first floating gate and the channel region; forming an inter-gate dielectric layer between the control gate and the first floating gate; as well as forming a source region and a drain region in the source formation region and the drain formation region respectively; The control gate is opposite to the first floating gate and the second floating gate respectively, the intergate dielectric layer between the control gate and the first floating gate and the first floating gate constitute a first capacitor, and the isolation structure between the control gate and the second floating gate and the second floating gate constitute a second capacitor.

6. The manufacturing method according to claim 5, wherein: The steps of forming the first active area, the isolation structure, the second floating gate and the gate dielectric layer include: forming a first hard mask layer on the semiconductor layer, and etching the semiconductor layer through the first hard mask layer to form a trench in the semiconductor layer; forming a liner dielectric layer at the bottom and sidewalls of the trench, and forming a first filling dielectric layer in the trench; Removing a portion of the first hard mask layer, and performing ion implantation on the semiconductor layer through the remaining first hard mask layer to form a first active region in the semiconductor layer, wherein the first filling dielectric layer defines a position of the first active region; the first active region includes a source formation region, a channel region, and a drain formation region arranged in a first axial direction; forming a gate dielectric layer, the gate dielectric layer being located on the channel region and extending above the trench in the second direction, and a portion extending above the trench extending downwardly into the interior of the trench; Removing the first filling dielectric layer in the trench, retaining the lining dielectric layer in the trench, and forming a second floating gate in the trench, wherein the second floating gate and the channel region are arranged in a second axial direction, and the second floating gate and the channel region are isolated via the gate dielectric layer and the lining dielectric layer; A second filling dielectric layer is formed in the trench to form an isolation structure, and the second filling dielectric layer and the liner dielectric layer together constitute an isolation dielectric of the isolation structure.

7. The manufacturing method according to claim 6, wherein: The method for forming the gate dielectric layer includes: forming a first photoresist on a surface of the first filling dielectric layer and a surface of the remaining first hard mask layer; Placing a mask on the first photoresist, and patterning the first photoresist through the mask, wherein the first photoresist exposes the first hard mask layer and a portion of the first filling dielectric layer adjacent to the first hard mask layer in the second axis direction; removing the exposed first hard mask layer and a portion of the first filling dielectric layer adjacent to the first hard mask layer in the second axis direction through the patterned first photoresist to form an opening; Filling a dielectric layer in the opening to form a gate dielectric layer in the opening; The method of forming the second floating gate includes: removing the first filling dielectric layer in the trench and retaining the lining dielectric layer in the trench; filling a gate conductor layer in the trench; forming a second hard mask layer on surfaces of the gate dielectric layer and the gate conductor layer; forming a second photoresist on the second hard mask layer; Similarly, a mask is placed on the second photoresist, and the second photoresist is patterned through the mask, wherein the second photoresist is patterned by using the mask used for patterning the first photoresist, and during the patterning of the second photoresist, an OVL adjustment is performed in the second axis direction, so that the formed second photoresist is located above the gate dielectric layer and extends in the second direction to a portion of the gate conductor layer; patterning the second hard mask layer via a second photoresist; The gate conductor layer is etched through the patterned second hard mask layer to form a second floating gate.

8. The manufacturing method according to claim 5, wherein: The steps of forming the first active area, the isolation structure, the second floating gate and the gate dielectric layer include: forming a trench in the semiconductor layer; forming a gate dielectric layer on the bottom and sidewall of the trench and the surface of the semiconductor layer; forming a second floating gate in the trench, wherein the second floating gate and the channel region are arranged in a second axis direction; Forming a filling dielectric layer in the trench to form an isolation structure, wherein the filling dielectric layer and the gate dielectric layer in the trench together constitute an isolation dielectric of the isolation structure; A first active region adjacent to the trench is formed in the semiconductor layer, the first active region comprising a source formation region, a channel region and a drain formation region arranged in a first axis direction, wherein the isolation structure defines a position of the first active region.

9. The manufacturing method according to claim 8, wherein: The method of forming the second floating gate includes: forming a gate conductor layer in the trench, wherein a top of the gate conductor layer is flush with a top of the gate dielectric layer; forming a patterned hard mask layer on the surfaces of the gate conductor layer and the gate dielectric layer, wherein the patterned hard mask layer is located on the surface of the gate dielectric layer above the channel region and extends in the direction of the second axis to a portion of the surface of the gate conductor layer adjacent to the channel region; The gate conductor layer is etched through the hard mask layer patterned by the mask layer to form a second floating gate, wherein the second floating gate is located in the trench and is aligned with the channel region in the second axis direction.

10. The manufacturing method according to claim 8, wherein: Ion implantation is performed on the semiconductor layer to form a first active area. During the process of forming the first active area, a first type of dopant is implanted into the semiconductor layer and the first floating gate. The first type of dopant and the second type of dopant in the second floating gate have a certain concentration gradient.

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