A testing method, device and equipment for a chip

Abstract

This application is applicable to the field of chip technology, and provides a method, device and equipment for testing a chip, including: in response to a trimming test instruction for the chip, determining the memory response values corresponding to multiple pin parameters of the chip; after determining that the chip programming is completed, in response to a read instruction for the chip, obtaining the memory write values corresponding to multiple pin parameters in the chip; judging whether the chip passes the trimming test according to the memory write values and the memory response values corresponding to multiple pin parameters; in the case of determining that the chip passes the trimming test, judging whether the output function of the chip is qualified by controlling the voltages or waveform frequencies of multiple pins of the chip; and when the output function of the chip is qualified, determining that the chip is qualified. By means of the present invention, the problem of how to test a chip and identify unqualified chips can be solved.

Description

Technical Field

[0001] This application belongs to the field of chip technology, and particularly relates to a method, device, and equipment for testing a chip. Background Art

[0002] A Hall chip is a sensor device based on the Hall effect. The Hall chip includes a Hall element and related amplifier circuits, temperature compensation circuits, and regulated power supply circuits, etc., which are integrated on a single chip to form a Hall IC (Hall Integrated Circuit). The Hall IC consists of a Hall element and a signal processing IC (Signal Processing Integrated Circuit). Among them, the Hall element outputs detailed information, and the signal processing IC compares the output voltage of the Hall element and converts it into a high / low level digital signal for output.

[0003] However, due to process problems or deficiencies in the manufacturing process of the Hall chip, the voltage of the manufactured chip may not match the input voltage range of the backend microcontroller, or the functional parameters of the chip do not meet the user's requirements. Using the chips with the above quality problems in the subsequent product production will affect the performance of the product and increase unnecessary costs. In order to avoid using the chips with quality problems in the subsequent products, it is necessary to test the chips, screen out the unqualified chips, and only apply the qualified chips to the subsequent product production. Summary of the Invention

[0004] Embodiments of this application provide a method, device, and equipment for testing a chip, which solve the problem of how to test a chip and screen out the unqualified chips.

[0005] In a first aspect, embodiments of this application provide a method for testing a chip, including:

[0006] In response to a trimming test instruction for the chip, determining the memory response values corresponding to the respective multiple pin parameters of the chip;

[0007] After determining that the chip has been programmed, in response to a read instruction for the chip, obtaining the memory write values corresponding to the respective multiple pin parameters in the chip;

[0008] Based on the memory write values and the memory response values corresponding to the respective multiple pin parameters, determining whether the chip passes the trimming test;

[0009] When it is determined that the chip passes the trimming test, by controlling the voltages or waveform frequencies of the multiple pins of the chip, determining whether the output function of the chip is qualified;

[0010] When the output function of the chip is qualified, it is determined that the chip is qualified.

[0011] In a possible implementation of the first aspect, before determining the memory response values corresponding to the respective multiple pin parameters of the chip in response to a trimming test instruction for the chip, the method further includes:

[0012] Obtain the voltages of the respective functional pins of the chip in a first state, where the first state is determined by the time of applying a preset current to the respective functional pins of the chip;

[0013] Obtain the static current of the power supply pin of the chip in a second state, where the second state is determined by the time of applying a preset voltage to the power supply pin of the chip;

[0014] Judge whether the DC parameters of the chip are qualified according to the static current of the power supply pin in the second state and the voltages of the respective functional pins in the first state;

[0015] When it is determined that the DC parameters of the chip are qualified, issue a trimming test instruction for the chip.

[0016] In a possible implementation of the first aspect, the determining the memory response values corresponding to the respective multiple pin parameters of the chip in response to a trimming test instruction for the chip includes:

[0017] In response to the trimming test instruction for the chip, send different write waveform instructions to the chip;

[0018] Determine a target write waveform instruction according to the target parameter values of the multiple pin parameters of the chip;

[0019] Calculate the memory response values corresponding to the respective multiple pin parameters in the chip according to the transition point time information of the target write waveform instruction and the preset baud rate of the chip.

[0020] In a possible implementation of the first aspect, the judging whether the chip passes the trimming test according to the memory write values and the memory response values corresponding to the respective multiple pin parameters includes:

[0021] Respectively judge whether the write results of the respective pin parameters of the chip are correct according to the memory write values and the memory response values corresponding to the respective pin parameters in the chip;

[0022] When the write results of all the pin parameters of the chip are correct, it is determined that the chip passes the trimming test.

[0023] In a possible implementation of the first aspect, determining whether the output function of the chip is qualified by controlling the voltage or waveform frequency of multiple pins of the chip includes:

[0024] Determining whether the voltage jump output function of the chip is qualified by raising or lowering the voltage of the power supply pin of the chip;

[0025] Determining whether the gain parameter output function of the chip is qualified by raising or lowering the voltage of the function pin of the chip;

[0026] Determining whether the voltage peak output function of the chip is qualified by controlling the waveform frequency of the function pin of the chip;

[0027] When it is determined that the voltage jump output function, the gain parameter output function, and the voltage peak output function of the chip are all qualified, it is determined that the output function of the chip is qualified.

[0028] In a possible implementation of the first aspect, the function pins of the chip include Hall voltage function pins;

[0029] The determining whether the voltage jump output function of the chip is qualified by raising or lowering the voltage of the power supply pin of the chip includes:

[0030] Controlling the voltage of the power supply pin of the chip to change from a first voltage to a second voltage;

[0031] Obtaining the output voltage of the Hall voltage function pin of the chip within a first time period, where the first time period is the time period during which the voltage of the power supply pin of the chip changes from the first voltage to the second voltage;

[0032] Determining whether there is a jump in the output voltage of the Hall voltage function pin of the chip within the first time period;

[0033] When there is a jump in the output voltage of the Hall voltage function pin of the chip, it is determined that the voltage jump output function of the chip is qualified.

[0034] In a possible implementation of the first aspect, the function pins of the chip include gain parameter function pins and enable function pins;

[0035] The determining whether the gain parameter output function of the chip is qualified by raising or lowering the voltage of the function pin of the chip includes:

[0036] Controlling the voltage of the enable function pin of the chip to change from a third voltage to a fourth voltage;

[0037] Obtain the output voltage difference of the gain parameter function pin of the chip within a second time period, where the second time period is the time period during which the voltage of the enable function pin of the chip changes from a third voltage to a fourth voltage;

[0038] Determine whether the output voltage difference of the gain parameter function pin of the chip within the second time period is within a first preset interval;

[0039] When the output voltage difference of the gain parameter function pin of the chip within the second time period is within the first preset interval, determine that the gain parameter output function of the chip is qualified.

[0040] In a possible implementation manner of the first aspect, the function pins of the chip include differential input function pins and voltage peak function pins. The method for determining whether the voltage peak output function of the chip is qualified by controlling the waveform frequency of the function pins of the chip includes:

[0041] Control the waveform frequency of the differential input function pin of the chip to change from a first frequency to a second frequency;

[0042] Obtain the output voltage peak of the voltage peak function pin of the chip within a third time period, where the third time period is the time period during which the waveform frequency of the differential input function pin of the chip changes from the first frequency to the second frequency;

[0043] Calculate the output voltage peak ratio of the voltage peak function pin of the chip within the third time period according to the output voltage peak of the voltage peak function pin of the chip within the third time period;

[0044] Determine whether the output voltage peak ratio of the voltage peak function pin of the chip within the third time period is within a second preset interval;

[0045] When the output voltage peak ratio of the voltage peak function pin of the chip within the third time period is within the second preset interval, determine that the voltage peak output function of the chip is qualified.

[0046] In a second aspect, an embodiment of the present application provides a chip testing device, including:

[0047] A chip memory response value determination module, configured to determine the memory response value corresponding to each of the multiple pin parameters of the chip in response to a trimming test instruction for the chip;

[0048] A chip data reading module, configured to, after determining that the chip programming is completed, in response to a reading instruction for the chip, obtain the memory write values corresponding to the multiple pin parameters in the chip;

[0049] A chip trimming test module, configured to determine whether the chip passes the trimming test according to the memory write values and the memory response values corresponding to the multiple pin parameters respectively;

[0050] A chip output function judging module, configured to, when it is determined that the chip passes the trimming test, judge whether the output function of the chip is qualified by controlling the voltage or waveform frequency of multiple pins of the chip;

[0051] A chip overall judging module, configured to determine that the chip is qualified when the output function of the chip is qualified.

[0052] In a third aspect, an embodiment of the present application provides a test device for a chip, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the method described in any one of the above is implemented.

[0053] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the method described in any one of the above is implemented.

[0054] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product runs on a terminal device, the terminal device is enabled to execute the method described in any one of the above.

[0055] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: By responding to a trimming test instruction for the chip, determining the memory response values corresponding to the multiple pin parameters of the chip, after determining that the chip programming is completed, in response to a reading instruction for the chip, obtaining the memory write values corresponding to the multiple pin parameters in the chip, and determining whether the chip passes the trimming test according to the memory write values and the memory response values corresponding to the multiple pin parameters respectively. When it is determined that the chip passes the trimming test, judge whether the output function of the chip is qualified by controlling the voltage or waveform frequency of multiple pins of the chip. When the output function of the chip is also qualified, determine that the chip is qualified, complete the test of the chip, screen out the qualified chips, identify the unqualified chips, and only apply the qualified chips to the subsequent product production, thereby effectively avoiding unnecessary cost waste in product production and reducing the product production cost. Description of the Drawings

[0056] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for use in the embodiments or the description of the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0057] Figure 1 is a schematic flowchart of a method for testing a chip provided by an embodiment of the present application;

[0058] Figure 2 is a schematic structural diagram of a testing system for a chip provided by an embodiment of the present application;

[0059] Figure 3 is a schematic flowchart of a method for testing a chip provided by another embodiment of the present application;

[0060] Figure 4 is a schematic diagram of the current of the pins of a chip provided by an embodiment of the present application;

[0061] Figure 5 is a schematic diagram of the current of the pins of a chip during trimming test provided by an embodiment of the present application;

[0062] Figure 6 is a schematic structural diagram of a testing device for a chip provided by an embodiment of the present application. Detailed Embodiments

[0063] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0064] It should be understood that when used in the specification of the present application and the appended claims, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0065] It should also be understood that the term " / and" as used in the specification of the present application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0066] As used in the specification of this application and the appended claims, the term "if" may be construed, depending on the context, as "when", "once", "in response to determining", or "in response to detecting". Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be construed, depending on the context, to mean "once determined", "in response to determining", "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]".

[0067] In addition, in the description of the specification of this application and the appended claims, the terms "first", "second", "third", etc. are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0068] Reference to "one embodiment" or "some embodiments" or the like described in the specification of this application means that a specific feature, structure, or characteristic described in connection with that embodiment is included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "comprising", "including", "having", and their variants all mean "including but not limited to", unless otherwise specifically emphasized in another way.

[0069] The embodiments of this application provide a method for testing a chip. Refer to Figure 1 , Figure 1 which is a schematic flowchart of a method for testing a chip provided by an embodiment of this application, including:

[0070] Step S11: In response to a trimming test instruction for the chip, determine the memory response value corresponding to each of the multiple pin parameters of the chip;

[0071] Step S12: After determining that the chip programming is completed, in response to a read instruction for the chip, obtain the memory write value corresponding to each of the multiple pin parameters in the chip;

[0072] Step S13: According to the memory write value and the memory response value corresponding to each of the multiple pin parameters, determine whether the chip passes the trimming test;

[0073] Step S14: In the case of determining that the chip passes the trimming test, by controlling the voltage or waveform frequency of the multiple pins of the chip, determine whether the output function of the chip is qualified;

[0074] Step S15: When the output function of the chip is qualified, determine that the chip is qualified.

[0075] It should be noted that the base material of the Hall chip is a wafer. After the wafer is manufactured and before the chip is packaged, the unencapsulated chip is connected to the test machine through probes for CP (circuit probing, wafer) testing of the chip. In this embodiment, a probe station (such as UF200 probe station) and a probe card are used to implement the testing of the Hall chip. Among them, the UF200 probe station is a fully automatic probe test station integrating various technologies such as precision machinery, computer control, servo control, and optics.

[0076] In an optional example, a tester (such as STS8200 tester) is selected to implement the testing of the chip. The STS8200 tester is a powerful and flexible expandable analog IC test system, and it is a large-mode small-number type of test machine, which can support multiple workstations to test multiple chips simultaneously. As Figure 2 shown, Figure 2 is a schematic structural diagram of a chip testing system provided by an embodiment of the present application. The tester sends chip-related data to the chip testing system, and the chip testing system generates corresponding control instructions according to the received chip-related data, and sends the control instructions to the tester to control the tester to test the chip. Among them, the chip can be a Hall chip.

[0077] After the chip is connected to the tester, through control commands, the chip is subjected to overall testing to determine whether the overall chip (which can be understood as the whole or all) is qualified. The overall testing of the chip includes DC parameter testing, trimming testing, and output function testing. Refer to Figure 3 , Figure 3 is a schematic flow diagram of a chip testing method provided by another embodiment of the present application. Among them, the purpose of DC parameter testing is to test the static current and reference voltage of the chip to determine whether the DC parameters of the chip are qualified. The purpose of trimming testing is to introduce a compensation mechanism through programming trimming testing of the chip, so that the chip can maintain a stable output voltage in different environments, accurately adjust the written value in the register of the chip, thereby controlling the output voltage of the chip, so that the output voltage of the chip can accurately reach the target voltage value required by the design. The purpose of output function testing is to determine whether the design specifications of the chip meet the user's requirements by testing the actual output parameters of the chip.

[0078] After the chip passes the DC parameter testing, trimming testing, and output function testing, it is determined whether the overall chip is qualified according to the corresponding test results.

[0079] It should be noted that the chip can be tested in sequence according to the order of DC parameter testing, trimming testing, and output function testing, or it can be tested in other orders. The embodiments of the present application do not make specific limitations on this.

[0080] In an optional example, when it is determined that the DC parameters of the chip are qualified, a trimming test instruction for the chip is generated.

[0081] Specifically, in response to the trimming test instruction for the chip, the chip connected to the tester enters the programming mode.

[0082] In an optional example, refer to Figure 4 , Figure 4 is a schematic diagram of the current of the pins of a chip provided by an embodiment of the present application. The power supply pin of the chip is Figure 4 the VDD pin 1 in . The VDD pin 1 is connected to a resource of the FPVI10 board of the tester. Among them, the FPVI10 board can provide a relatively high voltage range to meet the test requirements of different chips. The DC-DC power supply module (DC power supply module) of the tester provides a first preset voltage (such as 8.9V) to the VDD pin 1 of the chip within a short time (1ms). After a short period of time (such as 2ms), the voltage of the VDD pin 1 decreases (such as decreases by 5V), then the chip connected to the tester enters the programming mode.

[0083] Assume that the communication method of the chip is UART serial port (Universal Asynchronous Receiver-Transmitter serial port) communication. As Figure 5 shown, Figure 5 is a schematic diagram of the current of the pins of the chip during trimming test provided by an embodiment of the present application. The VOUT pin 3 of the chip is the input / output port (I / O port) of the serial port communication. The VOUT pin 3 usually works together with pins such as the ground pin (GND pin) to form a complete circuit system. When the chip enters the programming mode, the VOUT pin 3 of the chip is connected to the DI / DO and QTMU modules of the tester through CBIT (control bit, control relay signal) to write and read data. Among them, DI / DO (Digital Input / Output) is the digital input / output port of the tester, which sends a write waveform instruction or a read waveform instruction to the VOUT pin 3 of the chip. By controlling the baud rate of the waveform, the response data is written into the memory of the chip (such as the memory from 0x00 to 0x0F), or the data in the memory of the chip is read. The QTMU module is a module in the tester that can be used to test frequency and time-related parameter information. The baud rate of the waveform is determined by the baud rate of the chip.

[0084] It can be understood that the time of the waveform jump point of the sent write waveform instruction can determine the response data written to the temporary memory of the chip, and the time of the waveform jump point of the sent write waveform instruction can also determine the parameter value of the pin parameter. The response data of each temporary memory in the chip corresponds to a parameter value of a pin parameter, and each parameter value corresponds to a unique response data.

[0085] It should be noted that the time of the waveform jump point of the waveform instruction sent by the DI / DO of the tester can be obtained using the QTMU module of the tester.

[0086] Specifically, according to the parameter requirements of the user for the chip, the target parameter values of multiple pin parameters of the chip can be determined. When the pin parameter of the chip is the target parameter value, the response data of the temporary memory corresponding to the pin parameter at this time is determined as the memory response value. In this way, the memory response value corresponding to each pin parameter of the chip is determined.

[0087] Use the STORECHIP command (write command) to burn the memory response value corresponding to each determined pin parameter into the EEPROM memory (Electrically Erasable Programmable Read-Only Memory) of the chip to complete the burning of the chip.

[0088] After determining that the chip burning is completed, a read instruction is sent to the chip to control the DI / DO of the tester to send a read waveform instruction to the I / O port of the chip, and the current written value in the EEPROM memory of the chip is read to obtain the memory write value corresponding to each pin parameter in the chip.

[0089] For each pin parameter, there is a memory response value and a memory write value. According to the memory response values and memory write values corresponding to all the pin parameters, it is judged whether the chip passes the trimming test.

[0090] When the chip does not pass the trimming test, it is determined that the chip is unqualified, and the chip is screened out for re-trimming test or directly scrapped to ensure that only qualified chips enter the market. When the chip passes the trimming test, after each power-on of the chip, the multiple pin parameters of the chip are the target parameter values, and the output voltage of the chip is the parameter requirement of the user for the chip, which matches the input voltage range of the backend microcontroller.

[0091] In an optional example, as Figure 4 shown, after the chip passes the trimming test, Figure 4Among them, the output voltage of the functional pin TST0 pin 7 is 1.219V, and the output waveform frequency of the functional pin TST3 pin 10 is 9.6KHz, which matches the input voltage range of the backend microcontroller.

[0092] After the chip passes the trimming test, in order to improve the qualification rate of the chip, the output function test of the chip is continued. For example: power on and reset the chip, and through controlling the pin voltage of the chip, perform under-voltage test, over-voltage test, gain parameter test and / or output voltage test, etc., to test whether the output function of the chip meets the preset requirements of the user. When the preset requirements of the user are met, it is determined that the output function of the chip is qualified. When the preset requirements of the user are not met, it is determined that the output function of the chip is unqualified.

[0093] When the output function of the chip is qualified, it is determined that the chip is qualified, that is, the chip is overall qualified and can be put into use. When the output function of the chip is unqualified, it is determined that the chip is unqualified, that is, the chip is overall unqualified and cannot be put into use.

[0094] It should be noted that when the chip is tested not in the order of DC parameter test, trimming test and output function test, only when the DC parameter test is qualified, the trimming test is passed and the output function test is qualified, it is determined that the chip is qualified and the chip can be put into use. When any one of the DC parameter test, trimming test or output function test is unqualified, it is determined that the chip is unqualified and the chip cannot be put into use.

[0095] It can be understood that in the embodiment of the present application, in response to the trimming test instruction for the chip, the memory response values corresponding to the multiple pin parameters of the chip are determined. After it is determined that the chip is burned successfully, in response to the read instruction for the chip, the memory write values corresponding to the multiple pin parameters in the chip are obtained. According to the memory write values and the memory response values corresponding to the multiple pin parameters, it is judged whether the chip passes the trimming test. In the case where it is determined that the chip passes the trimming test, by controlling the voltage or waveform frequency of the multiple pins of the chip, it is judged whether the output function of the chip is qualified. When the output function of the chip is also qualified, it is determined that the chip is overall qualified, the test of the chip is completed, the qualified chips are screened out, the unqualified chips are identified, and only the qualified chips are applied to the subsequent product production, thereby effectively avoiding unnecessary cost waste in product production and reducing the product production cost.

[0096] In a possible implementation manner, before step S11, in response to the trimming test instruction for the chip, determining the memory response values corresponding to the multiple pin parameters of the chip, the above method further includes:

[0097] Obtain the voltages of each functional pin of the chip in the first state, where the first state is determined by the time of applying a preset current to each functional pin of the chip;

[0098] Obtain the static current of the power supply pin of the chip in the second state, where the second state is determined by the time of applying a preset voltage to the power supply pin of the chip;

[0099] Judge whether the DC parameters of the chip are qualified according to the static current of the power supply pin in the second state and the voltages of each functional pin in the first state;

[0100] When it is determined that the DC parameters of the chip are qualified, issue a trimming test instruction for the chip.

[0101] Specifically, before determining the memory response values corresponding to the respective pin parameters of the chip in response to the trimming test instruction for the chip, the above method further includes:

[0102] Use FPVI10 and FOVI100 in the DC-DC power supply module of the tester to perform current addition and voltage measurement and voltage addition and current measurement. Among them, FPVI10 and FOVI100 are resources that can test the current and voltage of the chip.

[0103] The voltage of the ground pin GND pin 2 is 0V, and a preset current (such as 40 μA) is applied to the ground pin GND pin 2. As Figure 4 shown, the currents of the power supply pin VDD pin 1 of the chip and all functional pins are preset currents. The functional pins include functional pin VOUT pin 3, functional pin VREF pin 4, functional pin STANDBY pin 5, functional pin TST0 pin 7, functional pin TST1 pin 8, functional pin TST2 pin 9, and functional pin TST3 pin 10. At this time, by measurement, the voltage of each functional pin of the chip is obtained as the voltage of each functional pin in the first state. Among them, the functional pin STANDBY pin 5 is the pin for controlling the tester to enter or exit the standby state. The functional pin VREF pin 4 is used to provide a stable reference voltage to ensure that the circuit can accurately perform signal processing. The functional pins TST0 pin 7 - functional pins TST3 pin 10 are used to test parameters such as the voltage, current, and frequency of the chip.

[0104] As Figure 5 shown, a preset voltage (such as +5V) is applied to the power supply pin VDD pin 1. At this time, the static current of the power supply pin VDD pin 1 of the chip is obtained by measurement as the static current of the power supply pin VDD pin 1 of the chip in the second state.

[0105] Judge whether the DC parameters of the chip are qualified according to the static current of the power supply pin VDD pin 1 in the second state and the voltage of each functional pin in the first state. When the static current of the power supply pin VDD pin 1 of the chip in the second state is within the first preset range (for example: 10 mA to 20 mA), and the voltage of each functional pin in the first state is within the second preset range (for example: -0.9 V to -0.2 V), it is determined that the DC parameters of the chip are qualified. When the static current of the power supply pin VDD pin 1 of the chip in the second state is not within the first preset range (for example: 10 mA to 20 mA), or there is any functional pin whose voltage in the first state is not within the second preset range (for example: -0.9 V to -0.2 V), it is determined that the DC parameters of the chip are unqualified.

[0106] When it is determined that the DC parameters of the chip are qualified, issue a trimming test instruction for the chip. When the DC parameters of the chip are unqualified, the chip is unqualified and needs to be retested, adjusted or scrapped.

[0107] It should be noted that the above first preset range and second preset range can be set according to the actual situation, and this embodiment does not make specific limitations on this. The chip can also be subjected to an open / short test (OS test) to confirm whether there is an open (Open) or short (Short) in the pins of the chip. Taking the OS test as the first link in the chip test process can quickly determine whether there are problems such as pin short circuit, bonding wire missing, pin damaged by static electricity, manufacturing defects, etc. during the chip manufacturing process. If the chip has an open or short circuit during the OS test stage, it is determined that the chip is unqualified and no subsequent test is required, thereby reducing the test cost and improving the test efficiency.

[0108] In a possible implementation manner, in step S11, in response to the trimming test instruction for the chip, determining the memory response value corresponding to each of the multiple pin parameters of the chip includes:

[0109] In response to the trimming test instruction for the chip, send different write waveform instructions to the chip;

[0110] Determine the target write waveform instruction according to the target parameter values of the multiple pin parameters of the chip;

[0111] Calculate the memory response value corresponding to each of the multiple pin parameters in the chip according to the jump point time information of the target write waveform instruction and the preset baud rate of the chip.

[0112] Specifically, in response to the trimming test instruction for the chip, determining the memory response value corresponding to each of the multiple pin parameters of the chip includes:

[0113] See Figure 2 ,Figure 2 In response to the trimming test instruction for the chip, the DI / DO of the control tester issues a write waveform instruction to the I / O of the chip, and the write waveform instruction carries the memory write address and the transition point time information. Among them, the memory write address is the address of the SARM memory (temporary memory) to be written by the chip. The transition point time information includes the transition point time of the write waveform instruction. When the transition point times of the waveform instructions are different, different parameter values appear for the pin parameters of the chip, and the written values in the SARM memory are different.

[0114] The pin parameters of the chip include the Hall voltage parameter of the functional pin TST0, the waveform frequency parameter of the functional pin TST3, the reference voltage parameter of the functional pin VREF, and the voltage difference parameter between the functional pin TST0 and the functional pin TST1.

[0115] According to the target parameter values of multiple pin parameters of the chip, when the multiple pin parameters of the chip appear the target parameter values, at this time, it is determined that the write waveform instruction issued by the DI / DO of the tester to the I / O of the chip is the target write waveform instruction. The transition point time of the target write waveform instruction is obtained through the QTMU module of the tester. Among them, one pin parameter corresponds to one target write waveform instruction.

[0116] For any one pin parameter, perform data conversion processing on the transition point time of the corresponding target write waveform instruction to obtain the binary transition point time, divide the binary transition point time by the preset baud rate of the chip to obtain the binary memory response value, and convert the binary memory response value to obtain the decimal memory response value, which is used as the memory response value corresponding to this pin parameter.

[0117] In an optional example, the target parameter value of the Hall voltage parameter of the functional pin TST0 is 1.2V, the target parameter value of the waveform frequency parameter of the functional pin TST3 is 9.6KHz, the target parameter value of the voltage difference parameter between the functional pin TST0 and the functional pin TST1 is 1.219V, the target parameter of the reference voltage parameter of the functional pin VREF is 2.5V, and one pin parameter corresponds to one memory.

[0118] In a possible implementation manner, in step S13, according to the memory write values and memory response values corresponding to the multiple pin parameters respectively, determining whether the chip passes the trimming test includes:

[0119] Respectively, according to the memory write values and memory response values corresponding to each pin parameter in the chip, determine whether the write results of each pin parameter of the chip are correct;

[0120] When the writing results of all the pin parameters of the chip are correct, it is determined that the chip passes the trimming test.

[0121] Specifically, according to the memory write values and memory response values corresponding to multiple pin parameters respectively, it is determined whether the chip passes the trimming test, including:

[0122] Read the current write values in the EEPROM memory of the chip to obtain the memory write values corresponding to each pin parameter in the chip.

[0123] For any pin parameter of the chip, there is a corresponding memory response value and a memory write value. According to the memory response value and the memory write value corresponding to this pin parameter, it is determined whether the writing result of the memory corresponding to this pin parameter is correct. When the memory response value and the memory write value corresponding to this pin parameter are consistent, it is determined that the writing result of the memory corresponding to this pin parameter is correct. When the memory response value and the memory write value corresponding to this pin parameter are inconsistent, it is determined that the writing result of the memory corresponding to this pin parameter is incorrect.

[0124] When the writing results of all the pin parameters of the chip are correct, it is determined that the chip passes the trimming test. When the writing result of any pin parameter of the chip is incorrect, it is determined that the chip fails the trimming test and needs to be scrapped or retested.

[0125] In a possible implementation manner, in step S14, by controlling the voltages or waveform frequencies of multiple pins of the chip, it is determined whether the output function of the chip is qualified, including:

[0126] Step S141, by raising or lowering the voltage of the power supply pin of the chip, it is determined whether the voltage jump output function of the chip is qualified;

[0127] Step S142, by raising or lowering the voltage of the function pin of the chip, it is determined whether the gain parameter output function of the chip is qualified;

[0128] Step S143, by controlling the waveform frequency of the function pin of the chip, it is determined whether the voltage peak output function of the chip is qualified;

[0129] Step S144, when it is determined that the voltage jump output function, the gain parameter output function and the voltage peak output function of the chip are all qualified, it is determined that the output function of the chip is qualified.

[0130] Specifically, by controlling the voltages or waveform frequencies of multiple pins of the chip, it is determined whether the output function of the chip is qualified, including:

[0131] After the chip passes the above trimming test, by raising or lowering the voltage of the power supply pin of the chip, it is determined whether the Hall voltage output by the chip jumps. When the output Hall voltage jumps, it is determined that the voltage jump output function of the chip is qualified; when the output Hall voltage does not jump, it is determined that the voltage jump output function of the chip is unqualified.

[0132] By raising or lowering the voltage of the functional pin of the chip, it is determined whether the output voltage difference of the chip meets the preset requirements. When the output voltage difference of the chip meets the preset requirements, it is determined that the gain parameter output function of the chip is qualified; when the output voltage difference of the chip does not meet the preset requirements, it is determined that the gain parameter output function of the chip is unqualified.

[0133] By controlling the waveform frequency of the functional pin of the chip, it is determined whether the output voltage peak value of the chip meets the conditions. When the output voltage peak value of the chip meets the conditions, it is determined that the voltage peak output function of the chip is qualified; when the output voltage peak value of the chip does not meet the conditions, it is determined that the voltage peak output function of the chip is unqualified.

[0134] When the voltage jump output function, gain parameter output function, and voltage peak output function of the chip are all qualified, it is determined that the output function of the chip is qualified. When at least one of the voltage jump output function, gain parameter output function, or voltage peak output function of the chip is unqualified, it is determined that the output function of the chip is unqualified. At this time, the chip is unqualified and needs to be retested, adjusted, or scrapped.

[0135] In a possible implementation manner, in step S141, the functional pin of the chip includes a Hall voltage functional pin. By raising or lowering the voltage of the power supply pin of the chip, determining whether the voltage jump output function of the chip is qualified includes:

[0136] Controlling the voltage of the power supply pin of the chip to change from a first voltage to a second voltage;

[0137] Obtaining the output voltage of the Hall voltage functional pin of the chip within a first time period, where the first time period is the time period during which the voltage of the power supply pin of the chip changes from the first voltage to the second voltage;

[0138] Determining whether there is a jump in the output voltage of the Hall voltage functional pin of the chip within the first time period;

[0139] When there is a jump in the output voltage of the Hall voltage functional pin of the chip, it is determined that the voltage jump output function of the chip is qualified.

[0140] Specifically, the functional pin of the chip includes a Hall voltage functional pin. By raising or lowering the voltage of the power supply pin of the chip, determining whether the voltage jump output function of the chip is qualified includes:

[0141] Among the functional pins of the chip, there is a Hall voltage functional pin (such as pin 7 of functional pin TST0) for outputting the Hall voltage. When the chip passes the trimming test, a memory response value is written into the memory of the chip. When the chip is powered on and reset, the output Hall voltage of pin 7 of functional pin TST0 is 1.219V, and the output waveform frequency of pin 10 of functional pin TST3 is 9.6KHz.

[0142] The control tester supplies voltage to the power pin VDD of the chip, and the voltage changes from the first voltage to the second voltage. The first voltage and the second voltage can be preset in advance. The time period during which the voltage of the power pin VDD changes from the first voltage to the second voltage is used as the first time period, and the output voltage of the Hall voltage functional pin (such as pin 7 of functional pin TST0) of the chip within the first time period is obtained.

[0143] It is judged whether there is a jump in the output voltage of the Hall voltage functional pin (such as pin 7 of functional pin TST0) of the chip within the first time period. When there is a jump in the output voltage of the Hall voltage functional pin (pin 7 of functional pin TST0) of the chip within the first time period, it is determined that the voltage jump output function of the chip is qualified. If there is no jump in the output voltage of the Hall voltage functional pin (pin 7 of functional pin TST0) of the chip within the first time period, it is determined that the voltage jump output function of the chip is unqualified.

[0144] In an optional example, after the chip passes the above-mentioned trimming test, the control tester supplies voltage to the power pin VDD of the chip, rising from 2.6V to 3.6V. The output voltage of pin 7 of functional pin TST0 of the chip changes from 0V to 0.3V. At this time, it is determined that there is a jump in the output voltage of the Hall voltage functional pin (pin 7 of functional pin TST0) of the chip within the first time period, and the voltage jump output function of the chip is qualified. When the voltage of the power pin VDD drops from 3.6V to 2.6V, the output voltage of pin 7 of functional pin TST0 of the chip changes from 0.3V to 0V. At this time, it is also determined that there is a jump in the output voltage of the Hall voltage functional pin (pin 7 of functional pin TST0) of the chip within the first time period, and the voltage jump output function of the chip is qualified.

[0145] In a possible implementation manner, in step S142, the functional pins of the chip include a gain parameter functional pin and an enable functional pin. By raising or lowering the voltage of the functional pins of the chip, judging whether the gain parameter output function of the chip is qualified includes:

[0146] Controlling the voltage of the enable functional pin of the chip to change from the third voltage to the fourth voltage;

[0147] Obtain the output voltage difference of the gain parameter function pin of the chip within the second time period, where the second time period is the time period during which the voltage of the enable function pin of the chip changes from the third voltage to the fourth voltage;

[0148] Determine whether the output voltage difference of the gain parameter function pin of the chip within the second time period is within the first preset range;

[0149] When the output voltage difference of the gain parameter function pin of the chip within the second time period is within the first preset range, determine that the gain parameter output function of the chip is qualified.

[0150] Specifically, the function pins of the chip include the gain parameter function pin and the enable function pin. By raising or lowering the voltage of the function pins of the chip, to determine whether the gain parameter output function of the chip is qualified, it includes:

[0151] Among the function pins of the chip, there is an enable function pin (such as pin 10 of function pin TST3), which is used to connect to the FOVI100 resource of the tester to provide voltage, and there are also gain parameter function pins (such as pin 8 of function pin TST1 and pin 9 of function pin TST2).

[0152] Control the voltage of pin 10 of function pin TST3 of the chip to change from the third voltage to the fourth voltage. The third voltage and the fourth voltage can be preset. The time period during which the voltage of pin 10 of function pin TST3 changes from the third voltage to the fourth voltage is used as the second time period, and obtain the output voltage difference between pin 8 of function pin TST1 and pin 9 of function pin TST2 of the chip within the second time period. Among them, the output voltage difference between pin 8 of function pin TST1 and pin 9 of function pin TST2 within the second time period represents the difference between the voltage output by pin 8 of function pin TST1 and the voltage output by pin 9 of function pin TST2 within the second time period.

[0153] Determine whether the output voltage difference between pin 8 of function pin TST1 and pin 9 of function pin TST2 of the chip within the second time period is within the first preset range. Among them, the first preset range can be set according to actual needs. For example, the first preset range is from -18 mV to 18 mV. When the output voltage difference of the gain parameter function pins (pin 8 of function pin TST1 and pin 9 of function pin TST2) of the chip within the second time period is within the first preset range, determine that the gain parameter output function of the chip is qualified. If the output voltage difference of the gain parameter function pins (pin 8 of function pin TST1 and pin 9 of function pin TST2) within the second time period is not within the first preset range, determine that the gain parameter output function of the chip is unqualified.

[0154] In an optional example, after the above trimming test, the voltage of the function pin TST3 pin 10 of the chip is changed from a high voltage to a low voltage. At this time, it is judged whether the output voltage difference between the function pin TST1 pin 8 and the function pin TST2 pin 9 of the chip is between -18 mV and 18 mV. When the output voltage difference between the function pin TST1 pin 8 and the function pin TST2 pin 9 of the chip is between -18 mV and 18 mV, it is determined that the gain parameter output function of the chip is qualified.

[0155] In a possible implementation manner, in step S143, the function pins of the chip include differential input function pins and voltage peak function pins. By controlling the waveform frequency of the function pins of the chip, it is judged whether the voltage peak output function of the chip is qualified, including:

[0156] Controlling the waveform frequency of the differential input function pins of the chip to change from a first frequency to a second frequency;

[0157] Obtaining the output voltage peak value of the voltage peak function pin of the chip within a third time period, where the third time period is the time period when the waveform frequency of the differential input function pin of the chip changes from the first frequency to the second frequency;

[0158] Calculating the output voltage peak ratio of the voltage peak function pin within the third time period according to the output voltage peak value of the voltage peak function pin within the third time period;

[0159] Judging whether the output voltage peak ratio of the voltage peak function pin of the chip within the third time period is within a second preset interval;

[0160] When the output voltage peak ratio of the voltage peak function pin of the chip within the third time period is within the second preset interval, it is determined that the voltage peak output function of the chip is qualified.

[0161] Specifically, the function pins of the chip include differential input function pins and voltage peak function pins. By controlling the waveform frequency of the function pins of the chip, it is judged whether the voltage peak output function of the chip is qualified, including:

[0162] The function pins of the chip include differential input function pins (such as function pin TST2 pin 9 and function pin TST3 pin 10), and voltage peak function pins (function pin VOUT pin 3). Among them, the differential input function pins appear in pairs and are used to receive differential signals. The differential signal is a signal form that transmits information through the voltage difference between two signal lines. The differential input function pins can effectively suppress common-mode noise and improve the anti-interference ability of the signal. The voltage peak function pin is used to output voltage.

[0163] By externally connecting an auxiliary THS4131 differential chip and the ACSM board of the tester to provide a sine wave waveform to the chip, the waveform frequency of the differential input function pins of the chip (function pin TST2 pin 9 and function pin TST3 pin 10) is changed from the first frequency to the second frequency. Among them, the first frequency and the second frequency can be set in advance according to actual needs. The time period during which the waveform frequency of the differential input function pins of the chip changes from the first frequency to the second frequency is used as the third time period.

[0164] Since the waveform frequency changes from the first frequency to the second frequency, the voltage peak function pin of the chip (function pin VOUT pin 3) will output waveforms with different voltage peaks during the third time period, and all the output voltage peaks of the voltage peak function pin during the third time period are obtained.

[0165] According to the current output voltage peak and the previous output voltage peak of the voltage peak function pin during the third time period, the current output voltage peak ratio of the voltage peak function pin during the third time period is calculated.

[0166] It is judged whether the output voltage peak ratio of the voltage peak function pin of the chip during the third time period is within the second preset interval. When all the output voltage peak ratios of the voltage peak function pin of the chip during the third time period are within the second preset interval, it is determined that the voltage peak output function of the chip is qualified. When there is an output voltage peak ratio of the voltage peak function pin of the chip during the third time period that is not within the second preset interval, it is determined that the voltage peak output function of the chip is unqualified.

[0167] In an optional example, the AC waveform frequencies of the function pin TST2 pin 9 and the function pin TST3 pin 10 of the chip are multiple AC waveforms such as 100KHz, 200KHz, and 1Vpp. At this time, the function pin VOUT pin 3 of the chip outputs waveforms with different voltage peaks, and all the output voltage peaks of the function pin VOUT pin 3 are obtained as 1.36V - 2.08V. The output voltage peak ratios of all the function pin VOUT pin 3 are calculated, and it is judged whether each output voltage peak ratio of the function pin VOUT pin 3 is within the second preset interval from -1.94 to -0.02DB. When all the output voltage peak ratios of the function pin VOUT pin 3 are between the second preset interval from -1.94 to -0.02DB, it is determined that the voltage peak output function of the chip is qualified. When there is an output voltage peak ratio of the function pin VOUT pin 3 that is not between the second preset interval from -1.94 to -0.02DB, it is determined that the voltage peak output function of the chip is qualified.

[0168] It should be noted that the tester can simultaneously test multiple chips. One station of the tester can test one chip, and multiple stations can simultaneously test multiple chips. Each station does not interfere with each other, enabling the simultaneous testing of multiple chips, improving the efficiency of chip testing, and reducing the testing cost.

[0169] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0170] Corresponding to the method described in the above embodiments, Figure 6 The structural schematic diagram of a chip testing device provided by an embodiment of the present application is shown. For the sake of convenience of description, only the parts related to the embodiments of the present application are shown.

[0171] Referring to Figure 6 , the device includes:

[0172] A chip memory response value determination module 21, configured to determine the memory response values corresponding to the respective multiple pin parameters of the chip in response to a trimming test instruction for the chip;

[0173] A chip data reading module 22, configured to obtain the memory write values corresponding to the respective multiple pin parameters in the chip in response to a reading instruction for the chip after determining that the chip has been programmed;

[0174] A chip trimming test module 23, configured to determine whether the chip passes the trimming test according to the memory write values and the memory response values corresponding to the respective multiple pin parameters;

[0175] A chip output function determination module 24, configured to determine whether the output function of the chip is qualified by controlling the voltage or waveform frequency of the multiple pins of the chip when it is determined that the chip passes the trimming test;

[0176] A chip overall determination module 25, configured to determine that the chip is qualified when the output function of the chip is qualified.

[0177] It should be noted that for the information interaction, execution process, etc. between the above devices / units, since they are based on the same concept as the method embodiments of the present application, their specific functions and the technical effects brought about can be specifically referred to in the method embodiment part, and will not be elaborated here.

[0178] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiments can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of this application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated here.

[0179] An embodiment of this application also provides a test device for a chip. The device includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor. When the processor executes the computer program, the steps in any of the foregoing method embodiments are implemented.

[0180] An embodiment of this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in each of the foregoing method embodiments can be implemented.

[0181] An embodiment of this application provides a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal is caused to execute the steps in each of the foregoing method embodiments.

[0182] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above method embodiments of this application, a computer program can be used to instruct relevant hardware to complete. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the photographing device / terminal device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disc, etc. In some jurisdictions, according to legislation and patent practice, the computer-readable medium cannot be an electrical carrier signal and a telecommunication signal.

[0183] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0184] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0185] In the embodiments provided in this application, it should be understood that the disclosed device / network device and method can be implemented in other ways. For example, the device / network device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in an electrical, mechanical or other form.

[0186] The unit described as the separation component may or may not be physically separated. The component displayed as a unit may or may not be a physical unit, that is, it may be located in one place or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0187] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A chip testing method, characterized in that: include: In response to a chip adjustment test instruction, determining a memory response value corresponding to each of a plurality of pin parameters of the chip; After determining that the chip is programmed, in response to a read instruction for the chip, obtaining a memory write value in the chip corresponding to each of the plurality of pin parameters; Determining whether the chip passes the trimming test according to the memory write values ​​and the memory response values ​​corresponding to the plurality of pin parameters respectively; When it is determined that the chip has passed the trimming test, determining whether the output function of the chip is qualified by controlling the voltage or waveform frequency of a plurality of pins of the chip; When the output function of the chip is qualified, the chip is determined to be qualified; The step of determining the memory response values ​​corresponding to the plurality of pin parameters of the chip in response to the chip adjustment test instruction includes: In response to the adjustment test instruction for the chip, sending different write waveform instructions to the chip, wherein the write waveform instructions carry transition point time information, and the transition point time information includes the transition point time of the write waveform instructions; Determining a target write waveform instruction according to target parameter values ​​of a plurality of pin parameters of the chip; For any one of the pin parameters, data conversion processing is performed on the jump point time of the target write waveform instruction to obtain a binary jump point time, the binary jump point time is divided by the preset baud rate of the chip to obtain a binary memory response value, and the binary memory response value is converted to obtain a decimal memory response value as the memory response value corresponding to any one of the pin parameters.

2. The chip testing method according to claim 1, characterized in that: Before determining the memory response values ​​corresponding to the plurality of pin parameters of the chip in response to the chip adjustment test instruction, the method further includes: Acquire the voltage of each functional pin of the chip in a first state, wherein the first state is determined by the time for which a preset current is applied to each functional pin of the chip; Obtaining a static current of a power pin of the chip in a second state, wherein the second state is determined by a time for applying a preset voltage to the power pin of the chip; Judging whether the DC parameters of the chip are qualified according to the static current of the power pin in the second state and the voltage of each of the functional pins in the first state; When it is determined that the DC parameters of the chip are qualified, a trimming and testing instruction for the chip is issued.

3. The chip testing method according to claim 1, characterized in that: The step of judging whether the chip passes the trimming test according to the memory write value and the memory response value respectively corresponding to the plurality of pin parameters includes: Determining whether the writing results of the pin parameters of the chip are correct according to the memory write values ​​and the memory response values ​​corresponding to the pin parameters in the chip; When the writing results of all the pin parameters of the chip are correct, it is determined that the chip has passed the trimming test.

4. The chip testing method according to claim 1, characterized in that: The step of determining whether the output function of the chip is qualified by controlling the voltages or waveform frequencies of the plurality of pins of the chip comprises: By increasing or decreasing the voltage of the power pin of the chip, determining whether the voltage jump output function of the chip is qualified; By increasing or decreasing the voltage of the function pin of the chip, determining whether the gain parameter output function of the chip is qualified; By controlling the waveform frequency of the functional pin of the chip, determining whether the voltage peak output function of the chip is qualified; In the case where it is determined that the voltage jump output function, the gain parameter output function and the voltage peak output function of the chip are all qualified, it is determined that the output function of the chip is qualified.

5. The chip testing method according to claim 4, characterized in that: The functional pins of the chip include Hall voltage functional pins; The step of judging whether the voltage jump output function of the chip is qualified by increasing or decreasing the voltage of the power pin of the chip comprises: Controlling the voltage of the power pin of the chip to change from a first voltage to a second voltage; Obtaining the output voltage of the Hall voltage function pin of the chip within a first time period, wherein the first time period is a time period in which the voltage of the power pin of the chip changes from a first voltage to a second voltage; Determine whether there is a jump in the output voltage of the Hall voltage function pin of the chip within the first time period; When the output voltage of the Hall voltage function pin of the chip jumps, it is determined that the voltage jump output function of the chip is qualified.

6. The chip testing method according to claim 4, characterized in that: The functional pins of the chip include a gain parameter functional pin and an enable functional pin; The step of judging whether the gain parameter output function of the chip is qualified by increasing or decreasing the voltage of the function pin of the chip comprises: Controlling the voltage of the enable function pin of the chip to change from a third voltage to a fourth voltage; Obtaining an output voltage difference of the gain parameter function pin of the chip within a second time period, wherein the second time period is a time period in which the voltage of the enable function pin of the chip changes from a third voltage to a fourth voltage; Determine whether the output voltage difference of the gain parameter function pin of the chip in the second time period is within a first preset interval; When the output voltage difference of the gain parameter function pin of the chip in the second time period is within the first preset interval, it is determined that the gain parameter output function of the chip is qualified.

7. The chip testing method according to claim 4, characterized in that: The functional pins of the chip include differential input functional pins and voltage peak functional pins, and the process of controlling the waveform frequency of the functional pins of the chip to determine whether the voltage peak output function of the chip is qualified includes: Controlling the waveform frequency of the differential input function pin of the chip to change from a first frequency to a second frequency; Obtaining an output voltage peak value of the voltage peak function pin of the chip within a third time period, wherein the third time period is a time period in which the waveform frequency of the differential input function pin of the chip changes from a first frequency to a second frequency; According to the output voltage peak value of the voltage peak function pin in the third time period, calculate and obtain the output voltage peak value ratio of the voltage peak function pin in the third time period; Determine whether the output voltage peak ratio of the voltage peak function pin of the chip in the third time period is within a second preset interval; When the output voltage peak ratio of the voltage peak function pin of the chip in the third time period is within the second preset interval, it is determined that the voltage peak output function of the chip is qualified.

8. A chip testing device, characterized in that: include: A chip memory response value determination module, for determining memory response values ​​corresponding to respective pin parameters of the chip in response to a chip adjustment test instruction; A chip data reading module, for obtaining the memory write values ​​corresponding to the plurality of pin parameters in the chip in response to a read instruction to the chip after determining that the chip is programmed; A chip trimming test module, used for judging whether the chip passes the trimming test according to the memory write value and the memory response value respectively corresponding to the plurality of pin parameters; A chip output function judgment module is used to judge whether the output function of the chip is qualified by controlling the voltage or waveform frequency of multiple pins of the chip when it is determined that the chip has passed the adjustment test; A chip overall judgment module, used to judge that the chip is qualified when the output function of the chip is qualified; The chip memory response value determination module is specifically used for: In response to the adjustment test instruction for the chip, sending different write waveform instructions to the chip, wherein the write waveform instructions carry transition point time information, and the transition point time information includes the transition point time of the write waveform instructions; Determining a target write waveform instruction according to target parameter values ​​of a plurality of pin parameters of the chip; For any one of the pin parameters, data conversion processing is performed on the jump point time of the target write waveform instruction to obtain a binary jump point time, the binary jump point time is divided by the preset baud rate of the chip to obtain a binary memory response value, and the binary memory response value is converted to obtain a decimal memory response value as the memory response value corresponding to any one of the pin parameters.

9. A chip testing device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

Images