Space-based edge intelligent acceleration processing system

Abstract

The application discloses a space-based edge intelligent acceleration processing system and relates to the technical field of space-based communication equipment.The system comprises a double-heterogeneous AI module, an intelligent management and control unit, a health management unit and a power supply unit.The double-heterogeneous AI module comprises a first AI acceleration processing unit and a second AI acceleration processing unit, and is connected with the power supply unit.The intelligent management and control unit is connected with the first AI acceleration processing unit, the second AI acceleration processing unit, the health management unit and the power supply unit.The health management unit is connected with the first AI acceleration processing unit, the second AI acceleration processing unit and the power supply unit.The application applies AI chips to space-based edge intelligent acceleration calculation, realizes space-based intelligent calculation, space-based edge computing power balance, endogenous AI hardware support, and greatly improves the on-orbit data analysis, processing and edge autonomy of space-based edge equipment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of space-based communication equipment, and more particularly to a space-based edge intelligent acceleration processing system. BACKGROUND

[0002] With the substantial improvement of satellite performance and the data explosion brought by large-scale constellation, satellite data downlink and satellite technology application are facing problems such as insufficient communication bandwidth between satellite and ground, limited ground base station resources and coverage. At the same time, due to the increasing complexity of satellite tasks, there are often sudden situations and changes in operating environment, so the use of intelligent acceleration technology on the spaceborne edge device to extract key information and filter redundant information not only improves the communication bandwidth efficiency, but also further improves the autonomous control and autonomous decision-making ability of the edge, promoting the intelligent development of satellite control and scheduling.

[0003] In the past two years, the ground artificial intelligence has developed explosively, comprehensively promoting the multi-ecological integration of AI and various industry technologies, and a trend of AI leading the technological revolution in various industries has emerged globally. At the same time, AI technology, industry and application have entered a period of rapid iteration and breakthrough exploration. China has also made rapid development in the field of AI technology, especially domestic high-performance special AI chips, which have achieved breakthrough development and wide application in the field of intelligent acceleration computing through their outstanding computing power, optimized algorithms and powerful data models.

[0004] Therefore, how to apply AI chips to the intelligent acceleration of spaceborne edge devices to further improve the data processing capability and intelligent degree of spaceborne edge devices is a problem that needs to be solved by those skilled in the art. SUMMARY

[0005] Therefore, the present application provides a space-based edge intelligent acceleration processing system, which applies AI chips to space-based edge intelligent acceleration computing, meets the demand for large-scale computing power and large data models in terms of complex task processing of low earth orbit satellites, multi-satellite cooperation in emergency situations, intelligent scheduling of distributed edge computing node tasks, intelligent management and control of spaceborne services, and realizes space-based intelligent computing, space-based edge computing power balancing, and hardware support for endogenous AI, greatly improving the on-orbit data analysis, processing and edge autonomy of space-based edge devices.

[0006] In order to achieve the above purpose, the present application adopts the following technical solutions:

[0007] A space-based edge intelligent acceleration processing system, comprising: a dual-heterogeneous AI module, an intelligent management and control unit, a health management unit and a power supply unit; the dual-heterogeneous AI module comprises a first AI acceleration processing unit and a second AI acceleration processing unit, which are connected to the power supply unit respectively; the intelligent management and control unit is connected to the first AI acceleration processing unit, the second AI acceleration processing unit, the health management unit and the power supply unit respectively; the health management unit is connected to the first AI acceleration processing unit, the second AI acceleration processing unit and the power supply unit respectively.

[0008] Preferably, the first AI acceleration processing unit comprises an NPU chip, a first SPI Flash circuit and a memory circuit, the first SPI Flash circuit adopts a board-mounted Flash chip mounted on the SPI bus of the NPU chip for storing NPU chip-related configuration information, and the memory circuit adopts a board-mounted LPDDR4 particle connected to the 96-bit LPDDR4X controller integrated in the NPU chip for storing processing data, with a maximum support of 12 GB; the second AI acceleration processing unit comprises a GPGPU chip and a second SPI Flash circuit, the second SPI Flash circuit adopts a board-mounted Flash chip mounted on the SPI bus of the GPGPU chip for storing GPGPU chip-related configuration information, and the GPGPU chip itself stores a HBM2E memory with a bandwidth support of 800 GB / s and a capacity of 32 GB for storing processing data; the NPU chip and the GPGPU chip are connected to the intelligent management and control unit through a high-speed data bus.

[0009] Preferably, the intelligent management and control unit comprises an FPGA chip, a configuration circuit, an information storage circuit, a PCIe interface circuit, a GPIO interface and an I 2 C interface; the configuration circuit adopts a board-mounted NOR Flash chip directly connected to the FPGA chip; the information storage circuit adopts a board-mounted DDR3 storage particle connected to the DDR3 memory controller inside the FPGA chip; the PCIe interface circuit is connected to the PCI bus interface of the FPGA chip; the GPIO interface is connected to the FPGA chip and connected to the GPIO interfaces of the NPU chip and the GPGPU chip respectively; the I 2 C interface is connected to the FPGA chip and the health management unit respectively. The FPGA chip inside uses its logic unit to identify and judge the on-board task data, classifies the on-board task data into low-level data and high-level data, transmits the low-level data to the NPU chip for processing, and transmits the high-level data to the GPGPU chip for processing; the low-level data includes image recognition task data, intelligent optimization task data, etc., and the high-level data includes target recognition task data, planning task data, intelligent control task data, etc.

[0010] Preferably, the FPGA is connected with the space-based edge device, the NPU chip and the GPGPU chip respectively through the PCIe bus, and is connected with the NPU chip and the GPGPU chip respectively through the GPIO interface, so as to intelligently control the acceleration processing system; the PCIe bus is used to realize data transmission with the space-based edge device, to realize distribution of different levels of task data of the NPU chip and the GPGPU chip on the satellite and return of the task acceleration results generated by the NPU chip and the GPGPU chip; the GPIO interface is used to realize identification of the online state of the double-heterogeneous AI module and the task designation function of the intelligent control unit. The GPIO interface can identify whether the NPU chip or the GPGPU chip has the state of processing the task, and by pulling up or pulling down a certain pin of the NPU chip or the GPGPU chip through the GPIO interface, the working state of the two chips can be read by the FPGA chip in the later stage, so as to realize the task designation.

[0011] Preferably, the health management unit comprises an embedded MCU and a plurality of temperature sensors, the temperature sensors are connected with the embedded MCU, the embedded MCU is connected with the space-based edge device through an IPMB bus, and the temperature sensors are connected with the embedded MCU through an I 2 C bus is connected with the I 2 C interface (realizing connection with the FPGA chip), the NPU chip and the GPGPU chip, and the embedded MCU is connected with the space-based edge device through an IPMB bus; the temperature sensors collect temperature and transmit the temperature to the embedded MCU, and an ADC converter integrated in the embedded MCU collects voltage.

[0012] Preferably, an anti-radiation protective cover based on tantalum-tungsten-aluminum composite material is arranged outside the double-heterogeneous AI module.

[0013] Compared with the prior art, the technical scheme provided by the application discloses a space-based edge intelligent acceleration processing system, special AI chips based on domestic NPU and GPGPU two kinds of heterogeneous computing resources, through the enhancement processing of high-performance domestic FGPA on the video, image and other information on the satellite and the control of the heterogeneous computing power of the double special AI chips, the acceleration ability of intelligent computing of the space-based edge device in processing massive video, picture tasks and the autonomous decision-making ability in dealing with complex tasks and emergency situations are realized, in addition, the health information management function of the intelligent acceleration processing module is realized through the high reliability MCU, which provides hardware support for the device state visualization between the satellite and the ground, and the power supply unit provides the required power voltage for the unit of the space-based edge intelligent acceleration processing system. Among them, the intelligent acceleration processing architecture based on domestic NPU+GPGPU double heterogeneous computing resources in the application supports multiple deep learning frameworks, has a wide range of deep learning algorithm models, has continuously optimized operator units and acceleration components, and supports the rapid iteration of various application algorithms on the satellite; the FPGA+heterogeneous AI bidirectional data transmission mode realizes the intelligent management and control and task distribution of double heterogeneous computing resources without passing through the switching chip, and the FPGA intelligently schedules according to the complexity of the task, further accelerating the timeliness of the space-based edge device in processing complex tasks, and improving the load balancing capability of the space-based edge device. As can be seen from the above, the application accelerates the timeliness of the on-board computer in real-time analyzing and processing massive video, picture and other information in space through the special architecture and algorithm optimization of the intelligent acceleration processing module, improves the on-orbit computing and task autonomous planning capability of the satellite, helps the satellite constellation to develop into an independent operation body that can be self-controlled and managed, and promotes the intelligent development of space-based communication. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only embodiments of the application, and for those skilled in the art, other drawings can be obtained without creative labor based on the provided drawings.

[0015] Figure 1 The space-based edge intelligent acceleration processing system structure schematic diagram provided by the application is shown in the figure.

[0016] Figure 2 The space-based edge intelligent acceleration processing system data flow control topology schematic diagram provided by the application is shown in the figure.

[0017] Figure 3 The heterogeneous resource control and information preprocessing unit-data processing flowchart provided by the application is shown in the figure.

[0018] Figure 4 The power supply principle block diagram of the space-based edge intelligent acceleration processing system provided by the application is shown in the figure. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the application.

[0020] The embodiment of the application discloses a space-based edge intelligent acceleration processing system, and the structure is shown in the figure. Figure 1 The space-based edge intelligent acceleration processing system comprises a dual-heterogeneous AI module, an intelligent management and control unit, a health management unit and a power supply unit. The dual-heterogeneous AI module comprises a first AI acceleration processing unit and a second AI acceleration processing unit, which are connected to the power supply unit. The intelligent management and control unit is connected to the first AI acceleration processing unit, the second AI acceleration processing unit, the health management unit and the power supply unit. The health management unit is connected to the first AI acceleration processing unit, the second AI acceleration processing unit and the power supply unit.

[0021] Further, the first AI acceleration processing unit adopts an NPU chip, the second AI acceleration processing unit adopts a GPGPU chip, and the NPU chip and the GPGPU chip are connected to the intelligent management and control unit through a high-speed data bus. The domestic NPU and the domestic GPGPU special AI chip are used as the core processing unit of the space-based edge intelligent acceleration processing module, and provide heterogeneous computing power resources for different task requirements for the space-based edge device. By virtue of the large data model, the deep learning acceleration operator library, the acceleration tool chain and other components and optimized intelligent algorithms integrated in the two special AI chips, the ability of the space-based edge device to process massive video, pictures and other complex intelligent computing tasks is improved, the processing timeliness of the space-based edge device in the AI computing application scenario is accelerated, the space-based edge device has certain edge autonomy when processing emergencies, and intelligent scheduling and autonomous decision-making can be realized. The space-based edge device provides hardware support for realizing the star-ground collaborative scheduling algorithm, the intelligent routing and the multi-dimensional fusion intelligent communication application of the space-based edge device. Meanwhile, by virtue of the strong edge computing capability of the special AI chip, the space-based edge device has higher data privacy and security, and is especially suitable for the application of the space-based edge node.

[0022] Further, the first AI acceleration processing unit includes an NPU chip, a first SPI Flash circuit, and a memory circuit. The first SPI Flash circuit adopts a board-mounted Flash chip mounted on an SPI bus of the NPU chip for storing NPU chip-related configuration information. The memory circuit adopts a board-mounted LPDDR4 particle connected to a 96-bit LPDDR4X controller integrated in the NPU chip for storing processing data, with a maximum support of 12 GB. The second AI acceleration processing unit includes a GPGPU chip and a second SPI Flash circuit. The second SPI Flash circuit adopts a board-mounted Flash chip mounted on an SPI bus of the GPGPU chip for storing GPGPU chip-related configuration information. The GPGPU chip itself encapsulates a HBM2E memory with a bandwidth support of 800 GB / s and a capacity of 32 GB for storing processing data.

[0023] Further, the dual-isomorphic AI module adopts an NPU chip of model Ascend 310B and a GPGPU chip of model ZhiGai 100. The two kinds of isomorphic special AI chips serve as core processing devices of the space-based edge intelligent acceleration processing system, helping the intelligent acceleration processing system and even the space-based edge device to realize AI acceleration processing functions for different task requirements and to have the ability to make autonomous decisions for tasks caused by emergency situations, environmental changes, and the like at any time. The NPU chip has a computing power of up to 20 TOPS and can perform complex image recognition, intelligent optimization, and the like. The GPGPU chip has a computing power of up to 192 TOPS and can perform complex target recognition, task planning, intelligent control, and the like. Therefore, the two AI acceleration processing units independently run, have different divisions of labor, and process suitable tasks through respective architecture advantages, big data models, deep learning acceleration operator libraries, acceleration tool chains, deep learning optimization engines, and the like. The number of core codes is reduced, and the characteristics of coping with operator diversity are provided. The hardware foundation is provided for the collaborative cooperation of the isomorphic computing power of the space-based edge intelligent acceleration processing module, the AI load balancing and intelligent scheduling of the space-based edge device.

[0024] Further, the NPU chip supports 8Lane SerDes, which is distributed in 2 SerDes Macro, and can realize flexible configuration of GE, USB 3.0, PCIe (supporting EP / RC) and SATA according to different product application scenarios. As a slave device of the intelligent management and control unit, the chip needs to configure the SerDes into the PCIe EP use scenario, and the SerDes configuration in the NPU EP mode is shown in Table 1, and the PCIE_EP_RC_FLASH pin is configured as high level to realize the capability of the intelligent management and control unit as a slave device, and then complete the interaction of data information; the GPGPU chip provides 1 PCIe 4.0 x 16 bus interface, which is downward compatible, and uses its x8 lane to directly connect with the PCIe bus of the intelligent management and control unit to realize the interaction of data information.

[0025] Table 1 NPU SerDes configuration (EP) mode

[0026]

[0027] Further, the debugging interface of the dual-heterogeneous AI module is mainly based on UART and JTAG, wherein the NPU chip has 7 UART interfaces inside, the GPGPU chip has 2 UART interfaces and 1 JTAG interface inside; the UART interface realizes online printing function based on RS422 level after level conversion by LevelShift; the JTAG interface is directly led out; the debugging interface of the dual-heterogeneous AI module is led out through the front panel, which is convenient for debugging.

[0028] Further, the intelligent management and control unit adopts an FPGA chip; as shown in Figure 2 , the FPGA chip is connected with the NPU chip and the GPGPU chip. The FPGA chip receives or reports the on-board task data through the PCIe bus, uses the internal logic unit to identify and judge the on-board task data, allocates the image recognition, intelligent optimization and other tasks with relatively low complexity to the AI acceleration processing unit based on domestic NPU, allocates the target recognition, task planning, intelligent control and other tasks with relatively high complexity to the AI acceleration processing unit based on domestic GPGPU, and realizes intelligent allocation of different task levels on board. The intelligent management and control of the dual-heterogeneous computing AI acceleration processing unit by the FPGA is realized through the PCIe bus and the GPIO interface, wherein the PCIe bus is used to realize distribution of different levels of on-board task data of the dual-heterogeneous computing AI acceleration processing unit and return of task acceleration results; the GPIO interface is used to realize online identification and task designation function of the intelligent management and control unit to the dual-heterogeneous AI module.

[0029] Further, the intelligent management and control unit adopts a domestic V7 series FPGA, mainly realizes the enhancement preprocessing function of massive video and picture task information from the star, the intelligent allocation function for tasks with different complexities, and the management and control function of heterogeneous computing resources.

[0030] The intelligent management and control unit first receives massive AI task information to be processed from the space-based edge device through a high-speed bus; secondly, relying on its high-speed parallel operation processing unit, the unit has high-performance digital signal processing capability and high-bandwidth data throughput capability, and pre-processes the video, picture and other information to be processed, realizes the enhancement of task information, reduces the load burden of the AI computing unit, and improves the timeliness of the AI computing unit; thirdly, through its rich programmable logic resources, the unit intelligently judges the task complexity of the information to be processed in combination with the current on-board task, and labels the information to be processed, and intelligently allocates the information and tasks according to the labeled task complexity, wherein the tasks with low complexity such as image recognition and intelligent optimization are allocated to the AI acceleration processing unit based on the domestic NPU, and the tasks with high complexity and high computing power such as target recognition, task planning and intelligent control, especially emergency tasks, are allocated to the AI acceleration processing unit based on the domestic GPGPU, thereby improving the energy efficiency and utilization rate of the two independently running intelligent processing units, accelerating the computing timeliness of the space-based edge device; finally, the data processed by the dual-heterogeneous AI module is recycled and packaged, and is transmitted to the space-based edge device through the high-speed bus. Thus, the preprocessing, management and control distribution and result feedback process of an AI computing task are completed. At the same time, through the I 2 The C interface is directly connected with the health management unit, and the health management unit reads the health information.

[0031] The preprocessing includes first converting the picture data into digital signals by using the ADC converter in the FPGA chip, then performing image filtering by using various filter algorithms provided in the FPGA chip, performing edge detection and image enhancement by using various edge algorithms provided in the FPGA chip, and finally converting the digital signals into analog signals by using the DAC converter in the FPGA chip, and transmitting the analog signals to the NPU chip or the GPGPU chip.

[0032] Further, the intelligent management and control unit is provided with a configuration circuit, an information storage circuit, a PCIe interface circuit, a GPIO interface, an I 2C interface and debugging interface, etc.; wherein, the configuration circuit adopts a board-mounted NOR Flash chip, which is directly connected to the FPGA chip, and uses JTAG, AS and other configuration methods to download the required configuration program into the Flash, thereby realizing the configuration management of the FPGA. The AS refers to the active serial mode, which realizes the online printing function based on the RS422 level after the UART interface is converted by the Level Shift level conversion. The programming data of the logic blocks and interconnections of the FPGA are defined by the configuration circuit, so that when the FPGA is powered on, such data is loaded into the device, thereby realizing the ability of the FPGA to perform predetermined functions. The information storage circuit adopts a board-mounted DDR3 memory particle connected to the DDR3 memory controller inside the FPGA chip, thereby realizing the high-speed data transmission, caching and parallel processing functions of the intelligent management and control unit, with a maximum speed of 1866Mb / s and an ECC error checking function. The PCIe interface circuit is connected to the three PCI bus interfaces of the FPGA chip, which supports PCIe3.0x8 at maximum. The AI computing task of the space-based edge device enters the intelligent management and control unit through the PCIe interface circuit and PCIe bus interface, is preprocessed and controlled and distributed, is distributed to the dual-heterogeneous AI module through the PCIe bus, and then the data information processed by the dual-heterogeneous AI module is returned to the intelligent management and control unit, which is fed back to the space-based edge device after being packaged. 2 The C interface is directly connected to the I 2 The C interface is connected, and the health management unit realizes real-time collection of information such as working state, thereby realizing real-time monitoring and reset, power-on control, etc. of the working state of the intelligent management and control unit. The debugging interface mainly includes a USB interface and an LVDS interface. The USB interface is directly configured and output by the FPGA chip, so ESD protection is needed. In addition, the LVDS interface level of the FPGA chip is 1.8V, which is different from the standard LVDS interface 1.2V level, so Level Shift is needed for level conversion to realize display output function. The debugging interface is led to the front panel connector, which is convenient for debugging.

[0033] Further, the health management unit includes an embedded MCU and a plurality of temperature sensors. The sensors are connected to the embedded MCU, and the embedded MCU is connected to the intelligent management and control unit through the I 2The C bus is connected with the FPGA chip, the NPU chip and the GPGPU chip respectively, and is connected with the space-based edge device through the IPMB bus; the temperature sensor collects temperature, and the ADC converter integrated in the embedded MCU collects voltage. Based on the domestic high-reliability embedded MCU, the on-board sensor device is matched, the key voltage, temperature and other information on the space-based edge intelligent acceleration processing system are monitored in real time, the health management unit reports the health status information to the space-based edge device through the IPMB bus, realizes the working state alarm function of the processing module, has the power-on, reset and other control capabilities, and provides a hardware basis for the health management of the space-based edge device. The NPU chip has 7 I 2 C interfaces, supports 1-way Slave and 6-way Master, the GPGPU chip has 4 I 2 C interfaces, supports 1-way Slave and 3-way Master, the NPU chip and the GPGPU chip are connected through I 2 C bus and the embedded MCU, the health management unit realizes reading of the health information of the double-heterogeneous AI module, realizes real-time monitoring of the working state of the double-heterogeneous AI module, reset, power-on timing control and the like; the embedded MCU is also connected with the over-voltage, under-voltage and over-temperature protection module, and sends a reset signal to the over-voltage, under-voltage and over-temperature protection module to control the reset thereof.

[0034] Further, the health management unit selects the domestic 32F4 series embedded MCU based on ARM Cortex-M432 bit RISC kernel, realizes real-time monitoring of the working state of the space-based edge intelligent acceleration processing system through I 2 C bus, in addition, the voltage of the key point is collected through the internally integrated ADC converter, the collected voltage and temperature are converted into analog voltage, temperature parameters and other information, and according to the set threshold, the pre-warning judgment is carried out, the pre-warning information is generated and reported to the space-based edge device, and the fault pre-warning function is realized. The monitored units are directly mounted on the health management unit through respective I 2 C bus, complete the working state reporting and accept the power-on, reset and other function control.

[0035] Further, the embedded MCU has a perfect minimum system circuit, including clock circuit, Flash storage circuit and BOOT starting, RST configuration circuit; the embedded MCU supports three clock sources of HIS, HSE, main PLL to drive the internal system clock SYSCLK, and has two secondary clock sources of 32 kHz and 32.768 kHz, in the embodiment, the HSE clock source (25 MHz) of the external crystal oscillator with higher precision can be used to drive the system clock (168 MHz) of the ARM, the internal PLL frequency multiplication, frequency division and the like are used to realize various clocks required by the APB bus peripherals (such as ADC), in addition, the LSE crystal oscillator of 32.768 kHz is used as the clock source of the ARM real-time clock RTC, so that the health management unit can record the system time in real time; the Flash storage circuit supports 128-bit wide data reading capability, is realized by hanging the SPI data type Flash chip on the SPI bus interface of the embedded MCU, and is used for the data information caching of the health management unit; the BOOT starting, RST configuration circuit is used for configuring the BOOT1 and BOOT0 pins, the MCU chip starting mode is controlled by the BOOT1 and BOOT0 pins, the 00 mode is set by pull-down, that is, the main Flash starting mode of the health management unit is realized; the MCU chip reset pin NRST is low effective, and the board key switch realizes the reset function of the health management unit.

[0036] Further, the health management unit has an I 2 C interface, ADC function circuit and corresponding debugging interface; 2 The I2C interface is used to realize the collection and reset of the working state of the double-isomorphic AI module and the intelligent processing unit and the control of the power-on sequence, the embedded MCU has three I2C bus interfaces, supports various purposes such as CRC production and verification, SMBus and PMBus, and in addition, supports the use of general GPIO interface to simulate I2C protocol to realize I2C function. 2 2 2 ​​The C bus function; the ADC function circuit realizes the collection and conversion of analog quantities such as main voltage parameters and temperature information, the MCU chip extracts and processes the converted digital signals, realizes the real-time monitoring of the voltage and temperature of the space-based edge intelligent computing module, the embedded MCU has a 12-bit successive approximation ADC converter, and has up to 19 multiplexing channels, of which the ADC[15:0] 16 channels can be provided externally, the ADC[13:0] 14 channels are connected to the voltage division processing circuit to collect 12V total voltage, NPU chip main voltage, GPGPU chip main voltage, FPGA chip main voltage, ADC[15:14] 2 channels collect temperature information close to the NPU chip temperature measuring point and GPGPU chip temperature measuring point, ADC16 is used to collect temperature information close to the FPGA chip temperature measuring point, and VREF is connected to the reference voltage. These channels support single, continuous, scanning or discontinuous sampling modes, and through the setting of the reference voltage (VREF=2.5V) and the voltage division processing, the analog quantity collection of 0~VREF is realized; the debugging interface is RS422 interface and SWD interface, wherein the RS422 interface realizes RS422 level after level conversion through Level Shift, supports online information printing, and the SWD interface is the SW debugging interface of the MCU, which can realize program download through SWCLK and SWDIO double lines. The debugging interface is connected to the front panel connector, which is convenient for debugging. The health management unit covers all voltage measurement points and temperature measurement points of the functional units, which is convenient for the work state early warning and real-time monitoring of the space-based edge intelligent acceleration processing system.

[0037] Further, the power supply unit provides corresponding power supply voltage for each functional unit of the space-based edge intelligent acceleration processing system, adopts a universal and modular design method, and ensures that the space-based edge intelligent acceleration processing system can operate stably and reliably.

[0038] Further, the domestic special AI chip itself does not have anti-radiation capability, so in the design and implementation, an anti-radiation shield based on tantalum-tungsten-aluminum composite material needs to be used for certain protection measures, so that it can be stably and reliably applied in space environment.

[0039] On the other hand, in one specific embodiment, the processing flow of the intelligent management and control unit is as follows Figure 3As shown, specifically: step 1: receiving the data cache of the on-orbit task of the space-based edge device, and performing enhancement processing; step 2: judging the task type of the enhanced data, and dividing the data into low-level tasks and high-level tasks; step 3: distributing the data contained in the low-level tasks to the NPU chip for processing to obtain the low-level task processing result, and distributing the data contained in the high-level tasks to the GPGPU chip for processing to obtain the high-level task processing result; and step 4: feeding back the low-level task processing result and the high-level task processing result to the space-based edge device.

[0040] On the other hand, in one specific embodiment, the structural framework of the power supply unit is as shown Figure 4 As shown, including three groups of power supply circuits and one group of current limiting protection circuits, each group of power supply circuits includes a first isolation DC / DC module, a current limiting and over / under voltage protection module, and a second isolation DC / DC module connected in sequence; the three groups of power supply circuits respectively connect the first AI acceleration processing unit, the second AI acceleration processing unit and the FPGA chip of the intelligent management and control unit to the 12V DC power supply; the health management unit is connected to the 12V DC power supply through the current limiting protection circuit, and the health management unit is respectively connected to the second isolation DC / DC module of the three groups of power supply circuits.

[0041] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between various embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0042] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A space-based edge intelligent acceleration processing system, comprising: Comprise: Dual-isomorphic AI module, intelligent management and control unit, health management unit and power supply unit; the dual-isomorphic AI module comprises a first AI acceleration processing unit and a second AI acceleration processing unit, which are connected with the power supply unit respectively; the intelligent management and control unit is connected with the first AI acceleration processing unit, the second AI acceleration processing unit, the health management unit and the power supply unit respectively; the health management unit is connected with the first AI acceleration processing unit, the second AI acceleration processing unit and the power supply unit respectively; The first AI acceleration processing unit comprises an NPU chip, a first SPI Flash circuit and a memory circuit, the first SPI Flash circuit adopts a board-mounted Flash chip mounted on an SPI bus of the NPU chip, and the memory circuit adopts a board-mounted LPDDR4 particle connected with a 96 bits LPDDR4X controller integrated in the NPU chip; the second AI acceleration processing unit comprises a GPGPU chip and a second SPI Flash circuit, the second SPI Flash circuit adopts a board-mounted Flash chip mounted on an SPI bus of the GPGPU chip, and the NPU chip and the GPGPU chip are connected with the intelligent management and control unit through a high-speed data bus; The intelligent management and control unit comprises an FPGA chip, a configuration circuit, an information storage circuit, a PCIe interface circuit, a GPIO interface and an I 2 C interface; the configuration circuit is directly connected to the FPGA chip by using a board-mounted NOR Flash chip; the information storage circuit is connected to a DDR3 memory controller inside the FPGA chip by using a board-mounted DDR3 storage particle; the PCIe interface circuit is connected to a PCI bus interface of the FPGA chip; The GPIO interface is connected with the FPGA chip, and is connected with the GPIO interfaces of the NPU chip and the GPGPU chip respectively; the I 2 The C interface is connected with the FPGA chip and the health management unit respectively.

2. The sky-based edge intelligent acceleration processing system of claim 1, wherein, The FPGA chip is connected with a space-based edge device, the NPU chip and the GPGPU chip through a PCIe bus respectively.

3. The sky-based edge intelligent acceleration processing system of claim 1, wherein, The health management unit comprises an embedded MCU and a plurality of temperature sensors connected to the embedded MCU, the embedded MCU being connected to a base station through an I 2 The C bus is connected to the I 2 C interface of the intelligent management and control unit, the NPU chip and the GPGPU chip, and the embedded MCU is connected to the space-based edge device through an IPMB bus.

4. The sky-based edge intelligent acceleration processing system of claim 1, wherein, An anti-radiation protective cover based on tantalum-tungsten-aluminum composite material is arranged outside the dual-isomorphic AI module.

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