Semiconductor device life prediction method, device, electronic equipment and medium

Abstract

The present disclosure relates to the field of semiconductor technology, and specifically to a method, device, electronic device and medium for predicting the life of a semiconductor device, the method comprising: obtaining parameter information of a semiconductor device through parameter pre-testing; constructing test conditions for performing life pre-testing on the semiconductor device according to the parameter information of the semiconductor device, so as to obtain life pre-testing data of the semiconductor device under different test conditions, determining the fastest degradation parameter among multiple target parameters and the fastest degradation test condition among different test conditions according to the life pre-testing data; the life test data is obtained by performing a formal life test on the semiconductor device using the fastest degradation parameter and the fastest degradation test condition; based on the life test data, the life of the semiconductor device is calculated by interpolation calculation or mathematical model fitting. The present disclosure can solve the problem of how to accurately predict the life of a semiconductor device whose degradation curve is easily saturated.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method, device, electronic equipment and medium for predicting the life of a semiconductor device. Background Art

[0002] Hot carriers include hot holes and hot electrons, which are the main failure mechanisms that affect the reliability of semiconductor processes. Hot carrier injection refers to the injection of high-energy carriers into the oxide layer through the silicon or silicon dioxide interface, generating interface states, oxide layer defects or being captured by traps, which in turn affects the channel carrier mobility and effective potential. Accelerated testing by applying voltage stress to the drain and gate is currently the main way to predict the life of semiconductor devices under the influence of hot carriers. However, due to the complexity of the design structure of some semiconductor devices (for example, 40V N-type laterally diffused metal oxide semiconductor, 40v NLDMOS), the long life of the device itself, it is not suitable for applying higher voltages, or the degradation curve is easy to reach saturation, resulting in the inability to directly obtain the device life through testing. Mathematical fitting and life derivation are required for the test data. The mathematical model used for fitting and derivation has become a key factor in accurately predicting the life of semiconductor devices. Summary of the invention

[0003] In order to solve the problems in the related art, the embodiments of the present disclosure provide a method, an apparatus, an electronic device and a medium for predicting the lifetime of a semiconductor device.

[0004] In a first aspect, an embodiment of the present disclosure provides a method for predicting the lifetime of a semiconductor device, comprising:

[0005] Acquiring parameter information of the semiconductor device, wherein the parameter information of the semiconductor device is acquired through parameter pre-testing;

[0006] constructing test conditions according to the parameter information of the semiconductor device, wherein the test conditions are used to perform a life pre-test on the semiconductor device to obtain life pre-test data of the semiconductor device under different test conditions, wherein the life pre-test data includes degradation data of a plurality of target parameters of the semiconductor device;

[0007] determining, according to the life pre-test data, a fastest degradation parameter among the plurality of target parameters and a fastest degradation test condition among the different test conditions;

[0008] Acquiring life test data, wherein the life test data is obtained by performing a formal life test on the semiconductor device using the fastest degradation parameter and the fastest degradation test condition;

[0009] Based on the life test data obtained from the formal life test, the life of the semiconductor device is calculated by interpolation calculation or mathematical model fitting.

[0010] According to an embodiment of the present disclosure, the life of the semiconductor device is the time required for the target parameter to degrade to a preset percentage under the influence of hot carriers. The parameter information of the semiconductor device includes: the maximum breakdown voltage of the drain under saturation conditions and the nominal maximum value of the normal working voltage of the gate; or the maximum breakdown voltage of the drain under saturation conditions and at least two of the following: the nominal maximum value of the normal working voltage of the gate, the gate voltage value when the gate current is maximum, and the gate voltage value when the substrate current is maximum.

[0011] According to an embodiment of the present disclosure, the parameter information of the semiconductor device is obtained through parameter pre-testing, including fixing the drain voltage, changing the gate voltage to obtain the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum; and fixing the gate voltage, changing the drain voltage to obtain the maximum drain breakdown voltage under the saturation condition.

[0012] According to an embodiment of the present disclosure, the fixed drain voltage transforms the gate voltage to obtain the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum, including fixing the drain voltage to the drain voltage during normal operation, transforming the gate voltage in equal steps within a preset gate voltage range, and obtaining a corresponding curve between the gate current and the gate voltage and / or a corresponding curve between the substrate current and the gate voltage; according to the corresponding curve between the gate current and the gate voltage and / or the corresponding curve between the substrate current and the gate voltage, obtaining the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum.

[0013] According to an embodiment of the present disclosure, the fixed gate voltage transforms the drain voltage to obtain the maximum drain breakdown voltage under the saturation condition, including fixing the gate voltage to the gate voltage during normal operation, transforming the drain voltage in equal steps within a preset drain voltage range, and determining the voltage when drain breakdown occurs as the maximum drain breakdown voltage.

[0014] According to an embodiment of the present disclosure, constructing a test condition according to the parameter information of the semiconductor device includes constructing at least two of the following test conditions:

[0015] Condition 1: V g =V g@Igmax , V d =Ratio×BV on ;

[0016] Condition 2: V g =V g@Isubmax , V d =Ratio×BV on ;

[0017] Condition 3: Vg =V gmax / p,V d =Ratio×BV on ;

[0018] Condition 4: V g =V gmax , V d =Ratio×BV on ;

[0019] Condition 5: V g =V gmax / q,V d =Ratio×BV on ,

[0020] Among them, V g is the gate voltage, V d is the drain voltage, V g@Igmax is the gate voltage value when the gate current is maximum, V g@Isubmax is the gate voltage value when the substrate current is maximum, V gmax BV is the maximum value of the gate normal working voltage. on is the maximum breakdown voltage of the drain under saturation conditions, and Ratio, p, and q are preset values. Among them, 0.7≤Ratio≤0.9; 1.5≤p≤2.5; 4.5≤q≤5.5; or 0.7≤Ratio≤0.9; p=2; q=5.

[0021] According to an embodiment of the present disclosure, the target parameters include at least two of the following: drain current in a linear region, drain current in a saturated region, gate threshold voltage in a linear region, and gate threshold voltage in a saturated region. The determining of the fastest degradation parameter among the multiple target parameters and the fastest degradation test condition among the different test conditions according to the life pre-test data includes determining any target parameter as the fastest degradation parameter when the target parameter among the multiple target parameters reaches a preset degradation rate first, and determining the test condition that makes the fastest degradation parameter reach the preset degradation rate first as the fastest degradation test condition.

[0022] According to an embodiment of the present disclosure, the use of the fastest degradation parameter and the fastest degradation test condition to perform a formal life test on the semiconductor device includes: obtaining the value of the fastest degradation parameter at each sampling time point under the fastest degradation test condition, and stopping the formal life test when the value meets at least one completion condition. The completion condition includes at least one of completion condition a, completion condition b, and completion condition c, wherein:

[0023] Completion condition a is that the fastest degradation parameter degrades to or exceeds a preset percentage;

[0024] Completion condition b is that the fastest degradation parameter has not degraded to a preset percentage but its degradation has been saturated;

[0025] Completion condition c is that the formal life test time reaches the initial experimental setting time.

[0026] According to an embodiment of the present disclosure, the preset percentage in the formal life test is greater than the preset degradation rate of the fastest degradation parameter adopted in the preliminary test.

[0027] According to an embodiment of the present disclosure, the method of calculating the semiconductor device life by interpolation calculation or mathematical model fitting based on the life test data obtained by the formal life test includes:

[0028] If the formal life test meets completion condition a, the following judgment is made:

[0029] If the fastest degradation parameter degrades to the preset percentage, the current sampling time point is the life span of the semiconductor device;

[0030] If the fastest degradation parameter degrades by more than the preset percentage, two sampling time points adjacent to the time point when the fastest degradation parameter degrades to the preset percentage are used for interpolation calculation to obtain the life time of the semiconductor device.

[0031] If the formal life test meets completion condition b or c, then based on the fastest degradation parameter value at the sampling time point obtained by the formal life test, a mathematical model is used to fit and calculate the degradation time when the fastest degradation parameter degrades to a preset percentage as the life time of the semiconductor device.

[0032] According to an embodiment of the present disclosure, the mathematical model includes at least one of the following: a gate oxide layer degradation curve model, a sidewall oxide layer degradation curve model, a fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model, and an enhanced fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model.

[0033] The gate oxide layer degradation curve model is expressed by the following formula:

[0034] If the fastest degradation parameter is the drain current, the following formula applies:

[0035]

[0036] If the fastest degradation parameter is the gate threshold voltage, the following formula applies:

[0037]

[0038] in:

[0039] Parameter A3, , as well as are coefficients determined in the fitting process. The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, t is the degradation time, is the channel width;

[0040] is the substrate current;

[0041] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0042] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0043] The sidewall oxide layer degradation curve model is expressed by the following formula:

[0044] If the fastest degrading parameter is the drain current, the following formula applies:

[0045]

[0046] If the fastest degradation parameter is the gate threshold voltage, the following formula applies:

[0047]

[0048] Among them, parameters A1, A2, , as well as are coefficients determined in the fitting process. The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, t is the degradation time, is the channel width;

[0049] is the substrate current;

[0050] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0051] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0052] The fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model is expressed by the following formula:

[0053] If the fastest degrading parameter is the drain current, the following formula applies:

[0054]

[0055] If the fastest degradation parameter is the gate threshold voltage, the following formula applies:

[0056]

[0057] Among them, parameters A1, A2, A3, , as well as are coefficients determined in the fitting process. The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, t is the degradation time, is the channel width;

[0058] is the substrate current;

[0059] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0060] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0061] The enhanced fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model is expressed by the following formula:

[0062] If the fastest degrading parameter is the drain current, the following formula applies:

[0063]

[0064] If the fastest degradation parameter is the gate threshold voltage, the following formula applies:

[0065]

[0066] Among them, parameters A1, A2, A3, A4, , as well as are coefficients determined in the fitting process. The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, t is the degradation time, is the channel width;

[0067] is the substrate current;

[0068] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0069] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0070] According to an embodiment of the present disclosure, the use of a mathematical model to fit and calculate the degradation time when the fastest degradation parameter degrades to a preset percentage includes using multiple mathematical models for fitting calculations, determining the best fitting model among the multiple mathematical models according to the calculation results, and using the best fitting model for fitting calculations to determine the degradation time when the fastest degradation parameter degrades to a preset percentage. When the gate oxide layer degradation curve model, the sidewall oxide layer degradation curve model, and the fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model all fail to fit or the goodness of fit R 2When the values ​​do not meet the requirements, the enhanced fusion model of the sidewall oxide layer degradation curve model is used as the best fitting model. When the enhanced fusion model of the sidewall oxide layer degradation curve model is used as the best fitting model, the fitting calculation using the best fitting model includes: An initial value, through fitting to obtain the unknown parameters A1, A2, A3, , as well as , and then calculate the goodness of fit R 2 If R 2 The value does not meet the requirements, change , and perform the fitting again until R 2 The value meets the requirements.

[0071] According to an embodiment of the present disclosure, the semiconductor device lifetime prediction method further includes determining a dominant factor causing parameter degradation of the semiconductor device according to a mathematical model with the best goodness of fit.

[0072] In a second aspect, an embodiment of the present disclosure provides a semiconductor device life prediction device, comprising:

[0073] A first acquisition module is configured to acquire parameter information of the semiconductor device, wherein the parameter information of the semiconductor device is acquired through parameter pre-testing;

[0074] a construction module, configured to construct test conditions according to parameter information of the semiconductor device, wherein the test conditions are used to perform a life pre-test on the semiconductor device to obtain life pre-test data of the semiconductor device under different test conditions, wherein the life pre-test data includes degradation data of a plurality of target parameters of the semiconductor device;

[0075] a first determination module configured to determine, according to the life pre-test data, a fastest degradation parameter among the plurality of target parameters and a fastest degradation test condition among the different test conditions;

[0076] A second acquisition module is configured to acquire life test data, wherein the life test data is obtained by performing a formal life test on the semiconductor device using the fastest degradation parameter and the fastest degradation test condition;

[0077] The calculation module is configured to calculate the life of the semiconductor device by using interpolation calculation or mathematical model fitting based on the life test data obtained from the formal life test.

[0078] The second determination module is configured to determine the dominant factor causing the parameter degradation of the semiconductor device according to the mathematical model with the best fitting goodness.

[0079] According to an embodiment of the present disclosure, in the semiconductor device life prediction device, the parameter information of the semiconductor device is obtained by parameter pre-testing, including fixing the drain voltage, changing the gate voltage to obtain the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum; fixing the gate voltage, changing the drain voltage to obtain the maximum breakdown voltage of the drain under the saturation condition. The fixing the drain voltage, changing the gate voltage to obtain the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum, includes fixing the drain voltage to the drain voltage during normal operation, changing the gate voltage with equal steps within a preset voltage range, and obtaining the corresponding curve between the gate current and the gate voltage and / or the corresponding curve between the substrate current and the gate voltage; according to the corresponding curve between the gate current and the gate voltage and / or the corresponding curve between the substrate current and the gate voltage, the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum is obtained. The fixed gate voltage and the transformed drain voltage are used to obtain the maximum drain breakdown voltage under the saturation condition, including fixing the gate voltage to the gate voltage during normal operation, transforming the drain voltage in equal steps within a preset voltage range, and determining the voltage when the drain breakdown occurs as the maximum drain breakdown voltage.

[0080] According to an embodiment of the present disclosure, in the semiconductor device lifetime prediction apparatus, constructing test conditions according to parameter information of the semiconductor device includes constructing at least two of the following test conditions:

[0081] Condition 1: Vg = Vg@Igmax, Vd = Ratio × BVon;

[0082] Condition 2: Vg = Vg@Isubmax, Vd = Ratio × BVon;

[0083] Condition 3: Vg = Vgmax / p, Vd = Ratio × BVon;

[0084] Condition 4: Vg = Vgmax, Vd = Ratio × BVon;

[0085] Condition 5: Vg = Vgmax / q, Vd = Ratio × BVon,

[0086] Wherein, Vg is the gate voltage, Vd is the drain voltage, Vg@Igmax is the gate voltage value when the gate current is maximum, Vg@Isubmax is the gate voltage value when the substrate current is maximum, Vgmax is the maximum value of the normal working voltage of the gate, BVon is the maximum breakdown voltage of the drain under saturation conditions, and Ratio, p, q are the preset values. 0.7≤Ratio≤0.9; 1.5≤p≤2.5; 4.5≤q≤5.5; or 0.7≤Ratio≤0.9; p=2; q=5.

[0087] According to an embodiment of the present disclosure, in the semiconductor device lifetime prediction device, the target parameters include at least two of the following: linear region drain current, saturation region drain current, gate linear region threshold voltage, gate saturation region threshold voltage.

[0088] According to an embodiment of the present disclosure, in the semiconductor device lifetime prediction device, the fastest degradation parameter among the multiple target parameters and the fastest degradation test condition among the different test conditions are determined based on the lifetime prediction test data, including when any target parameter among the multiple target parameters first reaches a preset degradation rate, determining the any target parameter as the fastest degradation parameter, and determining the test condition in which the fastest degradation parameter first reaches the preset degradation rate as the fastest degradation test condition.

[0089] According to an embodiment of the present disclosure, in the semiconductor device life prediction apparatus, the life test data is obtained by performing a formal life test on the semiconductor device using the fastest degradation parameter and the fastest degradation test condition, including obtaining the value of the fastest degradation parameter at each sampling time point under the fastest degradation test condition, and stopping the formal life test when the value meets at least one completion condition.

[0090] According to an embodiment of the present disclosure, in the semiconductor device lifetime prediction device, the completion condition includes at least one of completion condition a, completion condition b, and completion condition c, wherein:

[0091] Completion condition a is that the fastest degradation parameter degrades to or exceeds a preset percentage;

[0092] Completion condition b is that the fastest degradation parameter has not degraded to a preset percentage but its degradation has been saturated;

[0093] Completion condition c is that the formal life test time reaches the initial experimental setting time.

[0094] According to an embodiment of the present disclosure, in the semiconductor device life prediction apparatus, the preset percentage in the formal life test is greater than a preset degradation rate of the fastest degradation parameter used in a preliminary test.

[0095] According to an embodiment of the present disclosure, in the semiconductor device life prediction device, the life test data obtained based on the formal life test is used to calculate the semiconductor device life by interpolation, including if the formal life test meets the completion condition a, performing the following judgment: if the fastest degradation parameter degrades to the preset percentage, the current sampling time point is the semiconductor device life time; if the fastest degradation parameter degrades by more than the preset percentage, interpolating the two sampling time points adjacent to the time point when the fastest degradation parameter degrades to the preset percentage to obtain the semiconductor device life time.

[0096] According to an embodiment of the present disclosure, in the semiconductor device life prediction device, the life test data obtained based on the formal life test is used to calculate the semiconductor device life by using a mathematical model fitting, including if the formal life test meets completion condition b or c, based on the fastest degradation parameter value at the sampling time point obtained by the formal life test, using a mathematical model fitting to calculate the degradation time when the fastest degradation parameter degrades to a preset percentage as the semiconductor device life time.

[0097] According to an embodiment of the present disclosure, in the semiconductor device lifetime prediction device, the mathematical model includes at least one of the following: a gate oxide layer degradation curve model, a sidewall oxide layer degradation curve model, a fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model, and an enhanced fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model.

[0098] According to an embodiment of the present disclosure, in the semiconductor device life prediction device, the gate oxide layer degradation curve model is expressed by the following formula:

[0099] If the fastest degradation parameter is the drain current, the following formula applies:

[0100]

[0101] If the fastest degradation parameter is the gate threshold voltage, the following formula applies:

[0102]

[0103] in:

[0104] Parameter A3, , as well as are coefficients determined in the fitting process. The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, t is the degradation time, is the channel width;

[0105] is the substrate current;

[0106] is the drain current in the linear region or the drain current in the saturation region, and accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0107] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0108] According to an embodiment of the present disclosure, in the semiconductor device life prediction device, the sidewall oxide layer degradation curve model is expressed by the following formula:

[0109] If the fastest degradation parameter is the drain current, the following formula applies:

[0110]

[0111] If the fastest degradation parameter is the gate threshold voltage, the following formula applies:

[0112]

[0113] Among them, parameters A1, A2, , as well as are coefficients determined in the fitting process. The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, is the degradation time, is the channel width;

[0114] is the substrate current;

[0115] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0116] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0117] According to an embodiment of the present disclosure, in the semiconductor device life prediction device, the fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model is expressed by the following formula:

[0118] If the fastest degrading parameter is the drain current, the following formula applies:

[0119]

[0120] If the fastest degradation parameter is the gate threshold voltage, the following formula applies:

[0121]

[0122] Among them, parameters A1, A2, A3, , as well as are coefficients determined in the fitting process. The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, is the degradation time, is the channel width;

[0123] is the substrate current;

[0124] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0125] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0126] According to an embodiment of the present disclosure, in the semiconductor device life prediction device, the enhanced fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model is expressed by the following formula:

[0127] If the fastest degradation parameter is the drain current, the following formula applies:

[0128]

[0129] If the fastest degradation parameter is the gate threshold voltage, the following formula applies:

[0130]

[0131] Among them, parameters A1, A2, A3, A4, , as well as are coefficients determined in the fitting process. The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, is the degradation time, is the channel width;

[0132] is the substrate current;

[0133] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0134] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0135] According to an embodiment of the present disclosure, in the semiconductor device life prediction device, the use of a mathematical model to fit and calculate the degradation time when the fastest degradation parameter degrades to a preset percentage includes using multiple mathematical models to perform fitting calculations, determining the best fitting model among the multiple mathematical models based on the calculation results, and using the best fitting model to perform fitting calculations to determine the degradation time when the fastest degradation parameter degrades to a preset percentage.

[0136] According to an embodiment of the present disclosure, in the semiconductor device life prediction device, multiple mathematical models are used for fitting calculation, and the best fitting model among the multiple mathematical models is determined according to the calculation results, including when the gate oxide layer degradation curve model, the sidewall oxide layer degradation curve model, the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model are all fitted failed or the goodness of fit R 2 When all values ​​do not meet the requirements, the enhanced fusion model of the sidewall oxide layer degradation curve model is used as the best fitting model.

[0137] According to an embodiment of the present disclosure, in the semiconductor device life prediction device, when the enhanced fusion model of the sidewall oxide layer degradation curve model is used as the best fitting model, the best fitting model is used to perform fitting calculation, including: An initial value, through fitting to obtain coefficients A1, A2, A3, , as well as , and then calculate the goodness of fit R 2 If R 2 The value does not meet the requirements, change , and perform the fitting again until R 2 The value meets the requirements.

[0138] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising a memory and a processor, wherein the memory is used to store one or more computer instructions, and wherein the one or more computer instructions are executed by the processor to implement the method described in the first aspect.

[0139] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, the method described in the first aspect is implemented.

[0140] According to the technical solution provided by the embodiment of the present disclosure, parameter information of the semiconductor device is obtained through parameter pre-testing; test conditions are constructed according to the parameter information of the semiconductor device to perform life pre-testing, and life pre-testing data of the semiconductor device under different test conditions are obtained through the life pre-testing, the life pre-testing data includes degradation data of multiple target parameters of the semiconductor device, and the fastest degradation parameter among the multiple target parameters and the fastest degradation test condition among the different test conditions are determined according to the life pre-testing data; a formal life test is performed using the fastest degradation parameter and the fastest degradation test condition; based on the life test data obtained from the formal life test, the life of the semiconductor device is calculated by interpolation calculation or mathematical model fitting.

[0141] According to the semiconductor device life prediction method provided by the embodiment of the present disclosure, by selecting the fastest degradation parameter and the corresponding fastest degradation test condition of the semiconductor device, life test data is obtained based on the fastest degradation parameter and the corresponding fastest degradation test condition, and the life of the semiconductor device is calculated by interpolation calculation or mathematical model fitting based on the life test data, which can solve the problem of how to accurately predict the life of certain semiconductor devices whose degradation curves are easily saturated.

[0142] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0143] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0144] Figure 1 A flowchart of a method for predicting the lifetime of a semiconductor device according to an embodiment of the present disclosure is shown.

[0145] Figure 2 Shown is a schematic diagram of the structure of a 40v NLDMOS.

[0146] Figure 3 A schematic diagram showing the failure mechanism of a 40V NLDMOS using an enhancement-mode metal-oxide semiconductor field-effect transistor (MOSFET) and a depletion-mode MOSFET equivalent circuit is shown.

[0147] Figure 4 The fitting curves and goodness of fit R under various mathematical models are shown. 2 value.

[0148] Figure 5a A flowchart of a method for predicting the lifetime of a semiconductor device according to an embodiment of the present disclosure is shown.

[0149] Figure 5b A block diagram of a semiconductor device lifetime prediction apparatus according to an embodiment of the present disclosure is shown.

[0150] Figure 6 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0151] Figure 7 A schematic diagram showing the structure of a computer system suitable for implementing the method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0152] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0153] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0154] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0155] Hot carriers include hot holes and hot electrons, which are the main failure mechanism affecting the reliability of semiconductor processes. Hot carrier injection refers to the injection of high-energy carriers into the oxide layer through the silicon or silicon dioxide interface, generating interface states, oxide layer defects or being captured by traps, which in turn affects the channel carrier mobility and effective potential. Accelerated testing by applying voltage stress to the drain and gate is currently the main way to predict the life of semiconductor devices under the influence of hot carriers. However, due to the complexity of the design structure of some semiconductor devices, the long life of the device itself, the unsuitability for applying higher voltages, or the degradation curve easily reaching saturation, it is impossible to directly obtain the device life through testing, and mathematical fitting and life derivation are required for the test data. The mathematical model used for fitting and derivation has become a key factor in accurately predicting the life of semiconductor devices.

[0156] Specifically, the existing technical solutions are mainly applicable to the prediction and calculation of hot carrier lifetime of CMOS devices, and usually use power functions for lifetime derivation. However, some semiconductor devices, such as 40v N-type laterally diffused metal oxide semiconductor (NLDMOS) devices, have a significant difference in structure from CMOS devices. The design structure of 40v NLDMOS is more complex, the testing process is more complex, and the test results are also significantly different from those of CMOS devices. Generally, the degradation curve of 40v NLDMOS devices easily reaches saturation, resulting in the inability to directly obtain the device lifetime through testing. Mathematical fitting and lifetime derivation are required for the test data. Therefore, constructing a model suitable for mathematical fitting and lifetime derivation can effectively improve the accuracy of lifetime prediction.

[0157] The embodiment of the present disclosure provides a method for predicting the life of a semiconductor device, comprising: obtaining parameter information of the semiconductor device through parameter pre-testing; constructing test conditions according to the parameter information of the semiconductor device to perform life pre-testing, obtaining life pre-testing data of the semiconductor device under different test conditions through the life pre-testing, the life pre-testing data including degradation data of multiple target parameters of the semiconductor device, determining the fastest degradation parameter among the multiple target parameters and the fastest degradation test condition among the different test conditions according to the life pre-testing data; performing a formal life test using the fastest degradation parameter and the fastest degradation test condition; and calculating the life of the semiconductor device by interpolation calculation or mathematical model fitting based on the life test data obtained through the formal life test.

[0158] According to the semiconductor device life prediction method provided by the embodiment of the present disclosure, by selecting the fastest degradation parameter and the corresponding fastest degradation test condition of the semiconductor device, life test data is obtained based on the fastest degradation parameter and the corresponding fastest degradation test condition, and the life of the semiconductor device is calculated by interpolation calculation or mathematical model fitting based on the life test data, which can effectively avoid the prediction error caused by the saturation of the degradation curve and improve the accuracy of the semiconductor device life prediction.

[0159] Figure 1 A flow chart of a method for predicting the lifetime of a semiconductor device according to an embodiment of the present disclosure is shown. Figure 1 As shown, the semiconductor device lifetime prediction method includes the following steps S101 - S104.

[0160] In step S101, parameter information of the semiconductor device is obtained through parameter pre-testing.

[0161] According to an embodiment of the present disclosure, the parameter information of the semiconductor device includes: the maximum breakdown voltage of the drain under saturation conditions and the maximum value of the normal working voltage of the gate; or the maximum breakdown voltage of the drain under saturation conditions and at least two of the following: the maximum value of the normal working voltage of the gate, the gate voltage value when the gate current is maximum, and the gate voltage value when the substrate current is maximum. The parameters that affect the life of different semiconductor devices may be different, so different parameter information can be obtained for different semiconductor devices for testing.

[0162] When performing parameter pre-test, the drain voltage can be fixed, and the gate voltage can be changed in equal steps within the gate voltage range to obtain a corresponding curve between the gate current and the gate voltage and / or a corresponding curve between the substrate current and the gate voltage. According to the corresponding curve between the gate current and the gate voltage and / or the corresponding curve between the substrate current and the gate voltage, the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum can be obtained. In addition, the gate voltage can be fixed, and the drain voltage can be changed in equal steps within the drain voltage range, and the voltage when the drain breakdown occurs is determined as the maximum drain breakdown voltage.

[0163] The following takes 40V NLDMOS as an example to illustrate the process of obtaining parameter information of the semiconductor device through parameter pre-testing.

[0164] According to the embodiment of the present disclosure, the current-voltage curve of the 40V NLDMOS is tested, and the drain voltage V is fixed. d is 40v, the gate voltage V g Take values ​​from 0v to 5v with a step size of 0.01v to obtain the gate current I g and V g Voltage between I d -V g Curve, obtain the substrate current I sub and V g Voltage between I sub -V g Curve, get the gate current I g The maximum value of I gmax and I gmax Right V g Maximum V g@Igmax voltage value, and the substrate current I sub The maximum value of I submax and I submax The corresponding V g@Isubmax Voltage value.

[0165] According to an embodiment of the present disclosure, the maximum breakdown voltage BV of the drain of a 40V NLDMOS under saturation conditions is tested. on The gate voltage is fixed at 5V and the drain voltage is V d It starts from 0V and increases continuously with a step size of 0.1V. The gate current I is monitored during the test. g and drain current I d , when I g or I d If one of the currents increases by more than 10 times compared to the current change at the last sampling point, it is considered that the drain has broken down. At this time, the drain voltage V d The maximum breakdown voltage BV on .

[0166] In step S102, test conditions are constructed according to parameter information of the semiconductor device to perform a life pretest, and life pretest data of the semiconductor device under different test conditions are obtained through the life pretest, wherein the life pretest data includes degradation data of multiple target parameters of the semiconductor device, and the fastest degradation parameter among the multiple target parameters and the fastest degradation test condition among the different test conditions are determined according to the life pretest data.

[0167] According to an embodiment of the present disclosure, constructing a test condition according to the parameter information of the semiconductor device includes constructing at least two of the following test conditions:

[0168] Condition 1: V g =V g@Igmax , V d =Ratio×BV on ;

[0169] Condition 2: V g =V g@Isubmax , V d =Ratio×BV on ;

[0170] Condition 3: V g =V gmax / p,V d =Ratio×BV on ;

[0171] Condition 4: V g =V gmax , V d =Ratio×BV on ;

[0172] Condition 5: V g =V gmax / q,V d =Ratio×BV on ,

[0173] Among them, V g is the gate voltage, V d is the drain voltage, V g@Igmax is the gate voltage value when the gate current is maximum, V g@Isubmax is the gate voltage value when the substrate current is maximum, V gmax BV is the maximum value of the gate normal working voltage. on is the maximum breakdown voltage of the drain under saturation conditions, and Ratio, p, and q are preset values: 0.7≤Ratio≤0.9; 1.5≤p≤2.5; 4.5≤q≤5.5; or 0.7≤Ratio≤0.9; p=2; q=5.

[0174] According to an embodiment of the present disclosure, the target parameters include at least two of the following: linear region drain current, saturation region drain current, gate linear region threshold voltage, gate saturation region threshold voltage. Different target parameters can be selected for testing for different semiconductor devices.

[0175] The determining, based on the life pre-test data, the fastest degradation parameter among the multiple target parameters and the fastest degradation test condition among the different test conditions includes, when any target parameter among the multiple target parameters reaches a preset degradation rate first, determining the any target parameter as the fastest degradation parameter, and determining the test condition that causes the fastest degradation parameter to reach the preset degradation rate first as the fastest degradation test condition.

[0176] In an embodiment of the present disclosure, the following test conditions are constructed for a life pre-test of a 40V NLDMOS.

[0177] Condition 1: V g =V g@Igmax , V d =(0.7~0.90)×BV on ;

[0178] Condition 2: V g =V g@Isubmax , V d =(0.7~0.90)×BV on ;

[0179] Condition 3: V g =V gmax / 2=5 / 2=2.5v, V d =(0.7~0.90)×BV on ;

[0180] Condition 4: V g =V gmax =5v, V d =(0.7~0.90)×BV on ;

[0181] Condition 5: V g =1v, V d =(0.7~0.90)×BV on .

[0182] During the pre-test process, the drain terminal linear leakage current I is monitored simultaneously. dlin , Drain saturation leakage current I dlin , gate linear region threshold voltage V tlin , Gate saturation region threshold voltage V tsat The degradation of dlin Defined as Vd =0.1v, V g =Drain current at 5V; I dlin Defined as V d =40v, V g =5V drain current; V tlin Defined as V d =0.1v, I d =0.1×(W / L), the corresponding gate voltage V g； V tsat Defined as V d =40v, I d =0.1×(W / L), the corresponding gate voltage V g , where W is the channel width of the device (in um), L is the channel length of the device (in um), and (0.7~0.90) means selecting a coefficient from 0.7 to 0.9. dlin ,I dlin 、V tlin 、V tsat The first parameter degradation of one of the parameters reaches 3% as the life prediction test stop condition, that is, the preset degradation rate of the parameter in the life prediction test is 3%. The parameter with the fastest degradation is obtained as the fastest degradation parameter, and the test condition corresponding to the fastest degradation parameter index is found from conditions 1-5. For example, under the above test conditions 1-5, the monitoring parameter I dlin ,I dlin 、V tlin 、V tsat If parameter X first reaches or exceeds the preset degradation rate under condition y, parameter X is determined as the fastest degradation parameter, and condition y is the fastest degradation test condition.

[0183] In step S103, a formal life test is performed using the fastest degradation parameter and the fastest degradation test condition. The semiconductor device life is the time required for a single or multiple semiconductor device parameters to degrade by a preset percentage under the influence of hot carriers. The formal life test includes: monitoring the change of the fastest degradation parameter at each time point under the fastest degradation test condition, and making the following judgments. If any of the completion conditions is met, the formal life test is considered to be completed:

[0184] Completion condition a: the fastest degradation parameter degrades to or exceeds a preset percentage;

[0185] Completion condition b: the fastest degradation parameter has not degraded to or exceeded a preset percentage but its degradation has been saturated;

[0186] Completion condition c: The formal life test time reaches the initial experimental setting time.

[0187] The preset percentage in the formal life test is greater than the preset degradation rate in the preliminary test.

[0188] Specifically, the formal life test is performed according to the test conditions corresponding to the fastest degradation parameter index obtained in step S102, and the degradation of the fastest degradation parameter is monitored during the test. In the case of testing a 40V NLDMOS, the formal life test is completed when one of the following three conditions is met:

[0189] Completion condition a: The degradation rate of the fastest degradation parameter reaches 10%, that is, the preset percentage in the formal life test is 10%;

[0190] Completion condition b: The degradation rate of the fastest degradation parameter has not reached 10%, but the degradation has reached saturation;

[0191] Completion condition c: The test time reaches the initial test setting time, generally 100,000 seconds.

[0192] In step S104, based on the life test data obtained from the formal life test, the life of the semiconductor device is calculated by interpolation calculation or mathematical model fitting.

[0193] If the formal life test meets completion condition a, the following judgment is made: if the fastest degradation parameter degrades to the preset percentage, the current sampling time point is the life time of the semiconductor device; if the fastest degradation parameter degrades by more than the preset percentage, two sampling time points adjacent to the time point when the fastest degradation parameter degrades to the preset percentage are used for interpolation calculation to obtain the life time of the semiconductor device.

[0194] If the formal life test meets completion condition b or c, then based on the fastest degradation parameter value at the sampling time point obtained by the formal life test, a mathematical model is used to fit and calculate the degradation time when the fastest degradation parameter degrades to a preset percentage as the life time of the semiconductor device. The mathematical model includes at least one of the following: a gate oxide layer degradation curve model, a sidewall oxide layer degradation curve model, a fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model, and an enhanced fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model.

[0195] According to the embodiment of the present disclosure, the formal life test data of 40v NLDMOS is sorted and analyzed: that is, the degradation rate of the fastest degradation parameter of the semiconductor device at each sampling time point is calculated to determine whether it reaches or exceeds the preset percentage of 10%. If the degradation rate at a certain sampling time point just reaches the preset percentage of 10%, then this sampling time point is the life time required for the semiconductor device to degrade by 10% under the influence of hot carriers, that is, the hot carrier lifetime of the semiconductor device. If the degradation rate at a certain sampling time point exceeds the preset percentage of 10%, two sampling time points near 10% are used for interpolation calculation to obtain the life time when the degradation is 10%, that is, the hot carrier lifetime of the semiconductor device.

[0196] If completion conditions b or c occur, that is, the device has not degraded to the preset percentage of 10%, the relevant mathematical model is used to predict the 10% life. The mathematical models currently used in the industry mainly include linear function curve fitting, multiple function fitting, exponential function fitting, power function fitting, logarithmic function fitting, etc. Wafer factories generally use power functions for fitting. However, due to the complexity of the NLDMOS device structure, there are many failure mechanisms that affect its life and reliability. The existing mathematical models do not fully consider the failure mechanism of the device, resulting in poor fitting results.

[0197] Figure 2 The schematic diagram of the structure of 40v NLDMOS is shown. The exemplary 40v NLDMOS device adopts a P-type substrate, the device width W is 40um, and the device length is 0.25um. The drain end (DRAIN) and the source end (SOURCE) adopt a heavily doped shallow isolation trench (STI) process, and the gate (GATE) and the sidewall oxide layer (SPACE OXIDE) on the side of the gate oxide layer (OXIDE) adopt an n-type lightly doped drain (NLDD) process. Therefore, there are both NLDD structures and STI structures in the device. The hot carrier failure of the device is mainly caused by the degradation of the sidewall oxide layer (SPACE OXIDE) and the gate oxide layer (OXIDE) near the channel. The initial degradation mainly comes from the sidewall oxide layer, and over time, the degradation of the gate oxide layer slowly becomes the main part.

[0198] Figure 3 The figure shows a schematic diagram of the failure mechanism of 40V NLDMOS using the equivalent circuits of enhancement mode metal-oxide semiconductor field effect transistor (MOSFET) and depletion mode MOSFET. The enhancement mode MOSFET is used to represent the channel region, and its effective resistance is represented by R ch Indicates; depletion-type MOSFET is used to represent the sidewall n-doped region, and its effective resistance is R1 to R n The parallel resistance of

[0199] According to the embodiments of the present disclosure, the hot carrier degradation of MOSFET in the n-region usually originates from the maximum substrate current I sub The generated interface states will affect surface scattering. However, the carrier distribution in the n-region accumulation layer is farther from the Si / SiO2 interface than the carrier distribution in the channel inversion layer. The negative charge generated by stress will push the current path deeper in the direction of the substrate, so that even if the generated interface states hinder the electron flux, the electrons can flow through the deeper path. Therefore, even if the interface state charge continues to increase, the mobility degradation of the n-region will eventually saturate. Electrons pass through the channel resistance R ch After that, we reach the n-region R1 to R n At the beginning, R1 is the smallest resistor among all parallel resistors, so electrons mainly flow to the drain through the surface near R1. When the interface state is generated, the resistance of R1 increases, and electrons will choose a lower path to flow to the drain. After a long period of stress, due to the influence of the interface state generated by hot carriers, except for R n All resistors except for R n The reason why it is not affected is that n The distance from the position to the surface of the lightly doped n- region is too far. In fact, the current does not flow only through R n , but through R1 to R n The parallel equivalent resistance R eq Eventually, even though the interface state charge still increases, the current is not affected and the electron mobility degradation rate in the n- region reaches saturation.

[0200] According to the embodiments of the present disclosure, taking the drain current as an example, the hot carrier degradation in the channel region can be measured by the substrate current I sub , gate current I g , drain current I d , the interface state density calculation formula is used to derive formula (1). The critical energy required for interface trap generation, To generate the critical energy required for impact ionization, is the substrate current, is the channel width, is the drain current, and t is the degradation time.

[0201]

[0202] By transforming formula (1), we can obtain formula (2), which is used to describe the degradation curve trajectory of the gate oxide layer.

[0203]

[0204] in, is the drain current change, is the initial current at the drain end. By means of the equivalent circuits of enhancement mode MOSFET and depletion mode MOSFET, formula (3) can be derived, which describes the degradation curve trajectory of the sidewall oxide layer.

[0205]

[0206] By using formula (2) and (3), we can get formula (4), which can completely describe the trajectory of the fusion degradation curve of the sidewall oxide layer and the gate oxide layer.

[0207]

[0208] Parameters A1, A2, A3, , and n are coefficients determined in the fitting. The following parameters can be obtained through measurement, among which, The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, is the substrate current, is the channel width, is the drain current, The degradation time.

[0209] According to the embodiments of the present disclosure, assuming that the fastest degradation parameter of the semiconductor device is the drain current, the mathematical models of formula (2), formula (3), and formula (4) can be used for fitting calculation. Formulas (2), (3), and (4) can be called NLDD degradation models. The best fitting model is determined based on the calculation results, and the best fitting model is used to perform fitting calculation to determine the degradation time when the fastest degradation parameter degrades to a preset percentage. According to the best fitting model used, it can also be determined whether the sidewall oxide layer is the leading degradation or the gate oxide layer is the leading degradation.

[0210] According to an embodiment of the present disclosure, assuming that the fastest degradation test condition of a 40V NLDMOS device is condition 2, the 40V NLDMOS device is subjected to condition 2: V g =V g@Isubmax 、V d =(0.7~0.90)×BV on In this embodiment, V g =1.35v, V d =40v test condition, get I dlinAfter comparison of the complete degradation data, it was found that formula (4) was the best fitting model. Therefore, it was fitted using formula (4) and compared with the linear function, quadratic function curve, cubic function curve, power function curve and exponential function curve. It was found that the NLDD degradation model had the highest fitting degree and the curve was very consistent with the original data.

[0211] Figure 4 The fitting curves and goodness of fit R under various mathematical models are shown. 2 It is obvious that the NLDD degradation model curve is very consistent with the original data, and the goodness of fit R 2 The value is also closest to 1, which is a significant improvement compared to other mathematical models.

[0212] According to the embodiments of the present disclosure, when the gate oxide layer degradation curve model, the sidewall oxide layer degradation curve model, and the fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model all fail to fit or the goodness of fit R 2 When all values ​​do not meet the requirements, the enhanced fusion model of the sidewall oxide layer degradation curve model is used as the best fitting model.

[0213] Specifically, the NLDD degradation model shown in formulas (2), (3), and (4) is a nonlinear least squares fitting method to determine the parameters A1, A2, A3, , And n. It is not suitable for fitting all degradation data. Nonlinear least squares parameter fitting usually uses the curve_fit function of Python language with powerful data processing capabilities. The calculation method of this function is Levenberg-Marquardt algorithm. LM algorithm is an unconstrained algorithm that combines the advantages of gradient method and Newton method. However, LM algorithm process requires derivation. When fitting complex functions such as NLDD degradation model, if you encounter more complex reliability test data such as I dlin When the degenerate value is negative first and then positive, the zero point problem will be encountered during the derivation process, resulting in the LM calculation process failing to converge and the fitting failure or goodness of fit R 2 The value does not meet the requirements. In this case, it is necessary to construct a new model and use the curve_fit function of the Python language plus a loop iteration method to find the optimal value of the unknown parameter.

[0214] According to the embodiment of the present disclosure, the enhanced fusion model of the sidewall oxide layer degradation curve model shown in formula (5) changes the model denominator constant 1 to a variable coefficient A4. At the beginning of the iteration, an initial variable is given, and then the curve_fit function of the Python language is used to obtain the undetermined parameters A1, A2, A3, , And n, then calculate the goodness of fit R of the model2 If R 2 If the value does not meet the target requirement, A4 is increased or decreased, and the loop iteration calculation is performed again until R 2 until the target value is met.

[0215]

[0216] According to an embodiment of the present disclosure, the dominant factor causing the parameter degradation of the semiconductor device is determined based on the mathematical model with the best goodness of fit, that is, the best fitting formula can be used to determine whether the sidewall oxide layer or the gate oxide layer is the dominant factor in the degradation.

[0217] Figure 5a A flowchart of a method for predicting the lifetime of a semiconductor device according to an embodiment of the present disclosure is shown.

[0218] like Figure 5a As shown, the semiconductor device lifetime prediction method according to the embodiment of the present disclosure includes steps S501-S505.

[0219] In step S501, parameter information of the semiconductor device is obtained, wherein the parameter information of the semiconductor device is obtained through parameter pre-testing.

[0220] In step S502, test conditions are constructed according to parameter information of the semiconductor device, and the test conditions are used to perform a life pre-test on the semiconductor device to obtain life pre-test data of the semiconductor device under different test conditions, wherein the life pre-test data includes degradation data of multiple target parameters of the semiconductor device.

[0221] In step S503, the fastest degradation parameter among the plurality of target parameters and the fastest degradation test condition among the different test conditions are determined according to the life prediction test data.

[0222] In step S504, life test data is acquired, wherein the life test data is obtained by performing a formal life test on the semiconductor device using the fastest degradation parameter and the fastest degradation test condition.

[0223] In step S505, based on the life test data obtained from the formal life test, the life of the semiconductor device is calculated by interpolation calculation or mathematical model fitting.

[0224] According to an embodiment of the present disclosure, the life of the semiconductor device is the time required for the target parameter to degrade to a preset percentage under the influence of hot carriers. The parameter information of the semiconductor device includes: the maximum breakdown voltage of the drain under saturation conditions and the maximum value of the normal working voltage of the gate; or the maximum breakdown voltage of the drain under saturation conditions and at least two of the following: the maximum value of the normal working voltage of the gate, the gate voltage value when the gate current is maximum, and the gate voltage value when the substrate current is maximum. The parameters that affect the life of different semiconductor devices may be different. Therefore, different parameter information can be obtained for different semiconductor devices for testing.

[0225] According to an embodiment of the present disclosure, the drain voltage is fixed and the gate voltage is changed to obtain the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum; and the gate voltage is fixed and the drain voltage is changed to obtain the maximum drain breakdown voltage under the saturation condition.

[0226] According to an embodiment of the present disclosure, the fixed drain voltage transforms the gate voltage to obtain the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum, including fixing the drain voltage to the drain voltage during normal operation, transforming the gate voltage in equal steps within the gate voltage range, and obtaining a corresponding curve between the gate current and the gate voltage and / or a corresponding curve between the substrate current and the gate voltage; according to the corresponding curve between the gate current and the gate voltage and / or the corresponding curve between the substrate current and the gate voltage, obtaining the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum.

[0227] According to an embodiment of the present disclosure, the fixed gate voltage and the transformed drain voltage are used to obtain the maximum drain breakdown voltage under the saturation condition, including fixing the gate voltage to the gate voltage during normal operation, transforming the drain voltage in equal steps within the drain voltage range, and determining the voltage when drain breakdown occurs as the maximum drain breakdown voltage.

[0228] According to an embodiment of the present disclosure, constructing a test condition according to the parameter information of the semiconductor device includes constructing at least two of the following test conditions:

[0229] Condition 1: V g =V g@Igmax , V d =Ratio×BV on ;

[0230] Condition 2: V g =V g@Isubmax , V d =Ratio×BV on ;

[0231] Condition 3: Vg =V gmax / p,V d =Ratio×BV on ;

[0232] Condition 4: V g =V gmax , V d =Ratio×BV on ;

[0233] Condition 5: V g =V gmax / q,V d =Ratio×BV on ,

[0234] Among them, V g is the gate voltage, V d is the drain voltage, V g@Igmax is the gate voltage value when the gate current is maximum, V g@Isubmax is the gate voltage value when the substrate current is maximum, V gmax BV is the maximum value of the gate normal working voltage. on is the maximum breakdown voltage of the drain under saturation conditions, and Ratio, p, and q are preset values. Among them, 0.7≤Ratio≤0.9; 1.5≤p≤2.5; 4.5≤q≤5.5; or 0.7≤Ratio≤0.9; p=2; q=5.

[0235] According to an embodiment of the present disclosure, the target parameters include at least two of the following: drain linear leakage current, drain saturation leakage current, gate linear region threshold voltage, gate saturation region threshold voltage. The fastest degradation parameter among the multiple target parameters and the fastest degradation test condition among the different test conditions are determined according to the life pre-test data, including when any target parameter among the multiple target parameters reaches a preset degradation rate first, determining the any target parameter as the fastest degradation parameter, and determining the test condition that makes the fastest degradation parameter reach the preset degradation rate first as the fastest degradation test condition.

[0236] According to an embodiment of the present disclosure, the use of the fastest degradation parameter and the fastest degradation test condition to perform a formal life test includes: obtaining the value of the fastest degradation parameter at each sampling time point under the fastest degradation test condition, and stopping the formal life test when the value meets at least one completion condition. The completion condition includes at least one of completion condition a, completion condition b, and completion condition c, wherein:

[0237] Completion condition a is that the fastest degradation parameter degrades to or exceeds a preset percentage;

[0238] Completion condition b is that the fastest degradation parameter has not degraded to a preset percentage but its degradation has been saturated;

[0239] Completion condition c is that the formal life test time reaches the initial experimental setting time.

[0240] According to an embodiment of the present disclosure, the preset percentage in the formal life test is greater than the preset degradation rate of the fastest degradation parameter adopted in the preliminary test.

[0241] According to an embodiment of the present disclosure, the method of calculating the semiconductor device life by interpolation calculation or mathematical model fitting based on the life test data obtained by the formal life test includes:

[0242] If the formal life test meets completion condition a, the following judgment is made:

[0243] If the fastest degradation parameter degrades to the preset percentage, the current sampling time point is the life span of the semiconductor device;

[0244] If the fastest degradation parameter degrades by more than the preset percentage, two sampling time points adjacent to the time point when the fastest degradation parameter degrades to the preset percentage are used for interpolation calculation to obtain the life time of the semiconductor device.

[0245] If the formal life test meets completion condition b or c, then based on the fastest degradation parameter value at the sampling time point obtained by the formal life test, a mathematical model is used to fit and calculate the degradation time when the fastest degradation parameter degrades to a preset percentage as the life time of the semiconductor device.

[0246] According to an embodiment of the present disclosure, the mathematical model includes at least one of the following: a gate oxide layer degradation curve model, a sidewall oxide layer degradation curve model, a fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model, and an enhanced fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model.

[0247] According to an embodiment of the present disclosure, taking the drain current as an example, the gate oxide layer degradation curve model is expressed by the following formula:

[0248]

[0249] According to an embodiment of the present disclosure, taking the gate threshold voltage as an example, the gate oxide layer degradation curve model is expressed by the following formula:

[0250]

[0251] in:

[0252] Parameter A3, , as well as are coefficients determined in the fitting process. The following parameters can be obtained through measurement, among which, The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, is the degradation time, is the channel width;

[0253] is the substrate current;

[0254] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0255] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0256] According to an embodiment of the present disclosure, taking the drain current as an example, the fastest degradation parameter is the sidewall oxide layer degradation curve model is expressed by the following formula:

[0257]

[0258] According to an embodiment of the present disclosure, taking the gate threshold voltage as an example, the degradation curve model of the sidewall oxide layer is expressed by the following formula:

[0259]

[0260] Among them, parameters A1, A2, , as well as are coefficients determined in the fitting process. The following parameters can be obtained through measurement, among which, The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, is the degradation time, is the channel width;

[0261] is the substrate current;

[0262] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0263] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0264] According to an embodiment of the present disclosure, taking the drain current as an example, the fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model is expressed by the following formula:

[0265]

[0266] According to an embodiment of the present disclosure, taking the gate threshold voltage as an example, the fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model is expressed by the following formula:

[0267]

[0268] Among them, parameters A1, A2, A3, , as well as are coefficients determined in the fitting process. The following parameters can be obtained through measurement, among which, The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, is the degradation time, is the channel width;

[0269] is the substrate current;

[0270] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0271] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0272] According to an embodiment of the present disclosure, taking the drain current as an example, the enhanced fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model is expressed by the following formula:

[0273]

[0274] According to an embodiment of the present disclosure, taking the gate threshold voltage as an example, the enhanced fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model is expressed by the following formula:

[0275]

[0276] Among them, parameters A1, A2, A3, A4, , as well as are coefficients determined in the fitting process. The following parameters can be obtained through measurement, among which, The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, is the degradation time, is the channel width;

[0277] is the substrate current;

[0278] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0279] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0280] According to an embodiment of the present disclosure, the use of a mathematical model to fit and calculate the degradation time when the fastest degradation parameter degrades to a preset percentage includes using multiple mathematical models to perform fitting calculations, determining the best fitting model among the multiple mathematical models based on the calculation results, and using the best fitting model to perform fitting calculations to determine the degradation time when the fastest degradation parameter degrades to a preset percentage.

[0281] According to the embodiments of the present disclosure, the multiple mathematical models are used for fitting calculation, and the best fitting model among the multiple mathematical models is determined according to the calculation results, including when the gate oxide layer degradation curve model, the sidewall oxide layer degradation curve model, the fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model all fail to fit or the goodness of fit R 2 When the values ​​do not meet the requirements, the enhanced fusion model of the sidewall oxide layer degradation curve model is used as the best fitting model. When the enhanced fusion model of the sidewall oxide layer degradation curve model is used as the best fitting model, the fitting calculation using the best fitting model includes: An initial value, through fitting to obtain the unknown parameters A1, A2, A3, , as well as , and then calculate the goodness of fit R 2 If R 2 The value does not meet the requirements, change , and perform the fitting again until R 2 The value meets the requirement.

[0282] According to an embodiment of the present disclosure, the semiconductor device lifetime prediction method further includes: determining a dominant factor causing parameter degradation of the semiconductor device according to a mathematical model with the best goodness of fit.

[0283] Figure 5b A block diagram of a semiconductor device lifetime prediction apparatus according to an embodiment of the present disclosure is shown.

[0284] According to an embodiment of the present disclosure, the semiconductor device lifetime prediction apparatus may be implemented as part or all of an electronic device by software, hardware, or a combination of both.

[0285] like Figure 5bAs shown, according to an embodiment of the present disclosure, a semiconductor device life prediction apparatus 500 includes: a first acquisition module 501, configured to acquire parameter information of the semiconductor device, wherein the parameter information of the semiconductor device is acquired through parameter pre-testing; a construction module 502, configured to construct test conditions according to the parameter information of the semiconductor device, wherein the test conditions are used to perform a life pre-test on the semiconductor device to acquire life pre-test data of the semiconductor device under different test conditions, wherein the life pre-test data includes degradation data of multiple target parameters of the semiconductor device; a first determination module 503, configured to determine the fastest degradation parameter among the multiple target parameters and the fastest degradation test condition among the different test conditions according to the life pre-test data; a second acquisition module 504, configured to acquire life test data, wherein the life test data is obtained by performing a formal life test on the semiconductor device using the fastest degradation parameter and the fastest degradation test condition; and a calculation module 505, configured to calculate the life of the semiconductor device by using interpolation calculation or mathematical model fitting based on the life test data obtained by the formal life test. The second determination module 506 is configured to determine the dominant factor causing the parameter degradation of the semiconductor device according to the mathematical model with the best goodness of fit.

[0286] According to an embodiment of the present disclosure, the first acquisition module is configured to acquire parameter information of the semiconductor device through parameter pre-testing, and the information includes: the maximum breakdown voltage of the drain under saturation conditions and the maximum value of the normal working voltage of the gate; or the maximum breakdown voltage of the drain under saturation conditions and at least two of the following: the maximum value of the normal working voltage of the gate, the gate voltage value when the gate current is maximum, and the gate voltage value when the substrate current is maximum. The acquisition of the parameter information of the semiconductor device through parameter pre-testing includes fixing the drain voltage, changing the gate voltage to obtain the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum; and fixing the gate voltage, changing the drain voltage to obtain the maximum breakdown voltage of the drain under the saturation condition. The fixed drain voltage, the gate voltage is changed to obtain the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum, including fixing the drain voltage to the drain voltage during normal operation, changing the gate voltage in equal steps within the gate voltage range, obtaining the corresponding curve between the gate current and the gate voltage and / or the corresponding curve between the substrate current and the gate voltage; and obtaining the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum according to the corresponding curve between the gate current and the gate voltage and / or the corresponding curve between the substrate current and the gate voltage. The gate voltage is fixed to the gate voltage during normal operation, the drain voltage is changed in equal steps within the drain voltage range, and the voltage when the drain breakdown occurs is determined as the maximum drain breakdown voltage.

[0287] According to an embodiment of the present disclosure, the construction module is configured to construct a test condition according to the parameter information of the semiconductor device, including constructing at least two of the following test conditions:

[0288] Condition 1: V g =V g@Igmax , V d =Ratio×BV on ;

[0289] Condition 2: V g =V g@Isubmax , V d =Ratio×BV on ;

[0290] Condition 3: V g =V gmax / p,V d =Ratio×BV on ;

[0291] Condition 4: V g =V gmax , V d =Ratio×BV on ;

[0292] Condition 5: V g =V gmax / q,V d =Ratio×BV on ,

[0293] Among them, V g is the gate voltage, V d is the drain voltage, V g@Igmax is the gate voltage value when the gate current is maximum, V g@Isubmax is the gate voltage value when the substrate current is maximum, V gmax BV is the maximum value of the gate normal working voltage. on is the maximum breakdown voltage of the drain under saturation conditions, and Ratio, p, and q are preset values, where: 0.7≤Ratio≤0.9; 1.5≤p≤2.5; 4.5≤q≤5.5; or 0.7≤Ratio≤0.9; p=2; q=5.

[0294] According to an embodiment of the present disclosure, the first determination module is configured to determine the fastest degradation parameter among the multiple target parameters and the fastest degradation test condition among the different test conditions according to the life pre-test data; the target parameters include at least two of the following: linear region drain current, saturation region drain current, gate linear region threshold voltage, gate saturation region threshold voltage. When any target parameter among the multiple target parameters first reaches a preset degradation rate of 3%, the any target parameter is determined as the fastest degradation parameter, and the test condition that makes the fastest degradation parameter first reach the preset degradation rate is determined as the fastest degradation test condition.

[0295] According to an embodiment of the present disclosure, the second acquisition module is configured to acquire life test data. The life test data is obtained by performing a formal life test on the semiconductor device using the fastest degradation parameter and the fastest degradation test condition. The formal life test includes acquiring the value of the fastest degradation parameter at each sampling time point under the fastest degradation test condition, and stopping the formal life test when the value meets at least one completion condition. The completion condition includes at least one of completion condition a, completion condition b, and completion condition c, wherein:

[0296] Completion condition a is that the fastest degradation parameter degrades to or exceeds a preset percentage of 10%;

[0297] Completion condition b is that the fastest degradation parameter has not degraded to the preset percentage of 10% but its degradation has been saturated;

[0298] Completion condition c is that the formal life test time reaches the initial experimental setting time, that is, one hundred thousand seconds.

[0299] According to an embodiment of the present disclosure, the calculation module is configured to calculate the semiconductor device life by interpolation calculation or mathematical model fitting based on the life test data obtained by the formal life test.

[0300] If the formal life test meets completion condition a, the following judgment is made:

[0301] If the fastest degradation parameter degrades to the preset percentage, the current sampling time point is the life span of the semiconductor device;

[0302] If the fastest degradation parameter degrades by more than the preset percentage, two sampling time points adjacent to the time point when the fastest degradation parameter degrades to the preset percentage are used for interpolation calculation to obtain the life time of the semiconductor device.

[0303] If the formal life test meets completion condition b or c, then based on the fastest degradation parameter value at the sampling time point obtained by the formal life test, a mathematical model is used to fit and calculate the degradation time when the fastest degradation parameter degrades to a preset percentage as the life time of the semiconductor device. The mathematical model includes at least one of the following: a gate oxide layer degradation curve model, a sidewall oxide layer degradation curve model, a fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model, and an enhanced fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model.

[0304] Wherein, taking the drain current as an example, the gate oxide layer degradation curve model is expressed by the following formula:

[0305]

[0306] Taking the gate threshold voltage as an example, the gate oxide layer degradation curve model is expressed by the following formula:

[0307]

[0308] in:

[0309] Parameter A3, , as well as are coefficients determined in the fitting process. The following parameters can be obtained through measurement, among which, The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, t is the degradation time, is the channel width;

[0310] is the substrate current;

[0311] Linear region drain current or saturation region drain current Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0312] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0313] Taking the drain current as an example, the fastest degradation parameter is the sidewall oxide layer degradation curve model is expressed by the following formula:

[0314]

[0315] Taking the gate threshold voltage as an example, the fastest degradation parameter is the sidewall oxide layer degradation curve model is expressed by the following formula:

[0316]

[0317] Among them, parameters A1, A2, , as well as are coefficients determined in the fitting process. The following parameters can be obtained through measurement, among which, The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, t is the degradation time, is the channel width;

[0318] is the substrate current;

[0319] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0320] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0321] Taking the drain current as an example, the fusion model of the gate oxide degradation curve model and the sidewall oxide degradation curve model is expressed by the following formula:

[0322]

[0323] Taking the gate threshold voltage as an example, the fusion model of the gate oxide degradation curve model and the sidewall oxide degradation curve model is expressed by the following formula:

[0324]

[0325] Among them, parameters A1, A2, A3, , as well as are coefficients determined in the fitting process. The following parameters can be obtained through measurement, among which, The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, is the degradation time, is the channel width;

[0326] is the substrate current;

[0327] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0328] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0329] Taking the drain current as an example, the enhanced fusion model of the gate oxide degradation curve model and the sidewall oxide degradation curve model is expressed by the following formula:

[0330]

[0331] Taking the gate threshold voltage as an example, the enhanced fusion model of the gate oxide degradation curve model and the sidewall oxide degradation curve model is expressed by the following formula:

[0332]

[0333] Among them, parameters A1, A2, A3, A4, , as well as are coefficients determined in the fitting process. The following parameters can be obtained through measurement, among which, The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, is the degradation time, is the channel width;

[0334] is the substrate current;

[0335] is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region;

[0336] is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

[0337] A plurality of mathematical models are used for fitting calculation, and the best model among the plurality of mathematical models is determined according to the calculation results, and the best fitting model is used for fitting calculation to determine the degradation time when the fastest degradation parameter degrades to a preset percentage. When the gate oxide layer degradation curve model, the side wall oxide layer degradation curve model, and the fusion model of the gate oxide layer degradation curve model and the side wall oxide layer degradation curve model all fail to fit or the goodness of fit R2 value does not meet the requirements, the enhanced fusion model of the side wall oxide layer degradation curve model is used as the best fitting model.

[0338] When the enhanced fusion model of the sidewall oxide layer degradation curve model is used as the best fitting model, the fitting calculation using the best fitting model includes giving an initial value of A4, obtaining the unknown parameters A1, A2, A3, , And then calculate the goodness of fit R 2 If R 2 The value does not meet the requirements. Change A4 and perform fitting again until R 2 The value meets the requirements.

[0339] According to an embodiment of the present disclosure, the second determination module is configured to determine the dominant factor causing the parameter degradation of the semiconductor device based on the mathematical model with the best goodness of fit, that is, it can be determined whether the sidewall oxide layer or the gate oxide layer is the dominant factor in the degradation through the best fitting formula.

[0340] The present disclosure also discloses an electronic device, Figure 6 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0341] like Figure 6 As shown, the electronic device includes a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method according to an embodiment of the present disclosure.

[0342] Figure 7 A schematic diagram showing the structure of a computer system suitable for implementing the method according to an embodiment of the present disclosure is shown.

[0343] like Figure 7 As shown, the computer system includes a processing unit, which can execute various methods in the above-mentioned embodiments according to a program stored in a read-only memory (ROM) or a program loaded from a storage part into a random access memory (RAM). In the RAM, various programs and data required for the operation of the computer system are also stored. The processing unit, ROM and RAM are connected to each other through a bus. An input / output (I / O) interface is also connected to the bus.

[0344] The following components are connected to the I / O interface: an input part including a keyboard, a mouse, etc.; an output part including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage part including a hard disk, etc.; and a communication part including a network interface card such as a LAN card, a modem, etc. The communication part performs a communication process via a network such as the Internet. The drive is also connected to the I / O interface as needed. Removable media, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive as needed so that the computer program read therefrom can be installed into the storage part as needed. Among them, the processing unit can be implemented as a processing unit such as a CPU, a GPU, a TPU, an FPGA, an NPU, etc.

[0345] In particular, according to an embodiment of the present disclosure, the method described above can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program tangibly contained on a machine-readable medium, and the computer program includes a program code for executing the above method. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part, and / or installed from a removable medium.

[0346] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0347] The units or modules involved in the embodiments described in the present disclosure may be implemented by software or programmable hardware. The units or modules described may also be set in a processor, and the names of these units or modules do not constitute limitations on the units or modules themselves in some cases.

[0348] As another aspect, the present disclosure further provides a computer-readable storage medium, which may be a computer-readable storage medium included in the electronic device or computer system in the above embodiment; or a computer-readable storage medium that exists independently and is not assembled into a device. The computer-readable storage medium stores one or more programs, and the programs are used by one or more processors to execute the method described in the present disclosure.

[0349] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A method for predicting the life of a semiconductor device, characterized in that: include: Acquiring parameter information of the semiconductor device, wherein the parameter information of the semiconductor device is acquired through parameter pre-testing; constructing test conditions according to the parameter information of the semiconductor device, wherein the test conditions are used to perform a life pre-test on the semiconductor device to obtain life pre-test data of the semiconductor device under different test conditions, wherein the life pre-test data includes degradation data of a plurality of target parameters of the semiconductor device; Determining the fastest degradation parameter among the multiple target parameters and the fastest degradation test condition among the different test conditions according to the life pre-test data, including: when any target parameter among the multiple target parameters reaches a preset degradation rate first, determining the any target parameter as the fastest degradation parameter, and determining the test condition under which the fastest degradation parameter reaches the preset degradation rate first as the fastest degradation test condition; Acquiring life test data, wherein the life test data is obtained by performing a formal life test on the semiconductor device using the fastest degradation parameter and the fastest degradation test condition, wherein the formal life test on the semiconductor device using the fastest degradation parameter and the fastest degradation test condition comprises: acquiring a value of the fastest degradation parameter at each sampling time point under the fastest degradation test condition, and stopping the formal life test when the value meets at least one completion condition; Based on the life test data obtained from the formal life test, the life of the semiconductor device is calculated by interpolation calculation or mathematical model fitting; the mathematical model includes at least one of the following: a gate oxide layer degradation curve model, a side wall oxide layer degradation curve model, a fusion model of the gate oxide layer degradation curve model and the side wall oxide layer degradation curve model, and an enhanced fusion model of the gate oxide layer degradation curve model and the side wall oxide layer degradation curve model.

2. The semiconductor device lifetime prediction method according to claim 1, characterized in that: The semiconductor device lifespan is the time required for the target parameter to degrade to a preset percentage under the influence of hot carriers.

3. The semiconductor device lifetime prediction method according to claim 1, wherein: The parameter information of the semiconductor device includes: the maximum breakdown voltage of the drain under saturation conditions and the nominal maximum value of the normal operating voltage of the gate; or the maximum breakdown voltage of the drain under saturation conditions and at least two of the following: the nominal maximum value of the normal operating voltage of the gate, the gate voltage value when the gate current is maximum, and the gate voltage value when the substrate current is maximum.

4. The semiconductor device lifetime prediction method according to claim 3, characterized in that: The obtaining parameter information of the semiconductor device through parameter pre-testing includes: Fixing the drain voltage, changing the gate voltage to obtain the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum; The gate voltage is fixed and the drain voltage is changed to obtain the maximum breakdown voltage of the drain under the saturation condition.

5. The semiconductor device lifetime prediction method according to claim 4, characterized in that: The fixing of the drain voltage and the changing of the gate voltage to obtain the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum include: The drain voltage is fixed to the drain voltage during normal operation, and the gate voltage is changed in equal steps within a preset gate voltage range to obtain a corresponding curve between the gate current and the gate voltage and / or a corresponding curve between the substrate current and the gate voltage; According to the corresponding curve between the gate current and the gate voltage and / or the corresponding curve between the substrate current and the gate voltage, the gate voltage value when the gate current is maximum and / or the gate voltage value when the substrate current is maximum are obtained.

6. The semiconductor device lifetime prediction method according to claim 4, characterized in that: The fixed gate voltage and the transformed drain voltage are used to obtain the maximum breakdown voltage of the drain under the saturation condition, including: fixing the gate voltage to the gate voltage during normal operation, transforming the drain voltage in equal steps within a preset drain voltage range, and determining the voltage when the drain breakdown occurs as the maximum breakdown voltage of the drain.

7. The semiconductor device lifetime prediction method according to claim 3, characterized in that: The constructing of the test conditions according to the parameter information of the semiconductor device includes constructing at least two of the following test conditions: Condition 1: V g = V g@Igmax , V d = Ratio × BV on ; Condition 2: V g = V g@Isubmax , V d = Ratio × BV on ; Condition 3: V g = V gmax / p, V d = Ratio × BV on ; Condition 4: V g = V gmax , V d = Ratio × BV on ; Condition 5: V g = V gmax / q, V d = Ratio × BV on , Among them, V g is the gate voltage, V d is the drain voltage, V g@Igmax is the gate voltage value when the gate current is maximum, V g@Isubmax is the gate voltage value when the substrate current is maximum, V gmax BV is the maximum value of the gate normal working voltage. on is the maximum breakdown voltage of the drain under saturation conditions, and Ratio, p, and q are the preset values.

8. The semiconductor device lifetime prediction method according to claim 7, characterized in that: 0.7≤Ratio≤0.9; 1.5≤p≤2.5; 4.5≤q≤5.5; or 0.7≤Ratio≤0.9; p=2; q=5.

9. The semiconductor device lifetime prediction method according to claim 1, characterized in that: The target parameters include at least two of the following: a drain current in a linear region, a drain current in a saturated region, a gate threshold voltage in a linear region, and a gate threshold voltage in a saturated region.

10. The semiconductor device lifetime prediction method according to claim 1, characterized in that: The completion condition includes at least one of completion condition a, completion condition b, and completion condition c, wherein: Completion condition a is that the fastest degradation parameter degrades to or exceeds a preset percentage; Completion condition b is that the fastest degradation parameter has not degraded to a preset percentage but its degradation has been saturated; Completion condition c is that the formal life test time reaches the initial experimental setting time.

11. The semiconductor device lifetime prediction method according to claim 10, characterized in that: The preset percentage in the formal life test is greater than the preset degradation rate of the fastest degradation parameter used in the preliminary test.

12. The semiconductor device lifetime prediction method according to claim 10, characterized in that: The method of calculating the semiconductor device life by interpolation based on the life test data obtained from the formal life test comprises: If the formal life test meets completion condition a, the following judgment is made: If the fastest degradation parameter degrades to the preset percentage, the current sampling time point is the life span of the semiconductor device; If the fastest degradation parameter degrades by more than the preset percentage, two sampling time points adjacent to the time point when the fastest degradation parameter degrades to the preset percentage are used for interpolation calculation to obtain the life time of the semiconductor device.

13. The semiconductor device lifetime prediction method according to claim 10, characterized in that: The method of calculating the semiconductor device life by fitting a mathematical model based on the life test data obtained from the formal life test comprises: If the formal life test meets completion condition b or c, then based on the fastest degradation parameter value at the sampling time point obtained by the formal life test, a mathematical model is used to fit and calculate the degradation time when the fastest degradation parameter degrades to a preset percentage as the life time of the semiconductor device.

14. The semiconductor device lifetime prediction method according to claim 13, characterized in that: The gate oxide layer degradation curve model is expressed by the following formula: If the fastest degradation parameter is the drain current, the following formula applies: If the fastest degradation parameter is the gate threshold voltage, the following formula applies: in: Parameter A3, , as well as are coefficients determined in the fitting process. The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, t is the degradation time, is the channel width; is the substrate current; is the drain current in the linear region or the drain current in the saturation region, and accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region; is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

15. The semiconductor device lifetime prediction method according to claim 13, characterized in that: The sidewall oxide layer degradation curve model is expressed by the following formula: If the fastest degradation parameter is the drain current, the following formula applies: If the fastest degradation parameter is the gate threshold voltage, the following formula applies: Among them, parameters A1, A2, , as well as are coefficients determined in the fitting process. The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, is the degradation time, is the channel width; is the substrate current; is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region; is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

16. The semiconductor device lifetime prediction method according to claim 13, characterized in that: The fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model is expressed by the following formula: If the fastest degradation parameter is the drain current, the following formula applies: If the fastest degradation parameter is the gate threshold voltage, the following formula applies: Among them, parameters A1, A2, A3, , as well as are coefficients determined in the fitting process. The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, t is the degradation time, is the channel width; is the substrate current; is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region; is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

17. The semiconductor device lifetime prediction method according to claim 13, characterized in that: The enhanced fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model is expressed by the following formula: If the fastest degradation parameter is the drain current, the following formula applies: If the fastest degradation parameter is the gate threshold voltage, the following formula applies: Among them, parameters A1, A2, A3, A4, , as well as are coefficients determined in the fitting process. The critical energy required for interface trap generation, is the critical energy required for impact ionization, n is the slope of the degradation curve, t , is the channel width; is the substrate current; is the drain current in the linear region or the drain current in the saturation region Accordingly, is the change of drain current in the linear region or the change of drain current in the saturation region, is the initial drain current in the linear region or the initial drain current in the saturation region; is the gate linear region threshold voltage or the gate saturation region threshold voltage, accordingly, is the change of the gate threshold voltage in the linear region or the change of the gate threshold voltage in the saturation region, is the initial threshold voltage of the gate linear region or the initial threshold voltage of the gate saturation region.

18. The semiconductor device lifetime prediction method according to claim 17, characterized in that: The method of using a mathematical model to fit and calculate the degradation time when the fastest degradation parameter degrades to a preset percentage includes: A plurality of mathematical models are used for fitting calculation, and a best fitting model among the plurality of mathematical models is determined according to the calculation results. The best fitting model is used for fitting calculation to determine the degradation time when the fastest degradation parameter degrades to a preset percentage.

19. The semiconductor device lifetime prediction method according to claim 18, characterized in that: The method of using multiple mathematical models to perform fitting calculations and determining the best fitting model among the multiple mathematical models according to the calculation results includes: When the gate oxide degradation curve model, the sidewall oxide degradation curve model, and the fusion model of the gate oxide degradation curve model and the sidewall oxide degradation curve model all fail to fit or the goodness of fit R 2 When all values ​​do not meet the requirements, the enhanced fusion model of the sidewall oxide layer degradation curve model is used as the best fitting model.

20. The semiconductor device lifetime prediction method according to claim 19, characterized in that: When the enhanced fusion model of the sidewall oxide layer degradation curve model is used as the best fitting model, the fitting calculation using the best fitting model includes: Given An initial value, through fitting to obtain coefficients A1, A2, A3, , as well as , and then calculate the goodness of fit R 2 If R 2 The value does not meet the requirements, change , and perform the fitting again until R 2 The value meets the requirement.

21. The semiconductor device lifetime prediction method according to claim 1, characterized in that: Also includes: The dominant factor causing the parameter degradation of the semiconductor device is determined according to the mathematical model with the best goodness of fit.

22. A semiconductor device life prediction device, characterized in that: include: A first acquisition module is configured to acquire parameter information of the semiconductor device, wherein the parameter information of the semiconductor device is acquired through parameter pre-testing; a construction module, configured to construct test conditions according to parameter information of the semiconductor device, wherein the test conditions are used to perform a life pre-test on the semiconductor device to obtain life pre-test data of the semiconductor device under different test conditions, wherein the life pre-test data includes degradation data of a plurality of target parameters of the semiconductor device; A first determination module is configured to determine the fastest degradation parameter among the multiple target parameters and the fastest degradation test condition among the different test conditions according to the life pre-test data, including: when any target parameter among the multiple target parameters reaches a preset degradation rate first, determining the any target parameter as the fastest degradation parameter, and determining the test condition under which the fastest degradation parameter reaches the preset degradation rate first as the fastest degradation test condition; A second acquisition module is configured to acquire life test data, wherein the life test data is obtained by performing a formal life test on the semiconductor device using the fastest degradation parameter and the fastest degradation test condition, wherein the formal life test on the semiconductor device using the fastest degradation parameter and the fastest degradation test condition comprises: acquiring a value of the fastest degradation parameter at each sampling time point under the fastest degradation test condition, and stopping the formal life test when the value meets at least one completion condition; A calculation module is configured to calculate the life of the semiconductor device by interpolation calculation or mathematical model fitting based on the life test data obtained from the formal life test; the mathematical model includes at least one of the following: a gate oxide layer degradation curve model, a sidewall oxide layer degradation curve model, a fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model, and an enhanced fusion model of the gate oxide layer degradation curve model and the sidewall oxide layer degradation curve model.

23. The device according to claim 22, characterized in that Also includes: The second determination module is configured to determine the dominant factor causing the parameter degradation of the semiconductor device according to the mathematical model with the best fitting goodness of fit.

24. An electronic device, characterized in that: Comprises a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method according to any one of claims 1-21.

25. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the method according to any one of claims 1 to 21 is implemented.

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