Cross-domain error injection verification method, device, equipment and storage medium

Abstract

The present invention provides a cross-domain error injection verification method, device, equipment and storage medium, the method comprising: in the power-on state of the multi-core heterogeneous chip, running an error injection detection program, writing a first error value into a first register in a first domain at a first speed, and writing a second error value into a second register in a second domain at a second speed through inter-core communication, the first speed matches the frequency of a first clock, the second speed matches the frequency of a second clock, and the first speed is different from the second speed; asynchronously obtaining the error value detection results of the first domain and the second domain, wherein the time difference between obtaining the error value detection results of the first domain and the second domain is related to the frequency difference between the first clock and the second clock. The method of the present invention can complete the error injection verification of the chip system across hardware domains and time domains.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of injection error self-checking, and in particular to a cross-domain injection error verification method, device, equipment and storage medium. Background Art

[0002] Automotive chips have high requirements for safety and need to ensure that the chip works properly before each startup. Each time the chip is started, the chip will be verified for hardware security, and the software and hardware will work together to ensure that the verified part is in normal working condition. The commonly used security verification method is error injection, that is, actively injecting error data into the chip through specific means to see if the chip can detect the error and achieve the purpose of detection.

[0003] The chip's error injection register is a hardware-level error injection technology added to improve the chip's reliability and stability. These registers are usually added by chip designers when designing the chip. When the chip is started, the error injection value is written to the error injection register. The chip needs to recognize the error and then prompt the error through the error flag of the error status register. If the correct value is written to the error injection register, the chip will not recognize the error, thereby ensuring that the chip's error detection mechanism works properly.

[0004] Traditional error injection is usually done in the same hardware domain based on the same clock domain, which has limitations. However, automotive chips contain multiple isolated hardware domains, each of which consists of specific hardware resources and is configured to run a specific operating system. Different hardware domains may have clocks of different frequencies, and conventional error injection technology cannot meet this complex scenario. Summary of the invention

[0005] The present invention provides a cross-domain error injection verification method, device, equipment and storage medium capable of completing the error injection verification of a chip system across hardware domains and time domains.

[0006] In order to solve the above technical problems, an embodiment of the present invention provides a cross-domain error injection verification method, which is applied to a first domain of a multi-core heterogeneous chip, wherein the chip further includes at least one second domain, a first clock is used in the first domain, and a second clock is used in the second domain, and the frequency of the first clock is different from the frequency of the second clock. The method includes:

[0007] In a power-on state of the multi-core heterogeneous chip, an injection error detection program is run to write a first error value into a first register in a first domain at a first speed, and to write a second error value into a second register in a second domain at a second speed through inter-core communication, wherein the first speed matches a frequency of a first clock, the second speed matches a frequency of a second clock, and the first speed is different from the second speed;

[0008] The error value detection results of the first domain and the second domain are obtained asynchronously, wherein a time difference between obtaining the error value detection results of the first domain and the second domain is related to a frequency difference between a first clock and a second clock.

[0009] In some embodiments, the method further comprises:

[0010] When the error value detection result of the first domain and the error value detection result of the second domain are obtained, identifying the error value detection result;

[0011] If the error value detection result indicates that both the first domain and the second domain detect the error value correctly, write clear data into the first register based on the first speed, and write the clear data into the second register at the second speed through inter-core communication, wherein the clear data is used to clear the error value written into the register;

[0012] A clear operation detection result of the first domain and the second domain is obtained asynchronously, and the clear operation detection result indicates whether the corresponding domain clears the error value written in the register.

[0013] In some embodiments, the method further comprises:

[0014] Recording data stored in the first register and the second register before writing corresponding error values;

[0015] When the clear operation detection result of the first domain and the clear operation detection result of the second domain are obtained, identifying the clear operation detection result;

[0016] If the clear operation detection result indicates that the first domain and the second domain have cleared the corresponding error values, the previously stored data is written into the first register based on the first speed, and the previously stored data is written into the second register at the second speed through inter-core communication.

[0017] In some embodiments, the method further comprises:

[0018] Calculating and determining a difference between the frequency of the first clock and the frequency of the second clock;

[0019] The time difference is determined by calculation based on the difference, the writing speed of the domain where the corresponding low-frequency clock is located, and the size of the written error value.

[0020] In some embodiments, the first domain has a main core and a secondary core, and the running of the injection error detection program includes:

[0021] Running an injection error detection program based on the main core;

[0022] The method further comprises:

[0023] When the main core completes the startup, the secondary core is notified to start.

[0024] In some embodiments, the method further comprises:

[0025] Pre-store the write values ​​of different registers corresponding to different domains;

[0026] Based on the pre-stored information, corresponding values ​​are written into different registers in different domains during the power-on startup phase.

[0027] In some embodiments, the first domain is a security domain, the second domain is a power supply domain or a functional domain, or the first domain and the second domain are both functional domains.

[0028] Another embodiment of the present invention also provides a cross-domain error injection verification device, which is applied to a first domain of a multi-core heterogeneous chip, wherein the chip further includes at least one second domain, a first clock is used in the first domain, and a second clock is used in the second domain, wherein the frequency of the first clock is greater than the frequency of the second clock, and the device includes:

[0029] a writing module, configured to run an injection error detection program in a power-on state of the multi-core heterogeneous chip, write a first error value into a first register in a first domain at a first speed, and write a second error value into a second register in a second domain at a second speed through inter-core communication, wherein the first speed matches the frequency of a first clock, the second speed matches the frequency of a second clock, and the first speed is greater than the second speed;

[0030] An acquisition module is used to asynchronously obtain error value detection results of the first domain and the second domain, wherein a time difference between obtaining the error value detection results of the first domain and the second domain is related to a frequency difference between a first clock and a second clock.

[0031] Another embodiment of the present invention further provides an electronic device, including:

[0032] at least one processor; and,

[0033] a memory communicatively connected to the at least one processor; wherein,

[0034] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to implement the cross-domain error injection verification method as described in any one of the embodiments above.

[0035] Another embodiment of the present invention further provides a storage medium, which includes a stored program, wherein when the program is running, a device including the storage medium is controlled to execute the cross-domain error injection verification method as described in any one of the embodiments above.

[0036] Based on the disclosure of the above embodiments, it can be known that the beneficial effects of the embodiments of the present invention include that in the scenario of functional safety verification of the chip hardware, the solution based on the present application can realize cross-hardware domain and cross-clock domain detection, and the hardware function verification has a high accuracy rate, which effectively solves the technical problems of cumbersome and complex cross-hardware domain and clock domain verification and low accuracy in the existing solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 The present invention is a flowchart of a cross-domain error injection verification method in an embodiment of the present invention.

[0039] Figure 2 The present invention is a schematic diagram of an application process of a cross-domain error injection verification method in an embodiment of the present invention.

[0040] Figure 3 The present invention is another application flow diagram of a cross-domain error injection verification method in an embodiment of the present invention.

[0041] Figure 4 It is a structural block diagram of a cross-domain error injection verification device in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but are not intended to limit the present invention.

[0043] It should be understood that various modifications may be made to the embodiments disclosed herein. Therefore, the following description should not be considered as limiting, but merely as an example of an embodiment. Other modifications within the scope of the present disclosure will occur to those skilled in the art.

[0044] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0045] These and other characteristics of the invention will become apparent from the following description of a preferred form of embodiment given as a non-limiting example, with reference to the accompanying drawings.

[0046] It should also be understood that, although the invention has been described with reference to some specific examples, those skilled in the art will be able to realize many other equivalent forms of the invention that have the characteristics recited in the claims and are therefore within the scope of protection defined thereby.

[0047] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0048] Specific embodiments of the present disclosure are described hereinafter with reference to the accompanying drawings; however, it should be understood that the disclosed embodiments are merely examples of the present disclosure, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant details. Therefore, the specific structural and functional details disclosed herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present disclosure in a variety of ways with substantially any suitable detailed structure.

[0049] This specification may use the phrases "in one embodiment," "in another embodiment," "in a further embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present disclosure.

[0050] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0051] For chips with multiple hardware domains, especially when there are different clock domains, the traditional error detection hardware function mechanism is not applicable. Therefore, for chips with multiple hardware domains, the existing solution can only perform error detection on each hardware domain of the chip separately. However, error detection for each hardware domain separately will lead to a complicated security verification process, that is, there is a cumbersome and complex cross-hardware domain or cross-clock domain verification process, which is not only difficult to handle in software, but also cannot meet the time requirements, increasing the startup time of the chip.

[0052] In order to solve the above problems, Figure 1 As shown, an embodiment of the present invention provides a cross-domain error injection verification method, which is applied to a multi-core heterogeneous chip, mainly applied to a first domain of a multi-core heterogeneous chip, the chip also includes at least one second domain, a first clock is used in the first domain, a second clock is used in the second domain, and the frequency of the first clock is different from the frequency of the second clock. The method includes:

[0053] S1: in a power-on state of the multi-core heterogeneous chip, running an injection error detection program, writing a first error value into a first register in a first domain at a first speed, and writing a second error value into a second register in a second domain at a second speed through inter-core communication, wherein the first speed matches the frequency of a first clock, the second speed matches the frequency of a second clock, and the first speed is different from the second speed;

[0054] S2: asynchronously obtaining error value detection results of the first domain and the second domain, wherein a time difference between obtaining the error value detection results of the first domain and the second domain is related to a frequency difference between a first clock and a second clock.

[0055] Specifically, "cross-hardware domain" and "cross-clock domain" are two important concepts in hardware safety verification.

[0056] "Cross-hardware domain" refers to the data transmission and interaction between different hardware domains when there are multiple hardware domains in the system-on-chip SOC. In digital system design, the data interface and communication protocol between different hardware domains need to be reasonably designed and managed to ensure the correct transmission and processing of data.

[0057] "Cross-clock domain" refers to when there are multiple clock signals in a digital system, these clock signals may have different clock frequencies or phase relationships. In the design, special care should be taken to handle data transmission and synchronization across clock domains to ensure that there will be no timing problems after data transmission.

[0058] The cross-domain error injection verification method in this embodiment is that when the multi-core heterogeneous chip is powered on, the system runs the error injection detection program, writes the pre-configured first error value in the program into the first register in the first domain at a first speed, and writes the pre-configured second error value into the second register in the second domain at a second speed through inter-core communication. The process is performed by the first domain, that is, at this time, only the first domain is started to complete the error injection verification of multiple different domains, and the multiple different domains are assisted to complete the startup. There are multiple different hardware modules in each domain, such as multiple cores, including a main core and a negative core. The first domain and a hardware module corresponding to the main core in a second domain first complete the error injection verification, and then the hardware module completes the error injection verification and startup of the remaining hardware modules. Since the clock domains running in the first domain and the second domain are different, that is, the first clock of the first domain is different from the second clock of the second domain, the operating frequency of the first clock is greater than the operating frequency of the second clock, that is, the first clock is faster than the second clock. Therefore, in order to match the difference in clock frequency, the first domain writes error values ​​to its own register and the register in the second domain at different writing speeds to match the clock frequency of the corresponding domain. When the first domain completes the error injection operation of itself and a second domain, it will first obtain the error value detection result of the first domain, or it can also obtain the error value detection result of the second domain first, which is not determined. Assuming that the clock frequency of the first domain is high, its processing speed is high, and the clock frequency of the second domain is low, the processing speed is slower than the first domain. Therefore, in this case, the first domain will first obtain the detection result of its own domain, and then wait for a period of time to obtain the error value detection result fed back by the second domain through inter-core communication. The waiting period is the same as the time difference, and the time difference is related to the frequency difference between the first clock and the second clock, that is, the more the frequency of the second clock is less than the frequency of the first clock, the longer the time difference, and vice versa.

[0059] Based on the contents of the above embodiments, it can be seen that the beneficial effects of this embodiment include that in the scenario of functional safety verification of the chip hardware, the solution based on the present application can realize cross-hardware domain and cross-clock domain detection, and the hardware function verification has a high accuracy rate, which effectively solves the technical problems of cumbersome and complex cross-hardware domain and clock domain verification and low accuracy in the existing solutions.

[0060] In one embodiment, the process of writing corresponding error values ​​into different registers of the first domain and the second domain is performed synchronously, that is, the writing process is performed at the same time, so as to speed up the injection error detection efficiency.

[0061] The method further comprises:

[0062] S3: when the error value detection result of the first domain and the error value detection result of the second domain are obtained, identifying the error value detection result;

[0063] S4: if the error value detection result indicates that both the first domain and the second domain detect the error value correctly, write clear data into the first register based on the first speed, and write the clear data into the second register at the second speed through inter-core communication, wherein the clear data is used to clear the error value written into the register;

[0064] S5: asynchronously obtaining clear operation detection results of the first domain and the second domain, wherein the clear operation detection results indicate whether the corresponding domain clears the error value written in the register.

[0065] As described above, assuming that the frequency of the first clock of the first domain is higher than the frequency of the second clock of the second domain, in this embodiment, the first domain will first obtain the error value detection result of the first domain, and then wait for the error value detection result of the second domain. After obtaining the error value detection result of the second domain, the first domain will identify and analyze the obtained error value detection result. If it is determined based on the analysis and identification that the error value detection result indicates that both the first domain and the second domain have correctly detected the error value, then clear data is written to the first register based on the first speed, and the clear data is written to the second register at the second speed through inter-core communication at the same time. The clear data is used to clear the error value written in the register so that the error value is no longer stored in the register. Afterwards, the first domain will first obtain the clear operation detection result of its own domain, and also wait for the clear operation detection result fed back by the second domain through inter-core communication. The clear operation detection result indicates whether the corresponding domain has completed the clearing of the error value written in the register.

[0066] In another embodiment, the method further comprises:

[0067] S6: Recording the data stored in the first register and the second register before writing the corresponding error value;

[0068] S7: when the clear operation detection result of the first domain and the clear operation detection result of the second domain are obtained, identifying the clear operation detection result;

[0069] S8: If the clear operation detection result indicates that the corresponding error values ​​of both the first domain and the second domain have been cleared, the previously stored data is written into the first register based on the first speed, and the previously stored data is written into the second register at the second speed through inter-core communication.

[0070] Exemplarily, the first domain records the data stored in the first register and the second register before the corresponding error value is written, such as the number of the corresponding storage register or the number of the domain where the register is located and the corresponding initial data, that is, the data before the corresponding error value is written. When the clear operation detection result of the first domain and the clear operation detection result of the second domain are obtained, the clear operation detection result is identified. If it is known based on the identification result that the first domain and the second domain have cleared the corresponding error value, the corresponding initial data is determined in the stored data based on the number of the current domains, and then the first domain writes the corresponding initial data to the first register based on the first speed, and writes the initial data of the second register in the corresponding second domain to the second register at the second speed through inter-core communication. At this time, the error injection verification process of the first domain is completed, and the domains that are subjected to error injection verification by the first domain, including the first domain and part or all of the second domain, at least complete the verification of the main hardware module, such as the main core, so the main core is started, and other hardware modules in the domain, such as the secondary core, can be verified to complete the startup.

[0071] Specifically, in this embodiment, the first domain has a main core and a secondary core, and the running of the injection error detection program includes:

[0072] S9: running an injection error detection program based on the main core;

[0073] That is, the executor of the scheme in this embodiment is the main core in the first domain, and the main core in each domain is powered on, verified, and started first. Therefore, when the main core of the first domain runs the error injection detection program, it also communicates with the main cores of other domains through inter-core communication to write, clear, and write initial data of error values ​​to complete the error injection verification of the main core.

[0074] In another embodiment, the method further comprises:

[0075] S10: When the main core completes the startup, notify the secondary core to start up.

[0076] In this embodiment, the startup and error injection verification of the secondary cores in the hardware domain are both implemented by the main core in the corresponding domain, and as mentioned above, the startup of the main core needs to rely on the main core in the first domain to complete. When the main core in the domain completes the startup, the main core will notify the secondary core to start up. The specific process of the startup is not fixed and can be flexibly configured. For example, the main core can perform error injection verification on some or all of the secondary cores, and allow the secondary core to start after the verification passes, or it can skip the error injection verification and directly control the startup of the secondary core, or the secondary core itself completes the error injection detection and starts after passing the detection.

[0077] In another embodiment, the method further comprises:

[0078] S11: pre-store write values ​​of different registers corresponding to different domains;

[0079] S12: Writing corresponding values ​​into different registers in different domains during the power-on startup phase based on pre-stored information.

[0080] For example, the error injection program in the first domain will pre-configure the numbers of different domains and the corresponding error values, that is, write values. For example, the error value corresponding to the second domain a is 1, the error value corresponding to the second domain b is 2, and so on. When the chip is powered on, the main core in the first domain is powered on first to complete the startup, and then the error injection program is run to write the corresponding error values ​​to different registers in different domains based on the pre-stored information to complete the injection of error values.

[0081] Furthermore, the method further comprises:

[0082] S13: Calculate and determine the difference between the frequency of the first clock and the frequency of the second clock;

[0083] S14: Calculate and determine the time difference based on the difference, the writing speed of the domain where the corresponding low-frequency clock is located, and the size of the written error value.

[0084] Specifically, the writing speed of the error value can be pre-configured, or it can be formed by adjusting the first domain based on the clock frequency and the pre-configured basic writing speed value. For the time difference, the time difference is different for different domains and different clock frequencies. The first domain can calculate the time difference in real time, or it can calculate it only once, and then record the time difference, and then count based on the recorded duration value to determine whether the test result value is received in the corresponding time period. When calculating the time difference, it includes calculating and determining the difference between the frequency of the first clock and the frequency of the second clock. Assuming that the frequency of the first clock in this embodiment is lower than the frequency of the second clock, such as the frequency of the first clock is 32KHz and the frequency of the second clock is 24MHz, the two frequencies are subtracted to obtain the frequency difference, and then the time difference is calculated based on the difference, the first speed and the size of the written value. That is, the time difference is not only controlled by the clock frequency difference, but also by the first speed and the size of the written value. If the written value is large and the corresponding binary digits are large, then the time to complete the writing is longer, and the waiting time will be extended. Similarly, the first speed is the same. If the first speed is small, the time difference is long, and if the first speed is large, the time difference is shortened. In the case of the above embodiment, the first domain first obtains the detection result fed back by the second domain, and then obtains the detection result of the first domain itself.

[0085] In an application embodiment, if Figure 2As shown, the first domain is a power supply domain (such as the RTC domain in the figure), and the second domain is any one of a security domain (such as the SAF domain in the figure), a functional domain (such as the AP domain in the figure), or the first domain and the second domain are any one of functional domains. That is, the first domain can be any domain in the chip system, which is dynamically changing. For example, in the first scenario, the first domain is a security domain, and the second domain is other hardware domains, while in another scenario, a second domain is the first domain, and the first domain can be the second domain in other first scenarios for error injection verification. For example, the first functional domain can perform error injection detection in the power-on phase for one or more other functional domains, and the security domain can complete error injection detection in the power-on phase for the functional domain.

[0086] Continue to combine Figure 2 and Figure 3 As shown, taking the scenario shown in the figure as an example, the SAF domain is used to store content with functional safety requirements. The functions of the usual ASIL D and SIL 3 and other related requirements are all executed by the SAF domain. The RTC domain is in a normal power supply state most of the time, which is used to power the chip to enter the low power mode and wake up the chip from the low power mode to enter the normal working mode. The AP domain is an area of ​​normal functions, without the requirements of special functional safety requirements. Generally, it is equipped with a processor core with strong processing capabilities and a fast processing speed. There can be multiple clocks inside the chip, such as: 24MHz clock and 32KHz clock; the 24MHz clock is the clock used by each IP in the normal working state, and the 32KHz clock is the clock used in the normal low power mode, which is used for system timing and waking up the system. Each IP works based on different clocks in different working states. In this embodiment, a Power managment unit (PMU), i.e., a power management module, is provided in the RTC domain to control the power supply to different hardware domains. When the PMU is running, it needs to be based on a specific clock frequency. In this embodiment, the PMU supports access control under 24MHz clock and 32KHz clock respectively. When the system is in low power mode, the RTC domain remains powered on, the 32KHz clock remains running, and the system's 24MHz clock stops running. When waking up from low power mode or starting from shutdown state, the PMU controls the SAF domain to power on first, turns on the 24MHz clock and executes the safety error verification process. For the specific process, see Figure 3 The process shown includes backing up the original data of the register, injecting errors into the register, detecting the error injection identification results, clearing the injected error data, detecting the clearing results, and filling the backed-up original data into the register to complete the verification. After successful verification, the AP domain is powered on to complete the system startup process. The SAF domain usually contains multiple cores: the main core and the secondary core; when the chip is started, the main core is started first, and other secondary cores are started after the security mechanism is successfully verified.

[0087] When the system starts, the main core of each domain has corresponding registers that need to be noted, and each sub-core can also be set with registers that need to be noted, which can be completed by the main core or itself. Error injection detection. The RTC domain also contains registers that need to be noted at this stage. The error injection registers of the SAF domain need to work under a 24MHz clock, while the error injection registers in the RTC domain need to work under a 32KHz clock. This leads to the problem of cross-hardware domain and cross-clock domain when the RTC domain controls the error injection detection of its own domain and the SAF domain. When implementing the solution in this embodiment, the PMU of the first domain is the executor, which simultaneously injects errors into the registers of the SAF domain and the RTC domain, that is, writes the corresponding error values ​​in each register at different speeds. In order to speed up the error injection speed, this embodiment performs error injection on each register in parallel. When implementing error injection for the SAF domain and the RTC domain at the same time, this embodiment sets the error injection register of the RTC domain working at 32KHz to the SAF domain core read-write mode. At this time, the main core of the SAF domain working at 24MHz can be uniformly adopted to complete the reading and writing of the registers of the two domains, or the clocks of the currently operated domains can be used to complete the reading and writing of the registers, such as completing the reading and writing based on the first clock in the first domain and completing the reading and writing based on the second clock in the second domain. Since the 32K error injection register of the RTC domain works at a slower clock, when reading and writing it, a specific delay needs to be set to wait for the register of the RTC domain working at 32KHz to have sufficient time to complete the reading and writing of the register. The length of the delay can be determined by the frequency difference between the first clock and the second clock, the writing speed to the domain where the low-frequency clock is located (such as the first speed) and the size of the written value.

[0088] like Figure 4 As shown, another embodiment of the present invention also provides a cross-domain error injection verification device 100, which is applied to a first domain of a multi-core heterogeneous chip, the chip also includes at least one second domain, a first clock is used in the first domain, and a second clock is used in the second domain, the frequency of the first clock is greater than the frequency of the second clock, and the device includes:

[0089] a writing module, configured to run an injection error detection program in a power-on state of the multi-core heterogeneous chip, write a first error value into a first register in a first domain at a first speed, and write a second error value into a second register in a second domain at a second speed through inter-core communication, wherein the first speed matches the frequency of a first clock, the second speed matches the frequency of a second clock, and the first speed is greater than the second speed;

[0090] An acquisition module is used to asynchronously obtain error value detection results of the first domain and the second domain, wherein a time difference between obtaining the error value detection results of the first domain and the second domain is related to a frequency difference between a first clock and a second clock.

[0091] In some embodiments, the apparatus further comprises:

[0092] An identification module, configured to identify the error value detection result when the error value detection result of the first domain and the error value detection result of the second domain are obtained;

[0093] The writing module is further used for writing clearing data into the first register based on the first speed when the error value detection result indicates that both the first domain and the second domain have correctly detected the error value, and writing the clearing data into the second register at the second speed through the inter-core communication, wherein the clearing data is used for clearing the error value in the write register;

[0094] The obtaining module is further used to asynchronously obtain clearing operation detection results of the first domain and the second domain, wherein the clearing operation detection results indicate whether the corresponding domain clears the error value written in the register.

[0095] In some embodiments, the apparatus further comprises:

[0096] A recording module, used for recording data stored in the first register and the second register before writing corresponding error values;

[0097] An identification module, configured to identify the clear operation detection result when the clear operation detection result of the first domain and the clear operation detection result of the second domain are obtained;

[0098] The write module is also used to write previously stored data into the first register based on the first speed when the clear operation detection result indicates that the corresponding error values ​​of the first domain and the second domain have been cleared, and write the previously stored data into the second register at the second speed through inter-core communication.

[0099] In some embodiments, the apparatus further comprises:

[0100] A calculation module, used for calculating and determining the difference between the frequency of the first clock and the frequency of the second clock;

[0101] The determination module is used to calculate and determine the time difference according to the difference, the writing speed of the domain where the corresponding low-frequency clock is located, and the size of the written error value.

[0102] In some embodiments, the first domain has a main core and a secondary core, and the running of the injection error detection program includes:

[0103] Running an injection error detection program based on the main core;

[0104] The device also includes:

[0105] When the main core completes the startup, the secondary core is notified to start.

[0106] In some embodiments, the apparatus further comprises:

[0107] A pre-storage module, used to pre-store write values ​​of different registers corresponding to different domains;

[0108] The writing module is also used to write corresponding values ​​into different registers in different domains during the power-on startup phase according to pre-stored information.

[0109] In some embodiments, the first domain is a security domain, the second domain is a power supply domain or a functional domain, or the first domain and the second domain are both functional domains.

[0110] Another embodiment of the present invention further provides an electronic device, including:

[0111] at least one processor; and,

[0112] a memory communicatively connected to the at least one processor; wherein,

[0113] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to implement the cross-domain error injection verification method as described in any one of the embodiments above.

[0114] Another embodiment of the present invention further provides a storage medium, which includes a stored program, wherein when the program is running, a device including the storage medium is controlled to execute the cross-domain error injection verification method as described in any one of the embodiments above.

[0115] It should be noted that the computer storage medium of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access storage medium (RAM), a read-only storage medium (ROM), an erasable programmable read-only storage medium (EPROM or flash memory), an optical fiber, a portable compact disk read-only storage medium (CD-ROM), an optical storage medium, a magnetic storage medium, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate or transmit a program configured to be used by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, antenna, optical cable, RF, etc., or any suitable combination of the above.

[0116] The above embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention. The protection scope of the present invention is defined by the claims. Those skilled in the art may make various modifications or equivalent substitutions to the present invention within the essence and protection scope of the present invention, and such modifications or equivalent substitutions shall also be deemed to fall within the protection scope of the present invention.

Claims

1. A cross-domain error injection verification method, characterized in that: Applied to a first domain of a multi-core heterogeneous chip, the chip further includes at least one second domain, a first clock is used in the first domain, a second clock is used in the second domain, and a frequency of the first clock is different from a frequency of the second clock, the method includes: In a power-on state of the multi-core heterogeneous chip, an injection error detection program is run to write a first error value into a first register in a first domain at a first speed, and to write a second error value into a second register in a second domain at a second speed through inter-core communication, wherein the first speed matches a frequency of a first clock, the second speed matches a frequency of a second clock, and the first speed is different from the second speed; The error value detection results of the first domain and the second domain are obtained asynchronously, wherein a time difference between obtaining the error value detection results of the first domain and the second domain is related to a frequency difference between a first clock and a second clock.

2. The cross-domain error injection verification method according to claim 1, characterized in that: The method further comprises: When the error value detection result of the first domain and the error value detection result of the second domain are obtained, identifying the error value detection result; If the error value detection result indicates that both the first domain and the second domain detect the error value correctly, write clear data into the first register based on the first speed, and write the clear data into the second register at the second speed through inter-core communication, wherein the clear data is used to clear the error value written into the register; A clear operation detection result of the first domain and the second domain is obtained asynchronously, and the clear operation detection result indicates whether the corresponding domain clears the error value written in the register.

3. The cross-domain error injection verification method according to claim 2, characterized in that: The method further comprises: Recording data stored in the first register and the second register before writing corresponding error values; When the clear operation detection result of the first domain and the clear operation detection result of the second domain are obtained, identifying the clear operation detection result; If the clear operation detection result indicates that the first domain and the second domain have cleared the corresponding error values, the previously stored data is written into the first register based on the first speed, and the previously stored data is written into the second register at the second speed through inter-core communication.

4. The cross-domain error injection verification method according to claim 1, characterized in that: The method further comprises: Calculating and determining a difference between the frequency of the first clock and the frequency of the second clock; The time difference is determined by calculation based on the difference, the writing speed of the domain where the corresponding low-frequency clock is located, and the size of the written error value.

5. The cross-domain error injection verification method according to claim 1, characterized in that: The first domain has a main core and a secondary core, and the running of the injection error detection program includes: Running an injection error detection program based on the main core; The method further comprises: When the main core completes the startup, the secondary core is notified to start.

6. The cross-domain error injection verification method according to claim 1, characterized in that: The method further comprises: Pre-store the write values ​​of different registers corresponding to different domains; Based on the pre-stored information, corresponding values ​​are written into different registers in different domains during the power-on startup phase.

7. The cross-domain error injection verification method according to claim 1, characterized in that: The first domain is a security domain, the second domain is any one of a power supply domain and a functional domain, or the first domain and the second domain are both any one of a functional domain.

8. A cross-domain injection error verification device, characterized in that: The device is applied to a first domain of a multi-core heterogeneous chip, the chip further comprising at least one second domain, a first clock is used in the first domain, a second clock is used in the second domain, and a frequency of the first clock is different from a frequency of the second clock. The device comprises: a writing module, configured to run an injection error detection program in a power-on state of the multi-core heterogeneous chip, write a first error value into a first register in a first domain at a first speed, and write a second error value into a second register in a second domain at a second speed through inter-core communication, wherein the first speed matches the frequency of a first clock, the second speed matches the frequency of a second clock, and the first speed is different from the second speed; An acquisition module is used to asynchronously obtain error value detection results of the first domain and the second domain, wherein a time difference between obtaining the error value detection results of the first domain and the second domain is related to a frequency difference between a first clock and a second clock.

9. An electronic device, comprising: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to implement the cross-domain error injection verification method according to any one of claims 1 to 7.

10. A storage medium comprising a stored program, wherein: When the program is running, the device including the storage medium is controlled to execute the cross-domain error injection verification method as described in any one of claims 1-7.

Images