A chip and method for configuring electronic fuse

Abstract

The present disclosure provides a chip and method for configuring an electronic fuse, wherein the chip includes: a state machine, whose states include a burning state, a reading state, and a serial control state; a shift register, which receives and temporarily stores first control information and data to be burned sent from the outside, and is configured to receive, store and output the burning result; wherein the first control information is used to control the state machine to enter the burning state or the reading state; a first pin, through which the shift register receives the first control information sent from the outside; the state machine is configured to: in the serial control state, obtain the first control information and the data to be burned from the shift register in a clock counting cycle; in the burning state, write the data to be burned in the shift register into the electronic fuse; in the reading state, read the burning result of the electronic fuse and store it in the shift register; based on a reset signal, read the burning result of the electronic fuse and store it in the shift register.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and more particularly to a chip and method for configuring an electronic fuse. Background Art

[0002] One Time Programmable (OTP) memory such as an electronic fuse can be used for factory calibration of integrated circuits. Generally, an electronic fuse can include an electronic fuse (EFuse). The electronic fuse burns the calibration data into the electronic fuse by blowing the electronic fuse, thereby solidifying the calibration data. For example, the calibration data solidified in the electronic fuse can be used to calibrate the gain of the gain amplifier in the RF module.

[0003] For large chips, fully functional electronic fuses can be used, and all the control pins of the electronic fuses can be brought out to the chip pins to achieve direct configuration of the electronic fuses. However, in small chips, it is not possible to allocate many pins for electronic fuses because this will occupy too many pin resources of the small chip. Therefore, a solution is needed that can save chip pin resources and ensure calibration effect. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide a chip and method for configuring an electronic fuse, and the electronic fuse is configured using the chip, thereby saving chip pin resources and chip area, and ensuring the calibration effect.

[0005] The embodiment of the present disclosure provides a chip with an electronic fuse, including: a state machine, wherein the states of the state machine include a programming state, a reading state, and a serial control state; a shift register, configured to receive and temporarily store first control information and data to be programmed sent externally, and configured to receive, store, and output a programming result; wherein the first control information is used to control the state machine to enter the programming state or the reading state; a first pin, through which the shift register receives the first control information sent externally; the state machine is configured to: in the serial control state, obtain the first control information and the data to be programmed from the shift register in a clock counting cycle, wherein the clock counting cycle is an integer multiple of the number of bits of the shift register; in the programming state, write the data to be programmed in the shift register into the electronic fuse; in the reading state, read the programming result of the electronic fuse and store it in the shift register; based on a reset signal, read the programming result of the electronic fuse and store it in the shift register.

[0006] The disclosed embodiment also provides a method for configuring an electronic fuse, comprising: receiving external first control information and data to be written through the same pin and temporarily storing them in a shift register; wherein the first control information is used to determine the operating state of the electronic fuse, and the operating state includes a writing state, a reading state, and a serial control state; in the serial control state, obtaining the temporarily stored first control information and the data to be written with a clock counting cycle; the clock counting cycle is an integer multiple of the number of bits of the shift register; in the writing state, parsing the temporarily stored data to be written and writing it into the electronic fuse; in the reading state, parsing the writing result of the electronic fuse, reading it, and storing it in the shift register; based on a reset signal, reading the writing result of the electronic fuse and storing it in the shift register.

[0007] The disclosed embodiment provides a chip with an electronic fuse, including: a state machine, the states of the state machine including a burning state, a reading state, and a serial control state; a shift register, configured to receive and temporarily store first control information sent externally and data to be burned, and configured to receive, store and output the burning result; wherein the first control information is used to control the state machine to enter a burning state or a reading state; and a first pin, the shift register receives the first control information sent externally through the first pin.

[0008] In the serial control state, the state machine obtains the first control information and the data to be burned from the shift register in a clock counting cycle, and the clock counting cycle is an integer multiple of the number of bits of the shift register. Because the clock counting cycle is an integer multiple of the number of bits of the shift register, when the state machine reads from the shift register, the first control information and the data to be burned are respectively located at fixed positions in the shift register, and the state machine can accurately distinguish the first control information from the data to be burned. Therefore, the chip does not need to set up special decoders and other devices to parse the first control information and the data to be burned, which can reduce the area of ​​the chip and improve the integration. Using a shift register, only one first pin can be used to obtain the first control information and the data to be burned from the outside, which can save the number of chip pins.

[0009] In the programming state, the state machine writes the data to be programmed in the shift register into the electronic fuse; in the reading state, the state machine reads the programming result of the electronic fuse and stores it in the shift register. Using the state machine, the programming and reading of the electronic fuse can be easily realized.

[0010] Based on the reset signal, the state machine reads the burning result of the electronic fuse and stores it in the shift register. When the chip is powered on, the state machine can be reused to read the burning result of the electronic fuse, and the shift register can be reused to store the burning result. Because the burning result of the electronic fuse is stored in the shift register, the burning result stored in the shift register can be used to calibrate the chip after it is powered on. There is no need to directly use the data stored in the electronic fuse for calibration. The electronic fuse does not need to remain in working state all the time, which can prevent the electronic fuse from being damaged due to long-term operation.

[0011] In some schemes, the chip also includes a module to be calibrated, and the shift register is connected to the module to be calibrated and is configured to output the burning result to the module to be calibrated. That is, the present disclosure can output the burning result to the module to be calibrated through the shift register, without the need for multiple electronic fuses in the electronic fuse to be connected to the module to be calibrated respectively, which can further save the area of ​​the chip. In addition, after the electronic fuse is read, it is not necessary to continuously output the burning result, and the electronic fuse does not need to work, which further saves power consumption.

[0012] In some schemes, the chip further includes a first port and / or a second port; the first port is used to send an external clock signal outside the chip to the state machine and the shift register, and the first port includes a second pin; the second port is used to send first control information and data to be burned to the shift register, and the second port includes a first pin; the first port and / or the second port are also configured to transmit second control information, and the second control information is an analog signal provided by the chip to the chip when it is working. Before the chip leaves the factory, the first port can be used to provide an external clock signal to the state machine and the shift register, and the second port can be used to send the first control information and data to be burned to the shift register; when the chip is working after leaving the factory, the pins in the first port and / or the second port can be used to transmit the second control information to realize pin multiplexing, thereby further saving the pin resources of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of the structure of the chip provided in the embodiment of the present disclosure Figure 1 ;

[0014] Figure 2 A schematic diagram of an interface of a control module provided in an embodiment of the present disclosure;

[0015] Figure 3 A schematic diagram of the structure of the chip provided in the embodiment of the present disclosure Figure 2 ;

[0016] Figure 4 A schematic diagram of the structure of a state machine provided in an embodiment of the present disclosure;

[0017] Figure 5A schematic diagram of the structure of the chip provided in the embodiment of the present disclosure Figure 3 ;

[0018] Figure 6 A schematic diagram of the structure of a first port provided in an embodiment of the present disclosure;

[0019] Figure 7 A schematic diagram of the structure of a second port provided in an embodiment of the present disclosure;

[0020] Figure 8 A schematic diagram of the structure of the chip provided in the embodiment of the present disclosure Figure 5 ;

[0021] Fig. 9 A schematic diagram of the structure of the chip provided in the embodiment of the present disclosure Figure 6 ;

[0022] Fig.10 A schematic flow chart of a method for configuring an electronic fuse provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0024] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0025] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0027] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0028] Figure 1 1 is an optional structural diagram of the chip 100 provided in the embodiment of the present disclosure. The chip 100 can solidify some debugging and calibration chip data. The chip 100 solidifies some debugging and calibration chip data, which can be transmitted to the module to be calibrated 30 inside the chip to debug and calibrate the module to be calibrated 30. For example, the module to be calibrated 30 can be a radio frequency module, and the solidified data can be used to calibrate the gain of the gain amplifier in the radio frequency module to ensure the gain consistency of the chip 100 when it leaves the factory.

[0029] In the embodiments of the present disclosure, reference Figure 1 , the chip 100 may include a shift register 11, a state machine 12, an electronic fuse 20 and a first pin PAD2. The chip 100 may use the shift register 11 and the state machine 12 to burn part of the data of the debugging and calibration chip into the electronic fuse 20, that is to say: the shift register 11 and the state machine 12 are used to configure the electronic fuse 20. For example, the shift register 11 may receive data to be burned, and the data to be burned may include part of the data of the debugging and calibration chip that the chip 100 needs to solidify. The data to be burned may come from a host computer outside the chip. The electronic fuse 20 may include a plurality of electronic fuses, each of which may store one or more data bits of data. The state machine 12 may burn all the data bits of the data to be burned in the shift register 11 into the electronic fuses corresponding to the electronic fuses 20 for storage.

[0030] In some embodiments, the chip 100 may include a control module 10, which is used to control the programming and reading of the electronic fuse 20 and control the reception of the to-be-programmed data from outside the chip 100. The control module 10 may include a shift register 11 and a state machine 12. Figure 2 is a schematic diagram of an optional interface of the control module 10. It should be noted that: Figure 2 The serial digital interface 10 mainly includes an input interface and an output interface. Figure 2As shown, the input interface mainly includes a reset signal RST interface 101, a clock signal CLK interface 102, and an input data signal SDI interface 103. The output interface mainly includes an output data signal SDO interface 104, a parallel output data bus interface 105, a clock control interface 106, and an enable signal interface 107. The first control information outside the chip and the data to be burned can be transmitted to the control module 10 along the input data signal SDI interface 103. The burning result and other data can be output to the outside of the chip along the output data signal SDO interface 104. The external clock signal outside the chip or the internal clock signal generated inside the chip can be input to the control module 10 along the clock signal CLK interface 102.

[0031] In the embodiments of the present disclosure, reference Figure 1 , the control module 10 may include a shift register 11. The shift register 11 may be used to transmit and temporarily store external first control information and data to be burned, and the shift register 11 may receive and temporarily store external first control information and data to be burned from the first pin PAD2. The first control information is used to control the state of the state machine 12, and the first control information and data to be burned may be used to configure the electronic fuse 20. For example, the control module 10 may be configured as follows: Figure 2 The input clock signal CLK interface 102 shown receives an external clock signal outside the chip. In some embodiments, Figure 1 As shown, the chip 100 further includes a second pin PAD1, and the second pin PAD1 is connected to Figure 2 The input clock signal CLK interface 102 is connected to transmit an external clock signal. The accuracy of the external clock signal is higher than that of the internal clock signal. The external clock signal can come from a host computer outside the chip. When programming, the external clock signal can ensure that the phase of the clock driving the shift register 11 and the data received by the shift register 11 is controllable to avoid data transmission errors. The shift register 11 can be driven by the external clock signal, such as Figure 2 The input data signal SDI interface 103 shown receives the first control information and the data to be programmed from outside the chip, and temporarily stores the received first control information and the data to be programmed in the shift register 11 .

[0032] In the embodiments of the present disclosure, reference Figure 1, the control module 10 may further include a state machine 12. The state machine 12 may be a Moore state machine or a Mealy state machine. For example, the state of the state machine 12 may include a writing state, a reading state, and a serial control state. The writing state is a state in which the state machine 12 controls the electronic fuse 20 to be written, the reading state is a state in which the state machine 12 controls the electronic fuse 20 to be read, and the serial control state is a state in which the state machine 12 controls the shift register 11 to perform serial input or serial output. When writing or reading is not required, the state machine 12 is in a serial control state for a long time. In the serial control state, the state machine 12 obtains the first control information and the data to be written from the shift register 11 in a clock counting cycle, thereby obtaining the first control information from the shift register 11 at a fixed time to monitor the state of the first control information and determine whether it is necessary to jump to the writing state or the reading state. The state machine 12 may obtain the first control information at a fixed time according to the count of the clock signal, wherein the clock signal may be an external clock signal or an internal clock signal. Among them, the clock counting cycle is an integer multiple of the number of bits of the shift register 11. Because the clock counting cycle is an integer multiple of the number of bits of the shift register 11, when the state machine 12 reads from the shift register 11, the first control information and the data to be burned are respectively located at fixed positions in the shift register 11, and the state machine 12 can accurately distinguish the first control information from the data to be burned. Therefore, the chip 100 does not need to set up special decoders and other devices to parse the first control information and the data to be burned. Compared with obtaining the first control information through the serial peripheral interface (Serial Peripheral Interface, SPI) or I2C (Inter Integrated Circuit) interface, the embodiment of the present disclosure does not need a decoder in the serial peripheral interface or I2C interface to decode the first control information, which can reduce the area of ​​the chip and improve the integration.

[0033] In the embodiments of the present disclosure, reference Figure 1, the state machine 12 is connected to the shift register 11 and the electronic fuse 20 respectively. The state machine 12 is configured to receive the first control information and the data to be burned. For example, the state machine 12 can call the first control information and the data to be burned received by the shift register 11, or the shift register 11 can send the temporarily stored first control information and the data to be burned to the state machine 12. The first control information can be a control instruction for controlling the state of the state machine 12. The first control information can be encoded in a sequential coding (Sequential), Gray coding (Gray) or one hot coding (One hot). For example, when the first control information is encoded in a sequential coding, the code corresponding to the burning state of the state machine 12 is "10"; the code corresponding to the reading state of the state machine 12 is "01"; the code corresponding to the serial control state of the state machine 12 is "00" or "11".

[0034] In the embodiments of the present disclosure, reference Figure 1 The state machine 12 may write the data to be written into the electronic fuse 20 based on the first control information, or read the writing result of the data to be written from the electronic fuse 20 based on the first control information. For example, the state machine 12 may generate third control information based on the received first control information. The third control information is a control signal that can be recognized by the electronic fuse 20, and the third control information can control the electronic fuse 20 to write or read. The third control information may include a read waveform and a write waveform. The state machine 12 may be implemented by a trigger, and the trigger may be a D flip-flop. The trigger may include two input terminals, and the two input terminals of the trigger may receive the first control information and the clock signal respectively, and realize the state jump based on the control of the first control information and the clock signal. Among them, the clock signal may be an external clock signal or an internal clock signal.

[0035] If the state corresponding to the first control information received by the state machine 12 is "10", the state machine 12 will be in the burning state. At this time, under the control of the external clock signal, the state machine 12 generates the third control information according to the data in the shift register 11. The third control information generated by the state machine 12 is a burning waveform. When the third control information is a burning waveform, the burning waveform can also include the data to be burned. Then, the state machine 12 can transmit the data to be burned and the burning waveform to the electronic fuse 20. Based on the burning waveform, the electronic fuse 20 solidifies the data to be burned into the corresponding electronic fuse in the electronic fuse 20.

[0036] If the state corresponding to the first control information received by the state machine 12 is "01", the state machine 12 will be in the reading state. At this time, under the control of the external clock signal, the third control information generated by the state machine 12 is a reading waveform. Then, the state machine 12 can transmit the reading waveform to the electronic fuse 20. Based on the reading waveform, the electronic fuse 20 reads the data stored in the corresponding electronic fuse, which can be understood as the writing result of the data to be written, and transmits the writing result to the state machine 12.

[0037] In the embodiment of the present disclosure, only the first pin PAD2 and the second pin PAD1 of the electronic fuse 20 are needed to complete the read and write control of the chip 100 and input the data to be burned before leaving the factory. Compared with the related technology of configuring the electronic fuse 20 through a serial peripheral interface or an I2C interface, the embodiment of the present disclosure requires fewer pins, thereby saving pin resources and improving integration.

[0038] After the chip leaves the factory, when the chip 100 is powered on, the chip 100 can generate a reset signal based on the power-on, and the state machine 12 can read the burning result of the electronic fuse 20 based on the reset signal and store it in the shift register 11. Because the burning result of the electronic fuse 20 is stored in the shift register 11, the burning result stored in the shift register 11 can be used to calibrate the chip 100 after it is powered on, without directly using the data stored in the electronic fuse 20 for calibration, and the electronic fuse 20 does not need to keep working all the time, which can prevent the electronic fuse 20 from being damaged due to long-term operation.

[0039] It should be noted that the reference Figure 1 , the state machine 12 and the shift register 11 in the control module 10 both require clock signals during their operation. In some embodiments, before the chip leaves the factory, the chip can be configured with an external clock signal to improve the accuracy of the configuration; after the chip is delivered to the customer, the chip's internal clock signal can be used to save power consumption.

[0040] Therefore, in order to save power consumption, the chip 100 may further include a clock generation module 50. After the chip leaves the factory, the chip 100 may generate an internal clock signal using the clock generation module 50. Thus, the chip 100 may use the internal clock signal to drive the state machine 12 and the shift register 11 in the control module 10 to work.

[0041] In the embodiments of the present disclosure, reference Figure 1 The state machine 12 can generate a clock control signal after the chip 100 is powered on. The clock control signal controls the on and off of the clock generation module 50. For example, the clock generation module 50 can include an oscillator. The control module 10 can be configured as follows: Figure 2The "clock control" interface 106 shown outputs a clock control signal to the oscillator. The oscillator is in an off state when it does not receive the clock control signal. After receiving the clock control signal, the oscillator is in an on state, generates an internal clock signal, and transmits the internal clock signal to the control module 10. In this way, the embodiment of the present disclosure can control the control module 10 to control the turning off and on of the clock generation module 50, thereby preventing the clock generation module 50 from working for a long time and increasing the chip energy consumption.

[0042] In the embodiments of the present disclosure, reference Figure 1 , when the state machine 12 can work and power on the chip 100, after the state machine 12 receives the internal clock signal, the state machine 12 is configured to read the burning result of the data to be burned from the electronic fuse 20 based on the internal clock signal, and store the burning result in the shift register 11. For example, the state machine 12 can receive the internal clock signal, and based on the control of the internal clock signal, realize the state jump, and generate the third control information to read the electronic fuse 20. The shift register 11 can count the clock of the internal clock signal, and control the scheduling of the data by the clock counting result, that is, store the burning result in the shift register 11. That is to say, the embodiment of the present disclosure can use the shift register 11 to receive the data to be burned and the first control information outside the chip, and can also reuse the shift register 11 to store the burning result. Furthermore, the chip can be debugged and calibrated by storing the burning result by the shift register 11.

[0043] In this way, during the power-on calibration of the chip, the present disclosure can reuse the state machine 12 to read the programming result, reuse the shift register 11 to store the programming result, and the clock signal driving the state machine 12 and the shift register 11 is the internal clock signal generated by the clock generation module 50. In other words, the present disclosure only needs to set up the internal clock module 50, and the calibration after the chip is powered on can be completed by multiplexing the shift register 11 and the state machine 12. Therefore, the embodiment of the present disclosure does not need to set up other circuit structures, and the purpose of chip miniaturization can be achieved.

[0044] In other embodiments, when the chip 100 is powered on, the state machine 12 may also read the programming result of the electronic fuse 20 according to the received external clock signal and store it in the shift register 11 .

[0045] In some embodiments of the present disclosure, reference Figure 1 Before the chip leaves the factory, the state machine 12 is also configured to control the shift register 11 to output the programming result to the outside when it is in the serial control state. For example, the state machine 12 is also configured to control the shift register 11 to serially input or serially output data when it is in the serial control state.

[0046] If the state corresponding to the first control information received by the state machine 12 is "00", the state machine 12 can send a control instruction to the shift register 11 to enter the serial transmission mode. At this time, the shift register 11 can enter the serial input sub-state based on the control instruction of the serial transmission mode and the drive of the external clock signal, so as to Figure 2 The input data signal SDI interface 103 shown receives data to be programmed and first control information from outside the chip.

[0047] If the state corresponding to the first control information received by the state machine 12 is "11", the state machine 12 can send a serial transmission mode control instruction to the shift register 11. At this time, the shift register 11 can enter the serial output sub-state based on the received serial transmission mode control instruction and the drive of the external clock signal, and store the programming result from Figure 2 The output data signal SDO interface 104 shown is output to the host computer outside the chip. In this way, the host computer outside the chip can monitor whether the data in the shift register 11 meets expectations, that is, the host computer can verify the programming result by comparing the programming result with the data to be programmed to determine whether the electronic fuse 20 is successfully programmed. In other words, the embodiment of the present disclosure reuses the shift register 11, and there is no need to set up an additional device for verifying the programming result, thereby further reducing the chip area and improving the integration.

[0048] It should be noted that, usually, for cost considerations, some small chips will use electronic fuses with simpler functions. Due to design limitations such as overload protection and aging, such electronic fuses are not provided with protection circuits for overload protection and anti-aging, so that such electronic fuses cannot work continuously for a long time. If the electronic fuses work continuously for a long time, the components (such as transistors) in the electronic fuses may be damaged, causing the electronic fuses to fail to work normally. Therefore, during the process of debugging and calibrating the module to be calibrated 30 by the chip 100, such electronic fuses cannot continuously output the data of the debugging and calibration chips stored to the module to be calibrated.

[0049] To solve this problem, in some embodiments of the present disclosure, reference is made to Figure 1 The chip 100 further includes a module to be calibrated 30. The shift register 11 is connected to the module to be calibrated 30. The shift register 11 is configured to output the programming result to the module to be calibrated 30, so as to calibrate the module to be calibrated 30 of the chip according to the programming result stored in the electronic fuse 20.

[0050] In some embodiments, the module to be calibrated 30 may include a register, and the burning result may be output to the register of the module to be calibrated 30, so that the burning result may be temporarily stored in the register, and calibration may be continuously performed based on the burning result without powering off.

[0051] In the embodiments of the present disclosure, reference Figure 1 , shift register 11 can be Figure 2 The clock signal CLK interface 102 shown receives an external clock signal or an internal clock signal. The shift register 11 can count the received external clock signal or internal clock signal through a built-in clock counter. Furthermore, the shift register 11 can transmit the burning result received from the state machine 12 to the module to be calibrated 30 inside the chip in real time or according to the result of the clock counting, so as to achieve the purpose of debugging and calibration.

[0052] That is to say, the embodiment of the present disclosure can debug and calibrate the chip through the burning result in the shift register 11. In this way, the embodiment of the present disclosure can use the shift register 11 to continuously output the data for debugging and calibrating the chip (i.e., the burning result of the data to be burned) to the module to be calibrated 30 inside the chip, without the need for the multiple electronic fuses in the electronic fuse 20 to be connected to the module to be calibrated 30 respectively, and the circuit connection is simpler.

[0053] Moreover, when the chip is working after leaving the factory, the electronic fuse 20 only needs to output the burning result to the shift register 11 each time the chip is powered on. After the electronic fuse 20 completes the reading, the electronic fuse 20 does not need to continuously output the burning result to the module to be calibrated 30. The electronic fuse 20 can be powered off without having to work for a long time, which can effectively reduce the power consumption and cost of the chip.

[0054] In addition, the embodiment of the present disclosure can reuse the shift register 11, and there is no need to set up additional devices for verifying the burning result and continuously outputting the burning result, thereby further reducing the chip area and improving the integration.

[0055] Figure 3 is a schematic diagram of the structure of an optional control module 10 provided in an embodiment of the present disclosure. It should be noted that: Figure 3 The clock signal CLK, input data signal SDI and output data signal SDO can refer to Figure 2 In order to clearly show the structure of the shift register 11, Figure 3 The electronic fuse 20 is not shown.

[0056] It should also be noted that the data transmitted between the shift register 11 and the host computer is usually in serial form. For example, the data to be burned by the electronic fuse 20 is usually input serially from the host computer, and the burning result temporarily stored in the shift register 11 needs to be output serially to the host computer for verification. The data transmission between the shift register 11 and the inside of the chip is usually in parallel form. For example, the data to be burned temporarily stored in the shift register 11 needs to be transmitted in parallel to the state machine 12, and the burning result temporarily stored in the shift register 11 needs to be transmitted in parallel to the module to be calibrated 30.

[0057] In some embodiments of the present disclosure, reference Figure 3 The shift register 11 includes a serial input terminal, a serial output terminal, and a parallel input / output terminal. The serial input terminal of the shift register 11 is configured to receive the first control information and the data to be burned from the outside. For example, the serial input terminal of the shift register 11 is connected to the following Figure 2 The input data signal SDI interface 103 is shown. The shift register 11 can receive the first control information and the data to be programmed in serial from the input data signal SDI interface 103 of the control module 10, and store the first control information and the data to be programmed in the first register unit 110 and the second register unit 111 respectively.

[0058] In the embodiments of the present disclosure, reference Figure 3 , the parallel input / output end of the shift register 11, the parallel input / output end can be used to input and output data. The parallel input / output end is connected to the state machine 12 and the data bus 40 respectively, and is configured to output the first control information and the data to be programmed to the state machine 12, and / or, receive the programming result and output the programming result to the data bus 40. For example, the parallel input / output end of the shift register 11 is connected to the state machine 12. The parallel input / output end of the shift register 11 and the data bus 40 are both connected to the state machine 12. Figure 2 The control module 10 is shown with a "parallel output data bus" interface 105 for parallel input and output.

[0059] In this way, the shift register 11 can output the first control information and the data to be written to the state machine 12 in parallel, and receive the writing result of the data to be written read from the electronic fuse 20 from the state machine 12. In other words, the shift register 11 is used to store the data to be written written to the electronic fuse 20, and store the writing result of the data to be written read from the electronic fuse 20.

[0060] In the embodiments of the present disclosure, reference Figure 3 The serial output terminal of the shift register 11 is configured to output the programming result to the outside. For example, the serial output terminal of the shift register 11 is connected to Figure 2The output data signal SDO interface 104 is shown. The shift register 11 can output the burning result stored in the shift register 11 to the outside of the chip bit by bit through the output data signal SDO interface 104, for example, output the burning result to the host computer to feedback the burning result of the electronic fuse 20, so as to facilitate the judgment of whether the burning of the electronic fuse 20 meets the expectations. The external host computer can verify the burning result by comparing the burning result with the data to be burned to determine whether the electronic fuse 20 is burned successfully. In some embodiments, after the electronic fuse 20 is burned, the state machine 12 automatically enters the reading state, and transmits the burning result of the electronic fuse 20 to the shift register 11. The shift register 11 can output the burning result stored in the shift register 11 to the outside of the chip bit by bit through the output data signal SDO interface 104.

[0061] In some embodiments of the present disclosure, reference Figure 3 The shift register 11 includes a first register unit 110 and a second register unit 111. The first register unit 110 and the second register unit 111 may each include one or more data bits. The arrangement order of the first register unit 110 and the second register unit 111 is not limited to Figure 3 In the embodiment of the present disclosure, refer to Figure 3 Driven by an external clock signal, the shift register 11 can receive a first control signal and data to be programmed from a host computer outside the chip. The first control signal and the data to be programmed are sequentially injected into the first register unit 110 and the second register unit 111 in sequence. The data in the first register unit 110 is read in a clock counting cycle to distinguish the first control signal from the data to be programmed.

[0062] In some embodiments, when the first control information is encoded using a timing code, the encoding of the first control information may be 2 bits. The first register unit 110 may include two triggers connected in series, and the two triggers respectively store one bit of encoding of the first control information. The number of triggers included in the second register unit 111 may be greater than or equal to the data bit of the electronic fuse 20. Each trigger in the second register unit 111 stores one bit of encoding of the data to be burned.

[0063] In the embodiments of the present disclosure, reference Figure 3, the first register unit 110 and the second register unit 111 are both connected to the state machine 12. The first register unit 110 is configured to transmit the first control information to the state machine 12. For example, the state machine 12 can read the first control information (control instruction) in the first register unit 110 once every fixed clock cycle based on the control of the external clock signal or the internal clock signal, so as to determine the next step to jump to the state corresponding to the first control information. It should be noted that the fixed clock cycle is associated with the number of bits of the shift register 11. For example, if the number of bits of the shift register 11 is N bits, the state machine 12 can read it once every N, 2N, 3N, etc. clocks to ensure that the first control information and data can be correctly distinguished to avoid missed reading or misreading.

[0064] The second register unit 111 is configured to transmit the data to be programmed to the state machine 12. For example, if the state machine 12 jumps to the state machine 12 according to the encoding of the first control information, Figure 4 If the state machine 12 jumps to the state shown in the first control information, the second register unit 111 transmits the stored data to be written to the state machine 12 in parallel. Figure 4 If the state machine 12 jumps to the read state shown in FIG. 1 according to the encoding of the first control information, the state machine 12 transmits the programming result read from the electronic fuse 20 to the second register unit 111 for storage. Figure 4 In the serial control state shown, the second register unit 111 can Figure 2 The output data signal SDO interface 104 shown serially outputs the stored programming result bit by bit to the outside of the chip, for example, outputs the programming result to a host computer to feedback the programming result of the electronic fuse 20, so as to facilitate judgment on whether the programming of the electronic fuse 20 meets expectations.

[0065] In a specific example, assuming that the first register unit 110 is 2 bits, the second register unit 111 is 2 bits, and the initial value of the shift register 11 is 0000, wherein the first two bits are the data bits of the first register unit 110, and the last two bits are the data bits of the second register unit 111:

[0066] When the first clock counts, 1 is serially input into shift register 11, and the value of shift register 11 is 1000;

[0067] When the second clock counts, 1 is serially input into shift register 11, and the value of shift register 11 is 1100;

[0068] When the third clock counts, 0 is serially input into shift register 11, and the value of shift register 11 is 0110;

[0069] When the fourth clock counts, 1 is serially input into shift register 11, and the value of shift register 11 is 1011;

[0070] After four clock counts, the state machine 12 reads the first control information from the first register unit 110. At this time, the first control information is "10", and the state machine 12 enters the burning state. The data to be burned in the second register unit 111 is "11", and the state machine 12 writes "11" into the electronic fuse. At the same time, the data to be burned "11" can be transmitted to the module to be calibrated 30.

[0071] In the embodiments of the present disclosure, reference Figure 3 The chip 100 further includes a data bus 40. The second register unit 111 is also connected to the data bus 40. The second register unit 111 is also configured to output the stored programming result to the data bus 40. For example, the second register unit 111 can be driven by an external clock signal or an internal clock signal. Figure 2 The "parallel output data bus" interface 105 of the control module 10 shown outputs the stored programming result to the data bus 40. In addition, the data bus 40 is only connected to the second register unit 111, and is not connected to the first register unit 110. Thus, the first register unit 110 can be prevented from interfering with the process of the second register unit 111 transmitting data to the data bus 40.

[0072] It should be noted that if Figure 2 The output data signal SDO interface 104 and the input data signal SDI interface 103 shown can be connected to the Figure 1 The same first pin PAD2 as shown. In some embodiments, the first pin PAD2 is a pin of a bidirectional interface, and the state machine 12 can control whether the state of the bidirectional interface is input or output. For example, the first control information received by the state machine 12 is encoded as "00", and the state machine 12 controls the shift register 11 to perform serial input. At this time, the bidirectional interface is in the input state, and the first control information outside the chip and the data to be burned can be transmitted to the shift register 11 along the bidirectional interface. The first control information received by the state machine 12 is encoded as "11", and the state machine 12 controls the shift register 11 to perform serial output. At this time, the bidirectional interface is in the output state, and the burning result stored in the shift register 11 can be output to the outside of the chip along the bidirectional interface.

[0073] In some embodiments of the present disclosure, reference Figure 1 The chip 100 further includes a power-on reset module 60. The power-on reset module 60 is configured to generate a reset signal RST after the chip 100 is powered on. The state machine 12, connected to the power-on reset module 60, is further configured to receive the reset signal RST, and based on the reset signal RST, enter a reading state based on the reset signal, and read the programming result of the data to be programmed from the electronic fuse 20.

[0074] In the embodiments of the present disclosure, reference Figure 1After the chip 100 is powered on, the control module 10 can generate an enable signal and a clock control signal. In this way, the clock generation module 50 can provide the control module 10 with an internal clock signal that drives the state machine 12 and the shift register 11 to work. In addition, the first selector Mux1 can transmit the internal clock signal to the state machine 12 and the shift register 11 in the control module 10 under the triggering of the enable signal.

[0075] In the embodiments of the present disclosure, reference Figure 1 After the chip 100 is powered on, the reset module 60 will send a reset signal RST to the control module 10. After receiving the reset signal RST, the state machine 12 is in a reading state by default, and then, based on the control of the internal clock signal, a reading waveform is generated and sent to the electronic fuse 20. The electronic fuse 20 reads the burning result based on the reading waveform. In this way, the control module 10 can automatically read the burning result in the electronic fuse 20 after powering on. Therefore, the chip can be used directly without any configuration after leaving the factory. At the same time, the shift register 11 is connected to the data bus 40, and the stored burning result can be transmitted to the device such as the module to be calibrated through the data bus 40 to debug and calibrate the module to be calibrated.

[0076] In the embodiments of the present disclosure, reference Figure 1 After the state machine 12 finishes reading the data in the electronic fuse 20 based on the reset signal RST, the state machine 12 can automatically jump to the serial control mode. At this time, the control module 10 can stop generating the clock control signal and the enable signal, and turn off the clock generation module 50. In this way, the state machine 12 and the shift register 11 do not receive the clock signal, and the state machine 12 and the shift register 11 do not work, thereby further reducing power consumption.

[0077] In some embodiments of the present disclosure, reference Figure 1 The chip 100 further includes a first selector Mux1. The control module 10 is further configured to generate an enable signal based on the reset signal. The first selector Mux1 is connected to the control module 10, configured to receive the enable signal, the external clock signal and the internal clock signal, and configured to select one of the external clock signal and the internal clock signal for transmission based on the enable signal. The enable signal can be transmitted by Figure 2 The “enable signal” interface 107 is shown to be transmitted from the control module 10 to the first selector Mux1 .

[0078] In the embodiments of the present disclosure, reference Figure 1Before the chip leaves the factory, the control module 10 needs to receive an external clock signal to configure the electronic fuse 20. At this time, the control module 10 may not generate an enable signal, or the enable signal generated by the control module 10 may be a low level. After the first selector Mux1 receives the enable signal, or receives a low-level enable signal, it transmits the external clock signal to the control module 10. After the chip leaves the factory, the control module 10 may not receive an external clock signal outside the chip. At this time, the control module 10 can generate an enable signal based on the reset signal RST, and the generated enable signal can be a high level. After the first selector Mux1 receives the high-level enable signal, it transmits the internal clock signal generated by the clock generation module 50 to the control module 10.

[0079] Figure 5 is a schematic diagram of the structure of an optional chip 100 provided in an embodiment of the present disclosure. Figure 5 In the embodiment, the clock generation module 50 includes an oscillator 51, which can conveniently generate an internal clock signal. It should be noted that the analog signals A and B can also be other signals to be processed by the chip. Furthermore, the analog signals A and B can be the same or different, which is not limited here.

[0080] In some embodiments of the present disclosure, reference Figure 5 The chip 100 further includes a first port 41 and a second port 42, wherein the first port 41 may include Figure 1 As shown in the second pin, the second port 42 may include Figure 1 The first pin shown. The first port 41 and / or the second port 42 are configured to transmit the second control information. For example, the second control information may include an analog signal A and an analog signal B. For example, the chip 100 also includes analog devices such as an amplifier, a phase shifter or an attenuator, and the analog signal A or the analog signal B may be an input signal of the above analog device. When the chip is working normally, the analog signal A or the analog signal B is input to the input end of the analog device, and the analog device performs amplification, phase shifting or attenuation on the analog signal A or the analog signal B.

[0081] The analog signal A can be transmitted to the inside of the chip 100 through the first port 41, and the analog signal B can be transmitted to the inside of the chip 100 through the second port 42. Figure 5 , the first port 41 is connected to the state machine 12 and the shift register 11 respectively. The first port 41 is configured to send an external clock signal to the state machine 12 and the shift register 11. For example, the structure of the first port 41 can refer to Figure 6 It is understood that the first port 41 includes a second pin PAD1 , and can receive an external clock signal outside the chip through the second pin PAD1 , and transmit the external clock signal to the state machine 12 and the shift register 11 .

[0082] The second port 42 is connected to the shift register 11. The second port 42 is configured to send the first control information and the data to be written to the shift register. For example, the structure of the second port 42 can refer to Figure 7 It is understood that the second port 42 includes a first pin PAD2, and the second port 42 can receive the first control information and the burning data through the first pin PAD2, and transmit the first control information and the burning data to the shift register 11. The second port 42 can also receive the burning result of the data to be burned, and transmit the burning result from the first pin PAD2 to the host computer outside the chip.

[0083] The embodiment of the present disclosure utilizes the first port 41 and the second port 42 and the pins of the first port 41 and the second port 42 to receive the second control information, and the pins of the first port 41 and the second port 42 may also be utilized to transmit the external clock signal, the first control information, and the data to be burned required for configuring the electronic fuse 20. In other words, the embodiment of the present disclosure may reuse the pins for transmitting the second control information to configure the electronic fuse 20. Thus, the present disclosure does not need to set additional pins to transmit the data for configuring the electronic fuse 20, which can further save pin resources and improve the integration.

[0084] In some embodiments of the present disclosure, reference Figure 5 The first port 41 is further configured to receive a multiplexing control signal and select one of the external clock signal and the second control information for transmission based on the multiplexing control signal. Figure 6 As shown, the first port 41 may include a selector Mux2. The selector Mux2 selects one of the external clock signal and the second control information for transmission according to the level of the multiplexing control signal. Before the chip leaves the factory, the multiplexing control signal may be at a low level, and the first port 41 may send the external clock signal to the control module 10. After the chip leaves the factory, the multiplexing control signal may be at a high level, and the first port 41 may send the analog signal A to other devices such as the module to be calibrated 30. Thus, the embodiment of the present disclosure may reuse the first port 41 and the second pin PAD1, further saving pin resources and improving integration.

[0085] In the embodiments of the present disclosure, reference Figure 5 The second port 42 is further configured to receive the multiplexing control signal and select one of the first control information and the second control information for transmission based on the multiplexing control signal. Figure 7As shown, the second port 42 may include a selector Mux3. The selector Mux3 selects one of the first control information and the second control information for transmission according to the level of the multiplexing control signal. Before the chip leaves the factory, the multiplexing control signal may be at a low level, and the second port 42 may send an external clock signal and data to be burned to the shift register 11. After the chip leaves the factory, the multiplexing control signal may be at a high level, and the second port 42 may send an analog signal B to other devices such as the module to be calibrated 30. Thus, the embodiment of the present disclosure may reuse the second port 42 and the first pin PAD2, further saving pin resources and improving integration.

[0086] Figure 8 1 is a schematic structural diagram of an optional serial control circuit 100 provided in an embodiment of the present disclosure.

[0087] In some embodiments of the present disclosure, reference Figure 8 The chip 100 further includes a control pin PAD5 (label error). The control pin PAD5 is connected to the first port 41 and the second port 42 respectively. The control pin PAD5 is configured to send a multiplexing control signal to the first port 41 and the second port 42.

[0088] In the embodiments of the present disclosure, reference Figure 8 Before the chip leaves the factory, the control module 10 needs to receive the external clock signal, the first control information and the data to be burned from the outside of the chip to configure the electronic fuse 20. At this time, the host computer outside the chip can transmit the multiplexing control signal to the first port 41 and the second port 42 through the control pin PAD5, and the multiplexing control signal can be a high level. The selector in the first port 41 receives the external clock signal after receiving the high-level multiplexing control signal, and the selector in the second port 42 receives the first control information and the data to be burned after receiving the high-level multiplexing control signal.

[0089] In the embodiments of the present disclosure, reference Figure 8 After the chip leaves the factory, the chip 100 needs to transmit the second control information outside the chip through the first port 41 and / or the second port 42. At this time, the host computer outside the chip can transmit a low-level multiplexing control signal to the first port 41 and the second port 42 through the control pin PAD5. After the selector in the first port 41 and / or the second port 42 receives the low-level multiplexing control signal or does not receive the multiplexing control signal, the second control signal outside the chip is transmitted to the module to be calibrated 30. In other words, compared with the solution of configuring the electronic fuse 20 through the serial peripheral interface or the I2C interface in the related art, the configuration of the electronic fuse 20 in the embodiment of the present disclosure only needs to add a control pin PAD5 for transmitting the multiplexing control signal. Thereby, pin resources can be further saved and the integration can be improved.

[0090] Fig. 9 is a schematic diagram of the structure of another optional serial control circuit 100 provided in an embodiment of the present disclosure. It should be noted that: Fig. 9 Each of Bit0-BitN shown in the figure can correspond to an electronic fuse. The first port 41 and the second port 42 share the electronic fuse corresponding to BitX, and the electronic fuse corresponding to BitX is used to solidify the check control signal, and the remaining electronic fuses can solidify the debugging and calibration data. Multiple electronic fuses can also be used to solidify the check control signal, and the first port 41 and the second port 42 can also correspond to an electronic fuse respectively, which is not limited here.

[0091] In some embodiments of the present disclosure, reference Fig. 9 The electronic fuse 20 is also configured to store a multiplexed control signal. The first port 41 and the second port 42 are both connected to the electronic fuse 20 and configured to receive the multiplexed control signal from the electronic fuse 20 .

[0092] In the embodiments of the present disclosure, reference Fig. 9 , the data to be written may also include a reset control signal. The electronic fuse 20 may reserve one or more electronic fuses to write the multiplexing control signal. For example, the electronic fuse corresponding to BitX in the electronic fuse 20 may be used to store the multiplexing control signal. After the chip test is completed and the data for debugging and calibration are solidified into the electronic fuse 20, the state machine 12 may blow the electronic fuse corresponding to BitX.

[0093] In this way, before the chip leaves the factory, the electronic fuse corresponding to BitX is not blown, and the corresponding level is high. The first port 41 and the second port 42 can receive the external clock signal, the first control information and the data to be programmed from the outside of the chip to configure the electronic fuse 20. After the chip leaves the factory, since the electronic fuse corresponding to BitX is blown, the corresponding level is high, and the first port 41 and the second port 42 can receive the second control information from the outside of the chip. Therefore, the present disclosure does not need to set a pin for transmitting a multiplexed control signal, thereby further saving pin resources and improving integration. Fig.10 It is an optional flow chart of a configuration method of an electronic fuse provided in an embodiment of the present disclosure. The configuration method can be used to operate the chip 100 described above, and the configuration method can be executed by a host computer program.

[0094] S101, after receiving external first control information and data to be programmed through the same pin, temporarily storing them in a shift register; wherein the first control information is used to determine the operating state of the electronic fuse, and the operating state includes a programming state, a reading state, and a serial control state.

[0095] In the present disclosure, in combination Fig. 9To illustrate, before the chip leaves the factory, the host computer can configure the electronic fuse 20 through the state machine 12 and the shift register 11 in the control circuit 10, and fix part of the debugging and calibration data into the electronic fuse 20. Then, the electronic fuse 20 can send the fixed part of the debugging and calibration data to the module to be calibrated 30 to calibrate the module to be calibrated 30.

[0096] Specifically, the shift register 11 can obtain an external clock signal outside the chip from the first port 41 to receive the first control information and the data to be burned from the outside, and the first port 41 may include another pin (for example, a second pin). The shift register 11 can be a data exchange medium between the outside and inside of the chip. Before the chip leaves the factory, the shift register 11 can receive the first control information and the data to be burned from the second port 42, and temporarily store the external first control information and the data to be burned. The second port 42 includes a first pin, which is the same pin shared by the first control information and the data to be burned.

[0097] S102, in a serial control state, obtaining temporarily stored first control information and data to be programmed with a clock counting cycle, wherein the clock counting cycle is an integer multiple of the number of bits of the shift register.

[0098] Combination Fig. 9 When the chip 100 is not programmed or read, the state machine 12 is in the serial control state for a long time. Before the chip leaves the factory, the state machine 12 obtains the first control information and the data to be programmed from the shift register 11 in a clock counting cycle to correctly distinguish the first control information and the data to be programmed, thereby determining whether to enter the programming state or the reading state according to the first control information.

[0099] S103, in the burning state, the temporarily stored data to be burned is parsed and written into the electronic fuse.

[0100] This analysis can be performed through the state machine, and the analysis is used to confirm whether to jump from the serial control state to the programming state or the reading state. Fig. 9 In some embodiments, when the first control information indicates entering the programming state, the state machine 12 enters the programming state based on the triggering of the first control information and the external clock signal, and generates a corresponding programming waveform. The electronic fuse 20 burns the corresponding electronic fuse based on the received programming waveform and the data to be programmed, and completes the solidification of the data to be programmed.

[0101] S104, in the reading state, analyzing and reading the programming result of the electronic fuse and then storing it in the shift register.

[0102] Combination Fig. 9When the first control information indicates to enter the read state, the state machine 12 also enters the read state based on the triggering of the first control information and the external clock signal, and generates a corresponding read waveform. The electronic fuse 20 reads the reading result of the data to be burned based on the received read waveform, and transmits the reading result of the data to be burned to the shift register 11 through the state machine 12. The state machine 12 can output the burning result to the host computer outside the chip through the output data signal SDO interface of the shift register 11. The host computer program can monitor whether the data in the shift register 11 meets the expectations by comparing the burning result and the data to be burned, and judge whether the electronic fuse 20 is burned successfully.

[0103] In some embodiments, after the programming state or the reading state is completed, the system automatically jumps back to the serial control state. Alternatively, after the programming state is completed, the system automatically jumps to the reading state.

[0104] S105. Based on the reset signal, the programming result of the electronic fuse is read and stored in the shift register.

[0105] In the embodiments of the present disclosure, reference Fig. 9 After the chip leaves the factory, it is usually hoped that the chip 100 can be automatically calibrated directly without any configuration after power-on. Therefore, when the chip 100 is powered on after leaving the factory, the chip 100 generates a reset signal, and the state machine 12 reads the programming result of the electronic fuse 20 based on the reset signal and stores it in the shift register 11, so that the data stored in the shift register 11 can be used to directly perform calibration, for example, the programming result stored in the shift register 11 is output to the module to be calibrated 30, and the module to be calibrated 30 is calibrated.

[0106] Specifically, the power-on reset module 60 can automatically generate a reset signal RST after the chip is powered on. After the chip is powered on, the control module 10 can generate an enable signal and a clock control signal based on the reset signal RST. Then, the clock generation module 50 can generate an internal clock signal based on the triggering of the clock control signal. The first selector Mux1 can transmit the internal clock signal to the state machine 12 and the shift register 11 in the control module 10 under the triggering of the enable signal. In some embodiments, the enable signal can reuse the clock control signal, that is, the clock control signal can be reused to trigger the first selector Mux1. Based on the internal clock signal, the writing result of the data to be written is read from the electronic fuse, and the writing result is stored in the shift register.

[0107] In the embodiments of the present disclosure, reference Fig. 9After the state machine 12 receives the reset signal RST, it is in the reading state, automatically jumps to the reading mode, generates a reading waveform and sends it to the electronic fuse 20. Then, the state machine 12 reads the data solidified in the electronic fuse 20 and stores it in the shift register 11.

[0108] In addition, after the state machine 12 reads the data in the electronic fuse 20 based on the reset signal RST, the state machine 12 can automatically jump to the serial control mode. At this time, the control module 10 can stop generating the clock control signal and the enable signal, and turn off the clock generation module 50. The shift register 11 can output the data inside the shift register 11 to the module to be calibrated 30 inside the chip in real time or in parallel according to the result of clock counting, so as to achieve the purpose of debugging and calibration.

[0109] refer to Fig. 9 After the chip leaves the factory, an analog signal can be provided to the chip 100 through the first port 41 and / or the second port 42, so that the pins in the first port 41 and the pins in the second port 42 can be reused to further save the pin resources of the chip.

[0110] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0111] In some embodiments, the chip includes: a state machine, the states of the state machine include a burning state, a reading state, and a serial control state; a shift register, configured to receive and temporarily store first control information and data to be burned sent externally, and configured to receive, store and output the burning result; wherein, the first control information is used to control the state machine to enter the burning state or the reading state; a first pin, and the shift register receives the first control information sent externally through the first pin; the state machine is configured to: in the serial control state, obtain the first control information and the data to be burned from the shift register with a clock counting cycle, and the clock counting cycle is an integer multiple of the number of bits of the shift register; in the burning state, write the data to be burned in the shift register into the electronic fuse; in the reading state, read the burning result of the electronic fuse and store it in the shift register. Before the chip leaves the factory: in the serial control state, the first control information and the data to be burned are obtained from the shift register in the clock counting cycle; in the burning state, the data to be burned in the shift register is written into the electronic fuse; in the reading state, the burning result of the electronic fuse is read and stored in the shift register. After the chip leaves the factory, the chip can be calibrated directly by the burning result in the electronic fuse. The chip does not need to set up special decoders and other devices to parse the first control information and the data to be burned, which can reduce the area of ​​the chip and improve the integration.

[0112] In some embodiments, the chip includes: a state machine, the states of the state machine include a burning state, a reading state, and a serial control state; a shift register, configured to receive and temporarily store first control information and data to be burned sent externally, and configured to receive, store and output the burning result; wherein, the first control information is used to control the state machine to enter the burning state or the reading state; a first pin, and the shift register receives the first control information sent externally through the first pin; the state machine is configured to: in the serial control state, obtain the first control information and the data to be burned from the shift register, and the clock counting cycle is an integer multiple of the number of bits of the shift register; in the burning state, write the data to be burned in the shift register into the electronic fuse; in the reading state, read the burning result of the electronic fuse and store it in the shift register; based on the reset signal, read the burning result of the electronic fuse and store it in the shift register. Before the chip leaves the factory: the SPI interface (including the first pin) can be used to receive the first control information and the data to be burned sent from the outside; and the decoder of the SPI interface can be used to distinguish the first control information and the data to be burned; the state machine controls the burning or reading of the electronic fuse based on the decoded content. After the chip leaves the factory, the burning result of the electronic fuse can be read and stored in the shift register based on the reset signal. Therefore, the burning result stored in the shift register can be used to calibrate the chip after it is powered on, without the need to directly use the data stored in the electronic fuse for calibration, and the electronic fuse does not need to remain in working state all the time, which can prevent the electronic fuse from being damaged due to long-term operation.

[0113] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A chip with an electronic fuse, characterized in that: include: A state machine, wherein the states of the state machine include a programming state, a reading state, and a serial control state; A shift register, configured to receive and temporarily store first control information and data to be programmed sent externally, and configured to receive, store and output a programming result; wherein the first control information is used to control the state machine to enter the programming state or the reading state; A first pin, through which the shift register receives the first control information sent externally; The state machine is configured as follows: In the serial control state, the first control information and the data to be programmed are acquired from the shift register in a clock counting cycle, wherein the clock counting cycle is an integer multiple of the number of bits of the shift register; In the writing state, writing the data to be written in the shift register into the electronic fuse; In the reading state, the programming result of the electronic fuse is read and stored in the shift register; Based on a reset signal, the programming result of the electronic fuse is read and stored in the shift register.

2. The chip according to claim 1, characterized in that: The chip further includes: a module to be calibrated; wherein, The shift register is connected to the module to be calibrated and is configured to output the programming result to the module to be calibrated.

3. The chip according to claim 2, characterized in that: The chip further includes: a data bus; the shift register includes: a first register unit and a second register unit; wherein, The first register unit is connected to the state machine and is configured to transmit the first control information to the state machine; The second register unit is connected to the state machine and the data bus respectively, and is configured to transmit the data to be programmed to the state machine, and output the programming result to the module to be calibrated through the data bus.

4. The chip according to claim 3, characterized in that: The shift register and the first pin are serially transmitted, and the shift register and the state machine or the data bus are parallelly transmitted.

5. The chip according to any one of claims 1 to 4, characterized in that: The chip further includes: a first port and / or a second port; wherein, The first port is used to send an external clock signal outside the chip to the state machine and the shift register, and the first port includes a second pin; The second port is used to send the first control information and the data to be programmed to the shift register, and the second port includes the first pin; The first port and / or the second port are further configured to transmit second control information, where the second control information is an analog signal provided to the chip when the chip is working.

6. The chip according to claim 5, characterized in that: The first port is further configured to receive a multiplexing control signal, and select one of the external clock signal and the second control information for transmission based on the multiplexing control signal; and / or, The second port is further configured to receive the multiplexing control signal, and select one of the first control information and the second control information for transmission based on the multiplexing control signal.

7. The chip according to claim 6, characterized in that: The electronic fuse stores the multiplexing control signal; The first port or the second port obtains the multiplexing control signal from the electronic fuse.

8. The chip according to claim 6, characterized in that: The chip also includes a control pin; The control pin sends the multiplexing control signal to the first port and / or the second port.

9. The chip according to any one of claims 1 to 4, characterized in that: Also includes: A power-on reset module, configured to generate the reset signal after the chip is powered on; The state machine is further configured to enter the reading state from the serial control state based on the reset signal.

10. The chip according to claim 9, characterized in that: Also includes: A clock generation module, used for generating an internal clock signal; The state machine is further configured to generate a clock control signal based on the reset signal; The clock generation module is further configured to generate the internal clock signal after receiving the clock control signal; The state machine is further configured to shut down the clock generation module after storing the programming result in the shift register.

11. The chip according to claim 10, characterized in that: The chip further includes: a first selector; wherein, The state machine is further configured to generate an enable signal based on the reset signal; The first selector is connected to the state machine, configured to receive the enable signal, the internal clock signal and the external clock signal, and configured to select one of the external clock signal and the internal clock signal based on the enable signal and transmit it to the state machine and the shift register.

12. A method for configuring an electronic fuse, characterized in that: include: Receiving external first control information and data to be written through the same pin and temporarily storing them in the shift register; wherein the first control information is used to determine the operation state of the electronic fuse, and the operation state includes a writing state, a reading state, and a serial control state; In the serial control state, the first control information and the data to be programmed are obtained in a clock counting cycle; the clock counting cycle is an integer multiple of the number of bits of the shift register; In the burning state, the temporarily stored data to be burned is parsed and written into the electronic fuse; In the reading state, the burning result of the electronic fuse is parsed, read and stored in the shift register; Based on a reset signal, the programming result of the electronic fuse is read and stored in the shift register.

13. The configuration method according to claim 12, characterized in that: The programming result stored in the shift register is output to the module to be calibrated.

14. The configuration method according to claim 12 or 13, characterized in that: The parsing is performed by a state machine.

15. The configuration method according to claim 12, characterized in that: Also includes: Configure a clock signal, wherein the clock signal includes an internal clock signal and an external clock signal; The internal clock signal comes from the chip where the electronic fuse is located, and the external clock signal comes from the outside of the chip where the electronic fuse is located; In the programming state, selecting the external clock signal as the clock signal of the configuration method; In the reading state, selecting the external clock signal as the clock signal of the configuration method; When the chip is reset, the internal clock signal is selected as the clock signal of the configuration method.

16. The configuration method according to claim 15, characterized in that: Also includes: The external clock signal is received through another pin.

17. The configuration method according to claim 16, characterized in that: Also includes: The analog signal is received through the pin or the other pin in a time-sharing manner.

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