Wafer scheduling method and semiconductor process equipment

Abstract

This application discloses a wafer transfer scheduling method and semiconductor process equipment. The method includes: obtaining the workability status of two work positions in the process chamber corresponding to the wafer cassette to be scheduled; if the number of first-type process chambers where both work positions are workable is P (P > zero), then sequentially traversing the P chambers, and for each chamber, controlling a robotic arm to transfer two unworked wafers for processing; after traversing the P chambers, if the number of second-type process chambers where only one work position is workable is S (S > zero), then sequentially traversing the S chambers, and for each chamber, controlling a robotic arm to transfer a single unworked wafer for processing; after traversing the S chambers, determining the target process chamber based on the number of unworked wafers in the wafer cassette, and waiting for the target process chamber to complete its work before performing the corresponding transfer action. This application improves wafer transfer efficiency and equipment throughput.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a wafer transfer scheduling method and semiconductor process equipment. Background Technology

[0002] In the field of integrated circuit manufacturing, to improve the productivity of chip manufacturing equipment, it is particularly important to process two or more wafers at a time. This has led to the development of twin-chamber equipment (processing two wafers at a time) and furnace tube equipment (processing 50 to 200 wafers at a time). In twin-chamber equipment, the two positions (Stations, or STs) used for processing wafers are arranged horizontally, which is inconsistent with the vertical arrangement of wafers in a wafer cassette. Therefore, the requirements for scheduling algorithms are more stringent.

[0003] Chip manufacturing equipment can also include multiple process modules (PMs), each containing two process stations (STs). For example, a chip manufacturing equipment with two PMs would have four STs: PM1 includes ST1 and ST2, and PM2 includes ST3 and ST4. In this mode, wafers in the wafer cassette are grouped in pairs before the job begins. During the job, a pair of robotic arms simultaneously picks up and places wafers, achieving simultaneous entry and exit. However, in actual operation, one ST in a PM may become unusable (e.g., due to system failure, insufficient vacuum conditions, etc.). In such cases, the simultaneous entry and exit scheduling method would render the entire PM containing the unusable ST unusable, resulting in lower wafer transfer efficiency and equipment throughput. Summary of the Invention

[0004] The purpose of this application is to provide a wafer transfer scheduling method and semiconductor process equipment to solve the problem in related technologies where if one ST in a PM fails to operate, the entire PM becomes unusable, resulting in low wafer transfer efficiency and equipment capacity.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a wafer transfer scheduling method applicable to semiconductor process equipment having at least one process chamber, wherein the process chamber has two working positions, comprising: obtaining the workability status of the two working positions in the process chamber corresponding to the wafer cassette to be scheduled; if the number of first-type process chambers is P, wherein P is greater than zero, then sequentially traversing the P first-type process chambers, and for each first-type process chamber, controlling a robotic arm to transfer two unworked wafers in the wafer cassette for work; the first-type process chamber is one where both working positions are in a workable state. Process chambers; after the P first-type process chambers have been traversed, if the number of second-type process chambers is S, where S is greater than zero, then the S second-type process chambers are traversed sequentially. For each second-type process chamber, the robotic arm is controlled to transfer unworked single wafers for processing; the second-type process chamber is a process chamber with only one workable position; after the S second-type process chambers have been traversed, the target process chamber is determined based on the number of unworked wafers in the wafer cassette, and the process chamber is waited for to complete its work in order to perform the corresponding transfer action.

[0007] In a second aspect, embodiments of this application provide a semiconductor process apparatus, comprising: at least one process chamber, each process chamber including two work positions; a wafer transfer device for transferring unworked wafers to the work positions of each process chamber; and a controller including at least one processor and at least one memory, the memory storing a computer program, the computer program being executed by the processor to implement the wafer transfer scheduling method as described in the first aspect of this application.

[0008] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:

[0009] In this embodiment of the application, when scheduling wafer transfer within a wafer cassette, the workability status of two work positions in the process chamber corresponding to the wafer cassette to be scheduled is obtained. If the number of first-type process chambers is P, where P is greater than zero, then the P first-type process chambers are traversed sequentially. For each first-type process chamber, a robotic arm is controlled to transfer two unworked wafers from the wafer cassette for work. A first-type process chamber is a process chamber where both work positions are workable. After traversing the P first-type process chambers, if the number of second-type process chambers is S, where S is greater than zero, then the S second-type process chambers are traversed sequentially. For each second-type process chamber, a robotic arm is controlled to transfer a single unworked wafer for work. A second-type process chamber is a process chamber where only one work position is workable. After traversing the S second-type process chambers, the target process chamber is determined based on the number of unworked wafers in the wafer cassette, and the process chamber waits for the target process chamber to complete its work before executing the corresponding transfer action. This application embodiment identifies the workability status of two work positions in each process chamber, distinguishing between a first type of process chamber and a second type of process chamber. When the number of both types of process chambers is greater than zero, for each transfer of an unworked single wafer in a second type of process chamber, and for each transfer of two unworked wafers in a first type of process chamber, the single transfer requirement of two wafers per transfer is eliminated. This allows the entire second type of process chamber (PM) to remain usable even if one work position ST in a PM is unworkable, improving wafer transfer efficiency and equipment capacity. Furthermore, prioritizing the traversal of first type of process chambers during transfer further ensures efficiency. After the second type of process chambers are traversed, a target process chamber is determined based on the number of unworked wafers, and the transfer is initiated once the target chamber completes its work, further improving transfer efficiency and equipment capacity. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0011] Figure 1 A schematic flowchart of a chip transfer scheduling method provided in one embodiment of this application;

[0012] Figure 2 A schematic flowchart of a chip transfer scheduling method provided for another embodiment of this application;

[0013] Figure 3A schematic flowchart of a chip transfer scheduling method provided for another embodiment of this application;

[0014] Figure 4 A schematic flowchart of a chip transfer scheduling method provided for another embodiment of this application;

[0015] Figure 5 A schematic flowchart of a chip transfer scheduling method provided for another embodiment of this application;

[0016] Figure 6 A schematic diagram of the overall process of a slice scheduling method provided for another embodiment of this application;

[0017] Figure 7 This is a schematic diagram of the structure of a semiconductor process apparatus provided in one embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] The terms "first," "second," etc., used in this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, "and / or" in this application indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship. It should be noted that all data involved in this application was obtained with the user's authorization.

[0020] In the field of integrated circuit manufacturing, to improve the productivity of chip manufacturing equipment, it is particularly important to process two or more wafers at a time. This has led to the development of dual-cavity equipment (processing two wafers at a time) and furnace-tube equipment (processing 50-200 wafers at a time). In furnace-tube equipment, wafers are placed manually (horizontal furnace) or by a robotic arm (vertical furnace). Because the wafers are placed vertically in a vertical furnace, consistent with the arrangement in the wafer cassette, the requirements for scheduling algorithms in furnace-tube equipment are not high. However, in dual-cavity equipment, the two wafer processing positions (i.e., work positions) ST are arranged horizontally, inconsistent with the arrangement in the wafer cassette. Therefore, the requirements for scheduling algorithms are more demanding, especially when multiple wafer cassettes correspond to multi-cavity operations.

[0021] Chip manufacturing equipment can also include multiple process chambers (PMs), each PM containing two process stations (STs). For example, a chip manufacturing equipment with two PMs includes four STs: PM1 includes ST1 and ST2, and PM2 includes ST3 and ST4. In this mode, wafers in the wafer cassette are grouped in pairs before the operation begins. During the operation, a pair of robotic arms simultaneously pick up and place wafers, achieving simultaneous entry and exit. However, in actual operation, one ST in a PM may become unusable (e.g., due to system failure, insufficient vacuum conditions, etc.). In this case, the simultaneous entry and exit scheduling method will render the entire PM containing the unusable ST unusable, resulting in low wafer transfer efficiency and equipment capacity. To address this, this application proposes a wafer transfer scheduling method and semiconductor process equipment to solve the problem in related technologies where the inability of one ST in a PM to operate leads to the unusability of the entire PM, resulting in low wafer transfer efficiency and equipment capacity.

[0022] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0023] Figure 1 This is a flowchart illustrating a chip transfer scheduling method provided in one embodiment of this application. Figure 1 As shown, the chip transfer scheduling method of this application embodiment may specifically include the following steps:

[0024] S101, obtain the workability status of two work positions in the process chamber corresponding to the wafer cassette to be scheduled.

[0025] In this embodiment of the application, the execution subject of the wafer transfer scheduling method is a controller. The controller can be set in a semiconductor process equipment (e.g., a chip manufacturing equipment) with at least one process chamber PM. Specifically, it can be set in the host computer and / or slave computer of the semiconductor process equipment. Each PM has two working positions ST.

[0026] The PM corresponding to the wafer cassette to be scheduled, that is, the PM that the wafer in the wafer cassette is allowed to work on, can be obtained by reading the waferflow settings.

[0027] Obtain the operational status of two STs in each PM. The operational status includes operational and non-operable. Among them, the non-operable (or unusable) ST is mainly divided into two situations: one is that the ST is already in operation, that is, occupied and cannot operate; the other is that the hardware conditions of the ST are not met, such as the vacuum level does not meet the requirements for operation, or the necessary components are missing and cannot operate normally. These can be automatically identified by software through electrical signals.

[0028] S102, based on the workability status, process chambers in which both work positions are workable are defined as first-type process chambers, and process chambers in which only one work position is workable are defined as second-type process chambers.

[0029] In this embodiment of the application, if both STs in a PM are in a workable state, then the PM is determined to be a first type PM. If only one of the two STs in a PM is in a workable state, then the PM is determined to be a second type PM.

[0030] S103, for the second type of process chamber, control the robot to perform operations on each unworked single wafer transferred from the wafer cassette.

[0031] In the embodiments of this application, for the second type PM, since only one ST can be operated, when transferring unoperated wafers in the wafer cassette to the second type PM for operation, the robot arm is controlled to transfer a single wafer at a time.

[0032] S104, for the first type of process chamber, control the robot to transfer two unworked wafers from the wafer cassette for processing each time.

[0033] In this embodiment, for the first type PM, since both STs can operate, when transferring unoperated wafers from the wafer cassette to the first type PM for operation, the robot arm is controlled to transfer two wafers at a time. In a special case, when only one unoperated wafer remains in the wafer cassette, the robot arm is controlled to transfer a single wafer at a time.

[0034] It should be noted that the wafer transfer scheduling method in this application allows the second type of process chamber to still be used, improving wafer transfer efficiency and equipment capacity. For example, suppose there are 4 process rooms (PMs). One of these PMs has 1 unusable process station (ST), another PM has 2 unusable STs, and the remaining 2 PMs are normal. That is, there is 1 second type PM and 2 first type PMs. In related technical solutions, only 2 first type PMs are available, i.e., 4 STs are available. However, in the solution of this application embodiment, in addition to the 2 first type PMs available, there is also 1 second type PM available, i.e., 5 STs are available. The number of available STs has increased, thus improving wafer transfer efficiency and equipment capacity.

[0035] Furthermore, based on the number of the first type of process chambers and the number of the second type of process chambers determined in step S102, the transmission scheduling can be divided into the following four cases.

[0036] In the first scenario, if the number of first-type process chambers determined in step S102 is zero, and the number of second-type process chambers is S, where S is greater than zero, then only step S103 is executed, meaning that transmission scheduling (i.e., job task allocation) is performed only for the second-type process chambers. Figure 2 As shown, step S103, "For the second type of process chamber, control the robot to transfer unworked single wafers from the wafer cassette for processing each time," can specifically include the following steps:

[0037] S201, sequentially traverse the S second-type process chambers, and for each second-type process chamber, control the robot arm to transfer the unworked single wafer for processing.

[0038] In this embodiment, S second-type PMs are arranged sequentially. Starting from the first second-type PM, these S second-type PMs are traversed sequentially. For each second-type PM, a robotic arm is controlled to transfer an unworked wafer to the second-type PM for processing. After the processing is completed, the robotic arm is controlled to transfer the wafer back to the wafer cassette. Those skilled in the art will understand that if the number of wafers in the wafer cassette is limited (less than S wafers), during the traversal process, when all wafers in the wafer cassette have been processed, i.e., the number of unworked wafers is zero, the transfer operation stops, and no further transfer scheduling is performed on the untraversed second-type PMs.

[0039] S202, the S second-type process chambers have been traversed.

[0040] In this embodiment of the application, if the number of wafers in the wafer cassette is large (equal to or greater than S wafers), then wait for S second-type PMs to be traversed.

[0041] S203, the second-type process chamber with the shortest remaining operation time among the S second-type process chambers is identified as the target process chamber, and the process chamber is waited for to complete its operation.

[0042] In this embodiment of the application, if there are a large number of wafers in the wafer cassette (more than S wafers), and there are still unfinished wafers after traversing S second-type PMs, a new traversal starting point is determined: the second-type PM with the shortest remaining job time among the S second-type PMs is determined as the target PM (i.e., the new traversal starting point), and the target PM is waited to complete its job.

[0043] It should be noted here that for the second type of PM who is in an inactive state, the remaining working time is 0.

[0044] In addition, if there are multiple second-type PMs with the shortest remaining work time, one of the second-type PMs can be randomly selected as the target PM, or the second-type PM ranked first can be selected as the target PM. This application does not impose too many restrictions on this.

[0045] S204: Starting from the target process chamber, traverse sequentially to the last second-type process chamber. For each second-type process chamber that is not in operation, control the robot to transfer the unoperated single wafer for operation.

[0046] In this embodiment, the target PM determined in step S203 is used as the new traversal starting point. The process sequentially traverses to the last (i.e., the Sth) second-type PM. For each second-type PM, the robotic arm is controlled to transfer unworked wafers to the second-type PM for processing. After the processing is completed, the robotic arm is controlled to transfer the wafer back to the wafer cassette. Similarly, if all wafers in the wafer cassette have completed processing during the traversal to the last second-type PM, i.e., the number of unworked wafers is zero, the transfer process stops, and no further transfer scheduling is performed on untraversed second-type PMs.

[0047] S205, Traversal complete. Return to step S203.

[0048] In this embodiment, if there are many wafers in the wafer cassette, the process waits for the traversal to complete. If, after traversing to the last (i.e., the Sth) second-type PM and completing the transfer job, there are still unprocessed wafers, the process returns to step S203 to determine a new traversal starting point and proceeds to the next traversal.

[0049] It should be noted here that if the target PM is not the first second-type PM, the number of second-type PMs scheduled in this traversal process will definitely be less than S.

[0050] In the second scenario, if the number of second-type process chambers determined in step S102 is zero, and the number of first-type process chambers is P, where P is greater than zero, then only step S104 is executed, meaning that transmission scheduling (i.e., job task allocation) is performed only for the first-type process chambers. Figure 3 As shown, step S104, "For the first type of process chamber, control the robot to transfer two unworked wafers from the wafer cassette for processing each time," may specifically include the following steps:

[0051] S301, sequentially traverse P first-type process chambers, and for each first-type process chamber, control the robot to transfer two unworked wafers for processing.

[0052] In this embodiment of the application, P first-type PMs are arranged sequentially. Starting from the first first-type PM, the P second-type PMs are traversed sequentially. For each first-type PM, the robot arm is controlled to transfer two unworked wafers to the first-type PM for work. After the work is completed, the robot arm is controlled to transfer the two wafers back to the wafer cassette.

[0053] It should be noted here that when sequentially traversing the second type of wafer markers (PMs), for each first type of PM, if the number of unworked wafers in the wafer cassette is equal to or greater than two, the robot arm is controlled to transfer the two unworked wafers to the first type of PM for work, and after the work is completed, the robot arm is controlled to transfer these two wafers back to the wafer cassette. If the number of unworked wafers in the wafer cassette is one, the robot arm is controlled to transfer that wafer to the first type of PM for work, and after the work is completed, the robot arm is controlled to transfer that wafer back to the wafer cassette.

[0054] Those skilled in the art will understand that if the number of wafers in the wafer cassette is limited (less than 2P-2 wafers), during the traversal process, when all wafers in the wafer cassette have been processed, i.e., when the number of unprocessed wafers is zero, the transmission operation stops, and the transmission scheduling for the first type PM that has not been traversed is no longer performed.

[0055] S302, P first-type process chambers have been traversed.

[0056] In this embodiment of the application, if the number of wafers in the wafer cassette is large (equal to or greater than 2P wafers), then wait for P first-type PMs to be traversed.

[0057] S303, the first type of process chamber with the least remaining operation time among the P first type process chambers is identified as the target process chamber, and the process chamber is waited for to complete its operation.

[0058] In this embodiment of the application, if there are a large number of wafers in the wafer cassette (greater than 2P wafers), and there are still unfinished wafers after traversing P first-type PMs, a new traversal starting point is determined: the first-type PM with the shortest remaining job time among the P first-type PMs is determined as the target PM (i.e., the new traversal starting point), and the target PM is waited for to complete its job.

[0059] It should be noted here that for the first type of PM who is in an inactive state, the remaining working time is 0.

[0060] In addition, if there are multiple first-type PMs with the shortest remaining work time, one of the first-type PMs can be randomly selected as the target PM, or the first-ranked first-type PM can be selected as the target PM. This application does not impose too many restrictions on this.

[0061] S304, starting from the target process chamber, traverse sequentially to the last first-type process chamber. For each first-type process chamber that is not in operation, control the robot to transfer the two unoperated wafers for operation.

[0062] In this embodiment, the target PM determined in step S303 is used as the new traversal starting point. The process sequentially traverses to the last (i.e., the Pth) first-type PM. For each first-type PM, if the number of unworked wafers in the wafer cassette is equal to or greater than two, the robot arm is controlled to transfer the two unworked wafers to the first-type PM for work. After the work is completed, the robot arm is controlled to transfer these two wafers back to the wafer cassette. If the number of unworked wafers in the wafer cassette is one, the robot arm is controlled to transfer that wafer to the first-type PM for work. After the work is completed, the robot arm is controlled to transfer that wafer back to the wafer cassette. Similarly, if all wafers in the wafer cassette have been worked on during the traversal to the last first-type PM, i.e., the number of unworked wafers is zero, the transfer operation stops, and no further transfer scheduling is performed on the untraversed first-type PMs.

[0063] S305, Traversal complete. Return to step S303.

[0064] In this embodiment, if there are many wafers in the wafer cassette, the process waits for the traversal to complete. If, after traversing to the last (i.e., the Pth) first-type PM and completing the transfer job, there are still unprocessed wafers, the process returns to step S303 to determine a new traversal starting point and proceeds to the next traversal.

[0065] It should be noted here that when the target PM is not the first PM of type 1, the number of PMs of type 1 scheduled in this traversal process is definitely less than P.

[0066] In the third scenario, if the number of second-type process chambers determined in step S102 is S (S > zero), and the number of first-type process chambers is P (P > zero), then steps S103 and S104 are executed, i.e., transmission scheduling (i.e., task allocation) is performed for the second-type and first-type process chambers. Figure 4 As shown, steps S103 and S104 above, "For the second type of process chamber, control the robot to transfer an unworked single wafer from the wafer cassette for processing each time; for the first type of process chamber, control the robot to transfer two unworked wafers from the wafer cassette for processing each time," may specifically include the following steps:

[0067] S401, sequentially traverse P first-type process chambers, and for each first-type process chamber, control the robot to transfer two unworked wafers for processing.

[0068] In this embodiment, if both the number of second-type PMs and the number of first-type PMs are not zero, then the first-type PMs are traversed firstly. The process of traversing P first-type PMs in this step can be found in the relevant description of step S301 in the above embodiment, and will not be repeated here.

[0069] S402, P first-type process chambers have been traversed.

[0070] In the embodiments of this application, the specific process of this step can be found in the relevant description of step S302 in the above embodiments, and will not be repeated here.

[0071] S403, sequentially traverse the S second-type process chambers, and for each second-type process chamber, control the robot arm to transfer the unworked single wafer for processing.

[0072] In this embodiment of the application, the specific process of this step can be found in the relevant description of step S201 in the above embodiment, and will not be repeated here.

[0073] S404, after traversing S second-type process chambers, obtain the number of unprocessed wafers in the wafer cassette.

[0074] In this embodiment of the application, if the number of wafers in the wafer cassette is large (equal to or greater than 2P+S wafers), then wait for S second-type PMs to be traversed.

[0075] Considering that a wafer box typically contains 25 wafers, which is an odd number, or that some wafers may have been scrapped in previous processing steps, resulting in an odd number of fewer than 25 wafers, such as 23 or 21 wafers, the number of unprocessed wafers in the wafer box is obtained after traversing the S second-type process chambers.

[0076] S405: Based on the number of unprocessed wafers in the wafer cassette, determine the target process chamber and wait for the target process chamber to complete its work in order to perform the corresponding transfer action.

[0077] In this embodiment, the process chambers to be scheduled and the scheduling method are determined based on the number of unprocessed wafers in the wafer cassette. Specifically, this step may include the following steps:

[0078] S4051, if the number of unprocessed wafers in the wafer cassette is greater than two, then the first-type process chamber with the shortest remaining processing time among the P first-type process chambers is identified as the target process chamber, and the process waits for the target process chamber to complete its operation. Starting from the target process chamber, the process is re-traversed sequentially to the last first-type process chamber. For each first-type process chamber that is not currently in operation, the robot arm is controlled to transfer the two unprocessed wafers for operation, and the process waits for the traversal to complete. Return to step S403.

[0079] In this embodiment, if the number of unprocessed wafers in the wafer cassette is greater than two, a new traversal starting point is determined in P first-type process chambers, and a traversal process is performed. After the traversal is completed, the second-type process chambers are traversed. The specific process of this step can be found in the relevant descriptions in steps S303 and S304 above, and will not be repeated here.

[0080] S4052, if there are two unprocessed wafers in the wafer cassette, then the first-type process chamber with the least remaining processing time among the P first-type process chambers is identified as the target process chamber; wait for the target process chamber to complete its operation; control the robot arm to transfer the two wafers to the target process chamber for operation.

[0081] In this embodiment of the application, if there are two unprocessed wafers in the wafer cassette, one of the P first-type process chambers is selected for processing: the process chamber with the shortest remaining processing time among the P first-type process chambers is selected, and after the process chamber completes its processing, the robot is controlled to transfer the two wafers to the process chamber for processing, and after the processing is completed, the robot is controlled to transfer the two wafers back to the wafer cassette.

[0082] S4053, if the number of unprocessed wafers in the wafer cassette is one, then the process chamber with the least remaining processing time among the P first-type process chambers and S second-type process chambers is determined as the target process chamber; wait for the target process chamber to complete the operation; control the robot arm to transfer the wafer to the target process chamber for operation.

[0083] In this embodiment of the application, if the number of unprocessed wafers in the wafer cassette is one, then one of the P first-type process chambers and S second-type process chambers is selected for processing: the process chamber with the shortest remaining processing time among the P first-type process chambers and S second-type process chambers is selected, and after the process chamber completes its processing, the robot arm is controlled to transfer the wafer to the process chamber for processing, and after the processing is completed, the robot arm is controlled to transfer the wafer back to the wafer cassette.

[0084] In the fourth case, if the number of second-type process chambers determined in step S102 is zero and the number of first-type process chambers is also zero, then the following steps are executed: output an alarm message to prompt the user that there are no workable process chambers.

[0085] Furthermore, the second and third scenarios mentioned above can be combined, as follows:

[0086] If the number of first-type process chambers determined in step S102 is P, where P is greater than zero, then the number of second-type process chambers is not considered initially. Instead, step S104 is executed, i.e., transmission scheduling (i.e., job task allocation) is performed first for the first-type process chambers. After traversing all P first-type process chambers, the number of second-type process chambers is used to determine whether to execute step S103, i.e., whether to perform transmission scheduling (i.e., job task allocation) for the second-type process chambers. Figure 5 As shown, the specific steps may include:

[0087] S501, if the number of first-type process chambers is P, where P is greater than zero, then sequentially traverse the P first-type process chambers. For each first-type process chamber, control the robot arm to transfer the two unworked wafers for processing.

[0088] S502, P first-type process chambers have been traversed.

[0089] If the number of second-type process chambers is S, where S is greater than zero, then proceed to step S503. If the number of second-type process chambers is zero, then proceed to step S506.

[0090] S503 sequentially traverses the S second-type process chambers. For each second-type process chamber, the robot arm is controlled to transfer the unworked single wafer for processing.

[0091] S504, after traversing S second-type process chambers, obtain the number of unprocessed wafers in the wafer cassette.

[0092] S505: Based on the number of unprocessed wafers in the wafer cassette, determine the target process chamber and wait for the target process chamber to complete its work in order to perform the corresponding transfer action.

[0093] S506, the first type of process chamber with the least remaining operation time among the P first type process chambers is identified as the target process chamber, and the process chamber is waited for to complete its operation.

[0094] S507: Starting from the target process chamber, the process re-traverses sequentially to the last first-type process chamber. For each first-type process chamber that is not in operation, the robot arm is controlled to transfer the two unoperated wafers for operation.

[0095] S508, Traversal complete. Return to step S506.

[0096] In summary, the wafer transfer scheduling method of this application, when performing wafer transfer scheduling within a wafer cassette, obtains the workability status of two work positions in the process chamber corresponding to the wafer cassette to be scheduled. If the number of first-type process chambers is P, where P is greater than zero, then the P first-type process chambers are traversed sequentially. For each first-type process chamber, the robotic arm is controlled to transfer two unworked wafers from the wafer cassette for processing. A first-type process chamber is a process chamber where both work positions are in a workable state. After the process chambers are traversed, if the number of second-type process chambers is S (S is greater than zero), then the S second-type process chambers are traversed sequentially. For each second-type process chamber, the robot arm is controlled to transfer the unworked single wafer for processing. A second-type process chamber is a process chamber with only one working position and a working state of "working". After the S second-type process chambers are traversed, the target process chamber is determined according to the number of unworked wafers in the wafer cassette, and the process chamber waits for the target process chamber to complete its work in order to perform the corresponding transfer action. This application's embodiments identify the workability status of two work positions in each process chamber, distinguishing between a first-type and a second-type process chamber. For the second-type process chamber, each transfer involves a single unworked wafer; for the first-type process chamber, each transfer involves two unworked wafers. If only one unworked wafer remains, only that wafer is transferred, eliminating the requirement of transferring two wafers per transfer. This ensures that even if one work position (ST) in a process chamber (PM) is unworkable, the entire PM (i.e., the second-type process chamber) containing that unworkable ST remains usable, improving wafer transfer efficiency and equipment capacity. Different wafer transfer scheduling schemes are executed based on the number of first-type and second-type process chambers, further guaranteeing transfer efficiency. When both the number of first-type and second-type process chambers are not zero, the first-type process chambers are prioritized for traversal, further ensuring transfer efficiency. After traversal, when determining a new traversal starting point, the process chamber with the shortest remaining process time is selected, further guaranteeing transfer efficiency. When there are two unprocessed wafers, the first type of process chamber with the shortest remaining process time is selected for processing. When there is one unprocessed wafer, the process chamber with the shortest remaining process time between the first type of process chamber and the second type of process chamber is selected for processing, which further ensures wafer transfer efficiency.

[0097] To clearly illustrate the chip transfer scheduling method of this application embodiment, the following is combined with... Figure 6 A feasible implementation of the overall flow of the chip transfer scheduling method according to the embodiments of this application (corresponding to the four cases mentioned above) is described in detail. For example... Figure 6 As shown, the chip transfer scheduling method in this application embodiment may specifically include the following steps:

[0098] S601, execute the wafer cassette scanning function to obtain the number W of wafers in the wafer cassette.

[0099] S602, Read the number N of PMs allowed for wafers in the wafer cassette in the wafer path settings.

[0100] S603, let the PM's index n = 1, the number of second-type PMs S = 0, and the number of first-type PMs P = 0.

[0101] S604, determine if there is an unusable ST in the nth PM. If not, proceed to step S605. If yes, proceed to step S606.

[0102] S605, n = n+1, P = P+1. Execute step S609.

[0103] S606, determine if two STs in the nth PM cannot be used simultaneously. If not, proceed to step S607. If yes, proceed to step S608.

[0104] S607, n = n + 1, S = S + 1. Execute step S609.

[0105] S608, n = n + 1. Execute step S609.

[0106] S609, determine if n = N. If yes, proceed to step S610. If no, return to step S604.

[0107] It should be noted here that the purpose of steps S603-S609 above is to determine the number of second-type PMs and the number of first-type PMs among the N PMs.

[0108] S610, set the number of wafers already processed w = 0, the serial number of the first type PM p = 1, and the serial number of the second type PM s = 1. Continue to execute step S611.

[0109] S611, determine whether S = 0 and whether P = 0.

[0110] If P = 0 and S is greater than 0, then execute step S612 (corresponding to the first case in the above embodiment).

[0111] If P is greater than 0 and S = 0, then step S618 is executed (corresponding to the second case in the above embodiment).

[0112] If P is greater than 0 and S is greater than 0, then proceed to step S627 (corresponding to the third case in the above embodiments).

[0113] If P=0 and S=0, then execute step S646 (corresponding to the fourth case in the above embodiments).

[0114] S612, determine whether the s-th second-type PM is currently in operation. If not, proceed to step S613. If yes, proceed to step S615.

[0115] S613, transfer the unworked wafer to the s-th second-type PM for work, and set w = w + 1. Continue to execute step S614.

[0116] S614, determine if w = W. If yes, proceed to step S646. If no, proceed to step S615.

[0117] S615, s = s + 1. Continue to execute step S616.

[0118] S616, determine if s > S. If not, return to step S612. If yes, execute S617.

[0119] S617, assign the value s to the PM with the shortest remaining job time among the S second-type PMs, and wait for that PM to complete the job. Execute step S612.

[0120] S618, determine whether the p-th first-type PM is currently in operation. If not, proceed to step S619. If yes, proceed to step S624.

[0121] S619, determine if Ww≥2. If yes, proceed to step S620. If no, proceed to step S621.

[0122] S620, transfer the two unworked wafers to the p-th type 1 PM for work, and set w = w + 2. Execute step S623.

[0123] S621, Determine if Ww = 1. If yes, proceed to step S622. If no, proceed to step S646.

[0124] S622, transfer the unworked wafer to the p-th type 1 PM for work, and set w = w + 1. Execute step S646.

[0125] S623, determine if w = W. If yes, proceed to step S646. If no, proceed to step S624.

[0126] S624, p = p + 1. Continue to step S625.

[0127] S625, determine if p > P. If not, return to step S618. If yes, execute S626.

[0128] S626, assign the value p to the PM with the shortest remaining job time among the P PMs of type 1, and wait for that PM to complete the job. Return to step S618.

[0129] S627, determine whether the p-th first-type PM is currently in operation. If not, proceed to step S628. If yes, proceed to step S633.

[0130] S628, determine if the number of unprocessed wafers Ww ≥ 2. If yes, proceed to step S629. If no, proceed to step S630.

[0131] S629, transfer the two unworked wafers to the p-th type 1 PM for work, and set w = w + 2. Execute step S632.

[0132] S630, determine if Ww = 1. If yes, proceed to step S631. If no, proceed to step S646.

[0133] S631, transfer the unworked wafer to the p-th type 1 PM for work, and set w = w + 1. Execute step S646.

[0134] S632, determine if w = W. If yes, proceed to step S646. If no, proceed to step S633.

[0135] S633, p = p + 1. Continue to execute step S634.

[0136] S634, determine if p > P. If not, return to step S627. If yes, execute S635.

[0137] S635, determine if s > S. If not, proceed to step S636. If yes, proceed to step S640.

[0138] S636, determine whether the s-th second-type PM is currently in operation. If not, proceed to step S637. If yes, proceed to step S639.

[0139] S637, transfer the unworked wafer to the s-th type 2 PM for processing, and set w = w + 1. Continue to execute step S638.

[0140] S638, determine if w = W. If yes, proceed to step S646. If no, proceed to step S639.

[0141] S639, s = s + 1. Return to step S635.

[0142] S640, determine if Ww≤2. If not, proceed to step S641. If yes, proceed to step S642.

[0143] S641, assign the value p to the PM with the shortest remaining job time among the P PMs of type 1, and wait for that PM to complete the job. Execute step S627.

[0144] S642, determine if Ww = 1. If yes, proceed to step S643. If no, proceed to step S644.

[0145] S643, wait for the PM with the shortest remaining job time among the S second-type PMs and P first-type PMs to complete its job, and transfer the unfinished wafer to that PM for job processing. Execute step S646.

[0146] S644, wait for the PM with the shortest remaining job time among the P first-type PMs to complete its job, and then transfer the two unfinished wafers to that PM for job processing. Execute step S646.

[0147] S645 outputs an alarm message to the user indicating that there is no workable PM.

[0148] S646, end the film transfer scheduling process.

[0149] This application also provides a semiconductor process apparatus. For example... Figure 7 As shown, the semiconductor process equipment 700 includes:

[0150] At least one process chamber 400, each process chamber 400 including two working positions.

[0151] The wafer transfer device 300 is used to transfer unworked wafers to the work positions of each process chamber 400.

[0152] The robotic arm module includes an atmospheric robotic arm 110 located within the loading / unloading module 100 and a vacuum robotic arm 310 located within the wafer transfer device 300.

[0153] The semiconductor process equipment 700 of this application embodiment further includes: a controller (not shown), the controller including at least one processor and at least one memory, the memory storing a computer program, and the computer program, when executed by the processor, implements the wafer transfer scheduling method as shown in any of the above embodiments.

[0154] It should be noted that the controller can be set in the lower-level machine (not shown) and / or the upper-level machine (not shown) of the semiconductor process equipment 700, and the lower-level machine and the upper-level machine communicate with each other.

[0155] Furthermore, the semiconductor process equipment 700 in this embodiment of the application also includes a load locking module 200, which is disposed between the loading / unloading module 100 and the wafer transfer device 300, and is used to switch between a vacuum environment and an atmospheric environment.

[0156] The semiconductor process equipment of this application identifies a first type of process chamber and a second type of process chamber by recognizing the workability status of two work positions in each process chamber. For the second type of process chamber, it transfers a single unworked wafer each time; for the first type of process chamber, it transfers two unworked wafers each time. When only one unworked wafer is available, only one wafer is transferred, eliminating the requirement that each transfer must involve two wafers. This ensures that even if one work position ST in a process chamber PM is unworkable, the entire PM (i.e., the second type of process chamber) containing that unworkable ST can still be used, improving wafer transfer efficiency and equipment capacity. Different wafer transfer scheduling schemes are executed based on the number of first and second type process chambers, further guaranteeing wafer transfer efficiency. When both the number of first and second type process chambers are not zero, the first type of process chambers are traversed first, further ensuring wafer transfer efficiency. After traversal, when determining a new traversal starting point, the process chamber with the shortest remaining process time is selected, further guaranteeing wafer transfer efficiency. When there are two unprocessed wafers, the first type of process chamber with the shortest remaining process time is selected for processing. When there is one unprocessed wafer, the process chamber with the shortest remaining process time between the first type of process chamber and the second type of process chamber is selected for processing, which further ensures wafer transfer efficiency.

[0157] This application also proposes a readable storage medium storing one or more computer programs, the one or more computer programs including instructions. When the program or instructions are executed by a processor in a semiconductor process apparatus including multiple applications, the processor in the semiconductor process apparatus is able to execute the various processes of the above-described wafer transfer scheduling method embodiments, and is specifically used to execute the steps of any of the above-described wafer transfer scheduling method embodiments.

[0158] The readable storage medium of this application identifies the first type of process chamber and the second type of process chamber by recognizing the workability status of two work positions in each process chamber. For the second type of process chamber, it transfers a single unworked wafer each time; for the first type of process chamber, it transfers two unworked wafers each time. When there is only one unworked wafer, it transfers a single wafer, eliminating the requirement that each transfer must be two wafers. This ensures that even if one work position ST in a process chamber PM is unworkable, the entire PM (i.e., the second type of process chamber) containing that unworkable ST can still be used, improving wafer transfer efficiency and equipment capacity. Different wafer transfer scheduling schemes are executed based on the number of first and second type process chambers, further guaranteeing wafer transfer efficiency. When the number of both first and second type process chambers is not zero, the first type of process chambers are traversed first, further guaranteeing wafer transfer efficiency. When a new traversal starting point is determined after traversal, the process chamber with the shortest remaining process time is selected, further guaranteeing wafer transfer efficiency. When there are two unprocessed wafers, the first type of process chamber with the shortest remaining process time is selected for processing. When there is one unprocessed wafer, the process chamber with the shortest remaining process time between the first type of process chamber and the second type of process chamber is selected for processing, which further ensures wafer transfer efficiency.

[0159] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0160] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0161] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0162] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0163] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0164] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0165] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0166] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0167] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0168] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0169] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0170] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0171] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A wafer transfer scheduling method, applicable to semiconductor process equipment having at least one process chamber, said process chamber having two working positions, characterized in that, include: Obtain the workability status of the two work positions in the process chamber corresponding to the wafer cassette to be scheduled; If the number of first-type process chambers is P, where P is greater than zero, then the P first-type process chambers are traversed sequentially. For each first-type process chamber, the robotic arm is controlled to transfer the two unworked wafers in the wafer cassette for processing. The first type of process chamber is a process chamber in which both working positions are in a workable state; After the P first-type process chambers are traversed, if the number of second-type process chambers is S, where S is greater than zero, then the S second-type process chambers are traversed sequentially. For each second-type process chamber, the robotic arm is controlled to transfer the unworked single wafer for processing. The second type of process chamber is a process chamber in which only one of the aforementioned work positions is in an operable state; After the S second-type process chambers have been traversed, the target process chamber is determined based on the number of unprocessed wafers in the wafer cassette, and the process chamber waits for the target process chamber to complete its work in order to perform the corresponding transfer action.

2. The method according to claim 1, characterized in that, The step of determining the target process chamber based on the number of unprocessed wafers in the wafer cassette, and waiting for the target process chamber to complete its work in order to perform the corresponding transfer action includes: If the number of unprocessed wafers in the wafer cassette is one, then the process chamber with the least remaining processing time among the P first-type process chambers and the S second-type process chambers is determined as the target process chamber. The process chamber waits for the target process chamber to complete its operation, and then the robot arm is controlled to transfer the wafer to the target process chamber for processing.

3. The method according to claim 1, characterized in that, The step of determining the target process chamber based on the number of unprocessed wafers in the wafer cassette, and waiting for the target process chamber to complete its work in order to perform the corresponding transfer action includes: If there are two unprocessed wafers in the wafer cassette, the first-type process chamber with the shortest remaining processing time among the P first-type process chambers is identified as the target process chamber. The robot is then controlled to transfer the two wafers to the target process chamber for processing after the target process chamber has completed its operation.

4. The method according to claim 1, characterized in that, The step of determining the target process chamber based on the number of unprocessed wafers in the wafer cassette, and waiting for the target process chamber to complete its work in order to perform the corresponding transfer action includes: If the number of unprocessed wafers in the wafer cassette is greater than two, then the first-type process chamber with the shortest remaining processing time among the P first-type process chambers is identified as the target process chamber, and the process chamber is waited for to complete its operation. Starting from the target process chamber, the process is re-traversed sequentially to the last first-type process chamber. For each first-type process chamber that is not in operation, the robot is controlled to transfer the two unoperated wafers for operation. After the traversal is completed, the process returns to the step of sequentially traversing the S second-type process chambers.

5. The method according to claim 1, characterized in that, Also includes: After the P first-type process chambers have been traversed, if the number of second-type process chambers is zero, then the first-type process chamber with the shortest remaining operation time among the P first-type process chambers is determined as the target process chamber, and the target process chamber is waited for to complete its operation. Starting from the target process chamber, the process is sequentially traversed to the last first-type process chamber. For each first-type process chamber that is not in operation, the robot is controlled to transfer two unoperated wafers for operation. After the traversal is completed, the process returns to the step of determining the first-type process chamber with the shortest remaining operation time among the P first-type process chambers as the target process chamber.

6. The method according to any one of claims 1-5, characterized in that, When sequentially traversing the first type of process chambers, the step of controlling the robotic arm to transfer two unworked wafers for operation in each first type of process chamber that is not in operation includes: For each of the first type of process chambers that is not in operation, if the number of unoperated wafers is equal to or greater than two, the robot arm is controlled to transfer the two unoperated wafers for operation.

7. The method according to claim 6, characterized in that, When sequentially traversing the first type of process chambers, the step of controlling the robotic arm to transfer two unworked wafers for operation in each first type of process chamber that is not in operation further includes: If there is only one unprocessed wafer, the robotic arm is controlled to transfer that wafer for processing.

8. The method according to claim 1, characterized in that, Also includes: If the number of the first type of process chambers is zero and the number of the second type of process chambers is S, where S is greater than zero, then the S second type of process chambers are traversed sequentially. For each second type of process chamber, the robotic arm is controlled to transfer the unworked single wafer for processing. After the S second-type process chambers have been traversed, the second-type process chamber with the shortest remaining operation time among the S second-type process chambers is determined as the target process chamber, and the target process chamber is waited for to complete its operation. Starting from the target process chamber, the process is sequentially traversed to the last second-type process chamber. For each second-type process chamber that is not in operation, the robotic arm is controlled to transfer the unoperated single wafer for operation. After the traversal is completed, the process returns to the step of determining the second-type process chamber with the shortest remaining operation time among the S second-type process chambers as the target process chamber.

9. The method according to claim 1, characterized in that, Also includes: If the number of the second type of process chambers is zero and the number of the first type of process chambers is zero, an alarm message is output to indicate to the user that there are no operable process chambers.

10. A semiconductor process apparatus, characterized in that, include: At least one process chamber, each of which has two working positions; A wafer transfer device for transferring unworked wafers to the work positions in each of the process chambers; A controller, comprising at least one processor and at least one memory, wherein the memory stores a computer program that, when executed by the processor, implements the chip transfer scheduling method as described in any one of claims 1-9.

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