Package structure and method of manufacturing the same

Abstract

This disclosure relates to the semiconductor field, providing a packaging structure and its manufacturing method. The packaging structure includes: a chip stack, comprising a first sub-stack and a second sub-stack; the first sub-stack includes two layers of chips disposed back-to-back, with a first filler layer between the two layers of chips in the first sub-stack; the second sub-stack includes two layers of chips disposed front-to-front or front-to-back; the second sub-stack has a second filler layer between the two layers of chips in the second sub-stack, wherein the first filler layer and the second filler layer are made of different materials. This disclosure can at least improve the performance of the packaging structure.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductors, and specifically relates to a packaging structure and its manufacturing method. Background Technology

[0002] As electronic products evolve towards miniaturization, high density, high reliability, and low power consumption, 3D packaging, which integrates multiple layers of chips into a single package structure, has become a new direction to meet technological advancements. 3D packaging boasts broad application prospects due to its high integration, lightweight, and small package size.

[0003] However, the performance of the current packaging structure still needs to be improved. Summary of the Invention

[0004] This disclosure provides a packaging structure and a manufacturing method thereof, which at least helps to improve the performance of the packaging structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a packaging structure, the packaging structure including: a chip stack, including a first sub-stack and a second sub-stack; the first sub-stack includes two layers of chips disposed back-to-back, and a first fill layer is provided between the two layers of chips in the first sub-stack; the second sub-stack includes two layers of chips disposed front-to-front or front-to-back; a second fill layer is provided between the two layers of chips in the second sub-stack, and the first fill layer and the second fill layer are made of different materials.

[0006] According to some embodiments of this disclosure, another aspect of this disclosure also provides a method for manufacturing a packaging structure. The method includes: stacking multiple chips to form a chip stack; wherein two adjacent layers of chips with their back sides facing each other constitute a first sub-stack; a first filler layer is disposed between the two layers of chips in the first sub-stack; two adjacent layers of chips with their front sides facing each other or with their front sides facing each other constitute a second sub-stack; a second filler layer is disposed between the two layers of chips in the second sub-stack; and the first filler layer and the second filler layer are made of different materials.

[0007] The technical solutions provided in this disclosure have at least the following advantages:

[0008] A first filler layer is placed between two back-to-back chips, and a second filler layer is placed between front-to-front or front-to-back chips. The first and second filler layers can be made of different materials, which can make the characteristics of different chip surfaces and filler layers more compatible, thereby improving the performance of the packaging structure. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0010] Figures 1-2 Cross-sectional views of two packaging structures related to the technology are shown.

[0011] Figures 3-6 Cross-sectional views of different packaging structures provided in the embodiments of this disclosure are shown respectively.

[0012] Figures 7-12 The diagrams show the structural schematics corresponding to each step in the manufacturing method of the packaging structure provided in the embodiments of this disclosure. Detailed Implementation

[0013] As the background technology indicates, the manufacturing cost of packaging structures is relatively high, and their performance needs further improvement. This will be analyzed and explained below. (References) Figures 1-2 A filler layer is provided between adjacent chips 100 to serve to bond the chips 100 and buffer stress. For example, see reference... Figure 1 A first fill layer 200 is provided between adjacent chips 100, as shown in the reference. Figure 2 A second filler layer 300 is provided between adjacent chips 100. To standardize the process, chip stacks typically use only filler layers of the same material, and the multiple chips 100 in the chip stack have the same orientation, that is, adjacent chips 100 are bonded from front 110 to back 120. However, filler layers of the same material are difficult to match with different bonding methods of chips, thus affecting the performance of the package structure.

[0014] This disclosure provides a packaging structure in which adjacent chips have different bonding methods. For two layers of chips bonded back-to-back, a first filler layer is used; for two layers of chips bonded front-to-front or front-to-back, a second filler layer is used. The materials of the first and second filler layers are different. This allows for matching different chip bonding methods, thereby ensuring the performance of the packaging structure.

[0015] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0016] like Figures 3-6 As shown, one embodiment of this disclosure provides a packaging structure, which includes: a chip stack 10, including a first sub-stack 1a and a second sub-stack 1b; the first sub-stack 1a includes two layers of chips 1 disposed on opposite back sides 12, and a first filler layer 3 is provided between the two layers of chips 1 in the first sub-stack 1a; the second sub-stack 1b includes two layers of chips 1 disposed on opposite front sides 11 or opposite front sides 11; a second filler layer 2 is provided between the two layers of chips 1 in the second sub-stack 1b, and the first filler layer 3 and the second filler layer 2 are made of different materials.

[0017] In other words, the chip stack 10 includes multiple layers of chips 1 stacked together. Depending on the bonding type of adjacent chip layers 1, adjacent chip layers 1 are defined as either a first sub-stack 1a or a second sub-stack 1b, and different fill layers are provided for different bonding types. It should be noted that the front side 11 of the chip 1 can be understood as the active surface, and the back side 12 of the chip 1 can be understood as the side opposite to the active surface. The active surface has conductive structures such as circuit layers 13 and signal ports. It is worth noting that in... Figures 3-6 In the diagram, the black filler strip on the surface of chip 1 is used to indicate the circuit layer 13, representing that side as the front side 11, and the side without the black filler strip represents that side as the back side 12.

[0018] refer to Figures 3-4 In some embodiments, the chip stack 10 includes multiple second sub-stacks 1b, and the two layers of chips 1 on each of the multiple second sub-stacks 1b are arranged front-side 11 to front-side 11. That is, within the chip stack 10, there are only two bonding types: one is back-side 12 to back-side 12, and the other is front-side 11 to front-side 11. Reducing the bonding types of the chip stack 10 is beneficial for standardizing the manufacturing process and also for reducing the number of second filler layers 2, thereby reducing production costs.

[0019] In other embodiments, the bonding type of the chips 1 of the plurality of second sub-stacks 1b may also be different. For example, refer to Figures 5-6 Some of the second sub-stacking bodies 1b are configured with front side 11 to back side 12, and some of the second sub-stacking bodies 1b are configured with front side 11 to front side 11. That is to say, within the chip stack 10, there are three bonding types: back side 12 to back side 12, front side 11 to front side 11, and front side 11 to back side 12.

[0020] refer to Figures 3-6 Adjacent chips 1 have an interconnect structure 60, and chip 1 may also have a through-silicon via 61 electrically connected to the interconnect structure 60, so as to realize signal transmission of the chip stack 10 in the stacking direction.

[0021] In some embodiments, reference Figure 3 , Figure 5 and Figure 6 The interconnect structures 60 in the first sub-stack 1a and the second sub-stack 1b are identical, and each interconnect structure 60 includes a solder layer 63 and solder pads 62 located on the upper and lower sides of the solder layer 63, respectively. Two adjacent chip layers 1 are defined as a lower chip and an upper chip stacked together. One solder pad 62 and one solder layer 63 can form a bump structure and be formed on the lower surface of the upper chip, while another solder pad 62 can be formed on the upper surface of the lower chip. The solder layer 63 can be made of tin or silver, and the solder pad 62 can be made of copper.

[0022] In other embodiments, reference is made to Figure 4 The interconnect structure 60 in the first sub-stacking assembly 1a may differ from the interconnect structure 60 in the second sub-stacking assembly 1b. For example, the interconnect structure 60 in the first sub-stacking assembly 1a includes a solder layer 63 and two pads 62 located on the upper and lower sides of the solder layer 63. The interconnect structure 60 in the second sub-stacking assembly 1b includes two stacked and electrically connected solder layers 63 and two pads 62. One pad 62 and a solder layer 63 form a bump structure and are formed on the lower surface of the upper chip, while the other pad 62 and the other solder layer 63 can form a bump structure and are formed on the upper surface of the lower chip. When the two chip layers 1 are bonded, since the bonding is between solder layers 63, the intermetallic compound (IMC) generated at the bonding site is reduced, and the electrical performance of the bonding site can be improved. It should be noted that, since the number of solder layers 63 in the interconnect structure 60 of the second sub-stack 1b is greater, the distance between the two chip layers 1 of the second sub-stack 1b is greater than the distance between the two chip layers 1 of the first sub-stack 1a, and the thickness of the second fill layer 2 is greater than the thickness of the first fill layer 3.

[0023] Continue to refer to Figures 3-6 The first filling layer 3 will be described in detail below.

[0024] The material of the first filler layer 3 can be a molded underfill (MUF). The molded underfill is normally a liquid with rapid flow characteristics, allowing it to quickly penetrate the surface of the interconnect structure 60. At high temperatures, its viscosity first decreases and then increases, and it solidifies rapidly. After solidification, the first filler layer 3 can mitigate temperature shocks and absorb internal stress, thereby enhancing the interaction between chips 1 and significantly improving interconnect reliability and the strength of the package structure. In other words, the first filler layer 3 can reduce the impact of external forces such as vibration and drops, as well as thermal stress, on the interconnect structure 60, preventing breakage. Furthermore, the first filler layer 3 can protect the interconnect structure 60 from damage caused by moisture, atmosphere, or contamination in the environment, thus improving the lifespan of the package structure.

[0025] For example, the first filler layer 3 can be an epoxy resin underfill layer. The material of the first filler layer 3 may include an organic adhesive, filler particles, a curing agent, a catalyst, a coupling agent, a wetting agent, a flame retardant, a defoamer, and other additives. The organic adhesive may be bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenolic linear epoxy resin, or o-cresol linear epoxy resin, etc. The organic adhesive acts as a carrier for the filler particles and provides adhesive and mechanical properties. Furthermore, the catalyst can promote the crosslinking reaction, reduce curing time, and improve production efficiency. The curing agent is used to cure the reaction to generate a thermosetting compound with a three-dimensional network structure. The coupling agent can promote the connection between the first filler layer 3 and the surface of the chip 1, improving the adhesive strength between the first filler layer 3 and the surface of the chip 1. The wetting agent can enhance the film-forming properties between the first filler layer 3 and the chip 1, reducing the surface tension of the first filler layer 3 on the chip 1. The defoamer can remove air bubbles in the first filler layer 3, reducing voids and bubbles generated during filling, and improving the adhesive strength and thermal stability between the first filler layer 3 and the chip 1.

[0026] The filler particles can be beryllium oxide, aluminum oxide, aluminum nitride, silicon carbide, or silicon dioxide, etc. These filler particles can reduce the coefficient of thermal expansion of the first filler layer 3 and change the material modulus. The filler particles can also improve the thermal conductivity of the first filler layer 3. The filler particles in the bottom molded filler layer are relatively large, ranging from 1µm to 5µm, thus providing good heat dissipation.

[0027] In some embodiments, the packaging structure further includes a packaging layer 4, which covers at least the sidewalls and top surface of the chip stack 10. The packaging layer 4 can protect the chip stack 10 from external environmental influences, such as resisting external moisture and solvents, and also resisting thermal shock and mechanical vibration during packaging assembly. For example, the material of the packaging layer 4 is the same as the material of the first filler layer 3, thereby increasing the bonding strength between the packaging layer 4 and the first filler layer 3 to enhance the protection of the chip stack 10.

[0028] For example, the encapsulation layer 4 and the first filler layer 3 are formed using the same filling process. This simplifies the manufacturing process and reduces production costs. For instance, the encapsulation layer 4 and the first filler layer 3 can be an integral structure, meaning that the encapsulation layer 4 and the first filler layer 3 are not only made of the same material but are also connected, forming a single unit. In other embodiments, the encapsulation layer 4 and the first filler layer 3 may not be an integral structure, and they may be made of different materials.

[0029] In some embodiments, the packaging structure further includes a substrate 5, on which the chip stack 10 is disposed, and the packaging layer 4 may also cover the upper surface of the substrate 5. A filler layer is also provided between the bottommost chip 1 and the substrate 5. This filler layer can also reduce thermal stress mismatch caused by the difference in thermal expansion coefficients between the chip 1 and the substrate 5, preventing warping of the chip 1 and the substrate 5.

[0030] For example, when the back side 12 of the bottom chip 1 in the chip stack 10 faces the substrate 5, the filling layer between the chip 1 and the substrate 5 can be a first filling layer 3. That is, the first filling layer 3 here does not cover the front side of the chip 1. In addition, the first filling layer 3 between the bottom chip 1 and the substrate 5 can be an integral structure with the encapsulation layer 4, which helps to simplify the manufacturing process. In other embodiments, the first filling layer 3 between the bottom chip 1 and the substrate 5 and the encapsulation layer 4 may not be an integral structure, that is, the two are independent film layers.

[0031] In other embodiments, when the front side 11 of the bottom chip 1 of the chip stack 10 faces the substrate 5, the filling layer between the chip 1 and the substrate 5 may also be a non-conductive film layer.

[0032] For example, the substrate 5 can be an interposer, the bottommost chip 1 of the chip stack 10 is a logic chip, and the remaining chips 1 are memory chips. Alternatively, the substrate 5 can be a logic chip, and the multiple chips 1 of the chip stack 10 are all memory chips.

[0033] The second filling layer 2 will be described in detail below.

[0034] In some embodiments, the second filler layer 2 is formed using a different filler process than the encapsulation layer 4 and the first filler layer 3. This allows the material of the second filler layer 2 to differ from the materials of the encapsulation layer 4 and the first filler layer 3, thereby better matching different bonding methods of the chip 1. For example, the materials of the first filler layer 3 and the encapsulation layer 4 can be molded bottom filler layers, and the material of the second filler layer 2 can be a non-conductive film (NCF). The filler process will be described in detail later in conjunction with the manufacturing method.

[0035] Non-conductive films are normally solid films. After being adhered to the chip surface, they soften at high temperatures, thus providing filling and support. The filling particles in non-conductive films are small, typically below 1µm. These small particles are less likely to damage the front side 11 of chip 1. When the size ratio of the filling particles in the first filling layer 3 to the second filling layer 2 is within the aforementioned range, it better protects the front side 11 of chip 1 while ensuring effective filling and reducing bubble formation.

[0036] In some embodiments, the non-conductive film layer may be composed of a matrix adhesive, a diluent, a toughening agent, and other additives. The matrix adhesive mainly includes epoxy resin, phenolic resin, polyimide, and thermoplastic plastics; the diluent typically includes alcohols, esters, etc.; and the toughening agent includes non-reactive toughening agents such as low-molecular-weight liquid modifiers.

[0037] In other embodiments, the material of the second filler layer 2 may also include a molded bottom filler layer, wherein the size of the filler particles therein is smaller than the size of the filler particles in the first filler layer 3, thereby avoiding damage to the front side of the chip 1.

[0038] In some embodiments, the thickness of the second filler layer 2 is greater than the thickness of the first filler layer 3. That is, the spacing between the two chip layers 1 of the second sub-stack 1b can be greater than the spacing between the two chip layers 1 of the first sub-stack 1a. This design is because the two chip layers 1 of the second sub-stack 1b are arranged with their front sides 11 facing each other or with their back sides 12. The front side 11 generates a large amount of heat, and the thicker second filler layer 2 can provide more sufficient heat dissipation space for the front side of the chip 1. Furthermore, the thicker second filler layer 2 can provide greater dispersion space for the filler particles, thereby enhancing the heat dissipation effect of the front side 11 of the chip 1. In other embodiments, the thickness of the second filler layer 2 can also be equal to the thickness of the first filler layer 3, thereby improving the uniformity of the packaging structure and simplifying the manufacturing process.

[0039] In some embodiments, the filler particle content of the second filler layer 2 may be less than the filler content of the first filler layer 3. This prevents the filler particles of the second filler layer 2 from damaging the front surface 11 of the chip 1, thus ensuring the performance of the chip 1. For example, the content ratio of the second filler layer 2 to the first filler layer 3 can be 1:2 to 7:8. When the content ratio is within the above range, it helps to reduce the risk of damage to the front surface 11 of the chip 1.

[0040] Because the filler particles in the first filling layer 3 are larger, the overall heat dissipation effect of the first filling layer 3 is usually better than that of the second filling layer 2. For example, the heat dissipation rate of the first filling layer 3 is twice that of the second filling layer 2. To balance the heat dissipation effect, filler particles with higher thermal conductivity can be placed in the second filling layer 2 to transfer the heat from the front side 11 of the chip 1 to the outside in a timely manner, thereby avoiding the problem of heat accumulation. For example, the filler particles in the second filling layer 2 can be made of ceramic materials with high thermal conductivity, such as boron nitride, aluminum nitride, alumina, and silicon carbide. The filler particles in the first filling layer 3 can be made of silicon oxide.

[0041] In some embodiments, reference Figures 3-5 The second filling layer 2 can be a single-layer structure, which reduces the difficulty of manufacturing. In other embodiments, refer to... Figure 6 The second filling layer 2 can also be a double-layer structure.

[0042] Continue to refer to Figure 6 In the case where the second sub-stack 1b includes two layers of chips 1, front 11 and back 12: the second filling layer 2 includes a front filling sub-layer 21 and a back filling sub-layer 22 stacked together.

[0043] The front filler layer 21 does not contain filler particles, while the back filler layer 22 contains filler particles. The front filler layer 21 covers the front side 11 of one chip 1, and the back filler layer 22 covers the back side 12 of another chip 1. In other words, the second filler layer 2 can be formed using a double-layer bottom filler process. The front filler layer 21 without filler particles can prevent damage to the front side 11 of the chip 1, while the back filler layer 22 containing filler particles can ensure that the second filler layer 2 has a low coefficient of thermal expansion.

[0044] In summary, the embodiments of this disclosure adjust the orientation of chip 1, with two layers of chip 1 on the back side 12 forming a first sub-stack 1a, and two layers of chip 1 on the front side 11 or on the back side 12 forming a second sub-stack 1b. Filler layers of different materials are provided in the first sub-stack 1a and the second stack 1b to reduce production costs while avoiding damage to the front side 11 of chip 1 from larger filler particles.

[0045] like Figures 7-12 as well as Figure 3 As shown, another embodiment of this disclosure provides a method for manufacturing a packaging structure. The manufacturing method of the packaging structure provided in this application embodiment will be described in detail below with reference to the accompanying drawings. This manufacturing method can manufacture the packaging structure provided in the foregoing embodiments. For a detailed description of this packaging structure, please refer to the detailed description of the foregoing embodiments, which will not be repeated here.

[0046] The manufacturing method includes: stacking multiple chips 1 to form a chip stack 10; wherein, two adjacent layers of chips 1 on the back side 12 form a first sub-stack 1a, and a first filling layer 3 is disposed between the two layers of chips 1 in the first sub-stack 1a; two adjacent layers of chips 1 on the front side 11 or on the back side 12 form a second sub-stack 1b; and a second filling layer 2 is disposed between the two layers of chips 1 in the second sub-stack 1b, wherein the material of the second filling layer 2 is different from the material of the first filling layer 3.

[0047] The steps of “setting a second filling layer 2 between the two layers of chips 1 in the second sub-stack 1b” will be described in detail below.

[0048] refer to Figures 7-8 Two chips 1 are provided. For example, one chip 1 has its front face 11 facing down; this chip 1 serves as the upper layer chip. The other chip 1 has its front face 11 facing up; this chip 1 serves as the lower layer chip. (See reference) Figure 9 A non-conductive film layer is attached to the front side 11 of a chip 1, for example, to the lower surface of an upper chip. This non-conductive film layer also covers the solder layer 63 and pads 62 on the lower surface of the upper chip. (See reference.) Figure 10 The front side 11 or back side 12 of another chip 1 is positioned facing the non-conductive film layer, and the two chip layers 1 are bonded together to form a second sub-stack 1b. For example, the upper chip is placed on the lower chip, and the two are thermo-bonded. The non-conductive film layer serves as the second filler layer 2.

[0049] In other words, the wafer can be diced first to obtain discrete chips 1, and then a non-conductive film layer can be attached to the front side 11 of the chip 1. In other embodiments, a non-conductive film layer can be laminated on the surface of the wafer first, and then the wafer can be diced and the non-conductive film layer can be cut, thus forming discrete chips 1. Then, chip 1 is picked up, and the side of chip 1 with the non-conductive film layer attached is positioned facing another chip 1, and the two chips 1 are then bonded. Since the process of attaching the non-conductive film layer is wafer-level, the production efficiency is higher and the process is better controlled.

[0050] In other embodiments, a molded underfill layer is applied to the front side 11 of one chip 1 as a second filler layer 2, and another chip 1 is positioned facing the molded underfill layer. The two chips 1 are then thermocompressed and bonded. Thus, the second filler layer 2 can be formed first, and then the two chip layers 1 can be bonded. The second filler layer 2 can be cured during the bonding process. Since the bonding process and the curing of the second filler layer 2 are completed in the same process, production efficiency is higher.

[0051] In other embodiments, the two chips 1 can be bonded together first, and then a second filler layer 2 can be filled between them. The second filler layer 2 can fill the gap between the two chips 1 by capillary force. After that, the second filler layer 2 is heated and cured.

[0052] In some embodiments, the second filling layer 2 can be a single-layer structure, thereby reducing production costs and simplifying the manufacturing process. In other embodiments, when the second sub-stack 1b includes two layers of chips 1, front 11 and back 12, the second filling layer 2 can also be a double-layer structure.

[0053] The manufacturing method of the second sub-stack 1b and the second filling layer 2 of the double-layer structure will be described below. (Reference) Figure 11 First, a chip 1 is positioned with its front side 11 facing upwards; this chip 1 serves as the lower layer chip. A front filler layer 21, which does not contain filler particles, is first coated onto the front side 11 of the lower layer chip. A back filler layer 22, containing filler particles, is then drop-coated onto the upper surface of the front filler layer 21. The back filler layer 22 and the front filler layer 21 together constitute the second filler layer 2. (Reference) Figure 12 Another chip 1 is placed on the aforementioned lower chip as the upper chip and bonded. The front filler sublayer 21 covers the front side 11 of the lower chip to prevent the front side 11 of the lower chip from being damaged by filler particles, while the back filler sublayer 22 covers the back side 12 of the upper chip. The filler particles contained therein can ensure that the second filler layer 2 has a low coefficient of thermal expansion.

[0054] It should be noted that during the lamination process between the upper and lower chips, the second filler layer 2 flows due to compression. Compared to the single-layer structure of the second filler layer 2, the filler particles in the back filler sublayer 22 of the double-layer structure are less likely to remain on the bonding surface between the solder layer 63 and the pad 62. This ensures the conductivity and current carrying capacity of the interconnects and improves the reliability of the package structure under thermal cycling.

[0055] Furthermore, the viscosity of the back filler layer 22 can be lower than that of the front filler layer 21. The lower the viscosity, the better the wettability of the material and the faster the flow rate. Therefore, in order to ensure that the back filler layer 22 flows rapidly between adjacent interconnect structures 60 and to prevent filler particles of the back filler layer 22 from remaining at the solder interface between the solder layer 63 and the solder pad 62, the viscosity of the back filler layer 22 can be reduced.

[0056] The method for forming the first filling layer 3 will be described in detail below.

[0057] refer to Figure 3 In some embodiments, the chip stack 10 includes a plurality of first sub-stacks 1a, in which a first filler layer 3 is formed. For example, a molding process is used to form the first filler layer 3. The molding process has high throughput and low production cost. In some embodiments, multiple layers of the first filler layer 3 can be formed in the same process step to improve production efficiency. That is, the first filler layer 3 can be formed after all chips 1 are stacked and bonded.

[0058] In other embodiments, the first filler layer 3 may be formed before the formation of the first sub-stack 1a. For example, the first filler layer 3 is applied to the back surface 12 of one chip 1, and the back surface 12 of another chip 1 is positioned facing the first filler layer 3. The two chips 1 are then bonded to form the first sub-stack 1a, and the curing process of the first filler layer 3 is completed. Thus, it can be seen that multiple layers of the first filler layer 3 can also be formed by multiple process steps.

[0059] Continue to refer to Figure 3 The manufacturing method of the package structure further includes forming a package layer 4 covering the sidewalls and top surface of the chip stack 10. In some embodiments, the package layer 4 and the first filler layer 3 can be formed in the same process step to reduce production costs.

[0060] Specifically, the steps of forming the encapsulation layer 4 and the first filler layer 3 include: forming an initial molded bottom filler layer 34 covering the sidewalls and top surface of the chip stack 10 and filling between adjacent chips 1 using the same molding process. The initial molded bottom filler layer 34 covering the sidewalls and top surface of the chip stack 10 serves as the encapsulation layer 4, and the initial molded bottom filler layer 34 filling between adjacent chips 1 of the first sub-stack 1a serves as the first filler layer 3. For example, the chip stack 10 is placed in a mold, and the initial molded bottom filler layer 34 is injected into the mold so that the initial molded bottom filler layer 34 encapsulates the chip stack 10. Since the bottom filling and secondary molding encapsulation of the first sub-stack 1a are completed in one process step, costs can be reduced and production efficiency improved. In other words, the first filler layer 3 and the encapsulation layer 4 can be an integral structure, thereby improving the mechanical stability of the encapsulation structure and the reliability of the encapsulation.

[0061] Continue to refer to Figure 3 In some embodiments, the packaging structure further includes a substrate 5, and the initial molding bottom fill layer 34 can also fill the space between the substrate 5 and the chip 1, serving as a first fill layer 3 between them. Multiple chips 1 can be stacked sequentially on the substrate 5 according to a preset orientation to form a chip stack 10.

[0062] In the molding process, the content of filler particles in the initial mold bottom can be increased to reduce the coefficient of thermal expansion and improve the device's resistance to thermal fatigue. Due to the higher filler particle content, pressure treatment can be applied to promote the flow of the filler material layer and prevent air bubble formation. Molding is effective at filling small gaps, which is beneficial for miniaturizing and multifunctionalizing packaging structures.

[0063] It should be noted that in some embodiments, a thermocompression process is performed after each chip 1 is stacked to complete the bonding between chips 1. In other embodiments, the entire chip stack 10 can be bonded after all chips 1 have been stacked. That is, thermocompression bonding includes two steps: the first step is pre-bonding, which mainly realizes the picking and stacking of chips 1; the second step is main bonding, which completes the bonding of multiple chips 1 on the substrate 5 through a single thermocompression process.

[0064] To more clearly illustrate the manufacturing method of the packaging structure, the entire process of the manufacturing method will be illustrated below, but the embodiments disclosed herein are not limited to this example.

[0065] refer to Figure 10 A substrate 5 and a plurality of chips 1 are provided, wherein some chips 1 are disposed with their front faces 11 facing down, and some chips 1 are disposed with their front faces 11 facing up. A non-conductive film layer is attached to the chips 1 disposed with their front faces 11 facing down as a second filler layer 2. The chips 1 are sequentially stacked on the substrate 5 in the order of front faces 11 up and front faces 11 down to form a chip stack 10. Thereafter, the entire chip stack 10 is thermo-bonded. Then, refer to... Figure 3 An initial molded bottom fill layer 34 is formed using a molding process. The initial molded bottom fill layer 34 located between adjacent chips 1 and covering the back surface 12 of chip 1 serves as the first fill layer 3, and the initial molded bottom fill layer 34 covering the sidewalls and upper surface of the chip stack 10 serves as the encapsulation layer 4.

[0066] In summary, the embodiments of this disclosure adjust the orientation of the chips 1 during the chip 1 stacking process so that at least some chips 1 are arranged back-to-back. Different filling layers are formed between the two chip layers using different relative arrangements. Therefore, while protecting the front side 11 of the chips 1, production costs can be reduced and production efficiency improved.

[0067] This disclosure also provides a memory that may include the packaging structure provided in the foregoing embodiments. For a detailed description of this packaging structure, please refer to the detailed description of the foregoing embodiments, which will not be repeated here.

[0068] The memory can be high-bandwidth memory (HBM), and the chips within the package structure include memory chips, such as dynamic random access memory (DRAM). For example, the multiple layers of chips 1 in the chip stack 10 are all memory chips; or, the chip stack 10 also includes logic chips, with the multiple layers of memory chips stacked on top of the logic chips. The package structure also includes a substrate 5, on which the chip stack 10 is formed. The substrate 5 can be an interposer; or, the substrate 5 can be a logic chip, and the multiple layers of chips 1 in the chip stack 10 are all memory chips.

[0069] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0070] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and description of the present disclosure should fall within the scope of the patent coverage of the present disclosure.

Claims

1. A package structure, characterized by, include: A chip stack includes a first sub-stack and a second sub-stack; The first sub-stack includes two layers of chips disposed back-to-back, and a first fill layer is provided between the back sides of the two layers of chips in the first sub-stack; The second sub-stack includes two layers of chips arranged face to face; a second filling layer is provided between the front faces of the two layers of chips in the second sub-stack, the first filling layer and the second filling layer are made of different materials, and the second filling layer is a non-conductive film layer attached to the front face of the chip; A substrate, wherein the chip stack is disposed on the substrate, the back side of the bottom chip of the chip stack faces the substrate, and the bottom chip and the substrate have a first filling layer between them; An encapsulation layer, at least covering the sidewalls of the chip stack, is made of the same material as the first filler layer, and the encapsulation layer and the first filler layer are formed using the same filling process.

2. The package structure of claim 1, wherein, include: The chip stack includes multiple second sub-stacks, and the chips in the two layers of the multiple second sub-stacks are arranged face to face.

3. The package structure of claim 1 or 2, wherein, Also includes: An encapsulation layer, at least covering the sidewalls of the chip stack, and the material of the encapsulation layer is the same as the material of the first filler layer.

4. The package structure of claim 1, wherein, The second filler layer is formed using a different filling process than the encapsulation layer and the first filler layer.

5. The package structure of claim 1, wherein, The thickness of the second filler layer is greater than or equal to the thickness of the first filler layer.

6. The package structure of claim 5, wherein, The chip stack also includes interconnect structures located between adjacent chips; the interconnect structures in the first sub-stack include at least one solder layer, and the interconnect structures in the second sub-stack include at least two stacked and electrically connected solder layers.

7. The package structure of claim 1, wherein, The material of the first filler layer includes a molded bottom filler layer, and the size of the filler particles in the second filler layer is smaller than the size of the filler particles in the first filler layer.

8. The package structure of claim 1, wherein, In the case where the second sub-stack comprises two layers of chips facing each other: the second filling layer comprises a front filling sub-layer and a back filling sub-layer stacked together; The front filler layer does not contain filler particles, while the back filler layer contains filler particles; the front filler layer covers the front side of one of the chips, and the back filler layer covers the back side of another chip.

9. A method of manufacturing a package structure, characterized by, include: Multiple chips are stacked together to form a chip stack. A substrate is provided, and the chip stack is disposed on the substrate, with the back side of the bottom chip of the chip stack facing the substrate; In this structure, two adjacent layers of chips arranged back-to-back form a first sub-stack, and a first filling layer is provided between the back sides of the two layers of chips in the first sub-stack. The first filling layer is provided between the back side of the bottommost chip in the chip stack and the substrate. The two adjacent layers of the chips arranged face-to-face constitute a second sub-stack; a second filling layer is arranged between the two layers of the chips of the second sub-stack, the first filling layer and the second filling layer are made of different materials, and the second filling layer is a non-conductive film layer attached to the front surface of the chip; A packaging layer covering the sidewall of the chip stack is formed, the packaging layer and the first filling layer are formed by the same filling process, the second filling layer is formed by a filling process different from that of the packaging layer and the first filling layer, and the filling process for forming the second filling layer is prior to the filling process for forming the first filling layer.

10. The manufacturing method according to claim 9, wherein The step of arranging the second filling layer between the front surfaces of the two layers of the chips of the second sub-stack comprises: Two chips are provided, a non-conductive film layer is attached to the front surface of one chip, the front surface of another chip is arranged towards the non-conductive film layer, and the two layers of the chips are bonded to form the second sub-stack; the non-conductive film layer serves as the second filling layer.

11. The manufacturing method according to claim 9, wherein The first filling layer is formed by a molding process.

12. The manufacturing method according to claim 9, wherein The steps of forming the packaging layer and the first filling layer comprise: forming an initial molding bottom filling layer covering the sidewall of the chip stack, filled between adjacent chips and between the bottommost chip and the substrate by the same molding process; wherein the initial molding bottom filling layer covering the sidewall of the chip stack serves as the packaging layer, and the initial molding bottom filling layer filled between the adjacent chips of the first sub-stack serves as the first filling layer.

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