Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel, wherein the array substrate includes a substrate and a first conductive layer, a second conductive layer, a first insulating layer, and an oxide active layer arranged on the substrate, the first conductive layer includes a source electrode and a light-shielding electrode arranged at intervals, the second conductive layer includes a blocking electrode connected to the source electrode, the first insulating layer includes a first via hole arranged corresponding to the source electrode, the oxide active layer includes a channel portion and a source contact portion located on one side of the channel portion, part of the source contact portion is arranged in the first via hole and connected to the blocking electrode, the blocking electrode is connected between the source contact portion and the source, and is arranged corresponding to the first via hole to prevent the source contact portion from directly contacting the source electrode, and the blocking electrode can block the metal elements in the source electrode from diffusing to the source contact portion, so as to prevent the metal elements in the source electrode from diffusing into the oxide active layer to form deep energy level impurities, thereby causing device performance degradation and affecting device characteristics and bias temperature stress characteristics.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In the field of display technology, thin film transistor (TFT) array substrates are an important component of display panels, and the manufacture of TFT array substrates involves the use of multiple photomasks. The more photomasks used, the longer the overall process flow of the TFT array substrate, the greater the difficulty and the higher the cost. In order to reduce the number of photomasks used, the source electrode of the TFT can be set below the oxide active layer, and the oxide active layer can be overlapped with the source electrode below. However, this overlapping method will cause the performance of the TFT device to degrade, affecting the device characteristics and bias temperature stress (BTS) characteristics. Summary of the Invention

[0003] The present application provides an array substrate and a display panel to alleviate the technical problem of performance degradation of thin film transistor devices caused by the existing overlapping method of oxide active layer and source electrode.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] An embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] A first conductive layer is provided on one side of the substrate, wherein the first conductive layer includes a source electrode and a light-shielding electrode that are spaced apart;

[0008] a second conductive layer, disposed on a side of the first conductive layer away from the substrate, the second conductive layer comprising a blocking electrode connected to the source electrode;

[0009] a first insulating layer, disposed on a side of the first conductive layer away from the substrate, the first insulating layer comprising a first via hole disposed corresponding to the source;

[0010] an oxide active layer, disposed on a side of the first insulating layer away from the substrate, the oxide active layer including a channel portion and a source contact portion located on one side of the channel portion, wherein in a thickness direction of the array substrate, the channel portion is disposed corresponding to the light-shielding electrode, a portion of the source contact portion is disposed in the first via hole and connected to the blocking electrode, the blocking electrode being connected between the source contact portion and the source electrode and disposed corresponding to the first via hole, the blocking electrode being configured to prevent metal elements in the source electrode from diffusing toward the source contact portion;

[0011] a second insulating layer, disposed on a side of the oxide active layer away from the substrate, the second insulating layer being disposed corresponding to the channel portion;

[0012] The third conductive layer is arranged on a side of the second insulating layer away from the substrate, and the third conductive layer includes a gate arranged corresponding to the channel portion.

[0013] In the array substrate provided in an embodiment of the present application, the blocking electrode covers the surface of the source electrode away from the substrate, the first insulating layer covers part of the blocking electrode, and the first insulating layer is provided with the first via hole at the position corresponding to the blocking electrode, and the source contact portion is connected to the blocking electrode exposed by the first via hole.

[0014] In the array substrate provided in the embodiment of the present application, the orthographic projection of the blocking electrode on the substrate coincides with the orthographic projection of the source electrode on the substrate.

[0015] In the array substrate provided in an embodiment of the present application, the second conductive layer also includes an auxiliary electrode arranged corresponding to the light-shielding electrode, and the auxiliary electrode covers the surface of the light-shielding electrode away from the substrate. The first insulating layer also covers the auxiliary electrode and the gap between the light-shielding electrode and the source electrode.

[0016] In the array substrate provided in an embodiment of the present application, the first insulating layer covers part of the source, the light-shielding electrode, and the gap between the light-shielding electrode and the source, the first via hole exposes part of the source, the blocking electrode is located in the first via hole and is connected to the source exposed by the first via hole, and the source contact portion covers the blocking electrode in the first via hole.

[0017] In the array substrate provided in the embodiment of the present application, the blocking electrode extends from the first via hole to the surface of the first insulating layer away from the substrate, and the source contact portion also covers the blocking electrode located outside the first via hole.

[0018] In the array substrate provided in the embodiment of the present application, the orthographic projection of the opening of the first via hole close to the source electrode on the substrate is located within the range of the orthographic projection of the blocking electrode on the substrate.

[0019] In the array substrate provided in the embodiment of the present application, the thickness of the second conductive layer ranges from 100 angstroms to 800 angstroms.

[0020] In the array substrate provided in the embodiment of the present application, the material of the second conductive layer includes one of molybdenum, titanium, molybdenum-titanium alloy, and indium tin oxide.

[0021] In the array substrate provided in an embodiment of the present application, the first conductive layer includes a bonding layer and a main conductive layer located on the side of the bonding layer away from the substrate, the material of the bonding layer includes one of molybdenum, titanium, and molybdenum-titanium alloy, and the material of the main conductive layer includes copper.

[0022] In the array substrate provided in the embodiment of the present application, the array substrate further includes:

[0023] a third insulating layer, disposed on a side of the third conductive layer away from the substrate;

[0024] a planarization layer, disposed on a side of the third insulating layer away from the substrate;

[0025] a common electrode, disposed on a side of the planarization layer away from the substrate;

[0026] a fourth insulating layer disposed on a side of the common electrode away from the substrate, the oxide active layer further comprising a drain contact portion located on a side of the channel portion away from the source contact portion, and the fourth insulating layer comprising a second via hole disposed corresponding to the drain contact portion;

[0027] A pixel electrode is provided on a side of the fourth insulating layer away from the substrate, and a portion of the pixel electrode is located in the second via hole and connected to the drain contact portion.

[0028] An embodiment of the present application further provides a display panel, which includes the array substrate of one of the aforementioned embodiments.

[0029] The beneficial effects of the present application are as follows: in the array substrate and display panel provided by the present application, the array substrate includes a substrate and a first conductive layer, a second conductive layer, a first insulating layer, and an oxide active layer arranged on the substrate, the first conductive layer includes a source electrode, the second conductive layer includes a blocking electrode connected to the source electrode, the first insulating layer includes a first via hole arranged corresponding to the source electrode, a part of the source contact portion of the oxide active layer is arranged in the first via hole and connected to the blocking electrode, the blocking electrode is connected between the source contact portion and the source electrode, and is arranged corresponding to the first via hole to avoid direct contact between the source contact portion and the source electrode, and the blocking electrode can block the metal elements in the source electrode from diffusing to the source contact portion, so as to avoid the metal elements in the source electrode from diffusing into the oxide active layer to form deep energy level impurities, which will cause device performance degradation, affect device characteristics and bias temperature stress characteristics, and thus improve the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 As a preface to the embodiments of the present application, an array substrate is provided.

[0032] Figure 2 A schematic cross-sectional structure diagram of an array substrate provided in an embodiment of the present application.

[0033] Figure 3 This is another schematic cross-sectional structure diagram of the array substrate provided in an embodiment of the present application.

[0034] Figure 4 This is a schematic diagram of another cross-sectional structure of the array substrate provided in an embodiment of the present application.

[0035] Figure 5 This is a schematic diagram of another cross-sectional structure of the array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0037] In view of the problem that the connection between the oxide active layer and the source electrode leads to the degradation of the performance of the thin film transistor device, the inventors of this application found in their research that: Figure 1 , Figure 1 As a preface to an embodiment of the present application, an array substrate is provided, comprising a substrate 10' and a first insulating layer 11', a source electrode 21', and an oxide active layer 40' arranged on the substrate 10'. Part of the oxide active layer 40' is located in the first via hole of the first insulating layer 11' and overlaps with the source electrode 21'. The material of the source electrode 21' is copper. Compared with aluminum, copper has a lower resistivity. However, copper is easy to diffuse and can easily cause copper contamination. At the position where the oxide active layer 40' is in direct contact with the source electrode 21', the copper metal element of the source electrode 21' will diffuse into the oxide active layer 40', forming deep energy level impurities in the oxide active layer 40', resulting in degradation of the performance of the thin film transistor device, affecting the device characteristics and the bias temperature stress (BTS) characteristics.

[0038] To this end, the present application provides an array substrate and a display panel.

[0039] Please refer to Figure 2 , Figure 2 A schematic cross-sectional view of an array substrate provided in an embodiment of the present application. The array substrate 100 includes a substrate 10 and a first conductive layer 20, a second conductive layer 30, a first insulating layer 11, an oxide active layer 40, a second insulating layer 12, and a third conductive layer 50 disposed on the substrate 10. The first conductive layer 20 is disposed on one side of the substrate 10 and includes a source electrode 21 and a light-shielding electrode 22 spaced apart. The second conductive layer 30 is disposed on a side of the first conductive layer 20 away from the substrate 10 and includes a blocking electrode 31 connected to the source electrode 21. The first insulating layer 11 is disposed on a side of the first conductive layer 20 away from the substrate 10 and includes a first via 111 disposed corresponding to the source electrode 21.

[0040] The oxide active layer 40 is disposed on a side of the first insulating layer 11 away from the substrate 10. The oxide active layer 40 includes a channel portion 41 and a source contact portion 42 located on one side of the channel portion 41. In the thickness direction of the array substrate 100, the channel portion 41 is disposed correspondingly to the light shielding electrode 22. It should be noted that the term "corresponding arrangement" in this application refers to the correspondence between two structures in the thickness direction of the array substrate 100. The material of the oxide active layer can be indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium gallium oxide (IGO), indium zinc oxide (IZO), lanthanide IZO, etc.

[0041] Part of the source contact portion 42 is arranged in the first via 111 and is connected to the blocking electrode 31. The blocking electrode 31 is connected between the source contact portion 42 and the source 21 and is arranged corresponding to the first via 111, so that the source contact portion 42 is electrically connected to the source 21 through the blocking electrode 31. The blocking electrode 31 is configured to block the metal elements in the source 21 from diffusing into the source contact portion 42.

[0042] It should be noted that the connection described in this application is different from the electrical connection, where the connection refers to direct contact between two structures, while the electrical connection refers to the conduction between the two structures through other structures. For example, the connection between the source contact portion 42 and the blocking electrode 31 means that the source contact portion 42 is in direct contact with the blocking electrode 31, while the electrical connection between the source contact portion 42 and the source 21 means that the source contact portion 42 is conductively connected to the source 21 through the blocking electrode 31, but there is no direct contact between the source contact portion 42 and the source 21.

[0043] The second insulating layer 12 is disposed on a side of the oxide active layer 40 away from the substrate 10. In the thickness direction of the array substrate 100, the second insulating layer 12 is disposed corresponding to the channel portion 41. The third conductive layer 50 is disposed on a side of the second insulating layer 12 away from the substrate 10. The third conductive layer 50 includes a gate 51 disposed corresponding to the channel portion 41.

[0044] In this embodiment, the source contact portion 42 is electrically connected to the source 21 through the blocking electrode 31 to avoid direct contact between the source contact portion 42 and the source 21, and the blocking electrode 31 can block the metal elements in the source 21 from diffusing toward the source contact portion 42, so as to avoid the metal elements in the source 21 from diffusing into the oxide active layer 40 to form deep energy level impurities, which may cause device performance degradation, affect device characteristics and bias temperature stress characteristics, and thus improve device stability.

[0045] Specifically, the array substrate 100 further includes a first transistor disposed on the substrate 10. The first transistor may be a thin film transistor. The first transistor includes a source electrode 21, an oxide active layer 40, and a gate electrode 51. The oxide active layer 40 is disposed on a side of the source electrode 21 away from the substrate 10, and the gate electrode 51 is disposed on a side of the oxide active layer 40 away from the substrate 10. In other words, the oxide active layer 40 is disposed on a side of the source electrode 21 away from the substrate 10, and the gate electrode 51 is disposed on a side of the oxide active layer 40 away from the substrate 10. The oxide active layer 40 includes a channel portion 41 and a source contact portion 42 located on one side of the channel portion 41. Of course, the oxide active layer 40 also includes a drain contact portion 43 located on a side of the channel portion 41 away from the source contact portion 42. In other words, the drain contact portion 43 and the source contact portion 42 are located on opposite sides of the channel portion 41. The gate 51 is disposed opposite to the channel portion 41 , and an orthographic projection of the gate 51 on the substrate 10 coincides with an orthographic projection of the channel portion 41 on the substrate 10 .

[0046] Optionally, the substrate 10 can be a rigid substrate or a flexible substrate. When the substrate 10 is a rigid substrate, it can include a rigid substrate such as a glass substrate, a quartz substrate, or a silicon wafer. When the substrate 10 is a flexible substrate, it can include a flexible substrate such as a polyimide (PI) film or an ultra-thin glass film. When the substrate 10 is a polyimide substrate, moisture or oxygen can more easily penetrate the substrate 10 than when it is a glass substrate. To prevent this, a single-layer or multi-layer buffer layer comprising silicon oxide or silicon nitride can be provided on the substrate 10.

[0047] The first conductive layer 20 is disposed on the substrate 10. The first conductive layer 20 includes a source electrode 21 and a light-shielding electrode 22, which are spaced apart and insulated. The light-shielding electrode 22 is disposed at least in correspondence with the channel portion 41 to shield the channel portion 41 from light and reduce the photogenerated leakage current of the first transistor. The first conductive layer 20 includes a bonding layer 201 and a main conductive layer 202 located on the side of the bonding layer 201 away from the substrate 10. In other words, both the source electrode 21 and the light-shielding electrode 22 include the bonding layer 201 and the main conductive layer 202.

[0048] The thickness of the main conductive layer 202 is greater than that of the bonding layer 201. The bonding layer 201 is made of one of molybdenum, titanium, and a molybdenum-titanium alloy, while the main conductive layer 202 is made of copper. Copper has poor adhesion and is difficult to directly bond to glass substrates or silicon oxide substrates. By providing the bonding layer 201 within the first conductive layer 20, the bonding layer 201 can enhance the adhesion between the main conductive layer 202 and the substrate 10. Furthermore, the bonding layer 201 can prevent the copper metal element in the main conductive layer 202 from diffusing into the substrate 10, thereby preventing contamination of the substrate 10.

[0049] The second conductive layer 30 is disposed on a side of the first conductive layer 20 away from the substrate 10. The second conductive layer 30 is formed with a blocking electrode 31 disposed corresponding to the source 21. The blocking electrode 31 covers a surface of the source 21 away from the substrate 10.

[0050] For the convenience of description, this application defines the surface of each structure away from the substrate 10 as the upper surface, the surface opposite to the upper surface as the lower surface, and the structure connecting the upper surface and the lower surface as the sidewall. For example, the surface of the source 21 away from the substrate 10 is the upper surface of the source 21, the surface opposite to the upper surface of the source 21 is the lower surface of the source 21, the lower surface of the source 21 is in contact with the substrate 10, and the structure connecting the upper and lower surfaces of the source 21 is the sidewall of the source 21; for example, the surface of the blocking electrode 31 away from the substrate 10 is the upper surface of the blocking electrode 31, the surface opposite to the upper surface of the blocking electrode 31 is the lower surface of the blocking electrode 31, the lower surface of the blocking electrode 31 is in contact with the source 21, and the structure connecting the upper and lower surfaces of the blocking electrode 31 is the sidewall of the blocking electrode 31. The orthographic projection of the blocking electrode 31 on the substrate 10 coincides with the orthographic projection of the source electrode 21 on the substrate 10 , so that the same photomask can be used when patterning the blocking electrode 31 and the source electrode 21 , thereby reducing the number of photomasks and lowering costs.

[0051] The material of the second conductive layer 30 has properties such as diffusion properties lower than that of copper and is conductive. For example, the material of the second conductive layer 30 includes one of molybdenum, titanium, a molybdenum-titanium alloy, and indium tin oxide. The thickness of the second conductive layer 30 is less than that of the first conductive layer 20, and is also less than that of the main conductive layer 202. The thickness of the second conductive layer 30 ranges from 100 angstroms to 800 angstroms, such as 100 angstroms, 200 angstroms, 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, and 800 angstroms. When the thickness of the second conductive layer 30 is less than 100 angstroms, the blocking electrode 31 formed by the second conductive layer 30 may not effectively block the diffusion of metal elements in the source electrode 21. When the thickness of the second conductive layer 30 is greater than 800 angstroms, the conductivity of the source electrode 21 may be affected, resulting in severe topography.

[0052] Optionally, the second conductive layer 30 is provided with an auxiliary electrode 32 at a position corresponding to the light-shielding electrode 22. The auxiliary electrode 32 covers the surface of the light-shielding electrode 22 on the side away from the substrate 10 to prevent the metal elements in the light-shielding electrode 22 from diffusing into the first insulating layer 11. The orthographic projection of the auxiliary electrode 32 on the substrate 10 coincides with the orthographic projection of the light-shielding electrode 22 on the substrate 10, so that the same mask can be used when patterning the auxiliary electrode 32 and the light-shielding electrode 22, thereby reducing the number of masks and lowering costs.

[0053] The first insulating layer 11 covers the second conductive layer 30 and the substrate 10. Specifically, the first insulating layer 11 covers the top surface and sidewalls of the blocking electrode 31, the sidewalls of the source electrode 21, the top surface and sidewalls of the auxiliary electrode 32, the sidewalls of the light-shielding electrode 22, the gap between the light-shielding electrode 22 and the source electrode 21, and the substrate 10. The first insulating layer 11 covering the top surface of the blocking electrode 31 has a first via 111 formed at a position corresponding to the source electrode 21. The first via 111 exposes a portion of the blocking electrode 31, that is, the first insulating layer 11 covers a portion of the blocking electrode 31. The first via 111 penetrates the first insulating layer 11 to expose at least a portion of the blocking electrode 31. The diameter of the first via 111 is greater than 2 microns.

[0054] The orthographic projection of the opening of the first via 111 near the source electrode 21 on the substrate 10 is within the range of the orthographic projection of the blocking electrode 31 on the substrate 10. The opening of the first via 111 near the source electrode 21 is formed on the lower surface of the first insulating layer 11. Correspondingly, the opening formed on the upper surface of the first insulating layer 11 is away from the source electrode 21. The thickness of the first insulating layer 11 ranges from 3000 angstroms to 5000 angstroms. The depth of the first via 111 is equal to the thickness of the first insulating layer 11, that is, the depth of the first via 111 ranges from 3000 angstroms to 5000 angstroms, for example, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, etc. The material of the first insulating layer 11 includes an inorganic material. For example, the first insulating layer 11 can be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0055] The oxide active layer 40 is disposed on a side of the first insulating layer 11 away from the substrate 10. The source contact 42 and drain contact 43 of the oxide active layer 40 are formed by conductively converting the oxide active layer 40, forming conductive regions. The source contact 42 is located on a portion of the first insulating layer 11 and within the first via 111. The source contact 42 within the first via 111 covers the wall of the first via 111 and the exposed portion of the blocking electrode 31 through the first via 111, thereby connecting to the blocking electrode 31.

[0056] Because the orthographic projection of the opening of the first via 111 near the source electrode 21 on the substrate 10 is within the range of the orthographic projection of the blocking electrode 31 on the substrate 10, the source contact portion 42 located in the first via 111 is isolated from the source electrode 21 by the blocking electrode 31. Thus, the source contact portion 42 located in the first via 111 does not directly contact the source electrode 21. The oxide active layer 40 has a thickness ranging from 100 angstroms to 500 angstroms, for example, 100 angstroms, 200 angstroms, 220 angstroms, 250 angstroms, 280 angstroms, 300 angstroms, 350 angstroms, 380 angstroms, 400 angstroms, 500 angstroms, etc.

[0057] The second insulating layer 12 is disposed on a side of the oxide active layer 40 away from the substrate 10 and corresponding to the channel portion 41. The material of the second insulating layer 12 includes an inorganic material. For example, the second insulating layer 12 can be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0058] The third conductive layer 50 is disposed on a side of the second insulating layer 12 away from the substrate 10. The third conductive layer 50 includes a gate 51 of the first transistor, which is disposed corresponding to the second insulating layer 12. The third conductive layer 50 can be formed of multiple layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or alloys thereof, or a material with high corrosion resistance. For example, the third conductive layer 50 can be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, among others.

[0059] Continue to refer to Figure 2 The array substrate 100 further includes a third insulating layer 13, a planarization layer 14, a common electrode 60, a fourth insulating layer 15, and a pixel electrode 70. The third insulating layer 13 is disposed on a side of the third conductive layer 50 away from the substrate 10. For example, the third insulating layer 13 covers the upper surface and sidewalls of the gate 51, the sidewalls of the second insulating layer 12, the upper surface and sidewalls of the source contact 42, the upper surface and sidewalls of the drain contact 43, and a portion of the first insulating layer 11. The material of the third insulating layer 13 includes an inorganic material. For example, the third insulating layer 13 can be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0060] The planarization layer 14 is disposed on a side of the third insulating layer 13 away from the substrate 10. The planarization layer 14 is made of an organic material, for example, a resin such as polyacrylate or polyimide, or a silica-based organic material.

[0061] The common electrode 60 is disposed on a side of the planarization layer 14 away from the substrate 10. The common electrode 60 may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3).

[0062] The fourth insulating layer 15 is disposed on a side of the common electrode 60 away from the substrate 10. The fourth insulating layer 15 includes a second via hole 141 disposed corresponding to the drain contact portion 43. The second via hole 141 penetrates the fourth insulating layer 15, the planarization layer 14, and the third insulating layer 13 to expose a portion of the drain contact portion 43. The material of the fourth insulating layer 15 includes an inorganic material. For example, the fourth insulating layer 15 can be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0063] The second pixel electrode 70 is disposed on a layer of the fourth insulating layer 15 away from the substrate 10. A portion of the pixel electrode 70 is located within the second via hole 141 and is connected to the drain contact portion 43 exposed by the second via hole 141. The pixel electrode 70 is disposed opposite the common electrode 60. The material of the pixel electrode 70 can be the same as that of the common electrode 60. For example, the pixel electrode 70 can also be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3).

[0064] In one embodiment, please refer to Figures 1 to 3 , Figure 3 This is another cross-sectional structural diagram of the array substrate 100 provided in an embodiment of the present application. Figure 3 ,and Figure 2 The difference between the corresponding embodiment is that the blocking electrode 31 is located in the first via hole 111 , and the source contact portion 42 covers the blocking electrode 31 in the first via hole 111 .

[0065] Specifically, the first insulating layer 11 is provided with a first via hole 111 at a position corresponding to the source electrode 21, and the first via hole 111 exposes a portion of the source electrode 21. The blocking electrode 31 is provided within the first via hole 111 and is exposed by the first via hole 111. The blocking electrode 31 covers the hole wall of the first via hole 111 and the source electrode 21 exposed by the first via hole 111, and is connected to the source electrode 21. A portion of the source contact portion 42 is provided in the first via hole 111 and covers the blocking electrode 31 within the first via hole 111.

[0066] The orthographic projection of the opening of the first via 111 on the side closest to the source electrode 21 on the substrate 10 is within the range of the orthographic projection of the blocking electrode 31 on the substrate 10, so that the source contact 42 located within the first via 111 is separated from the source electrode 21 by the blocking electrode 31. Thus, the source contact 42 located within the first via 111 does not directly contact the source electrode 21. Furthermore, by disposing the blocking electrode 31 within the first via 111 and allowing the source contact 42 to cover the blocking electrode 31 within the first via 111, the contact area between the source contact 42 and the blocking electrode 31 is increased, thereby improving the reliability of the electrical connection between the source contact 42 and the source electrode 21. Thus, a smaller diameter first via 111 can be provided to achieve a highly reliable electrical connection between the source contact 42 and the source electrode 21, thereby reducing the occupied area of ​​the first transistor device.

[0067] It should be noted that the first insulating layer 11 has a relatively large thickness, while the oxide active layer 40 has a relatively small thickness, and the oxide active layer 40 is much thinner than the first insulating layer 11. When the aperture size of the first via 111 is small, due to the large thickness of the first insulating layer 11, the taper angle of the first via 111' is large. When the thin oxide active layer 40' slopes up within the first via 111', it is prone to problems such as disconnection, thereby affecting the reliability of the electrical connection between the source contact 42 and the source electrode 21. To avoid problems such as disconnection when the oxide active layer 40 slopes up within the first via 111, the first via 111 can be provided with a larger aperture, for example, the aperture of the first via 111 is larger than 2 microns. However, this will increase the occupied area of ​​the first transistor device.

[0068] In this embodiment, by setting the blocking electrode 31 in the first via hole 111 and making the source contact portion 42 cover the blocking electrode 31 located in the first via hole 111, the contact area between the source contact portion 42 and the blocking electrode 31 can be increased. Even if the source contact portion 42 is broken when climbing in the first via hole 111, the blocking electrode 31 can fill the broken part of the source contact portion 42, thereby improving the reliability of the electrical connection between the source contact portion 42 and the source 21. Therefore, a first via hole 111 with a smaller aperture can be set to achieve a high-reliability electrical connection between the source contact portion 42 and the source 21, thereby reducing the occupied area of ​​the first transistor device.

[0069] Optionally, the end of the blocking electrode 31 away from the source electrode 21 is flush with the upper surface of the first insulating layer 11. That is, the boundary of the blocking electrode 31 away from the source electrode 21 is flush with the upper surface of the first insulating layer 11. In other words, the blocking electrode 31 is located within the first via hole 111 but does not extend beyond the first via hole 111. This does not affect the flatness of the upper surface of the first insulating layer 11, facilitating the preparation of the oxide active layer 40. For other explanations, please refer to the above embodiment and will not be repeated here.

[0070] In one embodiment, please refer to Figures 1 to 4 , Figure 4 This is another cross-sectional structural diagram of the array substrate 100 provided in the embodiment of the present application. Figure 4 ,and Figure 3The difference from the corresponding embodiment is that the blocking electrode 31 extends from the first via 111 to the surface of the first insulating layer 11 on the side away from the substrate 10, and the source contact portion 42 also covers the blocking electrode 31 located outside the first via 111. In other words, the blocking electrode 31 is also provided on a portion of the upper surface of the first insulating layer 11. This further increases the contact area between the source contact portion 42 and the blocking electrode 31, thereby further improving the reliability of the electrical connection between the source contact portion 42 and the source electrode 21. For other explanations, please refer to the above embodiment and will not be repeated here.

[0071] In one embodiment, please refer to Figures 1 to 5 , Figure 5 This is another cross-sectional structural diagram of the array substrate 100 provided in the embodiment of the present application. Figure 5 ,and Figure 2 The difference between the corresponding embodiments is that the array substrate 100 is divided into a pixel area PA and a binding area BA located on one side of the pixel area PA. The first transistor, the common electrode 60, and the pixel electrode 70 are all located in the pixel area PA. The array substrate 100 also includes a binding terminal 80 located in the binding area BA. The binding terminal 80 is used to bind an external drive circuit to provide a signal to the pixel area PA. The first insulating layer 11 is provided with a third via at a position corresponding to the binding terminal 80, and the third via exposes the binding terminal 80.

[0072] The binding terminal 80 includes a first sub-binding portion 23 and a second sub-binding portion 33. The second sub-binding portion 33 is located on a side of the first sub-binding portion 23 away from the substrate 10. The first sub-binding portion 23 is formed by the first conductive layer 20, and the second sub-binding portion 33 is formed by the second conductive layer 30. That is, the first conductive layer 20 also includes the first sub-binding portion 23 located in the binding area BA, and the second conductive layer 30 also includes the second sub-binding portion 33 located in the binding area BA. The first sub-binding portion 23 is disposed in the same layer as the source electrode 21, and the second sub-binding portion 33 is disposed in the same layer as the blocking electrode 31.

[0073] The material of the second conductive layer 30 is indium tin oxide. Indium tin oxide is an oxide and will not be affected by subsequent processes such as oxygen ashing and high temperature, which will cause the impedance to increase. Molybdenum, titanium, and molybdenum-titanium alloys are easily affected by subsequent processes such as oxygen ashing and high temperature, which will cause the impedance to increase. Therefore, when the first conductive layer 20 and the second conductive layer 30 are also used to form the binding terminal 80 of the binding area BA, the material of the second conductive layer 30 is selected from indium tin oxide to avoid affecting the overall impedance of the binding terminal 80. For other explanations, please refer to the above embodiment and will not be repeated here.

[0074] Based on the same inventive concept, the present application further provides a display panel, which includes the array substrate 100 of one of the aforementioned embodiments. The display panel includes a liquid crystal display panel, an organic light emitting diode display panel, or other types of display panels.

[0075] According to the above embodiments, it can be seen that:

[0076] The present application provides an array substrate and a display panel, wherein the array substrate includes a substrate and a first conductive layer, a second conductive layer, a first insulating layer, an oxide active layer, a second insulating layer, and a third conductive layer arranged on the substrate, wherein the first conductive layer includes a source electrode and a light-shielding electrode arranged at intervals, the second conductive layer includes a blocking electrode connected to the source electrode, the first insulating layer includes a first via hole arranged corresponding to the source electrode, the first via hole exposing at least a portion of the blocking electrode, the oxide active layer includes a channel portion and a source contact portion located on one side of the channel portion, the channel portion is arranged corresponding to the light-shielding electrode, Part of the source contact portion is arranged in the first via hole and is connected to the blocking electrode. The blocking electrode is connected between the source contact portion and the source and is arranged corresponding to the first via hole, so that the source contact portion is electrically connected to the source through the blocking electrode to avoid direct contact between the source contact portion and the source. The blocking electrode can block the metal elements in the source from diffusing to the source contact portion to avoid the metal elements in the source from diffusing into the oxide active layer to form deep energy level impurities, which will cause device performance degradation, affect device characteristics and bias temperature stress characteristics, and thus improve device stability.

[0077] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0078] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A first conductive layer is provided on one side of the substrate, wherein the first conductive layer includes a source electrode and a light-shielding electrode that are spaced apart; a second conductive layer, disposed on a side of the first conductive layer away from the substrate, the second conductive layer comprising a blocking electrode connected to the source electrode; a first insulating layer, disposed on a side of the first conductive layer away from the substrate, the first insulating layer comprising a first via hole disposed corresponding to the source; an oxide active layer, disposed on a side of the first insulating layer away from the substrate, the oxide active layer comprising a channel portion and a source contact portion located on one side of the channel portion; In the thickness direction of the array substrate, the channel portion is arranged corresponding to the light shielding electrode, a portion of the source contact portion is arranged in the first via hole and connected to the blocking electrode, the blocking electrode is connected between the source contact portion and the source and is arranged corresponding to the first via hole, and the blocking electrode is configured to block the metal element in the source from diffusing toward the source contact portion; a second insulating layer, disposed on a side of the oxide active layer away from the substrate, the second insulating layer being disposed corresponding to the channel portion; a third conductive layer, disposed on a side of the second insulating layer away from the substrate, the third conductive layer comprising a gate disposed corresponding to the channel portion; The first insulating layer covers part of the source, the light-shielding electrode, and the gap between the light-shielding electrode and the source; the first via exposes part of the source; the blocking electrode is located in the first via, covers the hole wall of the first via and the source exposed by the first via, and is connected to the source exposed by the first via; the source contact portion covers the blocking electrode in the first via.

2. The array substrate according to claim 1, wherein: The blocking electrode extends from the first via hole to the surface of the first insulating layer on a side away from the substrate, and the source contact portion also covers the blocking electrode outside the first via hole.

3. The array substrate according to claim 1 or 2, wherein: The orthographic projection of the opening of the first via hole close to the source electrode on the substrate is located within the range of the orthographic projection of the blocking electrode on the substrate.

4. The array substrate according to claim 3, wherein: The thickness of the second conductive layer ranges from 100 angstroms to 800 angstroms.

5. The array substrate according to claim 3, wherein: The material of the second conductive layer includes one of molybdenum, titanium, molybdenum-titanium alloy, and indium tin oxide.

6. The array substrate according to claim 3, wherein: The first conductive layer includes a bonding layer and a main conductive layer located on a side of the bonding layer away from the substrate. The material of the bonding layer includes one of molybdenum, titanium, and molybdenum-titanium alloy. The material of the main conductive layer includes copper.

7. The array substrate according to claim 3, wherein: The array substrate further includes: a third insulating layer, disposed on a side of the third conductive layer away from the substrate; a planarization layer, disposed on a side of the third insulating layer away from the substrate; a common electrode, disposed on a side of the planarization layer away from the substrate; a fourth insulating layer disposed on a side of the common electrode away from the substrate, the oxide active layer further comprising a drain contact portion located on a side of the channel portion away from the source contact portion, and the fourth insulating layer comprising a second via hole disposed corresponding to the drain contact portion; A pixel electrode is provided on a side of the fourth insulating layer away from the substrate, and a portion of the pixel electrode is located in the second via hole and connected to the drain contact portion.

8. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 7.

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