A high voltage silicon carbide power MOSFET terminal structure and preparation method thereof

Abstract

The present invention relates to the field of MOS semiconductor technology, and discloses a high-voltage silicon carbide power MOSFET terminal structure, including a MOS cell structure located in the middle and a terminal structure located at the end, wherein the MOS cell structure and the terminal structure are both composed of a drain, a metal source and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer includes a substrate layer and a diffusion layer; the MOS cell structure includes a gate, a gate oxide layer covered on the gate surface, an N-well layer, a highly doped P-well layer 2 and a low-doped P-well layer 1, and the terminal structure is composed of a main junction and a junction terminal extension JTE; the junction terminal extension JTE includes a JTE region located at the surface of the diffusion layer. The present invention introduces multiple inner isolation rings as isolation rings in the main junction, which can block the current path formed by charging and discharging during the device switching process, prevent the formation of a strong electric field and leakage current at the main junction, and avoid the risk of damage to the device during high-speed switching.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a high-voltage silicon carbide power MOSFET terminal structure and a preparation method thereof. Background Art

[0002] SiC MOSFET devices have the significant advantages of high frequency and low loss, and are widely used in electric vehicles, photovoltaic inverters, charging piles and other fields. In order to meet the development needs of high energy efficiency, high power density and small and lightweight power electronic systems, SiC power devices are developing in the direction of high voltage, high power, high frequency and low loss. How to design the terminal structure for ultra-high voltage SiC power devices is very important. Considering the curvature effect of the actual chip, ultra-high voltage SiC power devices need to adopt a suitable terminal structure and main junction design to improve the electric field concentration phenomenon near the main junction.

[0003] The existing patent discloses a terminal structure of a super junction MOSFET (CN117476742A), wherein the terminal structure comprises a super junction structure region and a terminal lead-out region; the super junction structure region comprises alternatingly arranged P / N thin layers, wherein the P thin layers form P columns; the thickness of the P-type epitaxial layer determines the depth of the P column; the surface of the super junction structure region is covered with an insulating dielectric layer, and the insulating dielectric layer simultaneously extends to cover the surface of the P-type epitaxial layer in the terminal lead-out region; in the terminal lead-out region of the terminal structure, the P-type epitaxial layer comprises a heavily doped P-type injection region to form a P-type lead-out region.

[0004] In the technology disclosed in the above patent, a single main junction is used with a multi-zone junction terminal extension (JTE) or field limiting ring (FLR) terminal structure. In addition, due to the limited number of partitions, the concentration mutation between different regions of the former easily introduces new electric field spikes, resulting in the efficiency of the surface electric field being much lower than that of the ideal terminal; the latter field limiting ring junction terminal structure requires a large number of rings, a long terminal length, and an increased area occupied by the terminal. The design of the junction terminal structure is difficult, the process precision requirements are high, and the manufacturing cost is very high. In addition, this design usually has a large main junction area. During the rapid switching process of the power device, the charging and discharging effect of the terminal structure is prone to instantaneous overvoltage or overheating damage, especially the new generation of power devices such as SiC MOSFET, which have extremely fast switching speeds and are easily damaged during high-speed switching. Summary of the invention

[0005] The main technical problem solved by the present invention is to provide a high-voltage silicon carbide power MOSFET terminal structure and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0006] To solve the above technical problems, according to one aspect of the present invention, more specifically, a high-voltage silicon carbide power MOSFET terminal structure is provided, comprising a MOS cell structure located in the middle and a terminal structure located at the end, wherein the MOS cell structure and the terminal structure are both composed of a drain, a metal source and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises a substrate layer and a diffusion layer; the MOS cell structure comprises a gate, a gate oxide layer covering the gate surface, an N-well layer, a highly doped P-well layer 2 and a low-doped P-well layer 1, characterized in that: the terminal structure is composed of a main junction and a junction terminal extension JTE;

[0007] The junction terminal extension JTE includes a JTE region located on the surface of the diffusion layer; an oxide layer 1 is deposited above the JTE region, and the JTE region is isolated from the metal source by the oxide layer 1;

[0008] The main junction also includes a highly doped P-well layer 1 located on both sides of the main junction; an oxide layer 2 is deposited between the gate oxide layer and the oxide layer 1; the gate oxide layer, the oxide layer 1 and the oxide layer 2 block the main junction from ohmic contact with the metal source, and only the highly doped P-well layer 1 is in ohmic contact with the metal source;

[0009] Wherein, a plurality of inner isolation rings are formed by ion implantation inside the main junction and between the highly doped P well layers on both sides, and the spacings between the plurality of inner isolation rings are the same.

[0010] Furthermore, the JTE region further includes two non-adjacent high and low JTE regions, wherein the high and low JTE region with a smaller cross-sectional height is located outside the terminal structure;

[0011] A plurality of outer isolation rings with equal spacing are formed between the two high and low JTE regions by ion implantation, wherein the cross-sectional height of the outer isolation ring is the same as the cross-sectional height of the outer high and low JTE regions.

[0012] Furthermore, the JTE region also includes two non-adjacent JTE areas of equal height.

[0013] Furthermore, a low-concentration deeply doped guard ring is formed on the outer side of each of the equal-height JTE regions by ion implantation, and the cross-sectional height of the low-concentration deeply doped guard ring is the same as the cross-sectional height of the equal-height JTE region;

[0014] Three high-concentration isolation rings with equal spacing are formed inside each of the equal-height JTE regions by ion implantation.

[0015] Furthermore, a portion of the JTE region and its exterior are formed with a plurality of P+ protection rings with equal spacing by ion implantation.

[0016] A method for preparing a high voltage silicon carbide power MOSFET terminal structure further comprises the following steps:

[0017] S1, coating the oxide layer with photoresist and then performing photolithography, and removing the silicon oxide layer not protected by the photoresist by using plasma etching technology;

[0018] S2, introducing dopants into the silicon wafer by ion implantation or diffusion technology to form different conductivity regions in the source, drain and gate regions;

[0019] S3, bombarding the sample surface with high-energy ions to stimulate the sample to release secondary ions, and then measuring the mass and quantity of these secondary ions with a mass analyzer to determine the concentration and depth distribution of the dopant;

[0020] S4, inspecting the concentrations of the inner isolation ring, the high-concentration isolation ring, and the P+ guard ring in different batches of semiconductors to determine the doping qualification rate of the semiconductor terminal structure of the batch;

[0021] S5. Deposit a metal film on the entire surface to form contact points of the source, drain and gate.

[0022] Furthermore, in step S4, the qualified rate of the terminal structure doping concentration is determined by comparing the difference in doping concentration between the inner isolation ring, the high-concentration isolation ring and the P+ protection ring, and the following is obtained:

[0023]

[0024] in, Indicates the pass rate of MOSFET terminal structure, Indicates the detection concentration of the inner isolation ring, Indicates the detection concentration of the high concentration isolation ring, Indicates the detection concentration of the P+ guard ring; and:

[0025]

[0026] In the formula, The coefficient indicating the influence of the deviation between the expected doping concentration and the actual doping concentration on M, Represents the expected doping concentration of the inner isolation ring, high concentration isolation ring, and P+ guard ring.

[0027] Furthermore, when When , it means that the terminal structure doping of the MOS semiconductor device in the sampled batch is qualified;

[0028] when When , it means that the terminal structure doping of the MOS semiconductor devices in the sampled batch is unqualified.

[0029] Beneficial effects:

[0030] 1. The present invention introduces multiple inner isolation rings as isolation rings in the main junction, which can block the current path formed by charging and discharging during the device switching process, prevent the formation of a strong electric field and leakage current in the main junction, and avoid the risk of device damage during high-speed switching.

[0031] 2. The present invention introduces a high-concentration isolation ring in the JTE area and adds multiple low-concentration deeply doped protection rings outside the JTE area. This can reduce the impact of local strong electric field breakdown and overheating and burning caused by charging and discharging during the device switching process on the terminal, thereby ensuring the stability of the device terminal structure under various complex working conditions.

[0032] 3. The present invention can efficiently and accurately determine the doping qualification rate of the terminal structure of the MOS semiconductor device by comparing the difference in doping concentration between the inner isolation ring, the high-concentration isolation ring and the P+ protection ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a structural schematic diagram of Embodiment 1 of the present invention;

[0034] Figure 2 This is a schematic diagram of the structure of Embodiment 2 of the present invention;

[0035] Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention;

[0036] Figure 4 It is a structural schematic diagram of embodiment 4 of the present invention.

[0037] In the figure: 1. drain; 2. substrate layer; 3. diffusion layer; 4. metal source; 5. gate; 6. gate oxide layer; 7. main junction; 8. JTE region; 9. oxide layer 1; 10. oxide layer 2; 11. inner isolation ring; 12. highly doped P well layer 1; 13. N well layer; 14. highly doped P well layer 2; 15. low doped P well layer 1; 16. outer isolation ring; 17. low concentration deeply doped protection ring; 18. high concentration isolation ring; 19. P+ protection ring; 81. high and low JTE regions; 82. equal height JTE regions. DETAILED DESCRIPTION

[0038] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] like Figure 1 -4, according to one aspect of the present invention, a method for preparing a high voltage silicon carbide power MOSFET terminal structure is provided, which also includes the following steps:

[0040] Step 1: coating the oxide layer with photoresist and then performing photolithography, and removing the silicon oxide layer not protected by the photoresist by using plasma etching technology;

[0041] Step 2: introducing dopants into the silicon wafer by ion implantation or diffusion technology to form regions with different conductivity in the source, drain and gate regions;

[0042] Step 3: Use high-energy ions to bombard the sample surface to stimulate the sample to release secondary ions, and then use a mass analyzer to measure the mass and quantity of these secondary ions to determine the concentration and depth distribution of the dopant;

[0043] Step 4: Check the concentrations of the inner isolation ring 11, the high-concentration isolation ring 18 and the P+ protection ring 19 in different batches of semiconductors to determine the doping qualification rate of the semiconductor terminal structure of the batch;

[0044] Step 5: Deposit a layer of metal film on the entire surface to form contact points for the source, drain and gate.

[0045] In step 4, the doping concentration qualification rate of the terminal structure is determined by comparing the doping concentration difference between the inner isolation ring 11, the high concentration isolation ring 18 and the P+ guard ring 19, and the following is obtained:

[0046]

[0047] in, Indicates the pass rate of MOSFET terminal structure, represents the detection concentration of the inner isolation ring 11, represents the detection concentration of the high concentration isolation ring 18, represents the detection concentration of P+ guard ring 19; and:

[0048]

[0049] In the formula, The coefficient indicating the influence of the deviation between the expected doping concentration and the actual doping concentration on M, Expected doping concentrations of the inner isolation ring 11 , the high-concentration isolation ring 18 , and the P+ guard ring 19 are shown.

[0050] when When , it means that the terminal structure doping of the MOS semiconductor device in the sampled batch is qualified;

[0051] when When , it means that the terminal structure doping of the MOS semiconductor devices in the sampled batch is unqualified.

[0052] When testing the qualified rate of doping concentration of the terminal structure of the semiconductor in batch X, the detection concentration of the inner isolation ring 11 is ( atoms / cm3), the detection concentration of the high concentration isolation ring 18 is taken ( atoms / cm3), the detection concentration of P+ guard ring 19 is ( atoms / cubic centimeter).

[0053] The expected doping concentration of the doped P well gate 11, the high concentration isolation ring 18 and the P+ guard ring 19 is ( atoms / cubic centimeter), then:

[0054]

[0055] From the above calculation, we can know that the influence coefficient of the deviation between the expected doping concentration and the actual doping concentration on M is .in, The larger the value is, the greater the deviation between the actual detected concentration and the expected doping concentration is.

[0056] Then, the qualified rate of terminal structure doping concentration of semiconductors in test batch X is:

[0057]

[0058] From the above calculation, it can be known that the doping test of the semiconductor terminal structure in batch X is qualified.

[0059] Example 1

[0060] like Figure 1As shown, according to one aspect of the present invention, a high-voltage silicon carbide power MOSFET terminal structure is provided, including a MOS cell structure located in the middle and a terminal structure located at the end, the MOS cell structure and the terminal structure are both composed of a drain 1, a metal source 4 and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer includes a substrate layer 2 and a diffusion layer 3; the MOS cell structure includes a gate 5, a gate oxide layer 6 covered on the surface of the gate 5, an N-well layer 13, a highly doped P-well layer 2 14 and a low-doped P-well layer 15, and the terminal structure is composed of a main junction and a junction terminal extension JTE; the junction terminal extension JTE includes a JTE located at the surface of the diffusion layer 3 region 8; an oxide layer 9 is deposited above the JTE region 8, and the JTE region 8 is blocked from the metal source 4 by the oxide layer 9; the main junction 7 also includes a highly doped P well layer 12 located on both sides of the main junction 7; an oxide layer 2 10 is deposited between the gate oxide layer 6 and the oxide layer 9; the gate oxide layer 6, the oxide layer 9 and the oxide layer 2 10 block the main junction 7 from ohmic contact with the metal source 4, and only the highly doped P well layer 12 is in ohmic contact with the metal source 4; wherein, a plurality of inner isolation rings 11 are formed by ion implantation inside the main junction 7 and between the highly doped P well layers 12 on both sides, and the spacing between the plurality of inner isolation rings 11 is the same. Introducing a plurality of isolation rings (inner isolation rings 11) in the main junction 7 can block the current path formed by charging and discharging during the switching process of the device, prevent the formation of a strong electric field and leakage current in the main junction, and avoid the risk of damage to the device during high-speed switching. In addition, the present invention does not need to change the existing process and flow, only needs to change the design layout in one step, and does not increase additional production costs.

[0061] The main junction 7 is formed into a P-body region by ion implantation of low-concentration boron ions. The JTE region 8 is formed into a P-body region by ion implantation of low-concentration boron ions. The inner isolation ring 11 is formed into a P+body region by ion implantation of high-concentration boron ions.

[0062] Example 2

[0063] like Figure 2 As shown, the JTE region 8 also includes two non-adjacent high and low JTE regions 81, wherein the high and low JTE region 81 with a small cross-sectional height is located outside the terminal structure; a number of equally spaced outer isolation rings 16 are formed between the two high and low JTE regions 81 by ion implantation, wherein the cross-sectional height of the outer isolation ring 16 is the same as the cross-sectional height of the outer high and low JTE region 81. In order to suppress the influence of the junction terminal extended JTE structure on the device during the device switching process, the present invention divides the JTE region 8 into two high and low JTE regions 81, and introduces multiple isolation rings (external isolation rings 16) between the two high and low JTE regions 81, which can greatly improve the reliability of the device.

[0064] The high and low JTE regions 81 are formed as P-body regions by ion implantation of low-concentration boron ions, and the outer isolation ring 16 is formed as P-body regions by ion implantation of low-concentration boron ions.

[0065] Example 3

[0066] like Figure 3 As shown, the JTE region 8 also includes two non-adjacent equal-height JTE regions 82, and a low-concentration deeply doped protection ring 17 is formed on the outside of each equal-height JTE region 82 by ion implantation, and the cross-sectional height of the low-concentration deeply doped protection ring 17 is the same as the cross-sectional height of the equal-height JTE region 82; and three equally spaced high-concentration isolation rings 18 are formed inside each equal-height JTE region 82 by ion implantation. This embodiment continues to segment the JTE region 8 and introduce high-concentration isolation rings 18 in the JTE region 8, while adding multiple low-concentration deeply doped protection rings (low-concentration deeply doped protection rings 17) outside the JTE region 8, which can reduce the effects of local strong electric field breakdown and overheating and burning generated by the charging and discharging of the device switching process on the terminal, and ensure the stability of the device terminal structure under various complex working conditions.

[0067] The low-concentration deeply doped protection ring 17 is formed by ion implantation of low-concentration boron ions to form a P-body region, and the high-concentration isolation ring 18 is formed by ion implantation of high-concentration boron ions to form a P+body region.

[0068] Example 4

[0069] like Figure 4 As shown, the JTE region 8 also includes two non-adjacent equal-height JTE regions 82, and a portion of the equal-height JTE region 82 and its exterior are ion-implanted to form a number of equally spaced P+ guard rings 19. In order to suppress the influence of the junction terminal extended JTE structure on the device during the device switching process due to the charge and discharge, the present invention separates the JTE region 8 into two equal-height JTE regions 82.

[0070] In addition, since the doping concentration in the JTE of the existing mainstream design is mostly medium, this will lead to a decrease in efficiency of the device terminal at high temperature. The present invention introduces a P+ guard ring 19 as a guard ring to adjust the electric field distribution of the terminal (such as Figure 4 As shown), improve the stability of the terminal under long-term and complex working conditions.

[0071] Among them, the P+ guard ring is formed by ion implantation of high concentration boron ions into the P+ body region.

[0072] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A high-voltage silicon carbide power MOSFET terminal structure, comprising a MOS cell structure located in the middle and a terminal structure located at the end, wherein the MOS cell structure and the terminal structure are both composed of a drain (1), a metal source (4) and a semiconductor epitaxial layer, wherein: The semiconductor epitaxial layer comprises a substrate layer (2) and a diffusion layer (3); the MOS cell structure comprises a gate (5), a gate oxide layer (6) covering the surface of the gate (5), an N-well layer (13), a highly doped P-well layer 2 (14) and a low-doped P-well layer 1 (15), characterized in that: the terminal structure is composed of a main junction (7) and a junction terminal extension JTE; The junction terminal extension JTE comprises a JTE region (8) located on the surface of the diffusion layer (3); an oxide layer (9) is deposited above the JTE region (8), and the JTE region (8) and the metal source (4) are blocked by the oxide layer (9); The main junction (7) further comprises a highly doped P-well layer 1 (12) located on both sides of the main junction (7); an oxide layer 2 (10) is deposited between the gate oxide layer (6) and the oxide layer 1 (9); the gate oxide layer (6), the oxide layer 1 (9) and the oxide layer 2 (10) block the main junction (7) from ohmic contact with the metal source electrode (4), and only the highly doped P-well layer 1 (12) is in ohmic contact with the metal source electrode (4); Wherein, a plurality of inner isolation rings (11) are formed by ion implantation inside the main junction (7) and between the highly doped P well layers (12) on both sides, and the spacing between the plurality of inner isolation rings (11) is the same; The JTE region (8) further comprises two non-adjacent high and low JTE regions (81), wherein the high and low JTE region (81) with a smaller cross-sectional height is located outside the terminal structure; A plurality of equally spaced outer isolation rings (16) are formed between the two high and low JTE regions (81) by ion implantation, wherein the cross-sectional height of the outer isolation ring (16) is the same as the cross-sectional height of the outer high and low JTE regions (81).

2. The high voltage silicon carbide power MOSFET terminal structure according to claim 1, characterized in that: The JTE region (8) further includes two non-adjacent JTE areas (82) of equal height.

3. The high voltage silicon carbide power MOSFET terminal structure according to claim 2, characterized in that: A low-concentration deeply doped protection ring (17) is formed on the outside of each of the equal-height JTE regions (82) by ion implantation, and the cross-sectional height of the low-concentration deeply doped protection ring (17) is the same as the cross-sectional height of the equal-height JTE region (82); Three equally spaced high-concentration isolation rings (18) are formed inside each of the equal-height JTE regions (82) by ion implantation.

4. The high voltage silicon carbide power MOSFET terminal structure according to claim 2, characterized in that: A plurality of P+ protection rings (19) with equal spacing are formed through ion implantation in a partial segment area and the outside of the equal height JTE area (82).

5. A method for preparing a high voltage silicon carbide power MOSFET terminal structure according to any one of claims 1 to 4, characterized in that: The following steps are also included: S1, coating the oxide layer with photoresist and then performing photolithography, and removing the silicon oxide layer not protected by the photoresist by using plasma etching technology; S2, introducing dopants into the silicon wafer by ion implantation or diffusion technology to form different conductivity regions in the source, drain and gate regions; S3, bombarding the sample surface with high-energy ions to stimulate the sample to release secondary ions, and then measuring the mass and quantity of these secondary ions with a mass analyzer to determine the concentration and depth distribution of the dopant; S4, inspecting the concentrations of the inner isolation ring (11), the high-concentration isolation ring (18) and the P+ protection ring (19) in different batches of semiconductors to determine the doping qualification rate of the semiconductor terminal structure of the batch; S5. Deposit a metal film on the entire surface to form contact points of the source, drain and gate.

6. The method for preparing a high voltage silicon carbide power MOSFET terminal structure according to claim 5, characterized in that: In step S4, the qualified rate of the terminal structure doping concentration is determined by comparing the difference in doping concentration between the inner isolation ring (11), the high concentration isolation ring (18) and the P+ protection ring (19), and the following is obtained: in, Indicates the pass rate of MOSFET terminal structure, represents the detection concentration of the inner isolation ring (11), represents the detection concentration of the high concentration isolation ring (18), represents the detected concentration of the P+ guard ring (19); and: In the formula, The coefficient indicating the influence of the deviation between the expected doping concentration and the actual doping concentration on M, The expected doping concentrations of the inner isolation ring (11), the high concentration isolation ring (18) and the P+ protection ring (19) are shown.

7. The method for preparing a high voltage silicon carbide power MOSFET terminal structure according to claim 6, characterized in that: when When , it means that the terminal structure doping of the MOS semiconductor device in the sampled batch is qualified; when When , it means that the terminal structure doping of the MOS semiconductor devices in the sampled batch is unqualified.

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