Method and apparatus for determining transmission delay time, storage medium, electronic device, computer program product

Abstract

The application discloses a method and device for determining transmission delay time, a storage medium, an electronic device and a computer program product, relates to the technical field of time-sensitive networks, and the method comprises the following steps: determining a first time when a first component sends a first message, a second time when a second component receives the first message, a third time when the second component sends a second message, and a fourth time when the first component receives the second message; determining an asymmetry time according to a first receiving delay time, a first sending delay time, a second receiving delay time and a second sending delay time; and determining a first time and / or a second time according to the first time, the second time, the third time, the fourth time and the asymmetry time when the second time meets a first preset condition and the third time meets a second preset condition. The above technical scheme solves the problem that the transmission delay time of the message cannot be accurately determined.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of time-sensitive network, in particular to a method and device for determining transmission delay time, a storage medium, an electronic device and a computer program product. BACKGROUND

[0002] Vehicle Time-Sensitive Networking (TSN) is a network communication technology for cars and other vehicles. It is based on time-sensitive networking and aims to provide reliable and real-time data transmission and communication services, thereby improving the coordination and safety between vehicles and providing an important foundation for the development of future intelligent transportation systems.

[0003] Vehicle time mainly includes two categories: relative time (vehicle time) and absolute time (utc). Due to different characteristics, they are suitable for different application scenarios. Relative time is suitable for local area network clock synchronization and has high synchronization accuracy. It uses Generalized Precision Time Protocol (GPTP) and time domain synchronization protocol in accordance with the 802.1AS-2020 standard protocol to keep the clocks of various electronic control units in the vehicle synchronized. Absolute time is the world unified clock. In related technologies, the local clock is generally synchronized through Network Time Protocol (NTP) or Global Navigation Satellite System (GNSS), but the vehicle is a mobile unit, and NTP packets and GNSS may lose time. Therefore, the synchronization of the local time is prone to delay. At the same time, due to link delay, terminal node and bridge node internal clock characteristics, bridge node synchronization message residence time, etc., the related technology may cause delay when transmitting message data.

[0004] In view of the problem that the related technology cannot accurately determine the transmission delay time of the message, at present, no effective solution has been proposed, therefore, it is necessary to improve the related technology to overcome the defects in the related technology. SUMMARY

[0005] The embodiments of the present application provide a method and device for determining transmission delay time, a storage medium, an electronic device and a computer program product to at least solve the problem that the transmission delay time of the message cannot be accurately determined.

[0006] According to an aspect of the embodiments of the present application, a method for determining a transmission delay time is provided. The method includes: determining a first time when a first component sends a first message, a second time when a second component receives the first message, a third time when the second component sends a second message, and a fourth time when the first component receives the second message, wherein the second message is a message sent by the second component in response to the first message, the first time is a time when the first component has not eliminated a first sending delay time, the fourth time is a time when the first component has not eliminated a first receiving delay time, the first sending delay time is a transmission delay time of the first component, the first receiving delay time is a transmission delay time of the first component, and determining an asymmetry time according to the first receiving delay time, the first sending delay time, a second receiving delay time, and a second sending delay time, wherein the second receiving delay time is a transmission delay time of the second component, the second sending delay time is a transmission delay time of the second component, the asymmetry time is used to reflect an asymmetry between a first time and a second time, the first time is a transmission delay time of a message from the first component to the second component, and the second time is a transmission delay time of a message from the second component to the first component; and determining the first time and / or the second time according to the first time, the second time, the third time, the fourth time, and the asymmetry time when the second time meets a first preset condition and the third time meets a second preset condition, wherein the first preset condition includes that the second time is a time when the second component has not eliminated the second receiving delay time, and the second preset condition includes that the third time is a time when the second component has not eliminated the second sending delay time.

[0007] In an exemplary embodiment, the method further includes: when the second time does not meet the first preset condition and the third time does not meet the second preset condition, correcting the second time using the second receiving delay time to obtain a corrected second time, and correcting the third time using the second sending delay time to obtain a corrected third time; and determining the first time and / or the second time according to the first time, the corrected second time, the corrected third time, the fourth time, and the asymmetry time.

[0008] In an exemplary embodiment, determining the asymmetry time according to the first receiving delay time, the first sending delay time, the second receiving delay time and the second sending delay time comprises: adding the first receiving delay time and the second sending delay time to obtain a first intermediate value; and adding the first sending delay time and the second receiving delay time to obtain a second intermediate value; subtracting the second intermediate value from the first intermediate value to obtain a third intermediate value; and determining half of the third intermediate value as the asymmetry time.

[0009] In an exemplary embodiment, determining the first time and / or the second time according to the first time point, the second time point, the third time point, the fourth time point and the asymmetry time comprises: calculating the first time and / or by Formula One below, and calculating the second time by Formula Two below: wherein T ir is the first time, T ri is the second time, t1 is the first time point, t2 is the second time point, t3 is the third time point, t4 is the fourth time point, and T da is the asymmetry time.

[0010] In an exemplary embodiment, before determining the asymmetry time according to the first receiving delay time, the first sending delay time, the second receiving delay time and the second sending delay time, the method further comprises: determining a first Ethernet interface standard for the first component to send the packet, and determining the first sending delay time from a first table according to the first Ethernet interface standard, wherein the first table has corresponding sending delay times of the first component under different Ethernet interface standards; determining a second Ethernet interface standard for the first component to receive the packet, and determining the first receiving delay time from a second table according to the second Ethernet interface standard, wherein the second table has corresponding receiving delay times of the first component under different Ethernet interface standards; determining a third Ethernet interface standard for the second component to send the packet, and determining the second sending delay time from a third table according to the third Ethernet interface standard, wherein the third table has corresponding sending delay times of the second component under different Ethernet interface standards; and determining a fourth Ethernet interface standard for the second component to receive the packet, and determining the second receiving delay time from a fourth table according to the fourth Ethernet interface standard, wherein the fourth table has corresponding receiving delay times of the second component under different Ethernet interface standards.

[0011] In one exemplary embodiment, after the first time and / or the second time are determined, the method further comprises: in the case that the second packet carries the local time of the second component, determining the time after the local time is delayed by the second time as the local time of the first component.

[0012] According to another aspect of the embodiments of the present application, a device for determining transmission delay time is further provided, comprising: a first determining module, configured to determine a first time when a first component transmits a first packet, a second time when a second component receives the first packet, a third time when the second component transmits a second packet, and a fourth time when the first component receives the second packet, wherein the second packet is a packet transmitted by the second component in response to the first packet, the first time is a time when the first component has not eliminated a first transmission delay time, the fourth time is a time when the first component has not eliminated a first reception delay time, the first transmission delay time is a transmission delay time of the first component, and the first reception delay time is a transmission delay time of the first component; a second determining module, configured to determine an asymmetry time according to the first reception delay time, the first transmission delay time, a second reception delay time, and a second transmission delay time, wherein the second reception delay time is a transmission delay time of the second component, the second transmission delay time is a transmission delay time of the second component, and the asymmetry time is used to reflect asymmetry between a first time and a second time, the first time is a transmission delay time of a packet from the first component to the second component, and the second time is a transmission delay time of a packet from the second component to the first component; and a third determining module, configured to determine the first time and / or the second time according to the first time, the second time, the third time, the fourth time, and the asymmetry time in the case that the second time meets a first preset condition and the third time meets a second preset condition, wherein the first preset condition comprises that the second time is a time when the second component has not eliminated the second reception delay time, and the second preset condition comprises that the third time is a time when the second component has not eliminated the second transmission delay time.

[0013] According to still another aspect of the embodiments of the present application, a computer readable storage medium is further provided, which comprises a stored program, wherein the program is set to execute the above-mentioned method for determining transmission delay time when running.

[0014] According to still another aspect of the embodiments of the present application, an electronic device is further provided, which comprises a memory and a processor, and the memory stores a computer program, wherein the processor is set to execute the above-mentioned method for determining transmission delay time through the computer program.

[0015] According to still another aspect of the embodiments of the present application, a computer program product is provided, which comprises a computer program, and when the computer program is executed by a processor, the above-mentioned method for determining transmission delay time is implemented.

[0016] By the present application, when determining the transmission delay time of a message from a first component to a second component and / or the transmission delay time of a message from the second component to the first component, the delay time of the first component sending the message, the delay time of the first component receiving the message, the delay time of the second component receiving the message and the delay time of the second component sending the message are considered, and thus the transmission delay time of the message from the first component to the second component and / or the transmission delay time of the message from the second component to the first component can be accurately determined, and the problem that the transmission delay time of the message cannot be accurately determined is solved. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0019] Figure 1 is a hardware structure block diagram of a mobile terminal of a method for determining transmission delay time according to an embodiment of the present application;

[0020] Figure 2 is a flow chart of a method for determining transmission delay time according to an embodiment of the present application;

[0021] Figure 3 is a schematic diagram of transmission delay time according to an embodiment of the present application;

[0022] Figure 4 is a schematic diagram of the generation principle of transmission delay time according to an embodiment of the present application;

[0023] Figure 5 is a measurement principle diagram of link delay time according to an embodiment of the present application;

[0024] Figure 6 is a structure block diagram of a determination device of transmission delay time according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 FIG. 1 is a hardware structure diagram of a mobile terminal for determining a transmission delay time according to an embodiment of the present application. Figure 1 As shown, the mobile terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a microprocessor (MP) or a programmable logic device (FPGA) and a processing device) and a memory 104 for storing data. The mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0028] The memory 104 can be used to store computer programs, such as software programs and modules of application software, such as the computer program corresponding to the method for detecting aerodynamic imbalance in the embodiments of the present application. The processor 102 executes the computer program stored in the memory 104 to execute various functional applications and data processing, thereby implementing the above-mentioned method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories may be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0029] The transmission device 106 is used to receive or send data via a network. A specific example of the aforementioned network may include a wireless network provided by the mobile terminal's communications provider. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0030] It should be noted that in the relevant technology, the time types applicable to various functional scenarios in the car are shown in Table 1 below.

[0031] Table 1

[0032]

[0033]

[0034] A time-sensitive network that complies with the 802.1AS standard is primarily composed of end nodes and bridge nodes. The factors that affect synchronization accuracy include the following three aspects:

[0035] 1) Link latency: Link latency is one of the main factors affecting time synchronization accuracy. Data transmission delays between different devices can cause clock signal asynchrony, thus affecting time synchronization accuracy.

[0036] 2) Internal clock characteristics of terminal nodes and bridge nodes: The accuracy / drift / jitter of the internal clock affects the accuracy of time synchronization.

[0037] 3) Bridge point synchronization message residence time: The accuracy of the measurement of the synchronization message residence time in the bridge point affects the synchronization accuracy of the link.

[0038] The measurement of link delay in 802.1AS adopts a point-to-point delay measurement mechanism, assuming that the link round-trip delay is consistent (the link has symmetry), and the link delay (MeanLinkDelay) on a link is calculated by measuring four accurate time stamps. However, the actual terminal node and the bridge node have different hardware, resulting in asymmetric physical transmission and reception link delays in actual communication, and thus the transmission delay time of the packet cannot be accurately determined.

[0039] In the embodiment, a method for determining transmission delay time is provided, Figure 2 is a flowchart of a method for determining transmission delay time according to an embodiment of the application, as shown in the figure, the flow includes the following steps S202-S206: Figure 2

[0040] Step S202: determining a first time when a first component sends a first packet, a second time when a second component receives the first packet, a third time when the second component sends a second packet, and a fourth time when the first component receives the second packet, wherein the second packet is a packet sent by the second component in response to the first packet, the first time is a time when the first component has not eliminated a first sending delay time, the fourth time is a time when the first component has not eliminated a first receiving delay time, the first sending delay time is a transmission delay time of the first component, and the first receiving delay time is a transmission delay time of the first component;

[0041] Optionally, the second time is carried in the second packet, and the second component can send a third packet to the first component after sending the second packet to the first component, wherein the third time is carried in the third packet.

[0042] Optionally, the first component is a time-sensitive network initiator as shown in Figure 3 , and the second component is a time-sensitive network responder as shown in Figure 3 .

[0043] Optionally, the first time is a time when the first component captures the sending of the first packet at a network layer, the second time is a time when the second component captures the receiving of the first packet at a network layer, the third time is a time when the second component captures the sending of the second packet at a network layer, and the fourth time is a time when the first component captures the receiving of the second packet at a network layer.

[0044] For better understanding, the following is combined with Figure 4 ​It is specified that: when the first message leaves the Media Access Control layer (MAC layer) of the time-sensitive network initiator, the time-sensitive network initiator captures the time when the first message is sent; when the first message arrives at the MAC layer of the time-sensitive network responder, the time-sensitive network responder captures the time when the message is received; when the second message leaves the MAC layer of the time-sensitive network responder, the time-sensitive network responder captures the time when the second message is sent; and when the second message arrives at the MAC layer of the time-sensitive network initiator, the time-sensitive network initiator captures the time when the message is received.

[0045] Step S204: determining an asymmetry time according to the first receiving delay time length, the first sending delay time length, a second receiving delay time length and a second sending delay time length, wherein the second receiving delay time length is a delay time when the second component receives the message, the second sending delay time length is a delay time when the second component sends the message, the asymmetry time is used to reflect the asymmetry between a first time and a second time, the first time is a transmission delay time of the message from the first component to the second component, and the second time is a transmission delay time of the message from the second component to the first component;

[0046] It should be noted that the steps S202 and S204 are executed asynchronously, that is, when the method is executed, the step S202 can be executed first, or the step S204 can be executed first.

[0047] In an exemplary embodiment, before the step S204, the method further includes steps S11-S14.

[0048] Step S11: determining a first Ethernet interface standard of the first component for sending the message, and determining the first sending delay time length from a first table according to the first Ethernet interface standard, wherein the first table has sending delay time lengths corresponding to the first component under different Ethernet interface standards.

[0049] Optionally, the first table is shown in Table 2 as follows:

[0050] Table 2

[0051]

[0052] Optionally, the first sending delay time length can take typical values in Table 2, for example, when the first Ethernet interface standard of the first component for sending the message is RGMII, the first sending delay time length is 392 ns, and when the first Ethernet interface standard of the first component for sending the message is SGMII, the first sending delay time length is 472 ns.

[0053] It should be noted that, since the first table has a one-to-one correspondence with the first component in implementing the method of the present application, the first table corresponding to the first component produced by different hardware manufacturers is different.

[0054] Step S12: determining a second Ethernet interface standard of the first component receiving the packet, and determining the first receiving delay duration from a second table according to the second Ethernet interface standard, wherein the second table has the receiving delay duration corresponding to the first component under different Ethernet interface standards;

[0055] Optionally, the first table is shown in Table 3 as follows:

[0056] Table 3

[0057]

[0058] Optionally, the first receiving delay duration can take typical values in Table 3, for example, when the first Ethernet interface standard of the first component receiving the packet is RGMII, the first receiving delay duration is 4301ns, and when the first Ethernet interface standard of the first component receiving the packet is SGMII, the first receiving delay duration is 4401ns.

[0059] It should be noted that, since the second table has a one-to-one correspondence with the first component in implementing the method of the present application, the second table corresponding to the first component produced by different hardware manufacturers is different.

[0060] Step S13: determining a third Ethernet interface standard of the second component sending the packet, and determining the second sending delay duration from a third table according to the third Ethernet interface standard, wherein the third table has the sending delay duration corresponding to the second component under different Ethernet interface standards;

[0061] Optionally, the third table is shown in Table 4 as follows:

[0062] Table 4

[0063]

[0064] Optionally, the second sending delay duration can take typical values in Table 4, for example, when the first Ethernet interface standard of the second component sending the packet is RGMII, the second sending delay duration is 983ns, and when the first Ethernet interface standard of the second component sending the packet is SGMII, the second sending delay duration is 1005ns.

[0065] It should be noted that, in the implementation of the method, the fourth table has a one-to-one correspondence with the second component, and the fourth table corresponding to the second component produced by different hardware manufacturers is different.

[0066] It should be noted that, in the case that the first component and the second component are produced by the same hardware manufacturer, the first table and the third table are the same, and the second table and the fourth table are the same.

[0067] Step S14: determining a fourth Ethernet interface standard of the second component receiving the packet, and determining the second receiving delay duration from a fourth table according to the fourth Ethernet interface standard, wherein the fourth table has the receiving delay durations corresponding to the second component under different Ethernet interface standards.

[0068] Optionally, the fourth table is shown in Table 5 as follows:

[0069] Table 5

[0070]

[0071]

[0072] Optionally, the second receiving delay duration can take typical values in Table 5, for example, when the first Ethernet interface standard of the second component receiving the packet is RGMII, the second receiving delay duration is 901ns, and when the first Ethernet interface standard of the second component receiving the packet is SGMII, the second receiving delay duration is 1349ns.

[0073] It should be noted that, in the implementation of the method, the fourth table has a one-to-one correspondence with the second component, and the fourth table corresponding to the second component produced by different hardware manufacturers is different.

[0074] It should be noted that, through the above steps S21-S24, the first sending delay duration, the first receiving delay duration, the second sending delay duration and the second receiving delay duration can be accurately determined, and the asymmetry time can be accurately determined.

[0075] It should be noted that the above steps S11-S14 are executed asynchronously, i.e. there is no execution order between the above steps S11-S14, for example: step S14 can be executed first, or step S12 can be executed first.

[0076] In an exemplary embodiment, the above step S204 can be implemented by the following steps S21-S24:

[0077] Step S21: adding the first receiving delay duration to the second sending delay duration to obtain a first intermediate value;

[0078] Step S22: adding the first sending delay duration and the second receiving delay duration to obtain a second intermediate value;

[0079] Step S23: subtracting the second intermediate value from the first intermediate value to obtain a third intermediate value;

[0080] Step S24: determining half of the third intermediate value as the asymmetry time.

[0081] Optionally, the asymmetry time is determined through the above steps S21-S24, so that whether the transmission link time between the first component and the second component is symmetrical can be determined according to the asymmetry time. In the case that the asymmetry time is 0, it indicates that the transmission link delay is symmetrical, i.e., the transmission time of the message from the first component to the second component and the transmission time of the message from the second component to the first component are equal.

[0082] Step S206: in the case that the second time meets a first preset condition and the third time meets a second preset condition, determining the first time and / or the second time according to the first time, the second time, the third time, the fourth time and the asymmetry time, wherein the first preset condition comprises that the second time is the time when the second component does not eliminate the second receiving delay duration; and the second preset condition comprises that the third time is the time when the second component does not eliminate the second sending delay duration.

[0083] It should be noted that the execution subject of the above steps is the first component.

[0084] Through the above steps S202-S206, when determining the transmission delay time of the message from the first component to the second component and / or the transmission delay time of the message from the second component to the first component, the delay time of the first component sending the message, the delay time of the first component receiving the message, the delay time of the second component receiving the message and the delay time of the second component sending the message are considered, so that the transmission delay time of the message from the first component to the second component and / or the transmission delay time of the message from the second component to the first component can be accurately determined, and the problem that the transmission delay time of the message cannot be accurately determined is solved.

[0085] In an exemplary embodiment, the above step S206 can be implemented in the following manner: the first time is calculated through formula one below, and the second time is calculated through formula two below:

[0086]

[0087] wherein T ir is the first time, T rithe first time, T da the asymmetry time.

[0088] Optionally, the first time and the second time are calculated through the above steps, so that the determination of the transmission delay time is more accurate.

[0089] In an exemplary embodiment, the method further comprises steps S208-S210:

[0090] Step S208: in the case that the second time does not satisfy the first preset condition and the third time does not satisfy the second preset condition, the second time is corrected using the second receiving delay duration to obtain a corrected second time, and the third time is corrected using the second sending delay duration to obtain a corrected third time;

[0091] It should be noted that the corrected second time is equal to the second time plus the second receiving delay duration, and the corrected third time is equal to the third time minus the second sending delay duration.

[0092] Step S210: determining the first time and / or the second time according to the first time, the corrected second time, the corrected third time, the fourth time and the asymmetry time.

[0093] In an exemplary embodiment, the above step S210 can be implemented in the following manner: the first time is calculated through formula one below, and the second time is calculated through formula two below:

[0094]

[0095] wherein, T ir the first time, T ri the second time, t1 is the first time, t2 is the corrected second time, t3 is the corrected third time, t4 is the fourth time, T da the asymmetry time.

[0096] Optionally, the first time and the second time are calculated through the above steps, so that the determination of the transmission delay time is more accurate.

[0097] In one exemplary embodiment, after determining the first time and / or the second time, the method further comprises the step of: in the case that the second packet carries the local time of the second component, determining the time after the second time as the local time of the first component.

[0098] Optionally, the first packet is used to request the second component to obtain the absolute time to synchronize the local time, wherein the absolute time is stored in the second component and is determined by a world unified clock. After receiving the first packet, the second component responds to the first packet by sending a second packet, and the content of the second packet includes but is not limited to the absolute time (i.e., the local time of the response end of the time-sensitive network).

[0099] It should be noted that, in order to better understand the measurement method of the link delay, the following will be specifically described in combination with Figure 5 :

[0100] 1) The requester (equivalent to the first component) sends a Pdelay_Req packet to request to measure the propagation delay;

[0101] 2) When the Pdelay_Req packet leaves the MAC layer of the requester, the requester captures the t1 time stamp by using the free-running local clock; at the same time, when the Pdelay_Req packet arrives at the MAC layer of the responder, the responder captures the t2 time stamp;

[0102] 3) The responder (equivalent to the second component) returns a Pdelay_Resp packet to transmit the t2 time to the requester; at the same time, the Pdelay_Resp triggers the capture of the t3 and t4 time stamps by both parties;

[0103] 4) The responder transmits the t3 time to the requester by using a Pdelay_Resp_Follow_Up packet;

[0104] 5) Assuming that the transmission delay is symmetrical, that is, the transmission time of the packet from the requester to the responder is the same as the transmission time of the packet from the responder to the requester, then the link propagation delay (i.e., the average link delay Tmld) can be calculated by the following formula:

[0105]

[0106] 6) When the actual transmission delay is asymmetrical, then the link propagation delay can be calculated by the following formula:

[0107]

[0108] Wherein the value of Tda can be calculated by the data in the above table 2-5, from the above table 2-5, it can be seen that the delay time is related to the mac and phy transceiver physical characteristics of the actual terminal or bridge point Ethernet controller, when the entire time sensitive network adopts the same mac and phy of the hardware manufacturer, the communication network is basically symmetrical, and the link delay can be calculated by adopting step 5); if the mac and phy of different hardware manufacturers are adopted, the sending delay and receiving delay can be found in the application manual published by the hardware manufacturer, and the sending and receiving delay is mainly related to the interface type and network rate parameters. After the network hardware selection is determined, the delay value of the transceiver link can be accurately measured by means of calibration compensation.

[0109] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, and of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of instructions for making a terminal device (which can be a mobile phone, computer, server, or network device, etc.) execute the method of each embodiment of the present application.

[0110] In the present embodiment, a transmission delay time determination device is also provided, which is used to realize the above-mentioned embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that realizes a predetermined function. Although the devices described in the following embodiments are preferably realized in software, hardware, or a combination of software and hardware is also possible and contemplated.

[0111] Figure 6 The structure block diagram of a transmission delay time determination device according to an embodiment of the present application, the device comprises:

[0112] The first determination module 62 is configured to determine a first time when the first component sends a first message, a second time when the second component receives the first message, a third time when the second component sends a second message, and a fourth time when the first component receives the second message, wherein the second message is a message sent by the second component in response to the first message, the first time is a time when the first component has not eliminated a first sending delay time, the fourth time is a time when the first component has not eliminated a first receiving delay time, the first sending delay time is a transmission delay time of the first component, and the first receiving delay time is a transmission delay time of the first component.

[0113] The second determining module 64 is configured to determine an asymmetry time according to the first receiving delay time length, the first sending delay time length, a second receiving delay time length and a second sending delay time length, wherein the second receiving delay time length is a delay time of the second component receiving the packet, the second sending delay time length is a delay time of the second component sending the packet, and the asymmetry time is used to reflect an asymmetry between a first time and a second time, the first time being a transmission delay time of the packet from the first component to the second component, and the second time being a transmission delay time of the packet from the second component to the first component.

[0114] The third determining module 66 is configured to determine the first time and / or the second time according to the first time, the second time, the third time, the fourth time and the asymmetry time when the first preset condition is met at the second time and the second preset condition is met at the third time, wherein the first preset condition comprises that the second time is a time when the second component does not eliminate the second receiving delay time length, and the second preset condition comprises that the third time is a time when the second component does not eliminate the second sending delay time length.

[0115] The device determines the transmission delay time of the packet from the first component to the second component and / or the transmission delay time of the packet from the second component to the first component by considering the delay time of the first component sending the packet, the delay time of the first component receiving the packet, the delay time of the second component receiving the packet and the delay time of the second component sending the packet, thereby accurately determining the transmission delay time of the packet from the first component to the second component and / or the transmission delay time of the packet from the second component to the first component, and solving the problem that the transmission delay time of the packet cannot be accurately determined.

[0116] In an exemplary embodiment, the third determining module 66 is further configured to, when the first preset condition is not met at the second time and the second preset condition is not met at the third time, correct the second time by using the second receiving delay time length to obtain a corrected second time, correct the third time by using the second sending delay time length to obtain a corrected third time, and determine the first time and / or the second time according to the first time, the corrected second time, the corrected third time, the fourth time and the asymmetry time.

[0117] In an exemplary embodiment, the second determining module 54 is further configured to add the first receiving delay duration and the second sending delay duration to obtain a first intermediate value; add the first sending delay duration and the second receiving delay duration to obtain a second intermediate value; subtract the second intermediate value from the first intermediate value to obtain a third intermediate value; and determine half of the third intermediate value as the asymmetry time.

[0118] In an exemplary embodiment, the third determining module 56 is further configured to calculate the first time by Formula One below and calculate the second time by Formula Two below: wherein T ir is the first time, T ri is the second time, t1 is the first time point, t2 is the second time point, t3 is the third time point, t4 is the fourth time point, and T da is the asymmetry time.

[0119] In an exemplary embodiment, the apparatus further comprises a fourth determining module configured to, before determining the asymmetry time according to the first receiving delay duration, the first sending delay duration, the second receiving delay duration and the second sending delay duration, determine a first Ethernet interface standard of the first component for sending the packet, and determine the first sending delay duration from a first table according to the first Ethernet interface standard, wherein the first table has sending delay durations of the first component corresponding to different Ethernet interface standards; determine a second Ethernet interface standard of the first component for receiving the packet, and determine the first receiving delay duration from a second table according to the second Ethernet interface standard, wherein the second table has receiving delay durations of the first component corresponding to different Ethernet interface standards; determine a third Ethernet interface standard of the second component for sending the packet, and determine the second sending delay duration from a third table according to the third Ethernet interface standard, wherein the third table has sending delay durations of the second component corresponding to different Ethernet interface standards; and determine a fourth Ethernet interface standard of the second component for receiving the packet, and determine the second receiving delay duration from a fourth table according to the fourth Ethernet interface standard, wherein the fourth table has receiving delay durations of the second component corresponding to different Ethernet interface standards.

[0120] In an exemplary embodiment, the apparatus further comprises a fifth determining module configured to, after determining the first time and / or the second time, in a case where the second packet carries a local time of the second component, determine a time after delaying the local time of the second component by the second time as a local time of the first component.

[0121] Embodiments of the present application also provide a computer readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps in any of the method embodiments described above when running.

[0122] Optionally, in the embodiment, the storage medium described above can be configured to store a computer program for executing the following steps:

[0123] S1, determining a first time when a first component sends a first message, a second time when a second component receives the first message, a third time when the second component sends a second message, and a fourth time when the first component receives the second message, wherein the second message is a message sent by the second component in response to the first message, the first time is a time when the first component has not eliminated a first sending delay duration, the fourth time is a time when the first component has not eliminated a first receiving delay duration, the first sending delay duration is a delay time of the first component sending a message, and the first receiving delay duration is a delay time of the first component receiving a message;

[0124] S2, determining an asymmetry time according to the first receiving delay duration, the first sending delay duration, a second receiving delay duration, and a second sending delay duration, wherein the second receiving delay duration is a delay time of the second component receiving a message, the second sending delay duration is a delay time of the second component sending a message, and the asymmetry time is used to reflect an asymmetry between a first time and a second time, the first time is a transmission delay time of a message from the first component to the second component, and the second time is a transmission delay time of a message from the second component to the first component;

[0125] S3, in a case where the second time meets a first preset condition and the third time meets a second preset condition, determining the first time and / or the second time according to the first time, the second time, the third time, the fourth time, and the asymmetry time, wherein the first preset condition comprises that the second time is a time when the second component has not eliminated the second receiving delay duration, and the second preset condition comprises that the third time is a time when the second component has not eliminated the second sending delay duration.

[0126] In an example embodiment, the computer readable storage medium described above can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0127] The specific examples in the embodiments can refer to the examples described in the above embodiments and exemplary embodiments, which will not be repeated here.

[0128] The embodiments of the present application also provide a computer program product comprising a computer program which, when executed by a processor, performs the steps of any of the method embodiments.

[0129] The embodiments of the present application also provide an electronic device comprising a memory and a processor, the memory storing a computer program, and the processor being configured to run the computer program to perform the steps of any of the method embodiments.

[0130] Optionally, in the embodiments, the processor can be configured to perform the following steps by the computer program:

[0131] S1, determining a first time when a first component sends a first message, a second time when a second component receives the first message, a third time when the second component sends a second message, and a fourth time when the first component receives the second message, wherein the second message is a message sent by the second component in response to the first message, the first time is a time when the first component has not eliminated a first sending delay duration, the fourth time is a time when the first component has not eliminated a first receiving delay duration, the first sending delay duration is a delay time of the first component sending a message, and the first receiving delay duration is a delay time of the first component receiving a message;

[0132] S2, determining an asymmetry time according to the first receiving delay duration, the first sending delay duration, a second receiving delay duration, and a second sending delay duration, wherein the second receiving delay duration is a delay time of the second component receiving a message, the second sending delay duration is a delay time of the second component sending a message, and the asymmetry time is used to reflect an asymmetry between a first time and a second time, the first time is a transmission delay time of a message from the first component to the second component, and the second time is a transmission delay time of a message from the second component to the first component;

[0133] S3, in a case where the second time meets a first preset condition and the third time meets a second preset condition, determining the first time and / or the second time according to the first time, the second time, the third time, the fourth time, and the asymmetry time, wherein the first preset condition comprises that the second time is a time when the second component has not eliminated the second receiving delay duration, and the second preset condition comprises that the third time is a time when the second component has not eliminated the second sending delay duration.

[0134] In one example embodiment, the electronic device described above can further include a transmission device connected to the processor and an input / output device connected to the processor.

[0135] The specific examples in the present embodiment can refer to the examples described in the above embodiments and exemplary implementation, which will not be repeated here.

[0136] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be realized by general computing devices, which can be concentrated on a single computing device or distributed on a network composed of multiple computing devices, which can be realized by program codes executable by the computing devices, so that they can be stored in storage devices and executed by the computing devices, and in some cases, the steps shown or described can be executed in different order, or they can be made into individual integrated circuit modules, or multiple modules or steps can be made into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

[0137] The above description is only the preferred embodiments of the present application, and it should be pointed out that those skilled in the art can make several improvements and refinements without departing from the principles of the present application, and these improvements and refinements should be considered as the protection scope of the present application.

Claims

1. A method of determining a transmission delay time, characterized by, The method comprises: determining a first time when the first component sends the first message, a second time when the second component receives the first message, a third time when the second component sends a second message, and a fourth time when the first component receives the second message, wherein the second message is a message sent by the second component in response to the first message, the first time is a time when the first component has not eliminated a first sending delay time, the fourth time is a time when the first component has not eliminated a first receiving delay time, the first sending delay time is a delay time of the first component sending a message, and the first receiving delay time is a delay time of the first component receiving a message; and determining an asymmetry time according to the first receiving delay time, the first sending delay time, a second receiving delay time, and a second sending delay time, wherein the second receiving delay time is a delay time of the second component receiving a message, the second sending delay time is a delay time of the second component sending a message, and the asymmetry time is used to reflect an asymmetry between a first time and a second time, the first time is a transmission delay time of a message from the first component to the second component, and the second time is a transmission delay time of a message from the second component to the first component; in a case where the second time meets a first preset condition and the third time meets a second preset condition, determining the first time and / or the second time according to the first time, the second time, the third time, the fourth time, and the asymmetry time, wherein the first preset condition comprises that the second time is a time when the second component has not eliminated the second receiving delay time, and the second preset condition comprises that the third time is a time when the second component has not eliminated the second sending delay time.

2. The method of claim 1, wherein, The method further comprises: in a case where the second time does not meet the first preset condition and the third time does not meet the second preset condition, correcting the second time using the second receiving delay time to obtain a corrected second time, and correcting the third time using the second sending delay time to obtain a corrected third time; determining the first time and / or the second time according to the first time, the corrected second time, the corrected third time, the fourth time, and the asymmetry time.

3. The method of claim 1, wherein, Determining an asymmetry time according to the first receiving delay time, the first sending delay time, a second receiving delay time, and a second sending delay time comprises: adding the first receiving delay time to the second sending delay time to obtain a first intermediate value; and adding the first sending delay time to the second receiving delay time to obtain a second intermediate value; subtracting the second intermediate value from the first intermediate value to obtain a third intermediate value; determining half of the third intermediate value as the asymmetry time.

4. The method of claim 1, wherein, Determining the first time and / or the second time according to the first time, the second time, the third time, the fourth time, and the asymmetry time comprises: The first time is calculated by Formula One below and / or the second time is calculated by Formula Two below: wherein T ir is the first time, T ri is the second time, t1 is the first time, t2 is the second time, t3 is the third time, t4 is the fourth time, and T da is the asymmetry time.

5. The method of claim 1, wherein, Before determining the asymmetry time according to the first receiving delay duration, the first sending delay duration, the second receiving delay duration and the second sending delay duration, the method further comprises: determining a first Ethernet interface standard of the first component for sending the packet, and determining the first sending delay duration from a first table according to the first Ethernet interface standard, wherein the first table has corresponding sending delay durations of the first component under different Ethernet interface standards; determining a second Ethernet interface standard of the first component for receiving the packet, and determining the first receiving delay duration from a second table according to the second Ethernet interface standard, wherein the second table has corresponding receiving delay durations of the first component under different Ethernet interface standards; and determining a third Ethernet interface standard of the second component for sending the packet, and determining the second sending delay duration from a third table according to the third Ethernet interface standard, wherein the third table has corresponding sending delay durations of the second component under different Ethernet interface standards; and determining a fourth Ethernet interface standard of the second component for receiving the packet, and determining the second receiving delay duration from a fourth table according to the fourth Ethernet interface standard, wherein the fourth table has corresponding receiving delay durations of the second component under different Ethernet interface standards.

6. The method according to any one of claims 1-5, characterized in that, After determining the first time and / or the second time, the method further comprises: in the case that the second component's local time is carried in the second packet, determining the time after delaying the second component's local time by the second time as the first component's local time.

7. An apparatus for determining a transmission delay time, characterized by comprises: a first determining module, configured to determine a first time when a first component sends a first packet, a second time when a second component receives the first packet, a third time when the second component sends a second packet, and a fourth time when the first component receives the second packet, wherein the second packet is a packet sent by the second component in response to the first packet, the first time is a time when the first component has not eliminated a first sending delay duration, the fourth time is a time when the first component has not eliminated a first receiving delay duration, the first sending delay duration is a delay time of the first component for sending a packet, and the first receiving delay duration is a delay time of the first component for receiving a packet; a second determining module, configured to determine an asymmetry time according to the first receiving delay time length, the first sending delay time length, a second receiving delay time length and a second sending delay time length, wherein the second receiving delay time length is a delay time length of the second component receiving the packet, the second sending delay time length is a delay time length of the second component sending the packet, the asymmetry time is used to reflect asymmetry between a first time and a second time, the first time is a transmission delay time length of the packet from the first component to the second component, and the second time is a transmission delay time length of the packet from the second component to the first component; a third determining module, configured to determine the first time and / or the second time according to the first time, the second time, the third time, the fourth time and the asymmetry time in a case that the second time meets a first preset condition and the third time meets a second preset condition, wherein the first preset condition comprises that the second time is a time when the second component does not eliminate the second receiving delay time length, and the second preset condition comprises that the third time is a time when the second component does not eliminate the second sending delay time length.

8. A computer readable storage medium, characterized in that, The computer readable storage medium comprises a stored program, wherein the program performs the method in any one of claims 1 to 6 when running. 9.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is configured to execute the method in any one of claims 1 to 6 by using the computer program.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the method in any one of claims 1 to 6.

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