A method for manufacturing a buried circuit carrier with reduced or no circuit subsidence

Abstract

The present invention discloses a method for manufacturing a buried circuit substrate with reduced or no circuit sag. In this case, a second metal seed layer (such as a titanium metal layer) with a selective etching effect is added to the strippable copper foil layer, so that the strippable copper foil layer is first etched and then the second metal seed layer is etched in the subsequent etching step, thereby effectively controlling the circuit sag problem during the etching process, so that the circuit can maintain the flatness with the surface of the dielectric layer after etching, and even achieve no circuit sag, meeting the requirements of some application fields for no sag or sag <2um for the buried layer circuit of the packaging substrate. In addition, the method of this case can add a third metal seed layer (such as a copper metal layer) when it is detected that the resistance value of the current circuit carrier circuit is too high, while meeting the overall conductive performance of the carrier, further controlling the circuit sag problem during the etching process.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board processing, and in particular to a method for manufacturing an embedded circuit carrier with reduced or no circuit sinking. Background Art

[0002] Embedded circuit board is an advanced circuit board manufacturing technology, which is characterized by embedding circuits or components into the interior of the substrate, thereby achieving a more compact and higher-density circuit design.

[0003] The existing method of embedding circuit substrates is to electroplate the embedded circuit layer on a thin copper layer (called seed layer in the industry), and then etch away the seed layer after the circuit is embedded in the dielectric layer; as shown in the figure Figure 1-1 to Figure 1-5 As shown, it is a conventional process flow chart of embedded circuit substrate manufacturing, and its manufacturing method is: cutting of peelable substrate (reference Figure 1-1 ) → Electroplating circuit pattern layer on the peelable copper foil layer of the peelable carrier (reference Figure 1-2 )→ Upper dielectric layer (reference Figure 1-3 ) → Peel off the peelable carrier (reference Figure 1-4 ) → Etching can peel off the copper foil layer (reference Figure 1-5 ). However, the above existing method of embedding the circuit substrate will cause the buried layer circuit to sink to 5-7um relative to the surface of the dielectric layer when the seed layer is completely etched. The 5-7um sinking will increase the difficulty of subsequent packaging and the reliability after packaging. In addition, some application field chips require that the buried layer circuit of the packaging substrate has no sinking, or the sinking is less than 2um to complete the packaging and form a qualified packaged product with good reliability, and the above method of embedding the circuit substrate cannot meet this requirement.

[0004] Therefore, how to overcome the above-mentioned defects has become an important issue to be solved urgently by those skilled in the art. Summary of the invention

[0005] The present invention overcomes the shortcomings of the above-mentioned technology and provides a method for manufacturing an embedded circuit carrier with reduced or no circuit subsidence.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] The present invention discloses a method for manufacturing an embedded circuit carrier with reduced or no circuit subsidence, comprising the following steps:

[0008] Step A, preparing a peelable carrier; wherein the peelable carrier is provided with a peelable copper foil layer as a first metal seed layer;

[0009] Step B, forming a metal layer with a selective etching effect on the basis of the strippable copper foil layer to serve as a second metal seed layer;

[0010] Step C, testing the resistance of the current circuit carrier circuit, if it is determined that the resistance is higher than the preset conductivity resistance, if yes, then adding another metal layer as the third metal seed layer; if no, then no processing is required;

[0011] Step D, electroplating a circuit pattern layer on the basis of the second metal seed layer / the third metal seed layer;

[0012] Step E, covering the circuit pattern layer with a dielectric layer;

[0013] Step F, peeling off the peelable carrier plate at the bottom;

[0014] Step G: etching the circuit substrate after the peelable substrate is peeled off to form a substrate with embedded circuits.

[0015] Preferably, the second metal seed layer is a titanium metal layer.

[0016] Preferably, the thickness of the third metal seed layer is smaller than that of the first metal seed layer.

[0017] Preferably, the third metal seed layer is a copper metal layer.

[0018] Preferably, the "performing etching treatment to form a carrier having embedded circuits" in step G is performed by etching sequentially from the bottom layer upwards.

[0019] Preferably, the strippable copper foil layer is divided into a strippable layer and a copper foil layer.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. This case adds a second metal seed layer (such as a titanium metal layer) with a selective etching effect on the strippable copper foil layer, so that in the subsequent etching step, the strippable copper foil layer is etched first and then the second metal seed layer is etched, thereby effectively controlling the circuit sag problem during the etching process, so that the circuit can maintain the flatness with the surface of the dielectric layer after etching, and even achieve no circuit sag, meeting the requirements of some application fields for no sag or sag <2um for the buried layer circuit of the packaging substrate. In addition, the method of this case can add a third metal seed layer (such as a copper metal layer) when it is detected that the resistance value of the current circuit carrier circuit is too high, while meeting the overall conductive performance of the carrier, further controlling the circuit sag problem during the etching process.

[0022] 2. In this case, a thinner copper layer (third metal seed layer) is formed on the surface of the second metal seed layer, so that the etching depth can be more easily controlled during the etching process, so as to ensure that the copper layer is completely etched away, while avoiding unnecessary damage to the buried copper circuit, thereby effectively controlling the sink depth to less than 2um. In addition, the thinner copper layer will be removed faster during the etching process, and it is easier to achieve uniform etching, avoiding the problem of inconsistent circuit sinking caused by uneven etching, so as not to have a significant impact on the buried copper circuit, and can be applied to the buried circuit substrate for controlling the sink depth to less than 2um. Moreover, the thinner copper layer means a reduction in the amount of material used, thereby reducing material costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a flow chart of the method for manufacturing the embedded circuit carrier board in this case.

[0024] Figure 1-1 to Figure 1-5 Shown is a flow chart of the traditional manufacturing process of embedded circuit substrate.

[0025] Figure 2-1 to Figure 2-7 It is a process flow chart of manufacturing the embedded circuit carrier in the first embodiment.

[0026] Figure 3-1 to Figure 3-8 It is a process flow chart of manufacturing the embedded circuit carrier in the second embodiment.

[0027] in, Figure 2-1 Schematic diagram of the structure of the peelable carrier in step A of embodiment 1. Figure 2-2 It is a schematic diagram of the structure after the second metal seed layer is formed in step B of embodiment 1. Figure 2-3 It is a schematic diagram of the structure after the circuit pattern layer is electroplated on the second metal seed layer in step D. Figure 2-4 It is a schematic diagram of the structure after covering the dielectric layer in step E. Figure 2-5 It is a schematic diagram of the structure after the bottom peelable carrier plate is peeled off in step F. Figure 2-6 It is a schematic diagram of the structure after etching the first metal seed layer in step G. Figure 2-7 It is a schematic diagram of the structure of the second metal seed layer after etching in step G.

[0028] Figure 3-1 It is a schematic diagram of the structure of the peelable carrier in step A of embodiment 2. Figure 3-2 It is a schematic diagram of the structure after the second metal seed layer and the third metal seed layer are formed in sequence in step B and step C of embodiment 2. Figure 3-3 It is a schematic diagram of the structure after the circuit pattern layer is electroplated on the third metal seed layer in step D. Figure 3-4 It is a schematic diagram of the structure after covering the dielectric layer in step E. Figure 3-5 It is a schematic diagram of the structure after the bottom peelable carrier plate is peeled off in step F.

[0029] Figure 3-6 It is a schematic diagram of the structure after etching the first metal seed layer in step G. Figure 3-7 It is a schematic diagram of the structure of the second metal seed layer after etching in step G. Figure 3-8 It is a schematic diagram of the structure of the third metal seed layer after etching in step G. DETAILED DESCRIPTION

[0030] The features of the present invention and other related features are further described in detail below through embodiments to facilitate understanding by those skilled in the art:

[0031] Embodiment 1

[0032] like Figure 1 As shown, a method for manufacturing an embedded circuit substrate with reduced or no circuit subsidence comprises the following steps:

[0033] Step A: prepare a peelable carrier, and provide a peelable copper foil layer on the peelable carrier as a first metal seed layer; in specific implementation, the peelable carrier is provided with a carrier layer 11, a carrier copper foil layer 12 provided on the carrier layer 11, and the peelable copper foil layer 13 provided on the carrier copper foil layer 12. The peelable copper foil layer is divided into a copper foil layer 131 and a peelable layer 132.

[0034] Step B, forming a metal layer with a selective etching effect on the basis of the strippable copper foil layer to serve as the second metal seed layer 2;

[0035] Step C: determining that the resistance value is not higher than the preset conductive resistance value, and no need to add a third metal seed layer;

[0036] Step D, electroplating a circuit pattern layer 4 on the basis of the second metal seed layer;

[0037] Step E, covering the circuit pattern layer with a dielectric layer 5;

[0038] Step F, peeling off the peelable carrier plate at the bottom;

[0039] Step G, etching the circuit carrier after peeling off the strippable carrier to form a carrier with embedded circuits. In specific implementation, the second metal seed layer can be formed on the strippable copper foil layer by physical vapor deposition or other metal thin film build-up techniques.

[0040] As described above, this case adds a second metal seed layer (such as a titanium metal layer) with a selective etching effect on the strippable copper foil layer, so that in the subsequent etching step, the strippable copper foil layer is etched first and then the second metal seed layer is etched, thereby effectively controlling the circuit sag problem during the etching process, so that the circuit can maintain the flatness with the surface of the dielectric layer after etching, and even achieve no circuit sag, meeting the requirements of some application fields for no sag or sag <2um for the buried layer circuit of the packaging substrate. In addition, the method of this case can add a third metal seed layer (such as a copper metal layer) when it is detected that the resistance value of the current circuit carrier circuit is too high, while meeting the overall conductive performance of the carrier, further controlling the circuit sag problem during the etching process.

[0041] As a preferred embodiment, since titanium metal has a lower etching rate for commonly used etchants (such as copper etchants), while copper is relatively easy to etch. Therefore, the second metal seed layer in this case is designed to be a titanium metal layer. In this way, the titanium metal layer can be used as a protective layer during the etching process to reduce or prevent the underlying copper circuit from being over-etched, thereby avoiding the problem of circuit subsidence. In specific implementation, titanium etching solution and copper etchant are used for etching the titanium metal layer and the copper metal layer, respectively. Etching the titanium metal layer is not likely to cause etching effects on the copper metal layer, and etching the copper metal layer is not likely to cause etching effects on the titanium metal layer.

[0042] As a preferred embodiment, the thickness of the third metal seed layer is less than that of the first metal seed layer. The third metal seed layer is a thinner and easier to etch copper metal layer. In specific implementation, etching can be performed by stripping the copper foil layer and then etching the titanium metal layer, and finally etching the thinner and easier to etch copper metal layer.

[0043] As described above, since the thickness of the third metal seed layer is less than that of the first metal seed layer, the third metal seed layer is relatively thin, which makes it easier to control the etching depth during the etching process, so as to ensure that the copper layer is completely etched away, while avoiding unnecessary damage to the buried copper circuit, thereby effectively controlling the sink depth to be below 2um. In addition, the thinner copper layer (third metal seed layer) will be removed faster during the etching process, and it is easier to achieve uniform etching, avoiding the problem of circuit sink inconsistency caused by uneven etching, so as not to significantly affect the buried copper circuit, and can be applied to the buried circuit substrate for controlling the sink depth to less than 2um. Moreover, the thinner copper layer means a reduction in material usage, thereby reducing material costs.

[0044] As a preferred embodiment, the step G of "carrying out etching to form a carrier with embedded circuits" is to perform etching in sequence from the bottom layer to the top layer. In this way, by etching the bottom layer from the bottom layer to the top layer, the etching depth and uniformity can be more accurately controlled, the risk of over-etching and under-etching can be reduced, and the quality and reliability of the carrier can be further improved.

[0045] Embodiment 2

[0046] like Figures 3-1 to 3-8 As shown, a method for manufacturing an embedded circuit substrate with reduced or no circuit subsidence comprises the following steps:

[0047] Step A: prepare a peelable carrier, and provide a peelable copper foil layer on the peelable carrier as a first metal seed layer; in specific implementation, the peelable carrier is provided with a carrier layer 11, a carrier copper foil layer 12 provided on the carrier layer 11, and the peelable copper foil layer 13 provided on the carrier copper foil layer 12. The peelable copper foil layer is divided into a copper foil layer 131 and a peelable layer 132.

[0048] Step B, forming a metal layer with a selective etching effect on the basis of the strippable copper foil layer to serve as the second metal seed layer 2;

[0049] Step C: determining that the resistance value is higher than the preset conductive resistance value, adding a metal layer as the third metal seed layer 3;

[0050] Step D, electroplating a circuit pattern layer 4 on the basis of the third metal seed layer;

[0051] Step E, covering the circuit pattern layer with a dielectric layer 5;

[0052] Step F, peeling off the peelable carrier plate at the bottom;

[0053] Step G: etching the circuit substrate after the peelable substrate is peeled off to form a substrate with embedded circuits.

[0054] As mentioned above, this case protects a method for manufacturing an embedded circuit carrier with reduced or no circuit subsidence, and all technical solutions that are the same or similar to this case should be deemed to fall within the scope of protection of this case.

Claims

1. A method for manufacturing a buried circuit substrate with reduced or no circuit subsidence, characterized in that: The steps include: Step A, preparing a peelable carrier; wherein the peelable carrier is provided with a peelable copper foil layer as a first metal seed layer; Step B, forming a metal layer with a selective etching effect on the basis of the strippable copper foil layer to serve as a second metal seed layer; Step C, testing the resistance of the current circuit carrier circuit, if it is determined that the resistance is higher than the preset conductivity resistance, if yes, then adding another metal layer as the third metal seed layer; if no, then no processing is required; Step D, electroplating a circuit pattern layer on the basis of the second metal seed layer / the third metal seed layer; Step E, covering the circuit pattern layer with a dielectric layer; Step F, peeling off the peelable carrier plate at the bottom; Step G, etching the circuit carrier after peeling off the peelable carrier to form a carrier with embedded circuits; Wherein, the thickness of the third metal seed layer is smaller than that of the first metal seed layer.

2. The method for manufacturing a substrate with embedded circuits according to claim 1, characterized in that: The second metal seed layer is a titanium metal layer.

3. The method for manufacturing a substrate with embedded circuits according to claim 1, characterized in that: The third metal seed layer is a copper metal layer.

4. The method for manufacturing a substrate with embedded circuits according to claim 1, characterized in that: The step G of "performing etching to form a carrier having embedded circuits" is performed by etching from the bottom layer upwards.

5. The method for manufacturing a substrate with embedded circuits according to claim 1, characterized in that: The strippable copper foil layer is divided into a strippable layer and a copper foil layer.

Images