Semiconductor device

Abstract

In a semiconductor device (100), a gate electrode (140) includes a junction portion (141) which is in Schottky junction with a barrier layer (104), and a protruding portion (142d) which protrudes beyond the junction portion (141). An insulating layer (130) includes a first side wall (133d) and a second side wall (133s). The protruding portion (142d) includes a first gate field plate (143) and a second gate field plate (144). A lower surface highest position (P2) of the first gate field plate (143) has a tilt with a second elevation angle (θ2) from a first position (P0), and a drain electrode electrode side end (P3) of a lower surface lowest position of the second gate field plate (144) has a tilt with a third elevation angle (θ2) from the first position (P0). The second elevation angle (θ2) is larger than the third elevation angle (θ3). A lower surface of the second gate field plate (144) includes a monotonously increasing inclined surface (144c).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device, and particularly to a Group III nitride semiconductor device using a Group III nitride semiconductor. BACKGROUND

[0002] A Group III nitride semiconductor device using a Group III nitride semiconductor, particularly gallium nitride (GaN) or aluminum gallium nitride (AlGaN), has a high insulation breakdown voltage due to the width of the band gap of the material. Further, in a Group III nitride semiconductor device, a hetero structure of AlGaN / GaN or the like can be easily formed.

[0003] In the AlGaN / GaN hetero structure, a channel of a high concentration of electrons (hereinafter referred to as "two-dimensional electron gas") is formed on the GaN layer side of the AlGaN / GaN interface by piezoelectric polarization due to the difference in the lattice constant between the materials and spontaneous polarization of AlGaN and GaN. A Group III nitride semiconductor device using the channel of the two-dimensional electron gas is applied to a high-frequency power device because the electron saturation velocity is relatively high and the insulation resistance is relatively high, and the thermal conductivity is also relatively high.

[0004] With respect to these Group III nitride semiconductor devices, in order to improve the characteristics, it is effective to miniaturize the gate size (hereinafter denoted by Lg). Further, in the miniaturization of Lg, it is important to take into account both the field relaxation using a field plate and the reduction of the parasitic capacitance.

[0005] Figure 19 is a cross-sectional view showing the structure of the gate electrode 140x of the related art. Specifically, Figure 19 shows the structure in the vicinity of the gate electrode 140x in the semiconductor device 100x composed of a Group III nitride described in Patent Document 1.

[0006] In the semiconductor device 100x described in Patent Document 1, as shown in Figure 19 , a GaN layer 103x and an AlGaN layer 104x are provided in this order, and a two-dimensional electron gas 110x is generated on the GaN layer 103x side by the hetero structure. An insulating layer 130x is provided on the AlGaN layer 104x, and an opening portion 130Ax is provided in the insulating layer 130x to expose the AlGaN layer 104x. A first side wall 133dx on the drain electrode side and a second side wall 133sx on the source electrode side are provided in the opening portion 130Ax in such a manner as to come into contact with the side surface of the insulating layer 130x. Further, although not shown in the drawing, a gate electrode is provided on the GaN layer 103x side of the insulating layer 130x. Figure 19The drain electrode is disposed on the positive side of the X-axis with respect to the gate electrode 140x, and the source electrode is disposed on the negative side of the X-axis with respect to the gate electrode 140x. The drain electrode and the source electrode are ohmically connected to the two-dimensional electron gas 110x, respectively. The so-called cross-sectional shape of the gate electrode 140x is set to a T shape (T-shaped gate structure) to cover the insulating layer 130x and the opening portion 130Ax. It is described in Patent Document 1 that the Lg can be reduced by about 0.1 μm to about 0.3 μm by the T-shaped gate structure.

[0007] Prior Art Documents

[0008] Patent Documents

[0009] Patent Document 1: U.S. Patent Application Publication No. 2012 / 0119260 Specification SUMMARY

[0010] Problems to be Solved by the Invention

[0011] According to the structure described in Patent Document 1 described above, the parasitic capacitance between the gate electrode 140x and the drain electrode can be reduced by the insulating layer 130x interposed between the T-shaped gate electrode 140x and the AlGaN layer 104x. On the other hand, in the structure shown in FIG. 1, the electric field relaxation is insufficient. Specifically, in the T-shaped gate electrode 140x, a higher electric field is likely to be locally concentrated at the end portion of the portion of the gate electrode 140x that protrudes onto the insulating layer 130x on the drain electrode side. Thus, there is a first problem that the electric field relaxation and the reduction of the parasitic capacitance cannot be both satisfied. Figure 19

[0012] Further, in the T-shaped gate electrode 140x, the electron density of the two-dimensional electron gas 110x is high directly below the insulating layer 130x and the side walls 133dx and 133sx, so that the on-resistance can be reduced. On the other hand, in the structure shown in FIG. 1, the off characteristics are degraded. Specifically, when the transistor is off, the electric field generated directly below the gate electrode 140x is weak, so that the depletion layer is not easily expanded, and the off-leakage current between the source and the drain is likely to occur. Thus, there is a second problem that the reduction of the on-resistance and the improvement of the off characteristics cannot be both satisfied. Figure 19

[0013] Therefore, an object of the present disclosure is to provide a semiconductor device that can achieve at least one of (i) a balance between the electric field relaxation and the reduction of the parasitic capacitance or (ii) a balance between the reduction of the on-resistance and the improvement of the off characteristics.

[0014] Means for Solving the Problems

[0015] ​​To achieve the above object, a semiconductor device according to the present disclosure includes: a substrate; a channel layer provided above the substrate and composed of a Group III nitride semiconductor; a barrier layer provided above the channel layer and composed of a Group III nitride semiconductor having a larger band gap than the channel layer; a source electrode and a drain electrode provided above the barrier layer and spaced apart from each other in a first direction in a plan view of the substrate; a gate electrode provided between the source electrode and the drain electrode and spaced apart from them in the first direction; and an insulating layer provided above the barrier layer between the gate electrode and the source electrode and the drain electrode; the insulating layer includes a first insulating layer composed of silicon nitride at a lowermost layer and a second insulating layer composed of silicon oxide above the first insulating layer; the gate electrode includes a junction portion that is in Schottky junction with the barrier layer, and an extension portion that extends toward the source electrode side and the drain electrode side, respectively, than the junction portion in the first direction; between the extension portion and the barrier layer in a second direction orthogonal to a main surface of the substrate, the insulating layer includes a first side wall provided at a junction portion side end of the insulating layer between the junction portion and the drain electrode, and a second side wall provided at a junction portion side end of the insulating layer between the junction portion and the source electrode; the extension portion includes a first electric field plate of an interval from a first position to a second position in the plan view, the first position being the junction portion side end of the first side wall, and the second position being a drain electrode side end of the first side wall, and a second electric field plate of an interval from the second position to a third position in the plan view, the third position being a drain electrode side end of the extension portion; the first insulating layer and the second insulating layer are stacked between the second electric field plate and the barrier layer; in a cross section parallel to the first direction and the second direction and passing through the junction portion, a tangent line at the first position of an upper surface of the first side wall has a first inclination with respect to the main surface; a lowermost position of an upper surface of the first electric field plate has a second inclination with respect to the main surface from the first position; a drain electrode side end of a lowermost position of an upper surface of the second electric field plate has a third inclination with respect to the main surface from the first position; the second inclination is larger than the third inclination; and an upper surface of the second electric field plate includes an inclined surface in which a spacing between the barrier layer and the second electric field plate monotonously increases in a direction from the gate electrode to the drain electrode.

[0016] Furthermore, another technical solution of the semiconductor device disclosed herein includes: a substrate; a channel layer disposed above the substrate and made of a group III nitride semiconductor; a barrier layer disposed above the channel layer and made of a group III nitride semiconductor with a band gap larger than that of the channel layer; a source electrode and a drain electrode disposed above the barrier layer and spaced apart from each other in a first direction in plan view of the substrate; a gate electrode disposed in the first direction spaced apart from the source electrode and the drain electrode; and an insulating layer disposed between the gate electrode and the source electrode and the drain electrode. The electrodes are disposed above the aforementioned barrier layer; the aforementioned insulating layer includes a first insulating layer made of silicon nitride as the lowest layer and a second insulating layer made of silicon oxide above the first insulating layer; the aforementioned gate electrode includes: a junction portion, which is Schottky bonded to the aforementioned barrier layer; and a protrusion portion, which extends in the aforementioned first direction beyond the aforementioned junction portion toward the source electrode side and the aforementioned drain electrode side, respectively; between the aforementioned protrusion portion and the aforementioned barrier layer in the second direction orthogonal to the main surface of the aforementioned substrate, the aforementioned insulating layer includes: a first sidewall, which is disposed between the aforementioned junction portion and the aforementioned drain electrode of the aforementioned insulating layer. The extension includes: a first electric field plate extending from a first position to a second position in the top view, the first position being the joint end of the first sidewall, and the second position being the drain electrode end of the first sidewall; and a second electric field plate extending from the second position to a third position in the top view, the third position being the drain electrode end of the extension; and between the second electric field plate and the barrier layer, a first insulating layer and an upper insulating layer are stacked. The second insulating layer; in a cross section parallel to the first direction and the second direction and passing through the joint, the tangent at the first position on the upper surface of the first sidewall has an inclination of a first elevation angle relative to the main surface; the highest position of the lower surface of the first electric field plate has an inclination of a second elevation angle relative to the main surface when viewed from the first position; the drain electrode side end at the lowest position of the lower surface of the second electric field plate has an inclination of a third elevation angle relative to the main surface when viewed from the first position; the highest position of the upper surface of the first sidewall is lower than the highest position of the upper surface of the second sidewall.

[0017] Invention Effects

[0018] The semiconductor device according to this disclosure can achieve at least one of (i) a balance between electric field mitigation and reduction of parasitic capacitance, or (ii) a balance between low on-resistance and improved cut-off characteristics. Attached Figure Description

[0019] Figure 1is a cross-sectional view showing the structure of the semiconductor device of Embodiment 1.

[0020] Figure 2 is a cross-sectional view showing the structure of the gate electrode of the semiconductor device of Embodiment 1 in an enlarged manner.

[0021] Figure 3 is an enlarged cross-sectional view for illustrating the shape of the lower surface of the extension portion on the drain electrode side of the gate electrode of the semiconductor device of Embodiment 1.

[0022] Figure 4A is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 1.

[0023] Figure 4B is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 1.

[0024] Figure 4C is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 1.

[0025] Figure 4D is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 1.

[0026] Figure 4E is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 1.

[0027] Figure 4F is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 1.

[0028] Figure 4G is a cross-sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 1.

[0029] Figure 5 is a cross-sectional view showing the structure of the gate electrode of the semiconductor device of Embodiment 1.

[0030] Figure 6 is an enlarged cross-sectional view for illustrating the shape of the lower surface of the extension portion on the drain electrode side of the gate electrode of the semiconductor device of Embodiment 1.

[0031] Figure 7 is a cross-sectional view showing the structure of the gate electrode of the semiconductor device of Embodiment 1.

[0032] Figure 8 is an enlarged cross-sectional view for illustrating the shape of the lower surface of the extension portion on the drain electrode side of the gate electrode of the semiconductor device of Embodiment 1.

[0033] Figure 9FIG. 6 is an enlarged sectional view for explaining the positional relationship between the lower surface of the gate electrode of the semiconductor device of Embodiment 1 and the source field plate.

[0034] Figure 10 FIG. 7 is a sectional view showing the structure of the gate electrode of the semiconductor device of Embodiment 2.

[0035] Figure 11 FIG. 8 is an enlarged sectional view for explaining the shape of the side wall of the semiconductor device of Embodiment 2.

[0036] Figure 12 FIG. 9 is an enlarged sectional view for explaining the shape of the lower surface of the protruding portion on the drain electrode side of the gate electrode of the semiconductor device of Embodiment 2.

[0037] Figure 13A FIG. 10 is a sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 2.

[0038] Figure 13B FIG. 11 is a sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 2.

[0039] Figure 13C FIG. 12 is a sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 2.

[0040] Figure 13D FIG. 13 is a sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 2.

[0041] Figure 13E FIG. 14 is a sectional view showing each step of the manufacturing method of the semiconductor device of Embodiment 2.

[0042] Figure 14 FIG. 15 is an enlarged sectional view for explaining the shape of the side wall of the semiconductor device of Modification 1 of Embodiment 2.

[0043] Figure 15 FIG. 16 is an enlarged sectional view for explaining the shape of the side wall of the semiconductor device of Modification 2 of Embodiment 2.

[0044] Figure 16 FIG. 17 is an enlarged sectional view for explaining the shape of the side wall of the semiconductor device of Modification 3 of Embodiment 2.

[0045] Figure 17 FIG. 18 is an enlarged sectional view for explaining the shape of the side wall of the semiconductor device of Modification 4 of Embodiment 2.

[0046] Figure 18 FIG. 19 is an enlarged sectional view for explaining the shape of the side wall of the semiconductor device of Modification 5 of Embodiment 2.

[0047] Figure 19 is a sectional view showing a structure of a gate electrode of a related art. DETAILED DESCRIPTION

[0048] Hereinafter, a specific embodiment of a semiconductor device and the like of one aspect of the present disclosure will be described with reference to the drawings.

[0049] The embodiments described below indicate one specific example of the present disclosure. Thus, the numerical values, shapes, materials, component elements, arrangement positions and connection modes of the component elements, and steps (processes) and the order of the steps and the like indicated in the following embodiments are given as one example and are not intended to limit the present disclosure. Furthermore, regarding the component elements of the following embodiments, the component elements not recited in the independent claims are assumed to be arbitrary component elements.

[0050] Furthermore, each drawing is a schematic view and is not necessarily strictly illustrated. In each drawing, the same reference signs are given to substantially the same structures, and repeated description is omitted or simplified.

[0051] Furthermore, in the present specification, the terms indicating the relationship between elements such as parallel or perpendicular, the terms indicating the shape of the elements such as rectangle, and the numerical range are not intended to represent only the strict meaning but are intended to represent a substantially equivalent range, for example, a representation including a difference of several percent or so.

[0052] Furthermore, in the present specification, the terms such as "upper" and "lower" in the structure of the semiconductor device are not terms indicating the upper (vertically upward) and the lower (vertically downward) in the absolute spatial recognition, but are terms defined by the relative positional relationship based on the stacking order in the stacked structure. Furthermore, the terms such as "upper" and "lower" are applicable not only to the case where two component elements are arranged apart from each other with a space and there are other component elements between the two component elements, but also to the case where two component elements are arranged in contact with each other and the two component elements are in contact with each other.

[0053] Furthermore, in the present specification and the drawings, the X axis, the Y axis, and the Z axis represent three axes of a three-dimensional orthogonal coordinate system. In each embodiment, two axes parallel to a main surface (upper surface) included in a substrate possessed by the semiconductor device are assumed to be the X axis and the Y axis, and a direction orthogonal to the main surface is assumed to be the Z axis direction. Specifically, a direction in which a source electrode, a gate electrode, and a drain electrode are arranged in this order, that is, a so-called gate length direction is assumed to be the X axis direction. The X axis direction is one example of a first direction. Furthermore, the Z axis direction is one example of a second direction. In the embodiments described below, there are cases where the positive direction of the Z axis is described as "upper" and the negative direction of the Z axis is described as "lower". Furthermore, "plan view" described in the present specification means a view in which a main surface (upper surface) of a substrate possessed by the semiconductor device is observed from the positive direction of the Z axis, unless specifically stated otherwise.

[0054] Further, in the present specification, a Group III nitride semiconductor is a semiconductor containing one or more Group III elements and nitrogen. The Group III element is, for example, aluminum (Al), gallium (Ga), indium (In), or the like. Examples of the Group III nitride semiconductor are GaN, AlN, InN, AlGaN, InGaN, AlInGaN, and the like. In the Group III nitride semiconductor, one or more elements other than Group III, such as silicon (Si), phosphorus (P), or the like, can be contained. In addition, in the following description, in the case where the Group III nitride semiconductor is described as AlInGaN without a specific declaration, the Group III nitride semiconductor means all of Al, In, Ga, and N are contained. The same applies to other descriptions such as AlGaN, GaN, and the like.

[0055] Further, the layer composed of a Group III nitride semiconductor and the layer composed of a Group III nitride semiconductor mean that the layer substantially contains only a Group III nitride semiconductor. However, in the layer, for example, other elements, such as elements that cannot be avoided from being mixed in the manufacturing process, can be contained as impurities at a rate of 1 at% or less.

[0056] Further, in the present specification, the composition ratio (composition rate) of the Group III element of the nitride semiconductor (layer) indicates the ratio of the number of atoms of the Group III element as the object among the plurality of Group III elements contained in the nitride semiconductor. For example, in the case where the nitride semiconductor layer is composed of Al a In b Ga c N (a + b + c = 1, a > 0, b > 0, c > 0), the Al composition ratio of the nitride semiconductor layer can be represented by a / (a + b + c). Similarly, the In composition ratio and the Ga composition ratio are represented by b / (a + b + c) and c / (a + b + c), respectively.

[0057] Further, in the present specification, regarding ordinal numbers such as "first", "second", and the like, unless specifically declared, they do not refer to the number or order of the constituent elements, but are used in order to avoid confusion of the same constituent elements and to distinguish them.

[0058] (Embodiment 1)

[0059] First, the structure of the semiconductor device of Embodiment 1 will be described with reference to FIGS. 1A and 1B. Figures 1-3 The semiconductor device of Embodiment 1 will be described.

[0060] Figure 1 is a cross-sectional view indicating the structure of the semiconductor device 100 of Embodiment 1. Figure 2 is a cross-sectional view in which the structure of the gate electrode 140 of the semiconductor device 100 of Embodiment 1 is enlarged and indicated.

[0061] Figure 3 This is an enlarged cross-sectional view illustrating the shape of the lower surface 144a of the protrusion 142d on the drain electrode 122 side of the gate electrode 140 of the semiconductor device 100 in Embodiment 1. Additionally, Figures 1-3 Both represent the cross-section (XZ section) of the junction 141, which is orthogonal to the main surface of the substrate 101 and in the arrangement direction (X-axis direction) of the source electrode 121 and drain electrode 122, and passes through the Schottky junction of the gate electrode 140 and the barrier layer 104. Regarding... Figure 4A The same applies to subsequent sectional views.

[0062] In this embodiment, the case where the semiconductor device 100 is a high electron mobility transistor (HEMT) having a Schottky junction gate structure will be described.

[0063] like Figure 1 As shown, the semiconductor device 100 includes a substrate 101, a buffer layer 102, a channel layer 103, a barrier layer 104, a two-dimensional electron gas 110, a source electrode 121, a drain electrode 122, a source field plate 123, a T-type gate electrode 140, an insulating layer 130, and a fourth insulating layer 134. The insulating layer 130 includes a first insulating layer 131, a second insulating layer 132, a first sidewall 133d, and a second sidewall 133s.

[0064] The substrate 101 is, for example, a substrate made of Si. The substrate 101 is not limited to a substrate made of Si, but may also be a substrate made of sapphire, SiC, GaN or AlN.

[0065] A buffer layer 102 is disposed above the substrate 101. For example, the buffer layer 102 is disposed in contact with the upper surface of the substrate 101. The buffer layer 102 is, for example, a layer made of a group III nitride semiconductor. As an example, the buffer layer 102 is composed of multiple stacked layers of AlN and AlGaN with a thickness of 2 μm. In addition, the buffer layer 102 may be composed of a single layer or multiple layers of group III nitride semiconductors such as GaN, AlGaN, AlN, InGaN, and AlInGaN. Alternatively, the buffer layer 102 may not be provided.

[0066] The channel layer 103 is provided above the substrate 101. For example, the channel layer 103 is provided in contact with an upper surface of the buffer layer 102. The channel layer 103 is a layer composed of a Group III nitride semiconductor. The channel layer 103 is composed of, for example, GaN with a thickness of 200 nm. Note that the channel layer 103 is not limited to GaN, and can be composed of a Group III nitride semiconductor such as InGaN, AlGaN, AlInGaN, or the like. Further, the channel layer 103 can contain an n-type impurity. The thickness of the channel layer 103 is not limited to the above example.

[0067] The barrier layer 104 is provided above the channel layer 103. For example, the barrier layer 104 is provided in contact with an upper surface of the channel layer 103. The barrier layer 104 is a layer composed of a Group III nitride semiconductor having a larger band gap than the channel layer 103. The barrier layer 104 is composed of, for example, AlGaN with a thickness of 20 nm and an Al composition ratio of 25 %. A high-concentration two-dimensional electron gas 110 is generated on the channel layer 103 side of a heterojunction interface between the barrier layer 104 and the channel layer 103. The two-dimensional electron gas 110 is used as a channel of the transistor.

[0068] Note that the barrier layer 104 is not limited to AlGaN, and can be composed of a Group III nitride semiconductor such as AlInGaN or the like. Further, the barrier layer 104 can contain an n-type impurity. The thickness and the Al composition ratio of the barrier layer 104 are not limited to the above example.

[0069] Further, on the barrier layer 104, a cap layer composed of, for example, GaN with a thickness of about 1 nm to about 2 nm can be provided as a cap layer. Further, between the channel layer 103 and the barrier layer 104, a spacer layer composed of, for example, AlN with a thickness of about 1 nm can be provided as a spacer layer. In this way, the channel layer 103 and the barrier layer 104 can not be in contact.

[0070] The source electrode 121 and the drain electrode 122 are provided apart from each other above the barrier layer 104. Specifically, the source electrode 121 and the drain electrode 122 are provided so as to face each other with the gate electrode 140 interposed therebetween.

[0071] The source electrode 121 and the drain electrode 122 are formed using an electrically conductive material. For example, the source electrode 121 and the drain electrode 122 are a multilayer electrode film composed of a stacked structure in which a Ti film and an Al film are sequentially stacked, but are not limited thereto. In addition, the source electrode 121 and the drain electrode 122 are not limited to the stacked structure of the Ti film and the Al film, and can be a transition metal, a nitride or a carbide of a transition metal formed by sputtering. Specifically, the source electrode 121 and the drain electrode 122 can be Ta, Hf, W, Ni, TiN, TaN, HfN, WN, TiC, TaC, HfC, Au, Cu, or the like, can be a compound containing these elements, or can be a multilayer electrode film composed of a plurality of stacked structures.

[0072] In addition, the source electrode 121 and the drain electrode 122 are electrically connected in ohmic connection with the two-dimensional electron gas 110.

[0073] In addition, below at least one of the source electrode 121 and the drain electrode 122, a recessed portion in which a portion of the barrier layer 104 and / or the channel layer 103 is removed, or a contact layer containing an n-type impurity containing a donor such as Si can be provided. The contact layer containing the n-type impurity can be formed, for example, by plasma processing, ion implantation, and regrowth.

[0074] Between the gate electrode 140 and the source electrode 121 and the drain electrode 122, the insulating layer 130 is provided above the barrier layer 104. As shown in Figure 1 The insulating layer 130 includes a first insulating layer 131, a second insulating layer 132, a first side wall 133d, and a second side wall 133s.

[0075] The first insulating layer 131 is the lowermost layer among the insulating layer 130. The first insulating layer 131 is provided above the barrier layer 104. For example, the first insulating layer 131 is provided in contact with the upper surface of the barrier layer 104. The first insulating layer 131 is a layer composed of silicon nitride. For example, the first insulating layer 131 is composed of Si3N4 having a thickness of 50 nm. In addition, as shown in Figure 1 In the first insulating layer 131, a first opening portion 131A that penetrates the first insulating layer 131 to reach the barrier layer 104 is provided in a region in which the source electrode 121 and the drain electrode 122 are provided.

[0076] Furthermore, the first insulating layer 131 can be, for example, a stoichiometric composition of Si3N4 with low H content. This reduces electron trapping, and the second insulating layer 132 can be selectively removed by wet etching. Additionally, the first insulating layer 131 is not limited to Si3N4; it may not be a stoichiometric composition, or it may have a higher Si composition or a higher N composition compared to the stoichiometric composition. Furthermore, the first insulating layer 131 may not be a single layer but multiple layers. In a multilayer first insulating layer 131, the bottom layer is Si3N4, and the upper layers can be SiN with a higher Si composition or a higher N composition compared to the stoichiometric composition to control the etching rate during wet etching. Furthermore, the first insulating layer 131 can also be carbon-containing SiCN.

[0077] The second insulating layer 132 is disposed above the first insulating layer 131. Specifically, the second insulating layer 132 is disposed in contact with the upper surfaces of the first insulating layer 131, the source electrode 121, and the drain electrode 122. The second insulating layer 132 is a layer made of silicon oxide. For example, the second insulating layer 132 is made of SiO2 with a thickness of 50 nm. In addition, it is not limited to SiO2, and the dielectric constant of the second insulating layer 132 can be lower than that of the first insulating layer 131. Furthermore, it is possible to selectively remove the second insulating layer 132 from the first insulating layer 131. Specifically, the second insulating layer 132 can also be SiON containing oxygen in SiN, or it can be a Low-k film, such as SiOC, SiOCH, or an organic film.

[0078] In addition, such as Figure 1 As shown, a second opening 132A is provided between the source electrode 121 and the drain electrode 122, extending through the first insulating layer 131 and the second insulating layer 132 to the barrier layer 104. The width of the second opening 132A is, for example, 400 nm. Alternatively, the width of the second opening 132A can be in the range of 100 nm to 600 nm.

[0079] By providing a second opening 132A, such as Figure 2As shown in the cross-sectional view, the first insulating layer 131 and the second insulating layer 132 can be divided into a portion on the drain electrode 122 side and a portion on the source electrode 121 side. Specifically, the first insulating layer 131 includes a first insulating layer 131d on the drain electrode 122 side and a first insulating layer 131s on the source electrode 121 side. Furthermore, the second insulating layer 132 includes a second insulating layer 132d on the drain electrode 122 side and a second insulating layer 132s on the source electrode 121 side. In this embodiment, the upper surface shapes of the first insulating layer 131d and the second insulating layer 132d on the drain electrode 122 side are different from the upper surface shapes of the first insulating layer 131s and the second insulating layer 132s on the source electrode 121 side. Specific shape differences will be explained later.

[0080] Furthermore, while the first insulating layer 131s and the first insulating layer 131d have the same thickness and layer composition, this is not a limitation; at least one of the thickness and composition may differ. For example, the thickness of the first insulating layer 131s may be greater than the thickness of the first insulating layer 131d. Similarly, the second insulating layer 132s and the second insulating layer 132d also have the same thickness and layer composition, but this is not a limitation; at least one of the thickness and composition may differ.

[0081] In the following description, we will refer to the first insulating layer 131 as the first insulating layer 131, since the description is for matters common to both the first insulating layer 131s and the first insulating layer 131d. The same applies to the second insulating layers 132s and 132d.

[0082] like Figure 2 As shown, the first sidewall 133d and the second sidewall 133s are disposed between the barrier layer 104 and the protrusions 142d and 142s of the gate electrode 140. Specifically, the first sidewall 133d and the second sidewall 133s are disposed within the second opening 132A. More specifically, the first sidewall 133d is disposed at the end of the insulating layer 130 between the junction 141 of the gate electrode 140 and the drain electrode 122 on the junction 141 side. The second sidewall 133s is disposed at the end of the insulating layer 130 between the junction 141 and the source electrode 121 on the junction 141 side. That is, the first sidewall 133d is disposed in contact with the side surface of the first insulating layer 131d on the junction 141 side. The second sidewall 133s is disposed in contact with the side surface of the junction 141 side of each of the first insulating layer 131s and the second insulating layer 132s.

[0083] The first sidewall 133d and the second sidewall 133s are, for example, made of SiN with a width of 100 nm. Here, SiN generally has tensile stress. By providing the first sidewall 133d and the second sidewall 133s, the opening portion of the second opening 132A can be substantially narrowed, for example, the exposed width of the barrier layer 104 becomes 200 nm. In addition, the width of the first sidewall 133d and the second sidewall 133s can be set to any width from 20 nm to 200 nm. Furthermore, the width (length in the X-axis direction) of the first sidewall 133d and the second sidewall 133s can also be different.

[0084] Furthermore, the first sidewall 133d can be formed using a high dielectric material. This further reduces the electric field at the drain electrode 122 side of the portion (junction 141) where the gate electrode 140 is connected to the barrier layer 104. Additionally, the second sidewall 133s can be formed using a low dielectric material. This reduces the parasitic capacitance (gate-source capacitance Cgs) between the gate electrode 140 and the source electrode 121.

[0085] like Figure 1 As shown, the gate electrode 140 is disposed between the source electrode 121 and the drain electrode 122, spaced apart from each of them. The gate electrode 140 has a so-called T-type gate structure. Specifically, the gate electrode 140 is disposed on the barrier layer 104 exposed at the bottom surface of the second opening 132A, and a portion of the first insulating layer 131 and the second insulating layer 132, in a manner that covers the second opening 132A.

[0086] like Figure 2 As shown, the gate electrode 140 includes a junction 141 that is Schottky-junctionally bonded to the barrier layer 104. In this embodiment, the junction 141 is the contact surface where the gate electrode 140 contacts the barrier layer 104. In top view, the junction 141 corresponds to the portion between the first sidewall 133d and the second sidewall 133s. The length of the junction 141 in the X-axis direction corresponds to the so-called gate length Lg. The gate length Lg can be shortened by using the first sidewall 133d and the second sidewall 133s.

[0087] Furthermore, the gate electrode 140 includes protrusions that extend towards the source electrode 121 and the drain electrode 122 respectively, compared to the junction portion 141, when the main surface of the substrate 101 is viewed from above. Specifically, as Figure 2As shown, the gate electrode 140 includes an extension portion 142s that extends toward the source electrode 121 side in a plan view of the substrate 101 compared to the joint portion 141, and an extension portion 142d that extends toward the drain electrode 122 side in a plan view of the substrate 101 compared to the joint portion 141. The extension portions 142d and 142s correspond to arm portions (horizontal bar portions of a T letter) of a T-shaped gate structure, and the joint portion 141 corresponds to a sole portion (lower end of a vertical bar of a T letter) of the T-shaped gate structure. The extension portions 142d and 142s are positioned above the insulating layer 130 and do not contact the barrier layer 104.

[0088] In the present embodiment, as shown in FIG. 1, the source electrode 121 is formed of a single layer of a conductive material. The source electrode 121 is, for example, a single layer electrode film of TiN. The thickness of the TiN film is, for example, 50 nm, but is not limited thereto. Figure 2 Figure 3 As shown, the lower surface of the extension portion 142d on the drain electrode 122 side is not flat. In a cross section, the lower surface of the extension portion 142d changes in a cubic function. The specific shape of the lower surface of the extension portion 142d will be described later.

[0089] The gate electrode 140 is formed of a conductive material. The gate electrode 140 is, for example, a multi-layer electrode film of a stacked structure in which a TiN film and an Al film are sequentially stacked. The thickness of the TiN film is, for example, 50 nm, and the thickness of the Al film is, for example, 500 nm, but is not limited thereto. In addition, the gate electrode 140 is not limited to the stacked structure of the TiN film and the Al film, and can be a nitride or a carbide of a transition metal formed by sputtering. Specifically, the gate electrode 140 can be Ni, TiN, WN, HfN, TiC, WC, HfC, W, Au, Cu, or the like, can be a compound containing these elements, or can be a multi-layer electrode film of a plurality of stacked structures.

[0090] The fourth insulating layer 134 is provided above the second insulating layer 132 and the gate electrode 140. The fourth insulating layer 134 is, for example, composed of SiN with a thickness of 150 nm. In addition, the fourth insulating layer 134 is not limited to SiN, and can be SiO2, SiCN. Further, with respect to the SiN that constitutes the fourth insulating layer 134, the Si composition ratio or the N composition ratio can be changed to control stress.

[0091] The source field plate 123 is provided above the gate electrode 140 and is a source electric field plate that is set to the same potential as the source electrode 121. Specifically, the source field plate 123 is provided above the fourth insulating layer 134. The source field plate 123 is provided so as to be at least partially positioned between the gate electrode 140 and the drain electrode 122 in a plan view. The source field plate 123 is, for example, a single layer electrode film of TiN. The thickness of the TiN film is, for example, 50 nm, but is not limited thereto. Figure 1 ​In the illustrated example, the source field plate 123 is configured so as to overlap the gate electrode 140 in plan view in part. The source field plate 123 is electrically insulated from the gate electrode 140 and the drain electrode 122, and is set to an electric potential (source potential) applied to the source electrode 121. By providing the source field plate 123, it is possible to moderate the electric field concentrated on the gate electrode 140.

[0092] The source field plate 123 is formed using an electrically conductive material. The source field plate 123 is, for example, a multilayer electrode film structure composed of a stacked structure in which a TiN film and an Al film are sequentially stacked. The thickness of the TiN film is, for example, 50 nm, and the thickness of the Al film is, for example, 500 nm, but is not limited thereto. In addition, the source field plate 123 is not limited to the stacked structure of the TiN film and the Al film, and can be a nitride or a carbide of a transition metal formed by sputtering. Specifically, the source field plate 123 can be Ti, Ta, W, Ni, TiN, TaN, WN, W, Au, Cu, or the like, can be a compound containing these elements, or can be a multilayer electrode film composed of a plurality of stacked structures.

[0093] Next, the detailed configuration of the gate electrode 140 and the first insulating layer 131d and the second insulating layer 132d on the drain electrode 122 side will be described using Figure 2 and Figure 3 As illustrated in Figure 2 and Figure 3 , the protruding portion 142d of the gate electrode 140 protruding toward the drain electrode 122 side has the first gate field plate 143 and the second gate field plate 144.

[0094] The first gate field plate 143 is an example of the first electric field plate, and is an interval from the first position, which is the side end of the junction portion 141 of the first sidewall 133d in plan view of the substrate 101, to the second position, which is the drain electrode 122 side end of the first sidewall 133d. In addition, the first position is also the position of the drain electrode 122 side end of the portion (junction portion 141) at which the gate electrode 140 is in contact with the barrier layer 104. The first gate field plate 143 is a portion of the protruding portion 142d located directly above the first sidewall 133d, that is, a portion of the interval overlapping the first sidewall 133d in plan view.

[0095] As illustrated in Figure 2As shown, the lower surface 143a of the first gate field plate 143 is in contact with the upper surface 133da of the first sidewall 133d. In addition, the upper surface 133da of the first sidewall 133d is curved in a manner that protrudes upward. The lower surface 143a of the first gate field plate 143 is curved along the upper surface 133da. The lower surface 143a is inclined (curved) in a manner that the interval from the barrier layer 104 monotonously increases toward the positive direction of the X axis. In addition, the upper surface 133da and the lower surface 143a can also be inclined planes, or can be formed in a stepped manner. As for the upper surface 133sa of the second sidewall 133s, it can also be an inclined plane instead of a curved surface, or can be formed in a stepped manner.

[0096] The second gate field plate 144 is an example of the second electric field plate, and is an interval from the above-mentioned second position in the plan view of the substrate 101 to the drain electrode 122 side end of the protruding portion 142d, i.e., the third position. The second gate field plate 144 is a portion of the protruding portion 142d that is positioned directly above the first insulating layer 131, i.e., a portion of the interval that overlaps the first insulating layer 131 in the plan view. In the present embodiment, the first insulating layer 131d and the second insulating layer 132d are provided in a stacked manner between the second gate field plate 144 and the barrier layer 104.

[0097] As shown, the lower surface 143a of the first gate field plate 143 is in contact with the upper surface 133da of the first sidewall 133d. In addition, the upper surface 133da of the first sidewall 133d is curved in a manner that protrudes upward. The lower surface 143a of the first gate field plate 143 is curved along the upper surface 133da. The lower surface 143a is inclined (curved) in a manner that the interval from the barrier layer 104 monotonously increases toward the positive direction of the X axis. In addition, the upper surface 133da and the lower surface 143a can also be inclined planes, or can be formed in a stepped manner. As for the upper surface 133sa of the second sidewall 133s, it can also be an inclined plane instead of a curved surface, or can be formed in a stepped manner. Figure 2

[0098] The flat surface 144b is a plane (XY plane) that is parallel to the main surface of the substrate 101, and is in contact with the surface of the first insulating layer 131d. In the present embodiment, the flat surface 144b is positioned lower than the interface between the first insulating layer 131d and the second insulating layer 132d, but is not limited thereto. The flat surface 144b can also be coplanar with the interface between the first insulating layer 131d and the second insulating layer 132d.

[0099] The inclined surface 144c is a surface in which the interval from the barrier layer 104 monotonously increases toward the positive direction of the X axis. The inclined surface 144c is in contact with the end surface of the second insulating layer 132d on the source electrode 121 side and the sidewall of the recess of the first insulating layer 131d. The inclined surface 144c is a plane that is inclined with respect to the main surface of the substrate 101. The inclined surface 144c can also be a curved surface that protrudes upward or downward. The inclination angle (angle with respect to the XY plane) of the inclined surface 144c is not particularly limited, and is, for example, within the range of 45 degrees ± 5 degrees.

[0100] The flat surface 144d is a plane (XY plane) that is parallel to the main surface of the substrate 101, and is in contact with the upper surface of the second insulating layer 132d.

[0101] ​The lower surface 144a of the above-described shape can be defined by the elevation angle when viewed from position P1 at the drain electrode 122 side end of the junction 141 of the gate electrode 140. Hereinafter, using... Figure 3 The first elevation angle θ1 to the fifth elevation angle θ5, the imaginary lines VL1 to VL5 used to define each elevation angle, and their positions P1 to P5 are explained.

[0102] exist Figure 3 In the cross-sectional view shown, the first elevation angle θ1 to the fifth elevation angle θ5 are the elevation angles relative to the main surface (XY plane) of the substrate 101 when observing other specified positions (points) or specified directions from a specified position (point). Specifically, the first elevation angle θ1 to the fifth elevation angle θ5 are respectively determined by... Figure 3 The angles (<90°) formed by each of the imaginary lines VL1 to VL5 and the main surface (XY plane) of the substrate 101 are shown.

[0103] like Figure 3 As shown, imaginary line VL1 is the tangent at position P1 on the upper surface 133da of the first sidewall 133d. Imaginary line VL2 is the straight line connecting position P1 and position P2. Imaginary line VL3 is the straight line connecting position P1 and position P3. Imaginary line VL4 is the straight line connecting position P1 and position P4. Imaginary line VL5 is the straight line connecting position P3 and position P4.

[0104] Position P1 is the junction 141 side end of the first sidewall 133d. Specifically, position P1 is an example of the first position, and is also the drain electrode 122 side end of the junction 141.

[0105] Position P2 is the highest position of the lower surface 143a of the first gate field plate 143. Specifically, position P2 is also the highest position of the upper surface 133da of the first sidewall 133d.

[0106] Position P3 is the lower surface 144a of the second gate field plate 144 (refer to...) Figure 2 The lowest position of the drain electrode 122 side of the flat surface 144b. Specifically, position P3 is the drain electrode 122 side of the flat surface 144b. In this embodiment, position P3 is also the lower end of the inclined surface 144c.

[0107] Position P4 is the lower surface 144a of the second gate field plate 144 (refer to...) Figure 2 The highest position of the drain electrode 122 side. Specifically, position P4 is the drain electrode 122 side of the flat surface 144d.

[0108] Position P5 is the upper end of the inclined surface 144c. In this embodiment, position P5 is also the lower surface 144a of the second gate field plate 144 (see reference). Figure 2 The highest position of the joint 141 side end.

[0109] In the present embodiment, the second elevation angle Θ2 is larger than the third elevation angle Θ3. Thus, compared with the conventional structure shown in FIG. 6, the lowest position (position P3) of the lower surface 144a of the second gate field plate 144 is lower than the highest position (position P2) of the first sidewall 133d. Further, the lower surface of the extension portion 142d on the drain electrode 122 side of the gate electrode 140 includes a sloped surface 144c that monotonously increases toward the drain electrode 122 side in the X-axis direction. Figure 19

[0110] Thus, the local electric field at the drain electrode 122 side end (position P1) of the portion (junction 141) where the gate electrode 140 meets the barrier layer 104 can be dispersed not only to the position P4 but also to the position P3 and the sloped surface 144c. Therefore, electric field relaxation can be achieved.

[0111] Further, by making the lowest position (P3) of the lower surface of the second gate field plate 144 lower than the highest position (P2) of the upper surface 133da of the first sidewall 133d, at the time of transistor cutoff, the depletion layer easily expands toward the drain electrode 122 side below the gate electrode 140. Therefore, at the time of low voltage application between the gate electrode 140 and the drain electrode 122, the position of the two-dimensional electron gas 110 is more on the drain electrode 122 side, i.e., further away from the gate electrode 140, compared with the conventional technique. Thus, the area where the two-dimensional electron gas 110 opposes the gate electrode 140 becomes smaller. Further, in the case where the second elevation angle Θ2 is larger than the third elevation angle Θ3, the distance of the two-dimensional electron gas 110 from the first gate field plate 143 is lengthened, so the parasitic capacitance (gate-drain capacitance Cgd) can be reduced.

[0112] Thus, according to the semiconductor device 100 of the present embodiment, reduction of electric field strength and reduction of parasitic capacitance can be achieved in combination.

[0113] Further, as shown in FIG. 7, regarding the extension portion 142s on the source electrode 121 side, in the portion on the source electrode 121 side than the second sidewall 133s, the lowest position is not lower than the highest position (position P2) of the first sidewall 133d. Thus, the parasitic capacitance of the gate electrode 140 and the source electrode 121 can be suppressed from increasing. Figure 2

[0114] Further, as shown in FIG. 7, the fifth elevation angle Θ5 is smaller than the second elevation angle Θ2. In the case where the fifth elevation angle Θ5 is thus reduced, the slope from the position P3 to the position P4 can be made gentle. Therefore, the electric field at the drain electrode 122 side end (position P3) of the lowest position of the lower surface 144a of the second gate field plate 144 can be relaxed, and the fluctuation of electric field can be reduced. Figure 3

[0115] ​​​Further, at least one of the first insulating layer 131d and the second insulating layer 132s can be thinner than the film thickness of the first insulating layer 131s and the second insulating layer 132s on the source electrode 121 side. In this way, the local electric field concentration at the end portion (position PI) of the drain electrode 122 that is in contact with the junction 141 of the gate electrode 140 and the barrier layer 104 can be dispersed, and the electric field intensity can be further reduced.

[0116] As above, the semiconductor device 100 of this embodiment has: a substrate 101; a channel layer 103 provided above the substrate 101 and composed of a Group III nitride semiconductor; a barrier layer 104 provided above the channel layer 103 and composed of a Group III nitride semiconductor having a larger band gap than the channel layer 103; a source electrode 121 and a drain electrode 122 provided above the barrier layer 104 so as to be separated from each other by a space in the X-axis direction of the main surface of the substrate 101; a gate electrode 140 provided so as to be separated from the source electrode 121 and the drain electrode 122 by a space in the X-axis direction between the source electrode 121 and the drain electrode 122; and an insulating layer 130 provided above the barrier layer 104 between the gate electrode 140 and the source electrode 121 and the drain electrode 122. The insulating layer 130 includes a first insulating layer 131 composed of silicon nitride which is the lowermost layer, and a second insulating layer 132 composed of silicon oxide which is above the first insulating layer 131. The gate electrode 140 includes a junction portion 141 which is in Schottky junction with the barrier layer 104, and an extension portion 142s and an extension portion 142d which respectively extend from the junction portion 141 to the source electrode 121 side and the drain electrode 122 side in the X-axis direction. Between the extension portion 142d and the barrier layer 104 in the Z-axis direction orthogonal to the main surface of the substrate 101, the insulating layer 130 includes a first side wall 133d provided at the junction portion 141 side end (end portion on the junction portion 141 side) of the insulating layer 130 between the junction portion 141 and the drain electrode 122, and a second side wall 133s provided at the junction portion 141 side end (end portion on the junction portion 141 side) of the insulating layer 130 between the junction portion 141 and the source electrode 121. The extension portion 142d includes a first gate field plate 143 in an interval from a first position to a second position in plan view, the first position being the junction portion 141 side end of the first side wall 133d, and the second position being the drain electrode 122 side end of the first side wall 133d, and a second gate field plate 144 in an interval from the second position to a third position in plan view, the third position being the drain electrode 122 side end of the extension portion 142d. Between the second gate field plate 144 and the barrier layer 104, the first insulating layer 131d and the second insulating layer 132d are stacked. In a cross section (XZ cross section) parallel to the X-axis direction and the Z-axis direction respectively and passing through the junction portion 141, a tangent line (imaginary line VL1) at a first position (position P1) of an upper surface 133da of the first side wall 133d has an inclination of a first elevation angle θ1 with respect to the main surface, a highest position (position P2) of a lower surface 143a of the first gate field plate 143 has an inclination of a second elevation angle θ2 with respect to the main surface of the substrate 101 from the first position, and a drain electrode 122 side end (position P3) of a lowest position of a lower surface 144a of the second gate field plate 144 has an inclination of a third elevation angle θ3 with respect to the main surface of the substrate 101 from the first position. The second elevation angle θ2 is larger than the third elevation angle θ3.The lower surface 144a of the second gate field plate 144 includes a sloped surface 144c that monotonically increases in spacing from the gate electrode 140 toward the drain electrode 122.

[0117] Thus, a two-dimensional electron gas 110 is generated near the interface between the barrier layer 104 within the channel layer 103, so a transistor that utilizes the generated two-dimensional electron gas 110 as a channel can be implemented. Further, the gate electrode 140 includes the joint portion 141 and the overhang portion 142d, so the miniaturization of the gate length (Lg) and the electric field relaxation based on the overhang portion 142d can be easily implemented.

[0118] Further, in the semiconductor device 100, the lowest position (position P3) of the lower surface 144a of the second gate field plate 144 is lower than the highest position (position P2) of the lower surface 143a of the first gate field plate 143. Further, the lower surface 144a of the second gate field plate 144 includes a sloped surface 144c that monotonically increases.

[0119] Thus, the electric field can be dispersed toward the drain electrode 122 side end (position P4) of the second gate field plate 144, the lowest position (position P3) of the lower surface 144a of the second gate field plate 144, and the sloped surface 144c, and the electric field concentration can be relaxed.

[0120] Further, since the second elevation angle θ2 is larger than the third elevation angle θ3, the first side wall 133d is thickened. Thus, the distance between the two-dimensional electron gas 110 and the overhang portion 142d of the gate electrode 140 can be easily ensured to be long, so the parasitic capacitance (gate-drain capacitance Cgd) can be reduced.

[0121] Further, in the above structure, a laminated film of the first insulating layer 131d and the second insulating layer 132d is provided between the second gate field plate 144 and the barrier layer 104. Since the second insulating layer 132d is composed of a silicon oxide film having a lower relative dielectric constant than the silicon nitride film that constitutes the first insulating layer 131d, the parasitic capacitance (gate-drain capacitance Cgd) can be reduced. In this way, according to the above structure, the electric field relaxation and the reduction of the parasitic capacitance can be both achieved.

[0122] Further, the first insulating layer 131, the first side wall 133d, and the second side wall 133s composed of the silicon nitride film can compensate for the nitrogen deficiency of the barrier layer 104 and reduce the interface level. Thus, the off-leakage current between the gate electrode 140 and the drain electrode 122 can be reduced.

[0123] Further, for example, in the semiconductor device 100, the overhang portion 142s on the source electrode 121 side of the second side wall 133s is not lower than the highest position (position P2) of the upper surface 133da of the first side wall 133d.

[0124] Thus, the distance between the two-dimensional electron gas 110 on the source electrode 121 side and the extension portion 142s of the gate electrode 140 can be ensured, and thus the parasitic capacitance (gate-source capacitance Cgs) can be reduced.

[0125] Further, for example, in the semiconductor device 100, in the cross section shown in FIG. 1, the angle of elevation of the main surface of the substrate 101 with respect to the drain electrode 122 side end of the highest position of the lower surface 144a of the second gate field plate 144 (position P4) when the lower surface 144a of the second gate field plate 144 is observed from the drain electrode 122 side end of the lowest position of the lower surface 144a of the second gate field plate 144 (position P3) is the fifth angle of elevation Θ5. In this case, the fifth angle of elevation Θ5 is smaller than the second angle of elevation Θ2. Figure 3

[0126] Thus, the inclination from the position P3 to the position P4 can be made gentle. Therefore, the electric field at the drain electrode 122 side end of the lowest position of the lower surface 144a of the second gate field plate 144 (position P3) can be moderated, and the fluctuation of the electric field can be reduced.

[0127] Further, in the semiconductor device 100 of the present modified example, the inclined surface included in the lower surface 144a of the second gate field plate 144 includes at least one inclined surface 144c having an inclination angle of 45 degrees ± 5 degrees with respect to the main surface of the substrate 101.

[0128] Thus, the upper surface shape of the insulating layer 130 can be easily formed by an isotropic etching method such as wet etching. Since the lower surface shape of the extension portion 142d of the gate electrode 140 is a shape following the upper surface shape of the insulating layer 130, the manufacturing variation of the gate electrode 140 is reduced, and a device with high reliability can be realized.

[0129] In addition, in the present embodiment, at least one of the flat surface 144b and the flat surface 144d can be inclined. The inclination can be an inclination in which the interval from the barrier layer 104 increases toward the positive direction of the X axis, or can be an inclination in which the interval decreases. Further, the inclination can be flat or curved.

[0130] [Manufacturing method]

[0131] Hereinafter, the manufacturing method of the semiconductor device 100 of the present embodiment will be described with reference to the drawings. Figures 4A-4G The manufacturing method of the semiconductor device 100 of the present embodiment will be described.

[0132] Figures 4A-4G Each is a cross-sectional view for explaining each process of the manufacturing method of the semiconductor device 100 of the present embodiment. Figures 4A-4G Each shows the cross-sectional structure of the semiconductor device 100 at the manufacturing intermediate stage. In addition, in the cross sections shown in FIGS. 6A to 6D, the lower surface 144a of the second gate field plate 144 is inclined. Figure 4E and Figure 4F ​The image also shows an enlarged view of the vicinity of the first sidewall 133d.

[0133] In addition, Figures 4A-4D In order to easily understand the positional correspondence between the figures, three lines L1 to L3 extending from the upper surface of the barrier layer 104 in the Z-axis direction are represented by double-dotted lines. Line L1 indicates the position of the drain electrode 122 side end of the first sidewall 233d. Line L2 indicates the position of the source electrode 121 side end of the second sidewall 133s. Line L3 indicates the center position of the junction 141.

[0134] First, such as Figure 4A As shown, on a substrate 101 made of Si, metal-organic chemical vapor deposition (MOCVD) is used to deposit a layer in the +c plane direction. <0001> A buffer layer 102 with a thickness of 2 μm, composed of AlN and AlGaN, a channel layer 103 with a thickness of 200 nm, composed of GaN, and a barrier layer 104 with a thickness of 20 nm, composed of AlGaN with an Al composition ratio of 25%, are sequentially epitaxially grown in the direction of the barrier layer 104. As a result, a high concentration of two-dimensional electron gas 110 is generated on the channel layer 103 side of the heterogeneous interface between the barrier layer 104 and the channel layer 103, forming a channel of two-dimensional electron gas 110.

[0135] Next, as Figure 4B As shown, a first insulating layer 131, a source electrode 121, a drain electrode 122, and a second insulating layer 132 are formed. Specifically, firstly, a first insulating layer 131 composed of Si3N4 with a thickness of 50 nm is deposited by reduced pressure CVD (Chemical Vapor Deposition). Then, after coating with a photoresist, the photoresist is patterned using photolithography to form a mask outside the areas where the source electrode 121 and drain electrode 122 are formed.

[0136] Next, using a dry etching method, a first opening 131A is formed in the first insulating layer 131 to expose the barrier layer 104, and then the mask and polymer are removed. Alternatively, while a dry etching method is used in this embodiment, a wet etching method can also be used to form the first opening 131A in the first insulating layer 131.

[0137] Next, after sequentially depositing Ti and Al films by vapor deposition, the source electrode 121 and drain electrode 122 are formed by lift-off. Then, by performing heat treatment, the two-dimensional electron gas 110 is electrically ohmically connected to the source electrode 121 and drain electrode 122, respectively. Alternatively, the source electrode 121 and drain electrode 122 can be formed by sequentially depositing Ti and Al films by sputtering and then sequentially applying photolithography and dry etching.

[0138] Next, a second insulating layer 132 is formed on the first insulating layer 131, the source electrode 121, and the drain electrode 122. The second insulating layer 132 is formed by depositing a 50 nm thick SiO2 layer using plasma CVD.

[0139] Next, as Figure 4C As shown, a second opening 132A and a third insulating layer 133 are formed. Specifically, firstly, after applying a photoresist, the photoresist is patterned using photolithography to form a mask outside the area where the second opening 132A is formed. Next, the second opening 132A is formed in the first insulating layer 131 and the second insulating layer 132 using dry etching to expose the barrier layer 104. After forming the second opening 132A, the mask and polymer are removed.

[0140] Next, a third insulating layer 133 made of SiN with a thickness of 100 nm is deposited using plasma CVD. The third insulating layer 133 is provided in such a way that it fills the second opening 132A.

[0141] Next, as Figure 4D As shown, the third insulating layer 133 is etched back using a dry etching method. This forms the first sidewall 133d and the second sidewall 133s, exposing the barrier layer 104.

[0142] Next, as Figure 4E As shown, after applying the resist, a mask (resist pattern 150) is formed by patterning the resist using photolithography. The mask is formed to expose the first sidewall 133d and the second sidewall 133s. Figure 4E In the cross-sectional view shown, the resist pattern 150 includes a mask portion 151 on the drain electrode 122 side and a mask portion 152 on the source electrode 121 side.

[0143] Specifically, in top view, the end of the mask portion 151 of the resist pattern 150 is closer to the drain electrode 122 side than the end of the first sidewall 133d on the drain electrode 122 side. That is, the mask portion 151 is configured such that the end of the second insulating layer 132d on the source electrode 121 side and its vicinity are exposed. For example, in... Figure 4EAs shown in the enlarged representation, the distance D between the end of the source electrode 121 side of the mask portion 151 and the end of the drain electrode 122 side of the first sidewall 133d is ensured by a distance greater than 0.

[0144] On the other hand, the end of the mask portion 152 of the resist pattern 150 is closer to the drain electrode 122 side than the end of the second sidewall 133s on the source electrode 121 side. That is, the mask portion 152 completely covers the second insulating layer 132s and partially covers the second sidewall 133s. In addition, in this embodiment, the end of the mask portion 152 on the drain electrode 122 side may also coincide with the end of the second sidewall 133s on the source electrode 121 side in top view. Furthermore, the end of the mask portion 152 may also be located above the barrier layer 104.

[0145] Next, as Figure 4F As shown, a portion of the second insulating layer 132d (specifically, the portion near the end of the first sidewall 133d) is removed. Specifically, using a wet etching method, after selectively removing a portion of the second insulating layer 132d exposed from the mask portion 151 on the drain electrode 122 side, the resist pattern 150 is removed. For example, a portion of the second insulating layer 132d is selectively removed using room temperature BHF (Buffered Hydrofluoric Acid). Alternatively, the mixing ratio of BHF can be any value, or a portion of the second insulating layer 132d can be selectively removed using DHF (Diluted Hydrofluoric Acid). In wet etching, etching proceeds isotropically from the gap between the first sidewall 133d and the mask portion 151. Therefore, as... Figure 4F As shown, the end of the second insulating layer 132d on the source electrode 121 side becomes an inclined surface.

[0146] In this embodiment, the first insulating layer 131 and the third insulating layer 133 are SiN, and the second insulating layer 132 is SiO2. The second insulating layer 132 is selectively removed using a BHF-based wet etching method, but this combination is not limited to. Any insulating material can be used as long as the combination allows for the selective removal of the second insulating layer 132. Furthermore, while a wet etching method is used, it is also possible to use a chemical dry etching method where the first insulating layer 131 and the third insulating layer 133 are SiO2, and the second insulating layer 132 is SiN.

[0147] Next, as Figure 4GAs shown, a gate electrode 140 is formed. Specifically, a 50 nm thick TiN layer and a 450 nm thick Al layer are sequentially deposited by sputtering. Then, in the region where the gate electrode 140 is formed, a photoresist is applied and patterned to form a mask using photolithography. Next, the mask and polymer are removed using dry etching after the gate electrode 140 is formed.

[0148] Next, after depositing a fourth insulating layer 134 of SiN with a thickness of 150 nm using plasma CVD, a TiN layer with a thickness of 50 nm and an Al layer with a thickness of 450 nm are sequentially deposited using sputtering. Then, in the region where the source field plate 123 is formed, a photoresist is applied and patterned to form a mask using photolithography. Finally, the mask and polymer are removed using dry etching after the source field plate 123 is formed.

[0149] Through the above series of processes, Figure 1 The semiconductor device 100 with the shown structure is completed.

[0150] (A variation of Implementation Method 1)

[0151] Next, a variation of Implementation 1 will be described.

[0152] In the following variation, the shape of the lower surface of the protrusion 142d on the drain electrode 122 side of the gate electrode 140 is different from that of Embodiment 1. The description will focus on the differences from Embodiment 1, and the description of common points will be omitted or simplified.

[0153] [Variation Example 1]

[0154] First, use Figure 5 and Figure 6 The modified example 1 will be explained.

[0155] Figure 5 This is a cross-sectional view showing the structure of the gate electrode 140 of the semiconductor device 100A in a modified example of Embodiment 1. Figure 6 This is an enlarged cross-sectional view of the shape of the lower surface 144a of the protrusion 142d extending toward the drain electrode 122 side of the gate electrode 140 of the semiconductor device 100A of Embodiment 1, which is used to illustrate the variation of Embodiment 1.

[0156] like Figure 5 As shown, the lower surface 144a of the second gate field plate 144 includes an inclined surface 144c and a flat surface 144d. The lower surface 144a does not include... Figure 2 The flat surface 144b shown. The lowest position in the lower surface 144a of the second gate field plate 144 ( Figure 6The second insulating layer 132 is present below the position P3). In this modification, the first side wall 133d is provided so as to contact the side surface of each of the first insulating layer 131d and the second insulating layer 132d on the side of the junction 141.

[0157] As shown in FIG. 1, in the semiconductor device 100A of Modification 1, the third elevation angle Θ3 is larger than the fourth elevation angle Θ4. Thus, since the distance between the lowest position of the lower surface 144a of the second gate field plate 144 (position P3) and the two-dimensional electron gas 110 is lengthened, the electric field intensity at the position P3 can be reduced. Further, since the second insulating layer 132 composed of SiO2 has a lower dielectric constant than the first insulating layer 131 composed of SIN, the electric field intensity at the position P3 can be reduced and the parasitic capacitance (gate-drain capacitance Cgd) can be reduced. Figure 6 As described above, in the semiconductor device 100A of the present modification, in the cross section shown in FIG. 1, in a case where the elevation angle with respect to the main surface of the substrate 101 of the drain electrode 122 side end (position P4) of the highest position of the lower surface 144a of the second gate field plate 144 viewed from the first position (position PI) is the fourth elevation angle Θ4, the third elevation angle Θ3 is larger than the fourth elevation angle Θ4.

[0158] Figure 6 Thus, the distance between the lowest position (position P3) of the lower surface 144a of the second gate field plate 144 and the two-dimensional electron gas 110 can be lengthened, so the electric field concentration toward the position P3 can be alleviated, and the parasitic capacitance (gate-drain capacitance Cgd) can be reduced.

[0159] Further, in the semiconductor device 100A of the present modification, the second insulating layer 132d overlaps the lowest position of the lower surface 144a of the second gate field plate 144 in plan view.

[0160] Thus, by providing the second insulating layer 132d composed of a silicon oxide film having a low relative dielectric constant, the electric field concentration toward the position P3 can be alleviated, and the parasitic capacitance (gate-drain capacitance Cgd) can be reduced.

[0161] Further, in the semiconductor device 100A of the present modification, the second insulating layer 132d overlaps the lowest position of the lower surface 144a of the second gate field plate 144 in plan view.

[0162] Further, in the semiconductor device 100A of the present modification, the second insulating layer 132d overlaps the lowest position of the lower surface 144a of the second gate field plate 144 in plan view. Figure 2 ​The flat surface 144b shown is located above the flat surface, and a portion of the second insulating layer 132d is located below the flat surface. Therefore, it is possible to mitigate the concentration of electric field and reduce parasitic capacitance.

[0163] [Variation Example 2]

[0164] Next, use Figure 7 and Figure 8 The modified example 2 will be explained.

[0165] Figure 7 This is a cross-sectional view showing the structure of the gate electrode 140 of the semiconductor device 100B in a modified example 2 of Embodiment 1. Figure 8 This is an enlarged cross-sectional view of the shape of the lower surface 144a of the protrusion 142d extending toward the drain electrode 122 side of the gate electrode 140 of the semiconductor device 100B in Modified Example 2 of Embodiment 1.

[0166] like Figure 7 As shown, the lower surface 144a of the second gate field plate 144 includes three flat surfaces 144b, 144d, and 144f and two inclined surfaces 144c and 144e. Specifically, the flat surfaces 144b, 144e, 144f, 144c, and 144d are arranged sequentially towards the positive X-axis. Flat surface 144b is positioned below flat surface 144f, and flat surface 144f is positioned below flat surface 144d. That is, the lower surface 144a is arranged in a stepped manner. Flat surfaces 144b, 144e, and 144f are in contact with the first insulating layer 131d. Inclined surfaces 144c and flat surfaces 144d are in contact with the second insulating layer 132d. The inclination angles of inclined surfaces 144c and 144e are the same, but they can also be different. For example, the tilt angles of inclined surfaces 144c and 144e are each within the range of 45 degrees ± 5 degrees.

[0167] like Figure 8 As shown, in the semiconductor device 100B of Modified Example 2, the third elevation angle θ3 is smaller than the fourth elevation angle θ4. That is, the drain electrode 122 side end (position P3) at the lowest position of the lower surface 144a of the second gate field plate 144 is lower than the imaginary line VL4. As a result, the distance between position P3 and the two-dimensional electron gas 110 can be reduced, so the electric field strength at the drain electrode 122 side end (position P1) where the gate electrode 140 is connected to the barrier layer 104 can be reduced.

[0168] Furthermore, the dielectric constant of the first insulating layer 131d, composed of SiN, is higher than that of the second insulating layer 132d, composed of SiO2. Therefore, the electric field strength at the drain electrode 122 side (position P1) where the gate electrode 140 is connected to the barrier layer 104 can be further reduced. Consequently, the depletion layer easily extends towards the drain electrode 122 side below the gate electrode 140, thus suppressing the short-channel effect.

[0169] As described above, in the semiconductor device 100B of this modified example, in Figure 8 In the cross section shown, when the angle of elevation relative to the main surface of the substrate 101 is set to the drain electrode 122 side end (position P4) at the highest position of the lower surface 144a of the second gate field plate 144 when viewed from the first position (position P1), the fourth angle of elevation θ4 is larger than the third angle of elevation θ3.

[0170] As a result, the lowest position (position P3) of the lower surface 144a of the second gate field plate 144 approaches the two-dimensional electron gas 110, so the electric field concentration towards the drain electrode 122 side end (position P1) of the junction 141 can be mitigated.

[0171] Furthermore, in the semiconductor device 100B of this modified example, the lower surface 144a of the second gate field plate 144 is in contact with the first insulating layer 131d.

[0172] Therefore, the lowest position (position P3) of the lower surface 144a of the second gate field plate 144 approaches the two-dimensional electron gas 110, thus mitigating the electric field concentration towards the drain electrode 122 side (position P1) of the junction 141. Furthermore, the depletion layer easily extends towards the drain electrode 122 side below the gate electrode 140, suppressing the short-channel effect.

[0173] [Variation Example 3]

[0174] Next, use Figure 9 The modified example 3 will be explained.

[0175] Figure 9 This is an enlarged cross-sectional view used to illustrate the shape of the lower surface of the gate electrode 140 of the semiconductor device 100C in Modified Example 3 of Embodiment 1 and the positional relationship between the source field plate 123.

[0176] like Figure 9 As shown, in the semiconductor device 100C of Modified Example 3, the third elevation angle θ3 is equal to the fourth elevation angle θ4. As a result, the third elevation angle θ3 is equal to the fifth elevation angle θ5. That is, the imaginary line VL3 coincides with both imaginary lines VL4 and VL5. As a result, the lower surface 144a of the second gate field plate 144 becomes an inclined surface that monotonically increases from position P3 toward position P4.

[0177] Thus, the local concentration of the electric field acting on the gate electrode 140 disappears, and the electric field can be made uniform. Therefore, by making the third elevation angle θ3 smaller, the electric field strength can be reduced.

[0178] At this time, the fifth elevation angle θ5 can be within a range of 45 degrees ± 5 degrees. In the present modification example, the fifth elevation angle θ3 coincides with the inclination angle of the lower surface 144a that is the inclined surface. As described above, the shape of the lower surface 144a of the second gate field plate 144 is formed by the partial etching of the second insulating layer 132d. In this case, an isotropic etching method can be used, so the shape of the lower surface 144a can be easily formed.

[0179] Further, in the semiconductor device 100C of the present modification example, Figure 9 the source field plate 123 does not protrude to a position lower than the notional line VL4. Specifically, the surface of the source field plate 123 is in contact with the notional line VL4. More specifically, the drain electrode 122 side end (position P6) of the lower surface of the source field plate 123 is in contact with the notional line VL4.

[0180] Thus, the electric field strength of the drain electrode 122 side end (position P6) of the source field plate 123 can be reduced. Further, the electric fields acting on the drain electrode 122 side end (position P6) of the source field plate 123 and the drain electrode 122 side end portions (positions P1, P3, and P4) of the gate electrode 140, respectively, can be made uniform.

[0181] As described above, in the semiconductor device 100C of the present modification example, in the cross section shown in Figure 9 when the elevation angle of the drain electrode 122 side end (position P4) of the lower surface 144a of the second gate field plate 144, which is observed from the first position (position P1), with respect to the main surface of the substrate 101 is the fourth elevation angle θ4, the fourth elevation angle θ4 is equal to the third elevation angle θ3.

[0182] Thus, the uniformization of the electric field acting on the gate electrode 140 can be achieved, and the alleviation effect of the electric field concentration can be improved.

[0183] Further, the semiconductor device 100C of the present modification example is provided with the source field plate 123 that is disposed above the gate electrode 140 and is set to the same potential as the source electrode 121. In the cross section shown in Figure 9 the source field plate 123 does not protrude to a position lower than the notional line VL4 that connects the first position (position P1) and the drain electrode 122 side end (position P4) of the highest position of the lower surface 144a of the second gate field plate 144.

[0184] Therefore, the electric field concentrated on the gate electrode 140 can be mitigated by the source field plate 123. Furthermore, since the source field plate 123 does not protrude below the imaginary line VL4, localized electric field concentration on the source field plate 123 can be mitigated. This reduces parasitic capacitance (source-drain capacitance Cds).

[0185] Furthermore, in the semiconductor device 100C of this modified example, in Figure 9 In the cross-section shown, the surface of the source field plate 123 is in contact with the imaginary line VL4.

[0186] Therefore, the electric field acting on the gate electrode 140 and the source field plate 123 can be homogenized, and the mitigation effect of electric field concentration can be improved.

[0187] (Implementation Method 2)

[0188] Next, the semiconductor device of Embodiment 2 will be described.

[0189] In Embodiment 2, the difference from Embodiment 1 is that the heights of the sidewalls on the drain electrode side and the source electrode side are different. Hereinafter, the description will focus on the differences from Embodiment 1, omitting or simplifying the descriptions of the commonalities.

[0190] Figure 10 This is an enlarged cross-sectional view showing the structure of the gate electrode 140 of the semiconductor device 200 in Embodiment 2. Figure 11 This is an enlarged cross-sectional view used to illustrate the shape of the sidewall of the semiconductor device 200 in Embodiment 2.

[0191] like Figure 10 and Figure 11 As shown, in the semiconductor device 200 of this embodiment, the difference from the semiconductor device 100 of embodiment 1 is that a first sidewall 233d is provided instead of the first sidewall 133d on the drain electrode 122 side.

[0192] like Figure 10 and Figure 11 As shown, the highest point of the upper surface 233da of the first sidewall 233d is lower than the highest point of the upper surface 133sa of the second sidewall 133s. Simply put, the first sidewall 233d is shorter (lower in the Z-axis direction) than the second sidewall 133s. Additionally, the first sidewall 233d may also be narrower than the second sidewall 133s.

[0193] exist Figure 11 In the diagram, the highest position of the upper surface 233da of the first sidewall 233d is denoted by position P2. The height of the first sidewall 233d is the distance between the upper surface of the barrier layer 104 and position P2, determined by H. SWdThe highest position of the upper surface 133sa of the second sidewall 133s is denoted by position P7. The height of the second sidewall 133s is the distance between the upper surface of the barrier layer 104 and position P7, determined by H. SWs In this embodiment, H is satisfied. SWd <H SWs The relationship. In addition, in this embodiment, the term "height" refers to the distance in the Z-axis direction from the upper surface of the barrier layer 104 unless otherwise specified.

[0194] In addition, Figure 11 In the above, the thickness of the insulating layer 130 on the drain electrode 122 side, that is, the thickness of the stacked structure of the first insulating layer 131d and the second insulating layer 132d, is represented by H. FPd Indicates thickness H. FPd This corresponds to the height of the highest position of the lower surface of the protrusion 142d extending from the gate electrode 140 toward the drain electrode 122. Furthermore, the thickness of the first insulating layer 131d is represented by H. I express.

[0195] Furthermore, the thickness of the insulating layer 130 on the source electrode 121 side, that is, the thickness of the stacked structure of the first insulating layer 131s and the second insulating layer 132s, is represented by H. FPs Indicates thickness H. FPs The height is equivalent to the highest position of the lower surface of the protrusion 142s extending from the gate electrode 140 toward the source electrode 121.

[0196] In this case, H SWs =H FPd =H FPs This is established. As a result, the electron density of the two-dimensional electron gas 110 directly below the protrusions 142d and 142s can be increased on the source electrode 121 side and the drain electrode 122 side, respectively, thereby reducing the on-resistance.

[0197] In addition, H SWd <H IThat is, the highest position P2 of the first side wall 233d is located at a position lower than the interface between the first insulating layer 131d and the second insulating layer 132d. Specifically, the highest position P2 of the first side wall 233d becomes the same height as the upper surface of the first insulating layer 131d (the portion in contact with the flat surface 144b of the protruding portion 142d). Thus, the upper surface of the first insulating layer 131d and the upper surface 233da of the first side wall 233d are smoothly continuous. As a result, for the lower surface of the protruding portion 142d of the gate electrode 140, the lower surface 143a of the first gate field plate 143 and the lower surface 144a of the second gate field plate 144 (specifically, the inclined surface 144c) are smoothly continuous. The concave-convex is reduced and thus the coverage of the gate electrode 140 is improved, and the reliability of the device can be improved.

[0198] Further, in the present embodiment, the lower surface 144a of the second gate field plate 144, like in Embodiment 1, includes the inclined surface 144c in which the interval from the barrier layer 104 monotonously increases toward the positive direction of the X axis. Thus, like in Embodiment 1, it is possible to disperse the concentration of the electric field and reduce the electric field strength.

[0199] As above, the semiconductor device 200 of this embodiment has: a substrate 101; a channel layer 103 provided above the substrate 101 and composed of a Group III nitride semiconductor; a barrier layer 104 provided above the channel layer 103 and composed of a Group III nitride semiconductor having a larger band gap than the channel layer 103; a source electrode 121 and a drain electrode 122 provided above the barrier layer 104 so as to be separated from each other by a space in the X-axis direction in the main surface of the substrate 101; a gate electrode 140 provided so as to be separated from the source electrode 121 and the drain electrode 122 by a space with respect to them in the X-axis direction between the source electrode 121 and the drain electrode 122; and an insulating layer 130 provided above the barrier layer 104 between the gate electrode 140 and the source electrode 121 and the drain electrode 122. The insulating layer 130 includes a first insulating layer 131 composed of a silicon nitride which is the lowermost layer and a second insulating layer 132 composed of a silicon oxide which is above the first insulating layer 131. The gate electrode 140 includes a junction portion 141 which is in Schottky junction with the barrier layer 104 and a protruding portion 142s and a protruding portion 142d which respectively protrude from the junction portion 141 toward the source electrode 121 side and the drain electrode 122 side in the X-axis direction. Between the protruding portion 142d and the barrier layer 104 in the Z-axis direction orthogonal to the main surface of the substrate 101, the insulating layer 130 includes a first side wall 133d provided at the junction portion 141 side end (end portion on the junction portion 141 side) of the insulating layer 130 between the junction portion 141 and the drain electrode 122 and a second side wall 133s provided at the junction portion 141 side end (end portion on the junction portion 141 side) of the insulating layer 130 between the junction portion 141 and the source electrode 121. The protruding portion 142d includes a first gate field plate 143 in an interval from a first position to a second position in plan view, the first position being the junction portion 141 side end of the first side wall 133d and the second position being a drain electrode 122 side end of the first side wall 133d, and a second gate field plate 144 in an interval from the second position to a third position in plan view, the third position being a drain electrode 122 side end of the protruding portion 142d. Between the second gate field plate 144 and the barrier layer 104, a first insulating layer 131d and a second insulating layer 132d are stacked. In a cross section (XZ cross section) parallel to the X-axis direction and the Z-axis direction respectively and passing through the junction portion 141, a tangent line (imaginary line VL1) at a first position (position P1) of an upper surface 133da of the first side wall 133d has an inclination of a first elevation angle θ1 with respect to the main surface, a highest position (position P2) of a lower surface 143a of the first gate field plate 143 has an inclination of a second elevation angle θ2 with respect to the main surface of the substrate 101 from the first position, and a drain electrode 122 side end (position P3) of a lowest position of a lower surface 144a of the second gate field plate 144 has an inclination of a third elevation angle θ3 with respect to the main surface of the substrate 101 from the first position.The highest position (position P2) of the upper surface 233da of the first side wall 233d is lower than the highest position (position P7) of the upper surface 133da of the second side wall 133s.

[0200] Thus, the two-dimensional electron gas 110 is generated in the channel layer 103 in the vicinity of the interface with the barrier layer 104, so that a transistor using the generated two-dimensional electron gas 110 as a channel can be implemented. Further, the gate electrode 140 includes the joint portion 141 and the extension portion 142d, so that the miniaturization of the gate length (Lg) and the electric field relaxation based on the extension portion 142d can be easily implemented.

[0201] Further, in the semiconductor device 200, the height of the first side wall 233d is low, so that the distance between the first gate field plate 143 and the two-dimensional electron gas 110 is short. Thus, the depletion layer in the channel layer 103 can be easily expanded at the time of transistor cutoff, and the short channel effect can be suppressed. Thus, the off-leakage current between the source electrode 121 and the drain electrode 122 can be suppressed, so that the off characteristics of the semiconductor device 200 can be improved.

[0202] Further, the height of the second side wall 133s is high, so that the electron density of the two-dimensional electron gas 110 below the second side wall 133s is high. Thus, the parasitic resistance between the gate electrode 140 and the source electrode 121 can be low resistance, so that the on-resistance can be low resistance.

[0203] Thus, according to the semiconductor device 200 of the present embodiment, the on-resistance can be low resistance and the off characteristics can be improved.

[0204] Further, in the semiconductor device 200 of the present embodiment, the lower surface 144a of the second gate field plate 144 includes the inclined surface 144c in which the interval between the barrier layer 104 increases monotonously in the direction from the gate electrode 140 to the drain electrode 122.

[0205] Thus, the electric field can be dispersed toward the end portion of the gate electrode 140 on the drain electrode 122 side and the lowest position (position P3) of the lower surface 144a of the second gate field plate 144, and the electric field concentration can be relaxed.

[0206] Here, Figure 12 is an enlarged sectional view for illustrating the shape of the lower surface 144a of the extension portion 142d on the drain electrode 122 side of the gate electrode 140 of the semiconductor device 200 of the present embodiment. The first elevation angle θ1 to the fifth elevation angle θ5 are also defined as shown in Figure 12 the present embodiment. The first elevation angle θ1 to the fifth elevation angle θ5 are respectively defined by the imaginary lines VL1 to VL5 and the positions P1 to P5, as in the case of the semiconductor device 100 of Embodiment 1.

[0207] like Figure 12 As shown, the second elevation angle θ2 is larger than the third elevation angle θ3. Furthermore, the second elevation angle θ2 is larger than the fifth elevation angle θ5. The third elevation angle θ3 is larger than the fourth elevation angle θ4. Thus, similar to the case in Embodiment 1, it is possible to achieve electric field mitigation and a reduction in parasitic capacitance.

[0208] Furthermore, in the modified examples described later, there are cases where the second elevation angle θ2 is smaller than the third elevation angle θ3. Figure 15 (Semiconductor device 200B). Furthermore, although not shown in the figure, the second elevation angle θ2 can also be equal to the third elevation angle θ3. Furthermore, the third elevation angle θ3 can also be smaller than the fourth elevation angle θ4. Furthermore, the third elevation angle θ3, the fourth elevation angle θ4, and the fifth elevation angle θ5 can also be equal. Thus, the variations related to each elevation angle described in Embodiment 1 and its variations can also be applied in this embodiment.

[0209] [Manufacturing Method]

[0210] The following is for reference Figures 13A-13E The method for manufacturing the semiconductor device 200 of this embodiment will be explained.

[0211] Figures 13A-13E These are cross-sectional views of various structures used to illustrate the manufacturing method of the semiconductor device 200 of this embodiment. Figures 13A-13E These figures show the cross-sectional structure of the semiconductor device 200 during manufacturing. Additionally, the three lines L1 to L3 extending along the Z-axis from the upper surface of the barrier layer 104, as shown in each figure, are respectively... Figure 4A The lines L1 to L3 shown are the same.

[0212] First, the processes up to forming the second insulating layer 132 are the same as in Embodiment 1. That is, by using... Figure 4A and Figure 4B The described process forms a buffer layer 102, a channel layer 103, a barrier layer 104, a first insulating layer 131, a source electrode 121, a drain electrode 122, and a second insulating layer 132 on the substrate 101.

[0213] Next, as Figure 13A As shown, a resist pattern 250 with defined areas is formed. Specifically, after applying the resist, the resist is patterned using photolithography to form the third opening 132B (see reference). Figure 13B A mask (resist pattern 250) is formed outside the area of ​​the resist pattern 250. An opening in the resist pattern 250 is formed, for example, by removing the area between line L1 and line L3.

[0214] Next, as Figure 13BAs shown, after the second insulating layer 132 is selectively removed by a wet etching method to form the third opening portion 132B, the mask (resist pattern 250) is removed. For example, a portion of the second insulating layer 132 is selectively removed by BHF at room temperature. Alternatively, the second insulating layer 132 can be selectively removed by DHF, and the mixing ratio of BHF can take any value.

[0215] In the present embodiment, the first insulating layer 131 is SiN, the second insulating layer 132 is SiO2, and the second insulating layer 132 is selectively removed by a wet etching method based on BHF, but the combination is not limited to this. Any combination can be used as long as the second insulating layer 132 can be selectively removed. Although a wet etching method is used, the first insulating layer 131 can be SiO2, the second insulating layer 132 can be SiN, and a chemical dry etching method can be used.

[0216] Next, as shown in FIG. 6A, the second opening portion 132A and the third insulating layer 233 are formed. Specifically, first, after the resist is applied, the resist is patterned by photolithography to form a mask. Specifically, in plan view, the drain electrode 122 side end portion of the resist pattern is located in the third opening portion 132B (specifically, at a position coinciding with the line LI). In addition, the source electrode 121 side end portion of the resist pattern is located on the second insulating layer 132 on the source electrode 121 side of the third opening portion 132B (specifically, at a position coinciding with the line L2). Figure 13C Next, using a dry etching method, the second opening portion 132A is formed in the first insulating layer 131 and the second insulating layer 132 to expose the barrier layer 104. After the second opening portion 132A is formed, the mask and the polymer are removed.

[0217] Next, a third insulating layer 233 composed of SiN having a thickness of 100 nm is deposited by a plasma CVD method. The third insulating layer 233 is provided so as to fill the second opening portion 132A.

[0218] Next, as shown in FIG. 6B, the third insulating layer 233 is etched back using a dry etching method. As a result, the first side wall 233d and the second side wall 133s are formed so as to expose the barrier layer 104.

[0219] Figure 13D Next, as shown in FIG. 6B, the third insulating layer 233 is etched back using a dry etching method. As a result, the first side wall 233d and the second side wall 133s are formed so as to expose the barrier layer 104.

[0220] Next, as shown in FIG. 6B, the third insulating layer 233 is etched back using a dry etching method. As a result, the first side wall 233d and the second side wall 133s are formed so as to expose the barrier layer 104. Figure 13E ​The gate electrode 140 is formed. Specifically, TiN having a thickness of 50 nm and Al having a thickness of 450 nm are sequentially deposited by a sputtering method. Then, a mask is formed by patterning a resist after applying the resist using a photolithography method in the region where the gate electrode 140 is formed. Subsequently, the mask and the polymer are removed after the gate electrode 140 is formed using a dry etching method.

[0221] The subsequent processes are the same as in Embodiment 1. Specifically, the fourth insulating layer 134 and the source field plate 123 are formed.

[0222] By going through the above series of processes, Figure 10 The semiconductor device 200 having the configuration shown in FIG. 1 is completed.

[0223] (Modified Example of Embodiment 2)

[0224] Next, a modified example of Embodiment 2 will be described.

[0225] In the modified example shown below, the height of the first sidewall 233d and / or the shape of the lower surface of the overhang 142d of the gate electrode 140 is different from that of Embodiment 2. Hereinafter, the description will be focused on the difference from Embodiment 2, and the common description will be omitted or simplified.

[0226] [Modified Example 1]

[0227] First, the semiconductor device 200A of Modified Example 1 will be described with reference to FIG. 6. Figure 14 Modified Example 1 will be described.

[0228] Figure 14 is an enlarged sectional view for illustrating the shape of the sidewall of the semiconductor device 200A of Modified Example 1 of Embodiment 2. As shown in Figure 14 In this modified example, the height of the first sidewall 233d is higher than that of Embodiment 2. Specifically, the height H SWd of the first sidewall 233d is lower than the height H SWs of the second sidewall 133s, and is higher than the film thickness H I of the first insulating layer 131d.

[0229] With this configuration, the distance between the two-dimensional electron gas 110 and the overhang 142d of the gate electrode 140 is easily ensured to be long just below the first sidewall 233d, so the parasitic capacitance (gate-drain capacitance Cgd) can be reduced.

[0230] [Modified Example 2]

[0231] Next, the semiconductor device 200B of Modified Example 2 will be described with reference to FIG. 7. Figure 15 Modified Example 2 will be described.

[0232] Figure 15This is an enlarged cross-sectional view illustrating the shape of the sidewall of the semiconductor device 200B in Modified Example 2 of Embodiment 2. For example... Figure 15 As shown, in this modified example, the height of the first sidewall 233d is lower than that in Embodiment 2. Specifically, the height H of the first sidewall 233d is... SWd The film thickness H is greater than that of the first insulating layer 131d I It is lower than the upper surface of the first insulating layer 131d (the portion that contacts the flat surface 144b of the protrusion 142d). Therefore, a step difference is created between the upper surface 233da of the first sidewall 233d and the upper surface of the first insulating layer 131d.

[0233] With this structure, the first sidewall 233d becomes lower, making it easier for the depletion layer to extend directly below the first sidewall 233d when the transistor is turned off, thus suppressing the short-channel effect. As a result, the cutoff characteristics are improved.

[0234] [Variation Example 3]

[0235] Next, use Figure 16 The modified example 3 will be explained.

[0236] Figure 16 This is an enlarged cross-sectional view used to illustrate the shape of the sidewall of the semiconductor device 200C in Modified Example 3 of Embodiment 2. For example... Figure 16 As shown, in this modified example, the shape of the first sidewall 233d is the same as that in Embodiment 2, but the shape of the lower surface of the protrusion 142d of the gate electrode 140 is different. Specifically, the lower surface 144a of the second gate field plate 144 does not include an inclined surface. The lower surface 144a is a flat surface parallel to the main surface of the substrate 101.

[0237] Even with this structure, the distance between the first gate field plate 143 and the two-dimensional electron gas 110 is shorter due to the lower height of the first sidewall 233d. Therefore, when the transistor is turned off, the depletion layer within the channel layer 103 can easily expand, suppressing short-channel effects. Consequently, the cutoff leakage current between the source electrode 121 and the drain electrode 122 can be suppressed, thus improving the cutoff characteristics of the semiconductor device 200.

[0238] Furthermore, since the second sidewall 133s has a higher height, the electron density of the two-dimensional electron gas 110 below the second sidewall 133s is higher. Therefore, the parasitic resistance between the gate electrode 140 and the source electrode 121 can be made low, thus reducing the on-resistance.

[0239] Thus, the semiconductor device 200C of this modified example can also achieve both low on-resistance and improved cut-off characteristics.

[0240] [Variation Example 4]

[0241] Next, use Figure 17 The following explanation is given for variation 4.

[0242] Figure 17 This is an enlarged cross-sectional view used to illustrate the shape of the sidewall of the semiconductor device 200D in Modification 4 of Embodiment 2. For example... Figure 17 As shown, in this modified example, compared to modified example 3, the height of the first sidewall 233d is increased. Specifically, the height H of the first sidewall 233d is... SWd The height H of the second sidewall 133s SWs Low, compared to the film thickness H of the first insulating layer 131d I high.

[0243] With this structure, the distance between the two-dimensional electron gas 110 and the protrusion 142d of the gate electrode 140 can be made longer directly below the first sidewall 233d, so that the parasitic capacitance (gate-drain capacitance Cgd) can be reduced.

[0244] [Variation Example 5]

[0245] Next, use Figure 18 The modified example 5 will be explained.

[0246] Figure 18 This is an enlarged cross-sectional view illustrating the shape of the sidewall of the semiconductor device 200E in Modification 5 of Embodiment 2. For example... Figure 18 As shown, in this modified example, compared to modified example 3, the height of the first sidewall 233d becomes lower. Specifically, the height H of the first sidewall 233d is... SWd The film thickness H is greater than that of the first insulating layer 131d I It is lower than the upper surface of the first insulating layer 131d (the portion that contacts the flat surface 144b of the protrusion 142d). Therefore, a step difference is created between the upper surface 233da of the first sidewall 233d and the upper surface of the first insulating layer 131d.

[0247] With this structure, the first sidewall 233d becomes lower, making it easier for the depletion layer directly below the first sidewall 233d to extend when the transistor is turned off, thus suppressing the short-channel effect. As a result, the cutoff characteristics are improved.

[0248] (Other implementation methods)

[0249] The above describes the semiconductor device according to one or more of the embodiments based on the embodiments, but the present disclosure is not limited to these embodiments. For example, modes obtained by applying various modifications to the embodiments that a person skilled in the art can think of or modes obtained by arbitrarily combining constituent elements and functions of the embodiments within a range not departing from the gist of the present disclosure are also included in the present disclosure.

[0250] For example, in each of the above-described embodiments and modified examples, an example in which the second insulating layer 132 covers the source electrode 121 and the drain electrode 122 is described, but is not limited thereto. The second insulating layer 132 can be disposed at least directly below the overhangs 142s and 142d of the gate electrode 140. That is, in a range not overlapping with the gate electrode 140 in plan view, for example, between the gate electrode 140 and the source electrode 121, between the gate electrode 140 and the drain electrode 122, and directly above the source electrode 121 and the drain electrode 122, and the like, the second insulating layer 132 can not be provided.

[0251] Further, the above-described embodiments can be variously changed, replaced, added, omitted, and the like within the scope of the claims or the equivalent thereof.

[0252] Industrial Applicability

[0253] The semiconductor device of the present disclosure has utility for power switching elements and the like used in communication devices, inverters, power supply circuits, and the like that require high-speed operation.

[0254] Mark Description

[0255] 100, 100A, 100B, 100C, 200, 200A, 200B, 200C, 200D, 200E Semiconductor device

[0256] 101 Substrate

[0257] 102 Buffer layer

[0258] 103 Channel layer

[0259] 104 Barrier layer

[0260] 110 Two-dimensional electron gas

[0261] 121 Source electrode

[0262] 122 Drain electrode

[0263] 123 Source field plate

[0264] 130 Insulating layer

[0265] 131, 131d, 131s First insulating layer

[0266] 131A first opening portion

[0267] 132, 132d, 132s second insulating layer

[0268] 132A second opening portion

[0269] 132B third opening portion

[0270] 133, 233 third insulating layer

[0271] 133d, 233d first side wall

[0272] 133da, 133sa, 233da upper surface

[0273] 133s second side wall

[0274] 134 fourth insulating layer

[0275] 140 gate electrode

[0276] 141 junction portion

[0277] 142d, 142s protruding portion

[0278] 143 first gate field plate

[0279] 143a, 144a lower surface

[0280] 144 second gate field plate

[0281] 144b, 144d, 144f flat surface

[0282] 144c, 144e inclined surface

[0283] 150, 250 resist pattern

[0284] 151, 152 mask portion

Claims

1. A semiconductor device characterized by comprising: a substrate; a channel layer provided above the substrate, composed of a Group III nitride semiconductor; a barrier layer provided above the channel layer, composed of a Group III nitride semiconductor having a larger band gap than the channel layer; a source electrode and a drain electrode provided above the barrier layer, separated from each other by a space in a first direction in plan view of the substrate; a gate electrode provided above the barrier layer, separated from the source electrode and the drain electrode by a space in the first direction; and an insulating layer provided above the barrier layer between the gate electrode and the source electrode and the drain electrode; the insulating layer including a first insulating layer composed of silicon nitride as a lowermost layer and a second insulating layer composed of silicon oxide above the first insulating layer; the gate electrode including: a junction portion in Schottky junction with the barrier layer; and a protruding portion protruding toward the source electrode side and the drain electrode side, respectively, in the first direction, further than the junction portion; between the protruding portion and the barrier layer in a second direction orthogonal to a main surface of the substrate, the insulating layer including: a first side wall provided at a junction-portion-side end of the insulating layer between the junction portion and the drain electrode; and a second side wall provided at a junction-portion-side end of the insulating layer between the junction portion and the source electrode; the protruding portion including: a first electric field plate in a section from a first position to a second position in the plan view, the first position being a junction-portion-side end of the first side wall, the second position being a drain-electrode-side end of the first side wall; and a second electric field plate in a section from the second position to a third position in the plan view, the third position being a drain-electrode-side end of the protruding portion; between the second electric field plate and the barrier layer, the first insulating layer and the second insulating layer being stacked; in a cross section parallel to the first direction and the second direction, respectively, and passing through the junction portion, a tangent line at the first position of an upper surface of the first side wall has a first elevation angle with respect to the main surface; a highest position of a lower surface of the first electric field plate has a second elevation angle with respect to the main surface, as viewed from the first position; a drain-electrode-side end of a lowest position of a lower surface of the second electric field plate has a third elevation angle with respect to the main surface, as viewed from the first position; and a highest position of an upper surface of the first side wall is lower than a highest position of an upper surface of the second side wall.

2. The semiconductor device according to claim 1, characterized in that: a lower surface of the second electric field plate includes a sloping surface, a separation from the barrier layer of which monotonously increases in a direction from the gate electrode toward the drain electrode.

3. The semiconductor device according to claim 1 or 2, characterized in that: the protruding portion on the source-electrode side than the second side wall is not lower than the highest position of the upper surface of the first side wall.

4. The semiconductor device according to claim 2, characterized in that: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ In the above cross section, when a zenith angle with respect to the main surface when viewing the drain electrode side end of the lower surface highest position of the second electric field plate from the drain electrode side end of the lower surface lowest position of the second electric field plate is a fifth zenith angle, the fifth zenith angle is smaller than the second zenith angle.

5. The semiconductor device according to claim 1 or 4, wherein The inclined surface includes at least one inclined surface having an inclination angle with respect to the main surface within a range of 45 degrees ± 5 degrees.

6. The semiconductor device according to claim 1 or 4, wherein In the above cross section, when a zenith angle with respect to the main surface when viewing the drain electrode side end of the lower surface highest position of the second electric field plate from the first position is a fourth zenith angle, the third zenith angle is larger than the fourth zenith angle.

7. The semiconductor device according to claim 4, wherein The second insulating layer overlaps the lower surface lowest position of the second electric field plate in the above plan view.

8. The semiconductor device according to claim 1 or 4, wherein In the above cross section, when a zenith angle with respect to the main surface when viewing the drain electrode side end of the lower surface highest position of the second electric field plate from the first position is a fourth zenith angle, the fourth zenith angle is larger than the third zenith angle.

9. The semiconductor device according to claim 1 or 4, wherein The lower surface of the second electric field plate contacts the first insulating layer.

10. The semiconductor device according to claim 1 or 4, wherein In the above cross section, when a zenith angle with respect to the main surface when viewing the drain electrode side end of the lower surface highest position of the second electric field plate from the first position is a fourth zenith angle, the fourth zenith angle is equal to the third zenith angle.

11. The semiconductor device according to claim 3, wherein a source electric field plate is provided above the gate electrode and is set to the same potential as the source electrode; In the above cross section, the source electric field plate does not protrude to a position lower than an imaginary line connecting the first position and the drain electrode side end of the lower surface highest position of the second electric field plate.

12. The semiconductor device according to claim 11, wherein In the above cross section, a surface of the source electric field plate contacts the imaginary line.

Images