A SLAM hardware acceleration architecture suitable for resource-constrained environments

Abstract

The application discloses a SLAM hardware acceleration architecture suitable for a resource-limited environment and belongs to the field of autonomous navigation.The application is proposed to greatly improve the performance of a SLAM system in terms of power consumption, time delay and the like, and to realize SLAM acceleration under resource limitation. The application transplants the computation-intensive part in a SLAM algorithm to an FPGA for parallel computation, so that the performance of the SLAM system is greatly improved in terms of power consumption, time delay and the like. The method of the application can be customized according to specific application scenarios, the architecture of the application adopts a front-end and rear-end dual acceleration idea to improve the execution efficiency of the SLAM algorithm, and can be customized and optimized according to specific application requirements, and can provide method guidance for the design of a binocular SLAM SOC chip. The application is used in a SLAM hardware acceleration method.

Description

Technical Field

[0001] This invention belongs to the field of autonomous navigation, simultaneous localization and mapping technology, and specifically relates to a SLAM hardware accelerator architecture for resource-constrained embedded system platforms. Background Technology

[0002] SLAM (Simultaneous Localization and Mapping) is one of the most critical technologies in the field of autonomous navigation. It enables unmanned systems to incrementally build maps of their surroundings in an unknown environment based on data captured by sensors, and provides real-time, accurate self-position information, supporting the system to achieve autonomous operation and intelligent decision-making in complex and dynamic environments.

[0003] SLAM has wide applications in autonomous driving, navigation robots, and 3D reconstruction. Its core requirements include efficient data processing capabilities, real-time map building and localization, and robustness in complex environments. SLAM algorithms typically require processing large amounts of sensor data, including camera images, LiDAR data, and inertial measurement unit (IMU) data. The high throughput and real-time processing requirements of this data pose significant challenges to implementing SLAM on embedded platforms. Traditional CPUs often cannot meet the computationally intensive requirements of SLAM algorithms, leading to performance bottlenecks and high power consumption.

[0004] GPUs (Graphics Processing Units) possess thousands of computing cores, significantly improving the performance of SLAM systems by parallelizing computationally intensive tasks such as image data processing, feature extraction, and matching. However, GPUs have several significant drawbacks in SLAM acceleration: First, GPUs consume a lot of power, making them unsuitable for power-sensitive embedded systems; second, due to their complex architecture and long data transmission paths, GPUs are unsuitable for environments with extremely high real-time requirements; furthermore, while GPUs have powerful parallel computing capabilities, their high versatility means that performance optimization cannot be achieved through flexible architectural design in specific applications.

[0005] An FPGA (Field-Programmable Gate Array) is a flexible programmable logic device with a large number of programmable logic units (such as logic gates, registers, and DSP blocks) and programmable connectivity resources (such as on-chip interconnects). FPGAs can implement various digital circuit functions by configuring and connecting these resources, thereby enabling user-defined hardware functions. Compared to GPUs, FPGAs have the following significant advantages: First, FPGAs have high parallel processing capabilities, capable of processing multiple data streams simultaneously, which is particularly important for the numerous matrix operations and image processing tasks involved in SLAM algorithms; second, the programmability of FPGAs allows for customized optimization according to specific application requirements, thereby reducing power consumption while maintaining high performance; furthermore, FPGAs excel in low-latency data processing, meeting the stringent real-time requirements of SLAM systems.

[0006] The prior art, document number CN114253511A, discloses a SLAM hardware acceleration based on lidar, which includes a pose data memory, an odometry data memory, a laser data memory, and a map data memory; a motion model module connected to the pose data memory and the odometry data memory respectively, which calculates the initial particle pose at the current moment and superimposes Gaussian noise; a scan matching module connected to the motion model module, the laser data memory, and the map data memory respectively, which calculates particle scores based on the initial calculation values ​​output by the motion model module; a particle data memory connected to the scan matching module; a resampling module connected to the particle data memory, which accumulates the scores of the laser data, obtains the particle weights, and performs resampling based on the weights; and a particle post-calculation pose data memory connected to the resampling module.

[0007] Prior art, document number CN109919825A, discloses an ORB-SLAM hardware accelerator, which includes an FPGA hardware acceleration module for accelerating feature extraction and feature matching; a sensor module for capturing images; and a processor system that acts as the host to control the FPGA hardware acceleration module and the sensor module, and is responsible for performing pose estimation, pose optimization, and map updating. It utilizes the FPGA hardware acceleration module to accelerate the most computationally intensive and time-consuming processes in the ORB-SLAM workflow, effectively improving the ORB-SLAM running speed and reducing power consumption, significantly improving the energy efficiency ratio, and reducing the difficulty of deploying ORB-SLAM on power-constrained platforms.

[0008] In summary, no existing technology has focused on proposing solutions for embedded system platforms with severely limited resources such as computing power, storage, and energy. Summary of the Invention

[0009] The technical problem to be solved by this invention is:

[0010] The purpose of this invention is to propose a SLAM hardware acceleration architecture suitable for resource-constrained environments, so as to significantly improve the performance of SLAM systems in terms of power consumption and latency, and achieve SLAM acceleration under resource constraints.

[0011] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows:

[0012] A SLAM hardware acceleration architecture suitable for resource-constrained environments, the design process of which is as follows:

[0013] Step 1: FPGA-based synchronous binocular image acquisition

[0014] Utilizing the parallelism of the FPGA system, the left and right image data acquired by the binocular camera are synchronously stored in a FIFO buffer. For each image channel, two BANK storage spaces are allocated, and data management is performed using a ping-pong operation. After system initialization, the first data of the first frame image is written to the starting address of BANK1. The DRAM control module counts the output data and allocates these data to the corresponding address spaces. When the counter reaches the maximum write address of the current BANK, it indicates that the storage of one frame image is complete. When each frame reset signal arrives, the system switches to BANK2 for data storage. At this time, the pointer points to the starting address of BANK2, and the storage process of the next frame image data continues.

[0015] Simultaneously, the acquired RGB images are preprocessed. First, the RGB images are converted into grayscale images. Then, Gaussian filtering is used to remove isolated noise points and enhance the smoothness and stability of the images. Next, image distortion caused by the camera lens is corrected to ensure the accuracy and reliability of subsequent feature extraction and matching.

[0016] Step 2: Image Feature Extraction and Matching

[0017] The specific implementation process of this step is as follows: First, the image received in step one is divided into blocks and processed in parallel using a multi-level buffered pipeline; the input data and floating-point numbers in the intermediate calculation process are converted to fixed-point number format to avoid data overflow during the calculation process; the feature extraction step utilizes FPGA parallel computing to simultaneously detect multiple pixel blocks with significant changes in the image and outputs the coordinate pairs of these key points; the feature description step generates a unique descriptor for each feature point; the feature matching step uses methods such as Hamming distance to match image features and identify corresponding feature points between frames;

[0018] Step 3: High-speed data communication between FPGA and CPU

[0019] After SLAM feature matching is completed, the CPU sends memory address information to the FPGA via the high-speed bus and initiates data transfer. The FPGA writes the matching result to the specified memory address via DMA and updates its status to "processing complete." Upon detecting the status update signal, the CPU reads the matching result from memory and executes the following algorithm operations:

[0020] First, error calculation and optimization are performed, using algorithms such as RANSAC to remove mismatched feature points and ensure the reliability of the matching results. Next, the CPU performs pose estimation, calculates the pose transformation of the current frame relative to the map, and further optimizes the pose and map point positions using the BA optimization algorithm. Subsequently, keyframe management is updated to ensure that the system effectively selects and maintains keyframes. After completing the above steps, the CPU again transmits the processed pose data, map data, and motion model information to the FPGA via the DMA high-speed bus, where the FPGA performs hardware acceleration processing of the extended Kalman filter (EKF) process.

[0021] Step 4: Extended Kalman Filter Accelerator

[0022] In the previous step, the initial state estimate of the filter, the covariance matrix, the system model parameters, and the sensor observation data have been loaded into the internal memory of the FPGA. The FPGA is equipped with a state prediction unit, a covariance prediction unit, a Kalman gain calculation unit, a state update unit, and a covariance update unit. These units can perform parallel computing to accelerate the hardware of the core steps of the EKF algorithm, namely state prediction, covariance prediction, Kalman gain calculation, and state update.

[0023] The hardware architecture also includes multiple parallel computing modules for efficient matrix operations; the control unit coordinates the workflow of all computing units, manages data transmission, allocation of computing tasks and control of the iteration process, and ensures that the SLAM system runs stably and efficiently in real-time applications.

[0024] Step 5: Map Update, Storage, and Display

[0025] After EKF processing, the FPGA transmits the updated pose and map information back to the CPU; the CPU updates the pose estimation of the current frame based on the information output by the EKF; at the same time, the SLAM system identifies duplicate frames by executing a loop closure detection algorithm to optimize map accuracy; the map and positioning information are displayed in real time through a display device, and the updated map data is output in real time; the CPU stores the updated map information and keyframe data in memory or on disk for subsequent map optimization and path planning.

[0026] The present invention has the following beneficial technical effects:

[0027] This invention is an FPGA-based hardware accelerator that significantly improves the performance of SLAM systems in terms of power consumption and latency by porting the computationally intensive parts of the SLAM algorithm (such as feature extraction and matching, matrix operations, etc.) to the FPGA for parallel computing. The method of this invention can be customized according to specific application scenarios, providing an effective solution for SLAM acceleration under resource constraints. This invention addresses embedded system platforms with severely limited computing power, storage, and energy resources, proposing an FPGA-based SLAM hardware accelerator architecture and design method. It provides an effective way to deploy SLAM algorithms on various micro-sized unmanned motion systems and also provides practical guidance for the application of SLAM hardware acceleration methods in real-world systems.

[0028] This invention addresses the challenge of real-time performance in autonomous exploration by robots operating in computationally limited environments. It presents a FPGA-based synchronous localization and mapping architecture that employs a dual front-end and back-end acceleration approach to improve the execution efficiency of the SLAM algorithm. This architecture can be customized and optimized according to specific application requirements, providing methodological guidance for the design of binocular SLAM SOC chips. Compared to existing technologies, this invention offers the following advantages:

[0029] (1) For embedded system platforms with strictly limited hardware and software resources, a method is proposed that can significantly improve the frame rate of the SLAM algorithm without consuming more power than a pure CPU platform and without sacrificing positioning accuracy.

[0030] (2) To further leverage the parallelization capabilities of the hardware accelerator and improve hardware acceleration performance, a dual acceleration scheme involving both the front-end and back-end was designed. By introducing a SLAM back-end accelerator architecture, the core steps of EKF, such as state prediction, covariance calculation, and state update, are effectively parallelized, thereby further improving the performance of the SLAM algorithm on resource-constrained systems.

[0031] Furthermore, this invention employs customized hardware logic and a high-bandwidth DMA interface to exchange data between the FPGA and the CPU, which greatly improves the throughput of data transmission and storage and reduces data transmission latency, thus possessing strong practical value. Attached image description:

[0032] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0033] Figure 1 This is a design diagram of an FPGA-based SLAM hardware architecture.

[0034] Figure 2 Hardware architecture design diagram for a Gaussian filter block;

[0035] Figure 3 Hardware architecture design diagram for the filtering and feature extraction modules;

[0036] Figure 4 To describe the hardware architecture design diagram of the submodule;

[0037] Figure 5 Hardware architecture design diagram for the feature matching module;

[0038] Figure 6 This is a flowchart illustrating the high-speed communication between the FPGA and the CPU.

[0039] Figure 7 Design diagram for extended Kalman filter state machine;

[0040] Figure 8 This is a diagram showing the system hardware logic configuration.

[0041] Figure 9 Diagram showing the setup of the experimental platform;

[0042] Figure 10 The test results for the dataset are shown in the image. Detailed Implementation

[0043] This invention addresses the problem that existing SLAM algorithms struggle to run in real-time on low-power platforms. It proposes a SLAM hardware accelerator to improve the overall system performance-to-power ratio, enabling low-power real-time operation. The overall system block diagram is shown below. Figure 1 As shown, the hardware configuration involves modules such as parallel processing architecture, memory management, and driver development, while the algorithm optimization involves modules such as Gaussian filtering, feature point extraction, descriptor calculation, and feature point matching.

[0044] Next, we will combine specific examples with appendices. Figure 1-10 The design method of the SLAM hardware acceleration architecture suitable for resource-constrained environments described in this invention will be further described in detail below:

[0045] Step 1: FPGA-based synchronous binocular image acquisition

[0046] Leveraging the parallelism of the FPGA system, the left and right image data acquired by the binocular camera are synchronously stored in a FIFO (First In First Out) buffer. For each image stream, two BANK memory spaces are allocated, and data management is performed using a ping-pong operation. After system initialization, the first data of the first frame is written to the starting address of BANK1. The DRAM control module counts the output data and allocates it to the corresponding address space. When the counter reaches the maximum write address of the current BANK, it indicates that the storage of one frame of image data is complete. Upon the arrival of each frame reset signal, the system switches to BANK2 for data storage. At this time, the pointer points to the starting address of BANK2, and the storage process for the next frame of image data continues.

[0047] Meanwhile, the system preprocesses the acquired RGB images. First, the RGB images are converted to grayscale images; then, Gaussian filtering is used to remove isolated noise points, enhancing the smoothness and stability of the image; next, image distortion caused by the camera lens is corrected to ensure the accuracy and reliability of subsequent feature extraction and matching.

[0048] Step 2: Image Feature Extraction and Matching

[0049] The specific implementation process of this step is as follows: First, the image received in step one is divided into blocks, and parallel processing is performed using a multi-level buffered pipeline. To improve computational efficiency while maintaining accuracy, the input data and floating-point numbers in the intermediate calculation process need to be converted to fixed-point format, and data overflow during computation should be avoided. The feature extraction step leverages the advantages of FPGA parallel computing to simultaneously detect multiple pixel blocks with significant changes in the image and output the coordinate pairs of these key points; the feature description step generates a unique descriptor for each feature point; the feature matching step uses methods such as Hamming distance to match image features and identify corresponding feature points between frames.

[0050] Step 3: High-speed data communication between FPGA and CPU

[0051] After SLAM feature matching is completed, the CPU sends memory address information to the FPGA via the high-speed bus and initiates data transfer. The FPGA writes the matching result to the specified memory address via DMA and updates its status to "processing complete." Upon detecting the status update signal, the CPU reads the matching result from memory and executes the following algorithms: First, it performs error calculation and optimization, using algorithms such as RANSAC to remove mismatched feature points, ensuring the reliability of the matching result. Next, the CPU performs pose estimation, calculating the pose transformation of the current frame relative to the map, and further optimizing the pose and map point positions using the BA optimization algorithm. Then, it updates keyframe management to ensure the system effectively selects and maintains keyframes. After these steps are completed, the CPU again transmits the processed pose data, map data, motion model, and other information to the FPGA via the DMA high-speed bus, where the FPGA performs hardware-accelerated extended Kalman filter (EKF) processing.

[0052] Step 4: Extended Kalman Filter Accelerator

[0053] In the previous step, the initial state estimate of the filter, the covariance matrix, the system model parameters, and the sensor observation data were loaded into the FPGA's internal memory. The FPGA contains state prediction units, covariance prediction units, Kalman gain calculation units, state update units, and covariance update units. These units can perform hardware acceleration of the core steps of the EKF algorithm, such as state prediction, covariance prediction, Kalman gain calculation, and state update, through parallel computing. Furthermore, the hardware architecture includes multiple parallel computing modules for efficient matrix operations; the control unit coordinates the workflow of all computing units, manages data transmission, allocation of computational tasks, and control of the iteration process, ensuring the stable and efficient operation of the SLAM system in real-time applications.

[0054] Step 5: Map Update, Storage, and Display

[0055] After EKF processing, the FPGA transmits the updated pose and map information back to the CPU. The CPU updates the pose estimate for the current frame based on the EKF output. Simultaneously, the SLAM system identifies duplicate frames by executing a loop closure detection algorithm, optimizing map accuracy. The system displays the map and positioning information in real time via a display device and outputs updated map data in real time. The CPU stores the updated map information and keyframe data in memory or on disk for subsequent map optimization and path planning.

[0056] The implementation of the above steps will be further explained as follows:

[0057] Step 1: FPGA-based image acquisition and preprocessing system

[0058] In the FPGA, a row-sized First-In-First-Out (FIFO) memory area is implemented for image data processing. New valid data is allowed to be written when the area is empty after being read. Once all data in the row has been written, a read state machine is triggered to write the data to SDRAM until the area is empty again. Subsequently, a burst stop command and a precharge command are sent, and finally a refresh command is sent to maintain SDRAM data integrity.

[0059] During image acquisition, only odd-numbered rows are acquired to avoid falling into the field blanking period. Acquisition begins after a certain time lag in the field synchronization signal and stops after a certain number of rows have been acquired. Row data acquisition begins after a certain time lag in the row synchronization signal, and a frequency divider counter converts the input clock to a suitable acquisition frequency. This ensures that complete and valid data is acquired for 640×480 pixel input images, avoiding data falling into the blanking period.

[0060] The system stores the converted 30-bit RGB data into SDRAM. To accelerate storage, the SDRAM is virtualized into four data ports (two read ports and two write ports), working simultaneously with four banks. The first bank stores a portion of the R and G data, and the second bank stores the remaining G and B data, ensuring on-demand data access and improving efficiency. Then, the RGB image undergoes grayscale processing using the following formula:

[0061] Y = 0.299R + 0.587G + 0.144B (1)

[0062] Y=((77R+150G+29B)>>8) (2)

[0063] To reduce noise interference, Gaussian filtering is applied to the image. The hardware architecture of the Gaussian filtering module is as follows: Figure 2 As shown, the formula is:

[0064]

[0065] In the image filtering design, a BRAM module is used to cache pixel data for the filter core rows, while a MIG_IP core and a 128-bit wide FIFO are used to achieve continuous data reading and processing. During writing, data is first stored in the FIFO and repeated multiple times to cache the entire frame of the image; during reading, data is first retrieved from the FIFO and then passed to the subsequent image processing module to ensure efficient data processing and smooth operation.

[0066] To prevent image data interleaving, the system uses two DDR3 banks to cache data read by the acquisition modules. A ping-pong operation switches between the two storage spaces to ensure that each frame of image data is stored and read sequentially. When the count reaches the maximum write address of the DDR3 bank, the system switches to the other bank to continue storing, ensuring the continuity and stability of the data stream.

[0067] Using pre-calibrated camera parameters, the system applies a lens distortion correction algorithm to correct image distortion caused by the camera lens. This correction step is crucial for maintaining the accuracy and reliability of feature extraction and matching tasks.

[0068] Step 2: Image Feature Extraction and Matching Based on FPGA

[0069] The architecture design of the feature extraction module is as follows: Figure 3 As shown, due to the involvement of multi-line image operations, a 5-line row buffer is needed to temporarily store the image data. The row buffer is implemented using BRAM, and data is retrieved via addressing as a sequential circuit. To achieve parallel processing, a 5×5 image block composed of flip-flops is designed to ensure that the system can process multiple pixel values ​​simultaneously. The grayscale comparison module is responsible for calculating the difference between pixels in the image block and comparing it with a preset threshold. The result outputs two sets of logical values, representing whether a specific condition is met. The continuity detection module performs continuity detection on pixels that meet the condition in parallel. The two detection modules output the results simultaneously, and the final output is obtained by ORing the results.

[0070] In an FPGA, feature point extraction is completed and then stored in a row buffer. Since the RAM on the FPGA board is shared by multiple modules, it cannot be guaranteed that feature point data will be written to RAM at any time; therefore, it must be temporarily stored in a row buffer first. By employing a double-buffering mechanism, one row buffer writes to RAM while the other receives feature point data, ensuring sufficient margin for AXI HP bus transmission speed and RAM write speed. After the row buffer data is written to RAM, the space in the multiple row buffers awaits transmission from the PS-side CPU to the CPU processing board via Ethernet. The CPU utilizes its high performance to parse the data into the specified format and integrate it into the visual inertial odometry system.

[0071] In ORB-SLAM, the image pyramid is constructed using an 8-layer pyramid with a scaling factor of 1.2. The implementation utilizes the `resize` function provided by the OpenCV library, employing bilinear interpolation to achieve non-integer scaling. However, embedded SoCs typically have limited logic resources, making it impossible to support complex non-integer scaling. To conserve logic resources, this system adopts an integer scaling strategy, specifically a 3-layer image pyramid with a scaling factor of 2 for each layer, resulting in resolutions of 752×480, 376×240, and 188×120.

[0072] The image pyramid layering module mainly consists of a row and column counter, a pixel merging module, and a pixel buffer row. The row and column counter guides the pixel merging process. The pixel merging module includes two parts: adjacent pixel merging and inter-row same-column pixel merging. The adjacent pixel merging module adds adjacent pixels and outputs the result; the inter-row same-column pixel merging module extracts pixels in the same column from the pixel buffer row based on the column number of the current row's pixels, adds them, and outputs the merged pixel value. The pixel buffer row module stores the pixel values ​​of the previous row. When a new pixel is received from the camera, a pixel pulse triggers the 10-bit column counter to increment, and the least significant bit signal is sent to the adjacent pixel merging module to control the pixel storage or merging operation. The merged pixel data is stored in the first-layer buffer row and input to the inter-row pixel merging module. The inter-row pixel merging module extracts pixels in the same column from the previous row of the buffer row based on the least significant bit signal of the row counter, merges them, and outputs 10-bit wide pixel data, completing the 2x scaling process. Next, following the same principle, using the second-layer image pixels as input, the pixel scaling of the third-layer image continues. During the transition from the second to the third layer, the row and column counters use the previous bit of the count value as the control signal for the pixel merging module.

[0073] To improve the quality of feature points, this invention introduces a non-maximum suppression module during feature point extraction. This module eliminates multiple FAST corner points with small responses in local image patches, retaining only points with the most significant features. The non-maximum suppression module shares the same pixel buffer with the FAST corner detection module, effectively saving FPGA resources. First, the response value calculation module calculates the response values ​​of 16 representative pixels in the 7×7 image patch, stores these 12-bit response values ​​in a row buffer, and stores the temporary calculated values ​​in a 3×3 response value block. Finally, the response value comparison module compares the response value of the center point of the 3×3 response value block with the surrounding 8 response values ​​and outputs the final result.

[0074] Hardware architecture of the feature description module, such as Figure 4As shown, the pixel buffer is configured with 31 rows of pixel row buffers, and the row buffer data is synchronized to the 31×31 image block and the 7×7 image block. The point-to-point relationship calculation module calculates the grayscale value relationship of point pairs in the 31×31 image block and outputs 256 bits of descriptive information. The centroid angle calculation module calculates the centroid position in the 7×7 image block and converts it into 8 bits of centroid angle information. The descriptor shifting and rotating module performs a shift operation on the 256 bits of descriptive information based on the centroid angle information, realizing the dedirection operation of the descriptor, and finally outputs it. The two main operations of the ORB feature point extraction process are the BRIEF (Binary Robust Independent Elementary Features) description process and the BRIEF rotation process. The description process records the features in the pixel blocks surrounding the feature point through a data sequence of a certain length.

[0075] The hardware block diagram of the feature matching submodule is as follows: Figure 5 As shown. For two images, after using the ORB feature point detection and descriptor generation algorithm, detected feature point descriptors are generated. Assuming b1 and b2 are descriptors of a certain feature point in the two images, they are matched by calculating their Hamming distance D:

[0076]

[0077] The smaller the value of D, the higher the similarity between the two feature points. If D satisfies the set Hamming distance, the two feature points are successfully matched, thus obtaining the coordinates of the corresponding feature points in the two images. XOR calculation is very easy to implement in FPGA, which further speeds up the feature matching algorithm.

[0078] Step 3: High-speed communication between FPGA and CPU

[0079] The process in step three is as follows: Figure 6 As shown, the CPU prepares the raw image data to be processed and stores it in the system's DRAM. Specific memory address spaces are allocated in the DRAM for the raw data and processing results, and access permissions for the memory regions are configured to ensure that the FPGA and CPU can correctly access these regions.

[0080] The CPU configures the DMA controller, specifying the source and destination data addresses, and setting the data block size, transfer length, and mode. The CPU writes control commands to the FPGA's instruction register via the DMA controller, instructing the FPGA to activate the hardware acceleration module. These control commands include the source and destination data addresses, along with relevant configuration information, ensuring the FPGA can process data correctly. Upon receiving these instructions, the FPGA's internal registers begin executing the corresponding acceleration task.

[0081] After the FPGA accelerator is started, the CPU enters a loop, periodically querying the FPGA's status register to check the progress of data processing. This query is typically achieved by reading specific registers from the FPGA. Simultaneously, the FPGA hardware acceleration module initiates memory access requests to the CPU via the DMA controller. This request contains the address of the source data to be read and the address of the target data to be written.

[0082] When the CPU receives a memory access request from the FPGA, it forwards the request to the memory controller. The memory controller is responsible for performing the actual memory read / write operations based on the request, reading data from DRAM and transferring it to the FPGA. After obtaining the raw data, the FPGA uses its hardware acceleration module to perform high-speed processing. After processing, the result data is written back to the predetermined DRAM address via the DMA controller.

[0083] After the FPGA completes data processing, it updates its status register to indicate that processing is complete. When the CPU detects the completion flag in the FPGA status register while looping through the status, it exits the loop. After exiting the loop, the CPU reads the result data from DRAM for subsequent processing or application. Once the entire process is complete, the CPU can continue executing other tasks, while the FPGA can enter standby mode while waiting for new instructions.

[0084] Step 4: Extend the Kalman filter module

[0085] In this design, an FPGA is used to implement the hardware architecture of the extended Kalman filter algorithm. This architecture includes a state prediction unit, a covariance prediction unit, a Kalman gain calculation unit, a state update unit, and a covariance update unit. Initial state estimates, initial covariance matrices, system model parameters, and sensor observation data are loaded into the FPGA's internal memory for efficient processing.

[0086] The state prediction unit predicts the current state value by using the state estimate from the previous time step and the state transition matrix of the system model. The specific formula is as follows:

[0087] X(k|k-1)=A×X(k-1|k-1) (5)

[0088] FPGAs improve prediction speed by processing predictions of multiple state variables in parallel and employing pipelined design to optimize the hardware structure. The final output state prediction value is then used as input to the covariance prediction unit and the state update unit.

[0089] The covariance prediction unit predicts the error covariance matrix at the current time step based on the error covariance matrix from the previous time step and the state transition matrix of the system model. Its operation includes buffering input data using BRAM or FIFO for fast access, calculating the product of the state transition matrices, multiplying this product by the error covariance matrix from the previous time step to obtain an intermediate result, and adding the covariance matrix of the system process noise to the intermediate result to obtain the predicted error covariance value. The specific formula is as follows:

[0090] P(k|k-1)=A×P(k-1|k-1)×A T +Q (6)

[0091] The Kalman gain calculation unit calculates the Kalman gain based on the observed data, the observation matrix, and the prediction error covariance matrix. The calculation steps include matrix multiplication, adding the result to the observation noise covariance matrix, and then finding the inverse matrix using an iterative algorithm or a lookup table. The specific formula is as follows:

[0092] K(k)=P(k|k-1)×H T ×(H×P(k|k-1)×H T +R) -1 (7)

[0093] The state update unit updates the state estimate by combining the predicted state value, observed data, and Kalman gain. Its operation includes calculating the residual:

[0094] e(k)=Z(k)-H×X(k|k-1) (8)

[0095] Calculate the state update using Kalman gain and residuals:

[0096] ΔX(k)=K(k)ge(k) (9)

[0097] Updated state estimate:

[0098] X(k)=X(k|k-1)+ΔX(k) (10)

[0099] The covariance update unit updates the error covariance matrix based on the Kalman gain and the prediction error covariance matrix. Its operation involves matrix multiplication and addition to update the error covariance matrix for prediction and updating at the next time step. The specific formula is as follows:

[0100] P(k|k)=(IK(k)×H)×P(k|k-1) (11)

[0101] Finally, the updated state estimates are output to external devices or systems via appropriate data interfaces for subsequent control and decision-making tasks. This method achieves efficient and stable matrix operations and filtering, ensuring system reliability and real-time performance.

[0102] Furthermore, this design employs a Finite State Machine (FSM) to represent a finite number of states in the system and constrains the transitions and behaviors between these states. The state transitions and behaviors of the FSM depend on the current state and external inputs. Since the logical solution process of the EKF algorithm requires multiple steps, and each step is further broken down during implementation, this increases the complexity of the logic. Therefore, a reasonable FSM needs to be designed to control the transitions between each operational step and prevent logical confusion. Based on the logical relationships between the operational steps, the FSM can be divided into eight states. Starting from the initial state, the specific operational implementation of each state is as follows:

[0103] S0: Assign initial values ​​to each relevant variable, and enter state S1 after the assignment is completed.

[0104] S1: Calculate the product of the state Jacobian matrix and the error covariance matrix of the previous time step, store the result in the temporary register, and enter state S2.

[0105] S2: Calculate the product of the output value of state S1 and the transpose of the state Jacobian matrix, and sum the result with the process noise covariance matrix to obtain the prior error covariance matrix. After the calculation is completed, enter state S3.

[0106] S3: Calculate the product of the prior error covariance matrix and the transpose of the measurement Jacobian matrix, store the result in a temporary register, and enter state S4.

[0107] S4: Calculate the product of the measurement Jacobian matrix and the output value of state S3, sum the result with the measurement noise covariance matrix, send it to the matrix inversion module, and enter state S5.

[0108] S5: Calculate the product of the output value of state S3 and the output value of the matrix inversion module to obtain the Kalman gain. After the calculation is completed, enter state S6.

[0109] S6: Update the optimal state estimate and error covariance matrix, send the results to the state update module, and enter state S7.

[0110] S7: After the state update module completes the calculation, enter the S0 state and repeat the above process with the calculation result as the initial value.

[0111] The aforementioned FSM can effectively constrain the operational logic of the EKF algorithm, shorten the computation process, avoid unnecessary repetitive computations, and thus improve the real-time performance and system stability.

[0112] Step 5: Map Update and Display

[0113] After processing with an Extended Kalman Filter (EKF), the FPGA transmits the updated pose and map information back to the Central Processing Unit (CPU). The CPU updates the pose estimate for the current frame based on the EKF output. The camera pose in each frame is used as a node, and the relative transformations between frames are used as edges, forming a pose graph. Feature points detected in new keyframes are matched with existing map points; unmatched feature points are inserted as new map points. Each time a new frame is added, the local subgraph related to the current frame is optimized.

[0114] When a new keyframe is added, a bag-of-words model is used to find keyframes similar to the current frame as loop closure candidates. Geometric verification is performed on these candidate frames, calculating the relative pose transformation through 3D point and feature matching to validate their effectiveness. Once a loop closure is confirmed, new constraint edges are added to the pose graph. Global pose graph Bundle Adjustment (BA) is performed using all constraint edges (inter-frame constraints and loop closure constraints) to minimize the overall reprojection error, significantly reduce accumulated error, and improve the accuracy of map and pose estimation.

[0115] The computing power allocation module configures the FPGA logic circuits in real time according to the plan, adjusting the computing pipeline structure and adding or removing pipelines and matrix acceleration modules. When the platform is idle, the FPGA is turned off to save power. Considering the brief time delay in the configuration process, this module will incrementally update the computing flow, immediately and dynamically loading the computing pipelines / matrix acceleration circuits configured in the current clock cycle into the computing process to avoid waiting time and achieve zero-latency dynamic reconfiguration.

[0116] Adaptive Dynamic Adjustment of Computing Power: Optimal performance is achieved through the design of an energy efficiency ratio function. By designing a power consumption evaluation index function, the FPGA can adaptively adjust the logic circuit structure and scale based on the estimated computing power consumption index, dynamically balancing the computing power of the logic circuit with the navigation computing power requirements of the current environment, thus achieving optimal energy efficiency.

[0117] Hardware description language code (such as Verilog HDL or VHDL code) is synthesized into logic circuits and mapped onto the physical resources of the FPGA. After the embedded system powers on, the bootloader runs first. During the bootloader's startup process, a bitstream file is loaded from a predefined storage location (such as an SD card, eMMC, or flash memory) and written to the FPGA. After the FPGA configuration is complete, the bootloader continues by loading the Linux operating system, reading the device tree file, and identifying the FPGA configuration and hardware layout. After the Linux operating system boots, driver modules are loaded via the insmod command. At this point, the FPGA can work in conjunction with the ARM processor to perform tasks such as SLAM acceleration.

[0118] Through the above steps and methods, efficient real-time map updates and displays, reliable pose estimation and map optimization are achieved, ensuring the reliability and real-time performance of the system, while optimizing the system's energy consumption and performance.

[0119] To verify the effectiveness of the proposed embedded SLAM hardware acceleration method and test the functionality of the constructed FPGA-CPU hardware framework, the following methods are used for testing and verification:

[0120] The experimental platform uses the ZedBoard development board with the ZYNQ-7020 as the core chip. The ZYNQ chip mainly consists of a CPU, FPGA, and AXI bus. The CPU is a dual Cortex-A9 core ARM, and the memory is DDR3 SDRAM. The experimental platform is set up as follows: Figure 8 As shown. Based on the Vivado development environment, using the ORB-SLAM2 algorithm, and running the KITTI dataset, functions for measuring system time were added at the beginning and end of the main function. The results are as follows. Figure 9 As shown, running 271 frames of stereo images took 36.224 seconds in a pure CPU environment and 18.2857 seconds in an FPGA accelerated environment, improving the SLAM frame rate by 98.1% and running an average of 14.8 frames per second, thus verifying the effectiveness of the invention.

Claims

1. A hardware acceleration method for SLAM systems suitable for resource-constrained environments, characterized in that: Step 1: FPGA-based synchronous binocular image acquisition Utilizing the parallelism of the FPGA system, the left and right image data acquired by the binocular camera are synchronously stored in a FIFO buffer. For each image channel, two BANK storage spaces are allocated, and data management is performed using ping-pong operations. After system initialization, the first data of the first frame image is written to the starting address of BANK1. The DRAM control module counts the output data and allocates these data to the corresponding address spaces. When the counter reaches the maximum write address of the current BANK, it indicates that the storage of one frame image has been completed. When the frame reset signal arrives, the system will switch to BANK2 to store data. At this time, the pointer points to the first address of BANK2 and continues the storage process of the next frame of image data. Simultaneously, the acquired RGB images are preprocessed; Step 2: Image feature extraction and matching; Step 3: High-speed data communication between FPGA and CPU After feature matching in the SLAM system is completed, the CPU sends the memory address information to the FPGA via the high-speed bus and initiates data transmission. The FPGA writes the matching result to the specified memory address via DMA and updates its status to "processing complete." Upon detecting the status update signal, the CPU reads the matching result from memory and executes the following algorithmic operations: First, error calculation and optimization are performed, and the RANSAC algorithm is used to remove mismatched feature points. Next, the CPU performs pose estimation, calculates the pose transformation of the current frame relative to the map, and further optimizes the pose and the position of map points through the BA optimization algorithm. Then, the keyframe management is updated. After completing the above steps, the CPU once again transmits the processed pose data, map data, and motion model information to the FPGA via the DMA high-speed bus. Step 4: Hardware acceleration of the Extended Kalman Filter (EKF) process using FPGA. The FPGA contains a state prediction unit, a covariance prediction unit, a Kalman gain calculation unit, a state update unit, and a covariance update unit. Each unit performs parallel computation to accelerate the core steps of the EKF algorithm, including state prediction, covariance prediction, Kalman gain calculation, and state update. Step 5: Map Update, Storage, and Display After EKF processing, the FPGA transmits the updated pose and map information back to the CPU; the CPU updates the pose estimate of the current frame based on the information output by the EKF; at the same time, the SLAM system identifies duplicate frames by executing a loop closure detection algorithm to optimize map accuracy; the map and positioning information are displayed in real time through the display device, and the updated map data is output in real time; the CPU stores the updated map information and keyframe data in memory or disk for subsequent map optimization and path planning. The specific implementation process of step three is as follows: The CPU prepares the raw image data to be processed and stores it in the system's DRAM. Specific memory address spaces are allocated in the DRAM for the raw data and processing results, and access permissions for the memory regions are configured so that the FPGA and CPU can correctly access the memory regions. The CPU configures the DMA controller, specifies the original data address and the target data address, and sets the data block size, transfer length, and mode. The CPU writes control commands to the FPGA's instruction register through the DMA controller, notifying the FPGA to start the hardware acceleration module. These control commands include the original data address, the target data address, and related configuration information. After receiving these instructions, the FPGA's internal registers will begin executing the corresponding acceleration task. After the FPGA accelerator is started, the CPU enters a loop, periodically querying the FPGA's status register to check the progress of data processing. This query is usually achieved by reading specific registers of the FPGA. At the same time, the FPGA hardware acceleration module sends a memory access request to the CPU through the DMA controller. The request includes the address of the original data to be read and the address of the target data to be written. When the CPU receives a memory access request from the FPGA, it passes the request to the memory controller. The memory controller is responsible for performing the actual memory read and write operations according to the request, reading data from DRAM and transmitting it to the FPGA. After obtaining the raw data, the FPGA uses its hardware acceleration module to perform high-speed computation. After the processing is completed, the result data is written back to the predetermined DRAM address through the DMA controller. After the FPGA completes data processing, it updates its status register to indicate that the processing is complete. When the CPU is in the loop query state, it detects the processing completion flag in the FPGA status register and jumps out of the query loop. After jumping out of the query loop, the CPU reads the result data in DRAM for subsequent processing or application. After the whole process is completed, the CPU continues to execute other tasks, while the FPGA enters standby state while waiting for new instructions.

2. The hardware acceleration method for SLAM systems in resource-constrained environments according to claim 1, characterized in that, First, the RGB image is converted to a grayscale image; then, a Gaussian filter is used to remove isolated noise and enhance the smoothness and stability of the image; next, image distortion caused by the camera lens is corrected. The formula for grayscale processing of an RGB image is: （1） （2） To reduce noise interference, a Gaussian filter is applied to the image, using the following formula: （3） In the image filtering design, a BRAM module is used to cache the pixel data of the filter kernel row. At the same time, a MIG_IP core and a 128-bit wide FIFO are used to realize continuous data reading and processing. When writing, the data is first stored in the FIFO and repeated multiple times to cache the entire frame of the image. When reading, the data is first obtained from the FIFO and then passed to the subsequent image processing module. The acquisition module uses two BANK caches in DDR3 to prevent image data from being interleaved. It switches between the two storage spaces through a ping-pong operation, and each frame of image data is stored and read sequentially. When the count reaches the maximum write address of the DDR3 BANK, it switches to the other BANK to continue storing, ensuring the continuity and stability of the data stream.

3. The hardware acceleration method for SLAM systems in resource-constrained environments according to claim 2, characterized in that, The specific implementation process of step two is as follows: The specific implementation process of this step is as follows: First, the image received in step one is divided into blocks and processed in parallel using a multi-level buffered pipeline; the input data and floating-point numbers in the intermediate calculation process are converted into fixed-point number format to avoid data overflow during the calculation process; the feature extraction step uses FPGA for parallel computing to simultaneously detect multiple pixel blocks with significant changes in the image and output the coordinate pairs of these key points; the feature description step generates a unique descriptor for each feature point. The feature matching step uses the Hamming distance method to match image features and identify corresponding feature points between frames; The design consists of a 5×5 image block composed of triggers. The grayscale comparison module is responsible for calculating the difference between the pixels in the image block and comparing it with a preset threshold. The result outputs two sets of logical value data, which respectively indicate whether a specific condition is met. The continuity detection module performs continuity detection on the pixels that meet the condition in parallel. The two detection modules output the results at the same time, and the final output is obtained by OR operation. A dual-buffering mechanism is adopted, with one row buffer writing to RAM while the other buffer receives feature point data, so as to leave sufficient margin for the AXI HP bus transmission speed and RAM write speed. After the row buffer data is written to RAM, the space of multiple row buffers waits for the CPU on the PS side to transmit to the CPU processing board via Ethernet. The CPU uses its high performance to parse the feature point data into the specified format and integrate it into the visual inertial odometry. In ORB-SLAM, the image pyramid is constructed using an 8-layer pyramid with a scaling factor of 1.

2. The non-integer multiple image scaling is achieved by using the resize function provided by the OpenCV library through bilinear interpolation. An integer multiple image scaling strategy is adopted, specifically a 3-layer image pyramid with a scaling factor of 2 for each layer, and resolutions of 752×480, 376×240 and 188×120 respectively. The construction of the image pyramid mainly consists of row and column counters, a pixel merging module, and a pixel buffer row. The row and column counters are used to guide the pixel merging process. The pixel merging module includes two parts: merging adjacent pixels and merging pixels in the same column between rows. The adjacent pixel merging module is responsible for adding adjacent pixels and outputting the result. The inter-row same-column pixel merging module extracts same-column pixels from the pixel buffer row based on the column number of the current row pixels, performs an addition operation, and outputs the merged pixel value; The pixel buffer row module is responsible for storing the pixel values ​​of the previous row. When a new pixel is received from the camera, the pixel pulse triggers the 10-bit column counter to increment automatically, and the least significant bit signal is sent to the adjacent pixel merging module to control the pixel storage or merging operation. The merged pixel data is stored in the first-level buffer row and input to the inter-row pixel merging module. The inter-row pixel merging module extracts pixels from the previous row of the same column from the buffer row based on the least significant bit signal of the row counter, merges them, and outputs 10-bit wide pixel data to complete the 2x scaling process. Next, based on the same principle, the pixel scaling of the third layer image is continued using the pixels of the second layer image as input. In the process from the second layer to the third layer, the row and column counters use the previous bit of the count value as the control signal of the pixel merging module.

4. The hardware acceleration method for SLAM systems in resource-constrained environments according to claim 3, characterized in that, The specific implementation process of step two is as follows: A non-maximum suppression module is introduced during feature point extraction. This module is used to eliminate multiple FAST corner points with small responses in local image patches, retaining only the points with the most significant features. The non-maximum suppression module and the FAST corner detection module share the same pixel buffer to effectively save FPGA resources. First, the response value calculation module calculates the response values ​​of 16 representative pixels in the 7×7 image patch, stores these 12-bit response values ​​in the row buffer, and stores the temporary calculated values ​​in the 3×3 response value block. Finally, the response value comparison module compares the response value of the center point of the 3×3 response value block with the surrounding 8 response values ​​and outputs the final result. The pixel buffer is configured with 31 rows of pixel row buffers, and the row buffer data is synchronized to the 31×31 image block and the 7×7 image block; the point-to-point relationship calculation module calculates the grayscale value relationship of point pairs in the 31×31 image block and outputs 256 bits of descriptive information. The centroid angle calculation module calculates the centroid position in the 7×7 image block and converts it into 8-bit centroid angle information; The descriptor shifting and rotating module performs a shift operation on the 256-bit descriptor information based on the centroid angle information, thereby realizing the dedirection operation of the descriptor and finally outputting the result. After using the ORB feature point detection and descriptor generation algorithm, the detected feature point descriptors are generated, assuming... Given descriptors for a feature point in two images, matching is performed by calculating their Hamming distance D: （4） The smaller the value of D, the higher the similarity between the two feature points; if D satisfies the set Hamming distance, the two feature points are successfully matched, thus obtaining the coordinates of the corresponding feature points in the two images.

5. A hardware acceleration method for SLAM systems in resource-constrained environments according to claim 4, characterized in that, The specific implementation process of step four is as follows: Step 4: Extend the Kalman filter module The hardware architecture for implementing the extended Kalman filter algorithm on an FPGA includes a state prediction unit, a covariance prediction unit, a Kalman gain calculation unit, a state update unit, and a covariance update unit. The initial state estimate, initial covariance matrix, system model parameters, and sensor observation data are loaded into the FPGA's internal memory for efficient processing. The state prediction unit predicts the current state value by using the state estimate from the previous time step and the state transition matrix of the system model. The specific formula is as follows: （5） FPGA improves prediction speed by processing predictions of multiple state variables in parallel and by using pipelined design to optimize hardware structure. The final output state prediction value will be used as input to the covariance prediction unit and the state update unit. The covariance prediction unit predicts the error covariance matrix at the current time step based on the error covariance matrix of the previous time step and the state transition matrix of the system model. The operation process includes buffering input data using BRAM or FIFO for fast access, calculating the product of the state transition matrices, multiplying this product by the error covariance matrix of the previous time step to obtain an intermediate result, and adding the covariance matrix of the system process noise to the intermediate result to obtain the predicted error covariance value. The specific formula is as follows: （6） The Kalman gain calculation unit calculates the Kalman gain based on the observation data, the observation matrix, and the prediction error covariance matrix. The calculation steps include matrix multiplication, adding the result to the observation noise covariance matrix, and then finding the inverse matrix using an iterative algorithm or a lookup table. The specific formula is as follows: （7） The state update unit updates the state estimate by combining the predicted state value, observation data, and Kalman gain. Its operation includes calculating the residuals. （8） Calculate the state update using Kalman gain and residuals: （9） Updated state estimate: （10） The covariance update unit updates the error covariance matrix based on the Kalman gain and the prediction error covariance matrix. The operation involves matrix multiplication and addition to update the error covariance matrix for prediction and updating at the next time step. The specific formula is as follows: （11） Finally, the updated state estimate is output to external devices or systems through an appropriate data interface for use in subsequent control and decision-making tasks.

6. A hardware acceleration method for SLAM systems in resource-constrained environments according to claim 5, characterized in that, A finite state machine (FSM) is used to represent a finite number of states in the system, and constraints are imposed on the transitions and behaviors between these states. The state transitions and behaviors of the FSM depend on the current state and external inputs. A well-designed FSM is used to control the transitions between operational steps and prevent logical confusion. Based on the logical relationships between operational steps, the FSM is divided into eight states. Starting from the initial state, the specific operations of each state are implemented as follows: S0: Assign initial values ​​to each relevant variable, and enter state S1 after the assignment is completed; S1: Calculate the product of the state Jacobian matrix and the error covariance matrix of the previous time step, store the result in the temporary register and enter state S2. S2: Calculate the product of the output value of state S1 and the transpose of the state Jacobian matrix, and sum the result with the process noise covariance matrix to obtain the prior error covariance matrix. After the calculation is completed, enter state S3. S3: Calculate the product of the prior error covariance matrix and the transpose of the measurement Jacobian matrix, store the result in the temporary register and enter state S4. S4: Calculate the product of the measurement Jacobian matrix and the output value of state S3, sum the result with the measurement noise covariance matrix, send it to the matrix inversion module, and enter state S5. S5: Calculate the product of the output value of state S3 and the output value of the matrix inversion module to obtain the Kalman gain. After the calculation is completed, enter state S6. S6: Update the optimal state estimate and error covariance matrix, send the results to the state update module, and enter state S7. S7: After the state update module completes the calculation, enter the S0 state and repeat the above process with the calculation result as the initial value.

7. A hardware acceleration method for SLAM systems in resource-constrained environments according to claim 6, characterized in that, The specific implementation process of step five is as follows: After extended Kalman filtering, the FPGA transmits the updated pose and map information back to the central processing unit (CPU). The CPU updates the pose estimation of the current frame based on the information output by the EKF. The pose of each camera in each frame is used as a node, and the relative transformation between frames is used as an edge to form a pose graph. Feature points detected in the new keyframe are matched with existing map points, and unmatched feature points are inserted into the map as new map points. Each time a new frame is added, the local subgraph associated with the current frame is optimized; When a new keyframe is added, a bag-of-words model is used to find keyframes similar to the current frame as loop closure candidates. Geometric verification is performed on the loop closure candidates by calculating the relative pose transformation through 3D point and feature matching to verify the effectiveness of the loop closure candidates. Once the loop closure is confirmed, new constraint edges are added to the pose graph. Global pose graph BA optimization is performed using all constraint edges to minimize the overall reprojection error, thereby significantly reducing the cumulative error and improving the accuracy of map and pose estimation.

8. A hardware acceleration method for SLAM systems in resource-constrained environments according to claim 7, characterized in that, The computing power allocation module configures the FPGA logic circuit in real time according to the scheme, adjusts the computing pipeline structure, and adds or removes pipelines and matrix acceleration modules. When the platform is stationary, the FPGA is turned off to save power. Based on the brief time consumption in the configuration process, the module will incrementally update the computing process and immediately and dynamically load the computing pipeline / matrix acceleration circuit configured in the current clock cycle into the computing process to avoid waiting time and achieve zero-latency dynamic reconfiguration. Adaptive dynamic adjustment of computing power: By designing an energy efficiency ratio function, optimal performance is achieved; by designing a power consumption evaluation index function, the FPGA can adaptively adjust the logic circuit structure and scale according to the estimated computing power consumption index, so that the computing power of the logic circuit is dynamically balanced with the navigation computing power demand in the current environment, and the energy efficiency ratio is optimized.

9. A hardware acceleration method for a SLAM system suitable for resource-constrained environments according to claim 8, characterized in that, Hardware description language code is synthesized into logic circuits and mapped onto the physical resources of the FPGA. After the embedded system is powered on, the bootloader runs first. During the bootloader's startup process, a bitstream file is loaded from a predefined storage location and written to the FPGA. After the FPGA is configured, the bootloader continues to load the Linux operating system, reads the device tree file, and identifies the FPGA configuration and hardware layout. After the Linux operating system starts, the driver module is loaded via the insmod command. The FPGA and the ARM processor work together to execute SLAM acceleration tasks.

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