Layout structure of integrated circuit and manufacturing method thereof

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a layout structure of an integrated circuit and a manufacturing method thereof, wherein the layout structure of the integrated circuit comprises: a substrate; a plurality of transistors arranged in a first direction in sequence, two adjacent transistors are connected in series, each transistor comprises a gate on the substrate and a source region and a drain region on the opposite sides of the gate, and the two transistors connected in series share the source region or the drain region; a first metal silicide part, the first metal silicide part is located on the side of an edge transistor away from another transistor adjacent to the edge transistor, and is connected with the source region or the drain region of the non-common drain region in the edge transistor; a second metal silicide part, the second metal silicide part is located in the substrate, and the orthographic projection of the second metal silicide part on the surface of the substrate is arranged apart from the orthographic projection of the gate on the surface of the substrate, and the second metal silicide part is connected with the common drain region. The resistance of the whole structure can be reduced.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to the field of semiconductor, in particular to a layout structure of integrated circuit and a manufacturing method thereof. BACKGROUND

[0002] An integrated circuit is a kind of micro electronic device or component. By using certain process, transistors, resistors, capacitors, inductors and other components and wiring interconnections required in a circuit are interconnected together on one or several semiconductor chips or dielectric substrates, and then packaged in a tube shell to become a micro structure with required circuit functions; all components have been structurally integrated into a whole, which makes electronic components take a big step towards miniaturization, low power consumption, intelligence and high reliability.

[0003] Among them, as the integration level of integrated circuits is getting higher and higher, the spacing between adjacent transistors is getting smaller and smaller, and transistors with common source or common drain are developed to improve the integration level through common source or common drain.

[0004] However, there is a problem of large common source drain resistance value of the common source or common drain transistor. SUMMARY

[0005] The embodiment of the present disclosure provides a layout structure of integrated circuit and a manufacturing method thereof, which can at least reduce the resistance of the semiconductor structure.

[0006] According to some embodiments of the present disclosure, the embodiment of the present disclosure provides a layout structure of integrated circuit, comprising: a substrate; a plurality of transistors arranged in a first direction in sequence, two adjacent transistors are connected in series, each transistor includes a gate on the substrate and a source region and a drain region on the opposite sides of the gate, the source region and the drain region are located in the substrate, and the source region or the drain region of the two transistors in series is shared; the shared source region or drain region is defined as a common source drain region, and the transistor at the head stage and the transistor at the tail stage are defined as edge transistors; a first metal silicide part, the first metal silicide part is located in the substrate, the first metal silicide part is located on the side of the edge transistor away from another transistor adjacent to the edge transistor, and is connected with the source region or the drain region of the non-common source drain region in the edge transistor; a second metal silicide part, the second metal silicide part is located in the substrate, and the orthographic projection of the second metal silicide part on the substrate surface is spaced from the orthographic projection of the gate on the substrate surface, and the second metal silicide part is connected with the common source drain region.

[0007] In some embodiments, further comprising: a first conductive plug located on a side of the edge transistor away from the transistor adjacent thereto, the first conductive plug located on a top surface of the first metal silicide portion and connected thereto, a top surface of the first conductive plug being higher than a top surface of the substrate.

[0008] In some embodiments, further comprising: a second conductive plug located between gates of the transistors in series, the second conductive plug located on a top surface of the second metal silicide portion and connected thereto, a top surface of the second conductive plug being higher than a top surface of the substrate.

[0009] In some embodiments, the first conductive plug and the second conductive plug are of the same material.

[0010] In some embodiments, further comprising: a first conductive layer located on a top surface of the first conductive plug and in electrical contact therewith, the first conductive layer being insulated from the second conductive plug.

[0011] In some embodiments, further comprising: a dummy conductive layer located in the same layer as the first conductive layer, the dummy conductive layer being in contact with a top surface of the second conductive plug, the dummy conductive layer being insulated from the first conductive layer.

[0012] In some embodiments, the first metal silicide portion and the second metal silicide portion are of the same material.

[0013] In some embodiments, the first metal silicide portion and the second metal silicide portion are of different materials, and the second metal silicide portion material has a lower resistivity than the first metal silicide portion material.

[0014] In some embodiments, further comprising: a doped layer located within the substrate, the doped layer being adjacent to the second metal silicide portion.

[0015] According to some embodiments of the present disclosure, another aspect of the present disclosure provides a method for manufacturing a layout structure of an integrated circuit, comprising: providing a substrate; forming a plurality of transistors arranged in a first direction in sequence, two adjacent transistors being connected in series, each transistor comprising a gate on the substrate and a source region and a drain region on opposite sides of the gate, the source region and the drain region being located in the substrate, and the source region or the drain region of the two transistors in series being shared, wherein the shared source region or drain region is defined as a shared source-drain region, and the transistor at the head stage and the transistor at the tail stage are defined as edge transistors; forming a first metal silicide part located in the substrate, the first metal silicide part being located on a side of the edge transistor away from another transistor adjacent to the edge transistor, and being electrically connected to a source region or a drain region of a non-shared source-drain region in the edge transistor; forming a second metal silicide part located in the substrate, and a projection of the second metal silicide part on a surface of the substrate being spaced from a projection of the gate on the surface of the substrate, and the second metal silicide part being connected to the shared source-drain region.

[0016] In some embodiments, the method further comprises: forming the first metal silicide part and the second metal silicide part in the same process step.

[0017] In some embodiments, the method further comprises: a dielectric layer located on a surface of the substrate and surrounding the gate, and the process step of forming the first metal silicide part comprises: etching the dielectric layer and part of the substrate to form a first recess, the first recess exposing the source region or the drain region of the non-shared source-drain region in the edge transistor; forming a metal layer on a bottom surface of the first recess; reacting the metal layer with the substrate by an annealing process to form the first metal silicide part; and removing the unreacted metal layer.

[0018] In some embodiments, the process step of forming the second metal silicide part comprises: etching the dielectric layer and part of the substrate to form a second recess, the second recess exposing the shared source-drain region of the edge transistor; forming the metal layer on a bottom surface of the second recess; reacting the metal layer with the substrate by an annealing process to form the second metal silicide part; and removing the unreacted metal layer.

[0019] In some embodiments, before forming the first metal silicide part and the second metal silicide part, the method further comprises, after forming the second recess: performing ion implantation on the substrate along the second recess to form a doped layer in the substrate, the doped layer being in contact with the shared source-drain region.

[0020] In some embodiments, after forming the second metal silicide part, further comprising: forming a first conductive plug, the first conductive plug is located at the side of the transistor away from the adjacent transistor in the first and second series, the first conductive plug is located at the top surface of the first metal silicide part and connected with the first metal silicide part, the top surface of the first conductive plug is higher than the top surface of the substrate; forming a second conductive plug, the second conductive plug is located between the gate of the transistor in the second series, and the second conductive plug is located at the top surface of the second metal silicide part and connected with the second metal silicide part, the top surface of the second conductive plug is higher than the top surface of the substrate.

[0021] In some embodiments, the first conductive plug and the second conductive plug are formed in the same step.

[0022] The technical scheme provided by the embodiment of the present disclosure has at least the following advantages: a plurality of transistors arranged in a first direction are provided, and a common source region or a common drain region is arranged between adjacent transistors, so that a transistor with a common source and drain region is formed, two transistors at the edge in the series of transistors are defined as edge transistors, a first metal silicide part is connected with a source region or a drain region of a non-common source and drain region in the edge transistor, the first metal silicide part is arranged to facilitate the signal output of the source region or the drain region of the non-common source and drain region in the edge transistor, a second metal silicide part is arranged in the substrate and connected with the common source and drain region, and the resistance of the common source and drain region can be reduced through the second metal silicide part, so that the resistance of the series of transistors can be reduced, and the resistance of the entire integrated circuit can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0023] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not limiting of the embodiments, unless otherwise specifically indicated, the drawings in which: in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed to be used in the embodiments will be briefly introduced as follows, obviously, the drawings in the following description only some embodiments of the present disclosure, for those skilled in the art, without creating labor, according to these drawings, other drawings can also be obtained.

[0024] Figure 1 A structural schematic diagram of a layout structure of an integrated circuit provided by an embodiment of the present disclosure;

[0025] Figures 2 to 4 A structural schematic diagram corresponding to each step of a manufacturing method of a layout structure of an integrated circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] As can be known from the background art, at present, the resistance value of the common source-drain region of the common source region and common drain region transistor is large.

[0027] The layout structure of the integrated circuit provided by the present disclosure includes: a plurality of transistors arranged in a first direction X, and the common source region or common drain region between adjacent transistors, thereby forming a common source-drain region transistor, the two transistors at the edge of the series-connected transistors are defined as edge transistors, the first metal silicide part is connected with the source region or drain region of the non-common source-drain region of the edge transistor, the first metal silicide part is arranged to facilitate the signal output of the source region or drain region of the non-common source-drain region of the edge transistor, and the second metal silicide part is located in the substrate and connected with the common source-drain region. The resistance of the common source-drain region can be reduced through the second metal silicide part, so as to reduce the resistance of the series-connected transistors, and further reduce the resistance of the entire integrated circuit.

[0028] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0029] Reference Figure 1 , Figure 1 A cross-sectional view of the layout structure of the integrated circuit provided by the present disclosure.

[0030] In some embodiments, the layout structure of the integrated circuit can include: a substrate 100.

[0031] In some embodiments, the layout structure of the integrated circuit can include: a plurality of transistors 110 arranged in a first direction X in sequence, and two adjacent transistors 110 connected in series, each transistor 110 including a gate 111 located on the substrate 100 and a source region 112 and a drain region 113 located on the opposite sides of the gate 111, the source region 112 and the drain region 113 being located in the substrate 100, and the two transistors 110 connected in series sharing the source region 112 or the drain region 113, wherein the shared source region 112 or drain region 113 is defined as a common source-drain region 114, and the transistor 110 at the head stage and the transistor 110 at the tail stage are defined as edge transistors 115.

[0032] In some embodiments, the layout structure of the integrated circuit can further include a first metal silicide portion 120, the first metal silicide portion 120 is located within the substrate 100, the first metal silicide portion 120 is located at a side of the edge transistor 115 away from another transistor 110 adjacent to the edge transistor 115, and the first metal silicide portion 120 is connected to the source region 112 or the drain region 113 of the non-common source-drain region in the edge transistor 115.

[0033] In some embodiments, the layout structure of the integrated circuit can further include a second metal silicide portion 130, the second metal silicide portion 130 is located within the substrate 100, and a projection of the second metal silicide portion 130 on the surface of the substrate 100 is spaced apart from a projection of the gate 111 on the surface of the substrate 100, the second metal silicide portion 130 is connected to the common source-drain region 114.

[0034] By arranging a plurality of transistors 110 along the first direction X, and sharing the source region 112 or the drain region 113 between adjacent transistors 110 to form the transistor 110 of the common source-drain region 114, defining two transistors 110 at the edge of the series-connected transistors 110 as the edge transistor 115, connecting the first metal silicide portion 120 to the source region 112 or the drain region 113 of the non-common source-drain region in the edge transistor 115, arranging the first metal silicide portion 120 to facilitate the signal output of the source region 112 or the drain region 113 of the non-common source-drain region in the edge transistor 115, and locating the second metal silicide portion 130 within the substrate 100 and connecting it to the common source-drain region 114, the resistance of the common source-drain region 114 can be reduced by the second metal silicide portion 130, thereby reducing the resistance of the series-connected transistors 110, and further reducing the resistance of the entire integrated circuit.

[0035] In some embodiments, the material of the substrate 100 can include a semiconductor material, such as but not limited to silicon. In some embodiments, the substrate 100 can include a bulk semiconductor, a compound semiconductor, or an alloy semiconductor. For example, the bulk semiconductor includes germanium; the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or a III-V semiconductor material, etc.; the alloy semiconductor includes silicon germanium, silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide, etc. In some embodiments, the substrate 100 can also be a silicon-on-insulator structure, a germanium silicon-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0036] In addition, the substrate 100 can be doped according to design requirements (such as a P-type substrate or an N-type substrate). In some embodiments, the substrate 100 can be doped with P-type doping ions (such as boron ions, aluminum ions) or N-type doping ions (such as phosphorus ions, arsenic ions).

[0037] In some embodiments, the transistor 110 can be a MOS (Metal-Oxide-Semiconductor) transistor. In which the gate 111 of the transistor 110 is used to control the conduction between the source region 112 and the drain region 113 of the transistor 110. For example, in an NMOS transistor, when a positive voltage is applied to the gate 111 of the transistor 110, the carriers of the source region 112 and the drain region 113 are connected together to form a channel after the voltage received by the gate 111 is higher than a certain value, and the source region 112 and the drain region 113 are conducted.

[0038] In some embodiments, the transistor 110 can be a symmetric transistor, that is, the source region 112 and the drain region 113 of the transistor 110 are symmetric, that is, the source region 112 and the drain region 113 of the transistor 110 are exchanged, and the performance of the transistor 110 will not be affected.

[0039] In some embodiments, a gate dielectric layer 116 can also be included, which is located between the gate 111 and the substrate 100, so as to avoid the carriers in the substrate 100 directly flowing to the gate 111.

[0040] In some embodiments, the first metal silicide part 120 can be formed by metalizing part of the substrate 100, and through the first metal silicide part 120, the resistance of the source region 112 or the drain region 113 of the non-common drain region in the edge transistor 115 can be reduced.

[0041] It can be understood that the first metal silicide part 120 is formed by metalizing silicon when the material of the substrate 100 is silicon, and when the material of the substrate 100 is germanium, the first metal silicide part 120 can also be a first metal germanide part. Here, the first metal silicide part 120 is only a general term for the structure formed in the substrate 100, and is not limited to the material of the substrate 100 being silicon.

[0042] In some embodiments, the second metal silicide part 130 can be formed by metalizing part of the substrate 100, and through the second metal silicide part 130, the resistance of the common drain region 114 in the transistor 110 can be reduced, so as to reduce the resistance of the layout structure of the entire integrated circuit.

[0043] It can be understood that the second metal silicide part 130 is the same as the first metal silicide part 120, and the second metal silicide part 130 is formed after the material of the substrate 100 is silicon and the material of the substrate 100 is metallized. When the material of the substrate 100 is germanium, the second metal silicide part 130 can also be a second metal germanide part. Here, the second metal silicide part 130 is only a general term for the structure formed in the substrate 100, and is not limited to the material of the substrate 100 being silicon.

[0044] In some embodiments, the material of the first metal silicide part 120 is the same as the material of the second metal silicide part 130. By setting the material of the first metal silicide part 120 to be the same as the material of the second metal silicide part 130, the differences between different transistors 110 can be reduced, and the same process can be used to form the first metal silicide part 120 and the second metal silicide part 130, thereby further reducing the differences between adjacent transistors 110, thereby improving the reliability of the semiconductor structure corresponding to the layout structure of the integrated circuit, and even forming the first metal silicide part 120 and the second metal silicide part 130 in the same process step, and reducing the process steps corresponding to the layout structure of the integrated circuit.

[0045] In some embodiments, the material of the first metal silicide part 120 can also be different from the material of the second metal silicide part 130, and the resistivity of the material of the second metal silicide part 130 can be less than the resistivity of the material of the first metal silicide part 120. The second metal silicide part 130 affects the resistance of the common source-drain region 114, which is also the part that needs to be improved in the two transistors 110 in series, so a material with lower resistivity is needed to better reduce the resistance of the common source-drain region 114 in the series transistor 110.

[0046] In some embodiments, the material of the first metal silicide portion 120 can be titanium silicide, the material of the second metal silicide portion 130 can be cobalt silicide, or the material of the first metal silicide portion 120 can be cobalt silicide, and the material of the second metal silicide portion 130 can be nickel silicide. For titanium silicide, the resistance of titanium silicide increases with the decrease of line width or contact area, and when the line width becomes too narrow, in order to make titanium silicide change to an orthorhombic system with lower resistance, the annealing time and annealing temperature need to be increased, which may cause the diffusion of diffusion elements to be more intense, thereby causing the problem of short circuit; for cobalt silicide, compared with titanium silicide, the annealing temperature during the formation of cobalt silicide is relatively low, which is beneficial to the reduction of process thermal budget, and at the same time, the leakage and short circuit caused by the diffusion of diffusion elements can be improved; for nickel silicide, the resistance of nickel silicide is more stable in the layout structure of integrated circuits with higher integration, and the consumption of silicon in the source region 112 and the drain region 113 of the substrate 100 during the formation of nickel silicide is less, and the silicon near the surface is just the region with the highest doping concentration, so it is more beneficial to reduce the overall contact resistance.

[0047] In some embodiments, the layout structure of the integrated circuit can further include a doped layer 140, the doped layer 140 is located in the substrate 100, and the doped layer 140 is adjacent to the second metal silicide portion 130. By forming the doped layer 140 connected with the second metal silicide portion 130, the resistance of the common source-drain region 114 of the series transistor 110 is further reduced.

[0048] In some embodiments, the doped layer 140 coincides with part of the common source-drain region 114, that is, the doped layer 140 is located in the common source-drain region 114.

[0049] In some embodiments, the doped layer 140 is also located in the source region 112 or the drain region 113 of the non-common source-drain region in the edge transistor 115. By setting the doped layer 140 to be also located in the source region 112 or the drain region 113 of the non-common source-drain region in the edge transistor 115, the resistance value of the source region 112 or the drain region 113 of the non-common source-drain region in the edge transistor 115 can also be reduced, thereby further improving the resistance value of the layout structure of the integrated circuit.

[0050] In some embodiments, the doped layer 140 is also located in the source region 112 or the drain region 113 of the non-common source-drain region in the edge transistor 115, and the doped layer 140 also contacts the first metal silicide portion 120.

[0051] It should be noted that the doped layer 140 in contact with the first metal silicide portion 120 and the doped layer 140 in contact with the second metal silicide portion 130 are spaced apart.

[0052] In some embodiments, the layout structure of the integrated circuit can further include a first conductive plug 150, the first conductive plug 150 is located at a side of the edge transistor 115 away from the transistor 110 adjacent to the edge transistor 115, the first conductive plug 150 is located at the top surface of the first metal silicide part 120 and connected with the first metal silicide part 120, and the top surface of the first conductive plug 150 is higher than the top surface of the substrate 100. The signal of the source region 112 or the drain region 113 of the non-common-drain region of the edge transistor 115 can be led out through the first conductive plug 150, or the signal can be provided to the source region 112 or the drain region 113 of the non-common-drain region of the edge transistor 115.

[0053] In some embodiments, the layout structure of the integrated circuit includes the first conductive plug 150, and the first metal silicide part 120 can avoid direct contact between the first conductive plug 150 and the substrate 100, so that the substrate 100 can avoid directly providing the signal to the first conductive plug 150, or the first conductive plug 150 can avoid directly providing the signal to the substrate 100, so that the reliability of the signal transmission between the substrate 100 and the first conductive plug 150 can be improved.

[0054] In some embodiments, the material of the first conductive plug 150 can be a metal material, such as tungsten or cobalt, etc. By setting the material of the first conductive plug 150 as a metal material, the resistance of the first conductive plug 150 can be reduced, so that the speed of the signal transmission on the first conductive plug 150 can be improved. In some embodiments, the material of the first conductive plug 150 is a metal material, and the first metal silicide part 120 can avoid the diffusion of metal ions in the first conductive plug 150 into the substrate 100, so that the influence of the metal ions on the substrate 100 can be avoided, and the reliability of the layout structure of the integrated circuit can be improved.

[0055] In some embodiments, the layout structure of the integrated circuit can further include a second conductive plug 160, the second conductive plug 160 is located between the gate 111 of the transistor 110 in series, and the second conductive plug 160 is located at the top surface of the second metal silicide part 130 and connected with the second metal silicide part 130, and the top surface of the second conductive plug 160 is higher than the top surface of the substrate 100. By setting the second conductive plug 160, the signal of the common-drain region 114 of the transistor 110 in series can be led out, or the signal can be provided to the common-drain region 114 of the transistor 110.

[0056] In some embodiments, the layout structure of the integrated circuit includes the second conductive plug 160, and the second metal silicide portion 130 can also avoid direct contact between the second conductive plug 160 and the substrate 100, so that the substrate 100 can avoid directly providing signals to the second conductive plug 160, or the second conductive plug 160 can avoid directly providing signals to the substrate 100, so that the reliability of signal transmission between the substrate 100 and the second conductive plug 160 can be improved.

[0057] In some embodiments, the material of the second conductive plug 160 can be a metal material, such as tungsten or cobalt, etc. By setting the material of the second conductive plug 160 as a metal material, the resistance of the second conductive plug 160 can be reduced, so that the speed of signal transmission on the second conductive plug 160 can be improved. In some embodiments, the material of the second conductive plug 160 is a metal material, and the second metal silicide portion 130 can also avoid diffusion of metal ions in the second conductive plug 160 into the substrate 100, so that the metal ions can avoid affecting the substrate 100, and the reliability of the layout structure of the integrated circuit can be improved.

[0058] In some embodiments, the material of the first conductive plug 150 is the same as that of the second conductive plug 160. By setting the material of the first conductive plug 150 to be the same as that of the second conductive plug 160, the first conductive plug 150 and the second conductive plug 160 can be formed in the same process step, so that the process steps of the entire layout structure of the integrated circuit can be reduced.

[0059] In some embodiments, the first conductive layer 170 is further included, the first conductive layer 170 is located on the top surface of the first conductive plug 150 and is in contact with the first conductive plug 150, and the first conductive layer 170 is insulated from the second conductive plug 160. By setting the first conductive layer 170, signals can be provided to the first conductive plug 150 through the first conductive layer 170, so that the signals of the first conductive plug 150 can be led out or provided to the first conductive plug 150.

[0060] In some embodiments, the material of the first conductive layer 170 can be a metal material, and by setting the material of the first conductive layer 170 as a metal material, the signal transmission speed of the first conductive layer 170 can be improved.

[0061] In some embodiments, the material of the first conductive layer 170 can also be the same as that of the first conductive plug 150, so that the material difference between the first conductive layer 170 and the first conductive plug 150 can be reduced, and the reliability of signal transmission between the first conductive layer 170 and the first conductive plug 150 can be improved.

[0062] In some embodiments, the layout structure of the integrated circuit can further include a pseudo-conductive layer 180, the pseudo-conductive layer 180 is arranged in the same layer as the first conductive layer 170, and the pseudo-conductive layer 180 is in contact with the top surface of the second conductive plug 160, and the pseudo-conductive layer 180 is insulated from the first conductive layer 170. The pseudo-conductive layer 180 is actually a conductive layer that does not transmit signals, although it is connected to the second conductive plug 160, it actually does not provide signals to the second conductive plug 160, nor does it lead out the signals on the second conductive plug 160. By arranging the pseudo-conductive layer 180 and the second conductive plug 160, the resistance of the common source-drain region 114 can be further reduced.

[0063] By arranging the pseudo-conductive layer 180 and the first conductive layer 170 in the same layer, the first conductive layer 170 and the pseudo-conductive layer 180 can be formed in the same process step, that is, the first conductive layer 170 is compatible with the manufacturing process in the related art.

[0064] In some embodiments, the materials of the pseudo-conductive layer 180 and the first conductive layer 170 can be the same, and can both be metal materials.

[0065] In some embodiments, the related art does not include a second conductive plug and a pseudo-conductive layer, however, during the simulation process after the layout structure of the integrated circuit, due to the limitations of simulation, conductive plugs and conductive layers are usually arranged corresponding to the source region 112 and the drain region 113 of the transistor 110, therefore, there is a problem in the related art that the simulation corresponding structure and the layout structure of the actual integrated circuit are different, resulting in that the simulation structure is not accurate enough, and the present disclosure can further improve the alignment accuracy between the simulation result and the layout structure of the actual integrated circuit through the second conductive plug 160 and the pseudo-conductive layer 180, thereby further improving the reliability of the simulation result.

[0066] It should be noted that the above-mentioned simulation refers to simulating the performance of the actual produced semiconductor structure according to the layout structure of the integrated circuit, thereby further facilitating the adjustment of the layout structure of the integrated circuit according to the simulation result.

[0067] In some embodiments, the layout structure of the integrated circuit can further include a third conductive plug 190, the third conductive plug 190 is located on the top surface of the first conductive layer 170 electrically connected with the first transistor 110 or the last transistor 110, and is in contact with the first conductive layer 170; and a second conductive layer 200, the second conductive layer 200 is located on the top surface of the third conductive plug 190, and is in contact with the third conductive plug 190.

[0068] The second conductive layer 200 can provide electrical signals to the third conductive plug 190, or lead out the signals of the third conductive plug 190.

[0069] In some embodiments, the material of the second conductive layer 200 can be the same as the material of the first conductive layer 170.

[0070] In some embodiments, the first conductive layer 170 can be a first wiring layer, and the second conductive layer can be a second wiring layer. The signals of the first transistor 110 and the last transistor 110 in the series of transistors can be respectively led out through the first wiring layer and the second wiring layer.

[0071] In the embodiments of the present disclosure, a plurality of transistors 110 are arranged along the first direction X, and the source regions 112 or the drain regions 113 of adjacent transistors 110 are shared. The two transistors 110 at the edges in the series of transistors 110 are defined as edge transistors 115. The first metal silicide part 120 is connected to the source regions 112 or the drain regions 113 of the non-common source-drain region in the edge transistors 115. The first metal silicide part 120 is arranged to facilitate leading out the signals of the source regions 112 or the drain regions 113 of the non-common source-drain region in the edge transistors 115. The second metal silicide part 130 is located in the substrate 100 and is connected to the common source-drain region 114. The second metal silicide part 130 can reduce the resistance of the common source-drain region 114, thereby reducing the resistance of the series of transistors 110, and further reducing the resistance of the entire integrated circuit.

[0072] Another embodiment of the present disclosure also provides a manufacturing method of a layout structure of an integrated circuit. The manufacturing method can be used to form the layout structure of the integrated circuit. The manufacturing method of the layout structure of the integrated circuit provided by the another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts of the above embodiments can refer to the corresponding descriptions of the above embodiments, which will not be described herein.

[0073] Reference Figures 2 to 4 , Figures 2 to 4 The manufacturing method of the layout structure of the integrated circuit provided by the embodiments of the present disclosure includes the following steps.

[0074] The manufacturing method of the layout structure of the integrated circuit provided by the embodiments of the present disclosure includes the following steps.

[0075] The method for manufacturing the layout structure of the integrated circuit provided by the embodiment of the present disclosure comprises: forming a plurality of transistors 110 arranged along a first direction X in sequence, and two adjacent transistors 110 are connected in series, each transistor 110 comprises a gate 111 located on a substrate 100 and a source region 112 and a drain region 113 located on the opposite sides of the gate 111, the source region 112 and the drain region 113 are located in the substrate 100, and the source region 112 or the drain region 113 shared by the two transistors 110 connected in series is defined as a common source-drain region 114, and the transistor 110 at the head stage and the transistor 110 at the tail stage are defined as edge transistors 115.

[0076] The method for manufacturing the layout structure of the integrated circuit provided by the embodiment of the present disclosure further comprises: forming a first metal silicide part 120, the first metal silicide part 120 is located in the substrate 100, the first metal silicide part 120 is located on the side of the edge transistor 115 away from the other transistor 110 adjacent to the edge transistor 115, and is electrically connected with the source region 112 or the drain region 113 of the non-common source-drain region in the edge transistor 115.

[0077] The method for manufacturing the layout structure of the integrated circuit provided by the embodiment of the present disclosure further comprises: forming a second metal silicide part 130, the second metal silicide part 130 is located in the substrate 100, and the orthographic projection of the second metal silicide part 130 on the surface of the substrate 100 is arranged apart from the orthographic projection of the gate 111 on the surface of the substrate 100, and the second metal silicide part 130 is connected with the common source-drain region 114.

[0078] By forming a plurality of transistors 110 arranged along a first direction X, and sharing the source region 112 or the drain region 113 between the adjacent transistors 110, thereby forming the transistor 110 of the common source-drain region 114, by forming the first metal silicide part 120, the first metal silicide part 120 is connected with the source region 112 or the drain region 113 of the non-common source-drain region in the edge transistor 115, thereby leading out the signal of the source region 112 or the drain region 113 of the non-common source-drain region in the edge transistor 115 through the first metal silicide part 120, by forming the second metal silicide part 130, the second metal silicide part 130 is located in the substrate 100 and connected with the common source-drain region 114, and the resistance of the common source-drain region 114 can be reduced through the second metal silicide part 130, thereby reducing the resistance of the transistors 110 connected in series, and further reducing the resistance of the entire integrated circuit.

[0079] Reference Figure 2 , Figure 2 For the structure schematic diagram of the transistor forming step, the substrate 100 is provided, and a plurality of transistors 110 arranged along a first direction X are formed.

[0080] Reference Figure 3 , Figure Three For forming the first metal silicide part and the second metal silicide part, a structure diagram of the steps is shown in FIG. 1. A first metal silicide part 120 and a second metal silicide part 130 are formed.

[0081] In some embodiments, a dielectric layer 210 is further included, which is located on the surface of the substrate 100 and surrounds the gate 111. The process steps for forming the first metal silicide part 120 include: etching the dielectric layer 210 and part of the substrate 100 to form a first recess 220, which exposes the source region 112 or the drain region 113 of the non-complementary source-drain region in the edge transistor; forming a metal layer (not shown in the figure) on the bottom surface of the first recess 220; using an annealing process to react the metal layer with the substrate 100 to form the first metal silicide part 120; and removing the unreacted metal layer. By forming the first metal silicide part 120 in the form of metal silicide, the resistance of the formed first metal silicide part 120 can be reduced, and the resistance of the source region 112 or the drain region 113 of the non-complementary source-drain region in the edge transistor can also be reduced.

[0082] In some embodiments, the top surface of the dielectric layer 210 can be flush with the top surface of the gate 111, or the top surface of the dielectric layer 210 can be higher than the top surface of the gate 111.

[0083] In some embodiments, the process steps for forming the second metal silicide part 130 include: etching the dielectric layer 210 and part of the substrate 100 to form a second recess 230, which exposes the complementary source-drain region 114 of the edge transistor; forming a metal layer on the bottom surface of the second recess 230; using an annealing process to react the metal layer with the substrate 100 to form the second metal silicide part 130; and removing the unreacted metal layer. By forming the second metal silicide part 130 in the form of metal silicide, the resistance of the formed second metal silicide part 130 can be reduced, and the resistance of the complementary source-drain region 114 can also be reduced by forming the second metal silicide part 130.

[0084] In some embodiments, the first metal silicide part 120 and the second metal silicide part 130 can be formed in the same process step. By forming the first metal silicide part 120 and the second metal silicide part 130 in the same process step, the manufacturing process of the first metal silicide part 120 can be compatible, so that no additional process steps are needed, and the resistance of the complementary source-drain region 114 can also be reduced.

[0085] In some embodiments, the first metal silicide part 120 and the second metal silicide part 130 can also be formed in different process steps.

[0086] In some embodiments, the first metal silicide portion 120 and the second metal silicide portion 130 are formed in different process steps, and the materials of the first metal silicide portion 120 and the second metal silicide portion 130 can be different. The materials of the first metal silicide portion 120 and the second metal silicide portion 130 can be adjusted according to actual needs. For example, the material of the first metal silicide portion 120 can be cobalt silicide, and the material of the second metal silicide portion 130 can be nickel silicide, etc.

[0087] In some embodiments, the materials of the first metal silicide portion 120 and the second metal silicide portion 130 can be different, and the materials of the metal layers used in the process of forming the first metal silicide portion 120 and the second metal silicide portion 130 are also different.

[0088] In some embodiments, before forming the first metal silicide portion 120 and the second metal silicide portion 130, after forming the second recess 230, the method can further include: performing ion implantation on the substrate 100 along the second recess 230 to form a doped layer 140 in the substrate 100, the doped layer 140 being in contact with the common source-drain region 114. By forming the doped layer 140 in contact with the common source-drain region 114, the resistance of the common source-drain region 114 can be further reduced.

[0089] In some embodiments, in the process of forming the doped layer 140 in contact with the common source-drain region 114, the method can further include: performing ion implantation on the substrate 100 along the first recess 220 to form a doped layer 140 connected to the source region 112 or the drain region 113 of the non-common source-drain region 114 in the edge transistor 115, so that the resistance of the source region 112 or the drain region 113 of the non-common source-drain region 114 in the edge transistor 115 can be reduced.

[0090] In some embodiments, the doped layer 140 connected to the source region 112 or the drain region 113 of the non-common source-drain region 114 in the edge transistor 115 and the doped layer 140 in contact with the common source-drain region 114 can be formed in the same process step. In some embodiments, the doped layer 140 connected to the source region 112 or the drain region 113 of the non-common source-drain region 114 in the edge transistor 115 and the doped layer 140 in contact with the common source-drain region 114 can also be formed in different process steps.

[0091] Reference Figure 4 , Figure 4To form the structure of the first and second conductive plug forming steps, in some embodiments, after forming the second metal silicide portion 130, further comprising: forming the first conductive plug 150, the first conductive plug 150 is located at the side of the transistor 110 of the head and tail away from the adjacent transistor 110, the first conductive plug 150 is located at the top surface of the first metal silicide portion 120 and connected with the first metal silicide portion 120, the top surface of the first conductive plug 150 is higher than the top surface of the substrate 100; forming the second conductive plug 160, the second conductive plug 160 is located between the gate 111 of the transistor 110 in series, and the second conductive plug 160 is located at the top surface of the second metal silicide portion 130 and connected with the second metal silicide portion 130, the top surface of the second conductive plug 160 is higher than the top surface of the substrate 100.

[0092] By forming the first conductive plug 150, the signal of the source region 112 or the drain region 113 of the edge transistor 115 non-common drain region can be led out, or the signal can be provided to the source region 112 or the drain region 113 of the edge transistor 115 non-common drain region, and by forming the second conductive plug 160, the signal of the common drain region 114 of the transistor 110 in series can be led out, or the signal can be provided to the common drain region 114 of the transistor 110.

[0093] In some embodiments, the first conductive plug 150 and the second conductive plug 160 can be formed in the same process. In other words, the process of forming the second conductive plug 160 does not generate additional process steps, and the manufacturing process of the first conductive plug 150 is shared.

[0094] In some embodiments, the first conductive plug 150 and the second conductive plug 160 can also be formed in different processes.

[0095] In some embodiments, the first conductive plug 150 and the second conductive plug 160 are formed in different processes, and the materials of the first conductive plug 150 and the second conductive plug 160 can be different, wherein the electrical performance of the material of the first conductive plug 150 can be better than that of the second conductive plug material.

[0096] The electrical performance mentioned above refers to the material performance related to electricity, such as electrical conductivity and the like.

[0097] In some embodiments, after forming the first conductive plug 150 and the second conductive plug 160, a first conductive layer 170, a pseudo-conductive layer 180, a third conductive plug 190, and a second conductive layer 200 can be further formed.

[0098] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for realizing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the embodiments of the present disclosure, and therefore the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A layout structure of an integrated circuit, characterized by, The application relates to a semiconductor device, comprising: a substrate; a plurality of transistors arranged in series along a first direction, two adjacent transistors being connected in series, each transistor comprising a gate on the substrate and a source region and a drain region on opposite sides of the gate, the source region and the drain region being located in the substrate, and two adjacent transistors sharing the source region or the drain region, wherein the shared source region or drain region is defined as a common source-drain region, and the transistor at the head stage and the transistor at the tail stage are defined as edge transistors; a first metal silicide part located in the substrate, the first metal silicide part being located on the side of the edge transistor away from another transistor adjacent to the edge transistor, and connected to the source region or the drain region of the edge transistor which is not a common source-drain region; a second metal silicide part located in the substrate, and the top projection of the second metal silicide part on the substrate surface being spaced from the top projection of the gate on the substrate surface, and the second metal silicide part being connected to the common source-drain region; a first conductive plug located on the side of the edge transistor away from another transistor adjacent to the edge transistor, the first conductive plug being located on the top surface of the first metal silicide part and connected to the first metal silicide part, and the top surface of the first conductive plug being higher than the top surface of the substrate; a second conductive plug located between the gates of the transistors connected in series, and the second conductive plug being located on the top surface of the second metal silicide part and connected to the second metal silicide part, and the top surface of the second conductive plug being higher than the top surface of the substrate; a first conductive layer located on the top surface of the first conductive plug and in contact with the first conductive plug, and the first conductive layer being insulated from the second conductive plug; a pseudo conductive layer located in the same layer as the first conductive layer, and the pseudo conductive layer being in contact with the top surface of the second conductive plug, and the pseudo conductive layer being insulated from the first conductive layer.

2. The layout structure of an integrated circuit according to claim 1, wherein, The first conductive plug and the second conductive plug are made of the same material.

3. The layout structure of an integrated circuit according to claim 1, wherein The first metal silicide part and the second metal silicide part are made of the same material.

4. The layout structure of an integrated circuit according to claim 1, wherein The first metal silicide part and the second metal silicide part are made of different materials, and the resistivity of the material of the second metal silicide part is smaller than that of the material of the first metal silicide part.

5. The layout structure of an integrated circuit according to claim 1, wherein Further comprising: a doped layer located in the substrate, and the doped layer being adjacent to the second metal silicide part.

6. A method of fabricating a layout structure of an integrated circuit, characterized by, Comprising: providing a substrate; forming a plurality of transistors arranged in a first direction in sequence, two adjacent transistors being connected in series, each transistor comprising a gate on the substrate and a source region and a drain region on opposite sides of the gate, the source region and the drain region being in the substrate, and two transistors connected in series sharing the source region or the drain region, wherein the shared source region or the drain region is defined as a common source-drain region, and the transistor at the head stage and the transistor at the tail stage are defined as edge transistors; forming a first metal silicide part in the substrate, the first metal silicide part being on a side of the edge transistor away from another transistor adjacent to the edge transistor, and electrically connected to the source region or the drain region of the edge transistor which is not a common source-drain region; forming a second metal silicide part in the substrate, and a projection of the second metal silicide part on the substrate surface being spaced from a projection of the gate on the substrate surface, the second metal silicide part being connected to the common source-drain region; forming a first conductive plug on a side of the transistors at the head stage and the tail stage away from the adjacent transistors, the first conductive plug being on a top surface of the first metal silicide part and connected to the first metal silicide part, and a top surface of the first conductive plug being higher than a top surface of the substrate; forming a second conductive plug between the gates of the transistors connected in series, and the second conductive plug being on a top surface of the second metal silicide part and connected to the second metal silicide part, and a top surface of the second conductive plug being higher than the top surface of the substrate; forming a first conductive layer on the top surface of the first conductive plug and in contact with the first conductive plug, and the first conductive layer being insulated from the second conductive plug; and forming a pseudo-conductive layer in the same layer as the first conductive layer, and the pseudo-conductive layer being in contact with the top surface of the second conductive plug, the pseudo-conductive layer being insulated from the first conductive layer.

7. The method of claim 6, wherein The first metal silicide part and the second metal silicide part are formed in the same process step.

8. The method of producing a layout structure of an integrated circuit according to claim 6 or 7, wherein Further comprising: a dielectric layer on the surface of the substrate and surrounding the gate, and the process step of forming the first metal silicide part comprises: etching the dielectric layer and part of the substrate to form a first recess, the first recess exposing the source region or the drain region of the non-common source-drain region in the edge transistor; forming a metal layer on the bottom surface of the first recess; reacting the metal layer with the substrate by an annealing process to form the first metal silicide part; removing the unreacted metal layer.

9. The method of claim 8, wherein The process step of forming the second metal silicide part comprises: etching the dielectric layer and part of the substrate to form a second recess, the second recess exposing the common source-drain region of the edge transistor; forming the metal layer on the bottom surface of the second recess; reacting the metal layer with the substrate using an anneal process to form the second metal silicide portion; removing unreacted metal layer.

10. The method of claim 9, wherein prior to forming the first and second metal silicide portions, forming the second recess further comprises ion implanting the substrate along the second recess to form a doped layer within the substrate, the doped layer in contact with a common source drain region.

11. The method of claim 6, wherein forming the first and second conductive plugs in the same step.

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