A high-precision anti-interference leakage protection circuit

Abstract

The present invention provides a high-precision anti-interference leakage protection circuit, comprising a fully differential wide common-mode input operational amplifier AMP1, a sampler, a single-ended output amplifier AMP2, a first comparator CMP1, a second comparator CMP2, an integrator, a reference voltage source, a clock unit, a digital logic unit, a power-on reset POR, and a thyristor drive circuit. The high-precision anti-interference leakage protection circuit provided by the present invention effectively solves the problem of low stability of the voltage leakage protection circuit due to the common-mode level being easily affected by interference.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design, and in particular relates to a high-precision anti-interference leakage protection circuit. Background Art

[0002] Leakage protection circuits are divided into current leakage protection circuits and voltage leakage protection circuits. Compared with current leakage protection circuits, voltage leakage protection circuits have the advantages of high voltage resistance, electric shock protection and low latency. Common voltage leakage protection circuits need to collect the common-mode signal of the circuit to be detected. The voltage leakage protection circuit needs to set a common-mode level in advance, and then judge whether the circuit to be detected has leakage by comparing the common-mode signal with the common-mode level.

[0003] At present, since the common-mode level is easily disturbed by the external magnetic field, the voltage leakage protection circuit often makes misjudgments and has low stability, which makes it impossible to give full play to the advantages of the voltage leakage protection circuit. In addition, the cost of developing a voltage leakage protection circuit with protection against common-mode interference is too high, which has delayed the promotion of the application of the voltage leakage protection circuit. Summary of the invention

[0004] In view of this, the present invention provides a high-precision anti-interference leakage protection circuit, which effectively solves the problem of low stability of the voltage leakage protection circuit due to the common mode level being easily affected by interference.

[0005] The present invention provides a high-precision anti-interference leakage protection circuit, comprising a fully differential wide common-mode input operational amplifier AMP1, a sampler, a single-ended output amplifier AMP2, a first comparator CMP1, a second comparator CMP2, an integrator, a reference voltage source, a clock unit, a digital logic unit, a power-on reset POR, and a thyristor drive circuit;

[0006] The first input terminal and the second input terminal of the fully differential wide common mode input operational amplifier AMP1 are externally connected to the target detection circuit, the third input terminal of the fully differential wide common mode input operational amplifier AMP1 is connected to the common mode voltage output terminal of the reference voltage source, the first output terminal of the fully differential wide common mode input operational amplifier AMP1 is connected to the first input terminal of the sampler, and the second output terminal of the fully differential wide common mode input operational amplifier AMP1 is connected to the second input terminal of the sampler;

[0007] The third input terminal of the sampler is connected to the common mode voltage output terminal of the reference voltage source, and the output terminal of the sampler is connected to the non-inverting input terminal of the single-ended output amplifier AMP2;

[0008] The inverting input terminal of the single-ended output amplifier AMP2 is connected to the common-mode voltage output terminal of the reference voltage source, and the output terminal of the single-ended output amplifier AMP2 is respectively connected to one end of the filter capacitor CO, the non-inverting input terminal of the first comparator CMP1, and the input terminal of the power-on reset device POR; the other end of the filter capacitor C0 is grounded; the common-mode voltage output terminal of the reference voltage source outputs a reference common-mode voltage COM;

[0009] The inverting input terminal of the first comparator CMP1 is used to be connected to the reference voltage output terminal of the reference voltage source, and the output terminal of the first comparator CMP1 is connected to the input terminal of the integrator;

[0010] A first output end of the power-on reset device POR is connected to a first input end of the digital logic unit, a second output end of the power-on reset device POR is connected to a first input end of the clock unit, and a second input end of the clock unit is connected to a first output end of the digital logic unit;

[0011] The output end of the integrator is connected to one end of the integration capacitor CAP and the non-inverting input end of the second comparator CMP2 respectively, and the other end of the integration capacitor CAP is grounded;

[0012] The inverting input terminal of the second comparator CMP2 is connected to the reference voltage output terminal of the reference voltage source, and the output terminal of the second comparator CMP2 is connected to the second input terminal of the digital logic unit; the reference voltage output terminal of the reference voltage source outputs the reference reference voltage VREF;

[0013] The second output terminal of the digital logic unit is used to drive the controllable drive circuit to turn on, and the thyristor drive circuit drives the external circuit breaker OS to disconnect the target detection circuit.

[0014] Optionally, the fully differential wide common-mode input operational amplifier AMP1 includes a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, a ninth switch K9, a tenth switch K10, an eleventh switch K11, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first operational amplifier AMP0+, a second operational amplifier AMP0-, a first resistor R1, a second resistor R2 and a third resistor R3;

[0015] One end of the first switch K1 and one end of the second switch K2 are connected to the external target detection circuit, the other end of the first switch K1 is respectively connected to one end of the third switch K3 and one end of the first capacitor C1, the other end of the first capacitor C1 is respectively connected to one end of the fourth switch K4 and one end of the second capacitor C2, the other end of the second capacitor C2 is respectively connected to the other end of the second switch K2 and one end of the fifth switch K5, the other end of the third switch K3 is respectively connected to one end of the sixth switch K6, one end of the third capacitor C3, and the non-inverting input end of the first operational amplifier AMP0+, one end of the eighth switch K8 is respectively connected to the common-mode voltage output end of the reference voltage source, the other end of the sixth switch K6, and the other end of the third capacitor C3, the other end of the eighth switch K8 is respectively connected to one end of the fifth capacitor C5, one end of the first resistor R1, and one end of the second resistor R2, the other end of the fifth capacitor is respectively connected to the inverting input end of the first operational amplifier AMP0+ and one end of the tenth switch K10 The other end of the tenth switch K10 is respectively connected to the output end of the first operational amplifier AMP0+, the other end of the first resistor R1, and the first input end of the sampler; one end of the ninth switch K9 is respectively connected to the other end of the fourth switch K4, one end of the seventh switch K7, one end of the fourth capacitor C4, and the common-mode voltage output end of the reference voltage source; the other end of the ninth switch K9 is respectively connected to one end of the sixth capacitor C6, the other end of the second resistor R2, and one end of the third resistor R3; the other end of the seventh switch K7 is respectively connected to the other end of the fifth switch K5, the other end of the fourth capacitor C4, and the non-inverting input end of the second operational amplifier AMP0-; the other end of the sixth capacitor C6 is respectively connected to the inverting input end of the second operational amplifier AMP0- and one end of the eleventh switch K11; the other end of the eleventh switch K11 is respectively connected to the other end of the third resistor R3, the output end of the second operational amplifier AMP0-, and the second input end of the sampler.

[0016] Optionally, the high-precision anti-interference leakage protection circuit further includes a voltage stabilizer, which provides a stable power supply voltage for the high-precision anti-interference leakage protection circuit;

[0017] The voltage regulator includes a fourth resistor R4, a fifth resistor R5, a first NMOS transistor P1 and a third operational amplifier AMP3;

[0018] One end of the fourth resistor R4 is respectively connected to the external power supply VDD and the drain of the first NMOS tube P1, the other end of the fourth resistor R4 is respectively connected to one end of the fifth resistor R5 and the non-inverting input end of the third operational amplifier AMP3, the other end of the fifth resistor R5 is grounded, the inverting input end of the third operational amplifier AMP3 is connected to the reference voltage output end of the reference voltage source, the output end of the third operational amplifier AMP3 is connected to the gate of the first NMOS tube P1, and the source of the first NMOS tube P1 is grounded.

[0019] Optionally, the sampler includes a third comparator CMP3, a fourth comparator CMP4, a twelfth switch K12, a thirteenth switch K13, a fourteenth switch K14 and a seventh capacitor C7;

[0020] A first end of the twelfth switch K12 is respectively connected to the first output end of the fully differential wide common mode input operational amplifier AMP1 and the non-inverting input end of the third comparator CMP3, a second end of the twelfth switch K12 is respectively connected to the output end of the third comparator CMP3, a first end of the thirteenth switch K13 is respectively connected to the second output end of the fully differential wide common mode input operational amplifier AMP1 and the non-inverting input end of the fourth comparator CMP3, a second end of the thirteenth switch K13 is connected to the output end of the third comparator CMP3, one end of the fourteenth switch K14 is respectively connected to the third end of the twelfth switch K12, the third end of the thirteenth switch K13, one end of the seventh capacitor C7, and the non-inverting input end of the single-ended output amplifier AMP2, the other end of the fourteenth switch K14 is respectively connected to the inverting input end of the third comparator CMP3, the inverting input end of the fourth comparator CMP4, and the common mode voltage output end of the reference voltage source, and the other end of the seventh capacitor C7 is grounded.

[0021] Optionally, the thyristor driving circuit includes a second PMOS transistor P2, a third NMOS transistor P3 and a sixth resistor R6;

[0022] The source of the second PMOS tube P2 is connected to the external power supply VDD, the gate of the second PMOS tube P2 is respectively connected to the output end of the digital logic unit and the gate of the third NMOS tube P3, one end of the sixth resistor R6 is connected to the drain of the second PMOS tube P2, and the other end of the sixth resistor R6 is respectively connected to the drain of the third NMOS tube P3 and the external circuit breaker OS.

[0023] Optionally, the operating steps of a high-precision anti-interference leakage protection circuit are:

[0024] Step S1: The fully differential wide common-mode input operational amplifier AMP1 collects the first differential signal OP1 and the second differential signal OP2 of the target detection circuit respectively and amplifies the signals to obtain the first detection level signal OUT1+ and the second detection level signal OUT1-, and sends them to the sampler;

[0025] Step S2: the sampler samples the amplified first detection level signal OUT1+, the amplified second detection level signal OUT1-, and the reference common mode voltage COM to obtain the leakage test voltage OUT1 and sends it to the single-ended output amplifier AMP2;

[0026] Step S3: the leakage detection voltage OUT1 is amplified by the single-ended output amplifier AMP2 and filtered by the filter capacitor C0, and then transmitted to the first comparator CMP1 and the power-on reset device POR, and the power-on reset device resets the clock unit and the digital logic unit;

[0027] Step S4: the first comparator CMP1 compares the leakage check voltage OUT1 with the reference voltage VREF. If the leakage check voltage OUT1 is greater than the reference voltage VREF, the first comparator CMP1 controls the integrator to charge the integration capacitor CAP.

[0028] Step S5: The second comparator CMP2 compares the voltage of the charged integral capacitor CAP with the reference voltage VREF. If the voltage of the charged integral capacitor CAP is greater than the reference voltage VREF, the second comparator CMP2 controls the digital logic unit to generate a pulse signal to control the conduction of the thyristor drive circuit and the timing of the clock unit. The thyristor drive circuit drives the external circuit breaker OS to disconnect the target detection circuit.

[0029] Optionally, the operation mode of step S1 is:

[0030] Extracting the first differential signal OP1 and the second differential signal OP2 includes: closing the first switch K1 and the second switch K2, opening the third switch K3, the fourth switch K4, and the fifth switch K5, storing the first differential signal OP1 in the first capacitor C1, and storing the second differential signal OP2 in the second capacitor C2;

[0031] Eliminating the bias voltage of the fully differential wide common-mode input amplifier AMP1 includes: closing the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, the tenth switch K10, and the eleventh switch K11, discharging the voltages of the third capacitor C3 and the fourth capacitor C4 to 0V, storing the bias voltage of the first operational amplifier AMP0+ in the fifth capacitor C5, storing the bias voltage of the second operational amplifier AMP0- in the sixth capacitor C6, and disconnecting the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, the tenth switch K10, and the eleventh switch K11, so that the output end of the first operational amplifier AMP0+, the output end of the second operational amplifier AMP0-, and both ends of the second resistor R2 are all the reference common-mode voltage COM;

[0032] Amplifying the first differential signal OP1 and the second differential signal OP2 to obtain the first detection level signal OUT1+ and the second detection level signal OUT1- includes: disconnecting the first switch K1, the second switch K2, the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, the tenth switch K10 and the eleventh switch K11, closing the third switch K3, the fourth switch K4 and the fifth switch K5, so that the first differential signal OP1 stored in the first capacitor C1 is transmitted to the third capacitor C3, and the second differential signal OP2 stored in the second capacitor C2 is transmitted to the fourth capacitor C4, the first operational amplifier AMP0+ amplifies the first differential signal OP1 to obtain the first detection level signal OUT1+, and the second operational amplifier AMP0- amplifies the second differential signal OP2 to obtain the second detection level signal OUT1-.

[0033] Optionally, the operation mode of step S2 is:

[0034] Step S2 is divided into a sampling phase and a holding phase;

[0035] Sampling stage: the first differential signal OP1 and the second differential signal OP2 must be amplified by the fully differential wide common mode input operational amplifier AMP1, and sampling must be performed when the first detection level signal OUT1+ and the second detection level signal OUT1- are stable, and the amplified signal generated by AMP1 is stored in the seventh capacitor C7; the voltage of the seventh capacitor C7 during the sampling stage is divided into the following three conditions:

[0036] First, the first detection level signal OUT1+ is subtracted from the reference common mode voltage COM. If the difference is greater than a preset threshold, the first detection level signal OUT1+ is sampled to the seventh capacitor C7 through the twelfth switch K12;

[0037] Second, the second detection level signal OUT1- is subtracted from the reference common mode voltage COM. If the difference is greater than a preset threshold, the second detection level signal OUT1- is sampled to the seventh capacitor C7 through the thirteenth switch K13;

[0038] Third, if the difference between the first detection level signal OUT1+ and the reference common mode voltage COM, and the difference between the second detection level signal OUT1- and the reference common mode voltage COM are not greater than the preset threshold, the reference common mode voltage COM is sampled to the seventh capacitor C7 through the fourteenth switch K14;

[0039] Holding stage: except for the sampling stage, the seventh capacitor C7 maintains the original voltage during the rest of the time;

[0040] The seventh capacitor C7 sends the leakage detection voltage OUT1 to the single-ended output amplifier AMP2.

[0041] The beneficial effects of the present invention compared with the prior art are:

[0042] The present invention provides a high-precision anti-interference leakage protection circuit, comprising a fully differential wide common-mode input operational amplifier AMP1, a sampler, a single-ended output amplifier AMP2, a first comparator CMP1, a second comparator CMP2, an integrator, a reference voltage source, a clock unit, a digital logic unit, a power-on reset POR, and a thyristor drive circuit. The high-precision anti-interference leakage protection circuit provided by the present invention effectively solves the problem of low stability of the voltage leakage protection circuit due to the common-mode level being easily affected by interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0044] Figure 1 It is a circuit principle diagram of a high-precision anti-interference leakage protection circuit provided by the present invention;

[0045] Figure 2 It is a circuit schematic diagram of a fully differential wide common-mode input operational amplifier AMP1 provided by the present invention;

[0046] Figure 3 is a circuit schematic diagram of a sampler provided by the present invention;

[0047] Figure 4 It is a working waveform diagram of a high-precision anti-interference leakage protection circuit of the present invention. DETAILED DESCRIPTION

[0048] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0049] In order to make the purpose, technical solutions and advantages of the present invention more clear, specific embodiments will be described below in conjunction with the accompanying drawings.

[0050] See attached Figure 1The embodiment of the present invention provides a high-precision anti-interference leakage protection circuit, including a fully differential wide common-mode input operational amplifier AMP1, a sampler, a single-ended output amplifier AMP2, a first comparator CMP1, a second comparator CMP2, an integrator, a reference voltage source, a clock unit, a digital logic unit, a power-on reset POR, and a thyristor drive circuit;

[0051] The first input terminal and the second input terminal of the fully differential wide common mode input operational amplifier AMP1 are externally connected to the target detection circuit, the third input terminal of the fully differential wide common mode input operational amplifier AMP1 is connected to the common mode voltage output terminal of the reference voltage source, the first output terminal of the fully differential wide common mode input operational amplifier AMP1 is connected to the first input terminal of the sampler, and the second output terminal of the fully differential wide common mode input operational amplifier AMP1 is connected to the second input terminal of the sampler;

[0052] The third input terminal of the sampler is connected to the common mode voltage output terminal of the reference voltage source, and the output terminal of the sampler is connected to the non-inverting input terminal of the single-ended output amplifier AMP2;

[0053] The inverting input terminal of the single-ended output amplifier AMP2 is connected to the common-mode voltage output terminal of the reference voltage source, and the output terminal of the single-ended output amplifier AMP2 is respectively connected to one end of the filter capacitor CO, the non-inverting input terminal of the first comparator CMP1, and the input terminal of the power-on reset device POR; the other end of the filter capacitor C0 is grounded; the common-mode voltage output terminal of the reference voltage source outputs a reference common-mode voltage COM;

[0054] The inverting input terminal of the first comparator CMP1 is used to be connected to the reference voltage output terminal of the reference voltage source, and the output terminal of the first comparator CMP1 is connected to the input terminal of the integrator;

[0055] A first output end of the power-on reset device POR is connected to a first input end of the digital logic unit, a second output end of the power-on reset device POR is connected to a first input end of the clock unit, and a second input end of the clock unit is connected to a first output end of the digital logic unit;

[0056] The output end of the integrator is connected to one end of the integration capacitor CAP and the non-inverting input end of the second comparator CMP2 respectively, and the other end of the integration capacitor CAP is grounded;

[0057] The inverting input terminal of the second comparator CMP2 is connected to the reference voltage output terminal of the reference voltage source, and the output terminal of the second comparator CMP2 is connected to the second input terminal of the digital logic unit; the reference voltage output terminal of the reference voltage source outputs the reference reference voltage VREF;

[0058] The second output terminal of the digital logic unit is used to drive the controllable drive circuit to turn on, and the thyristor drive circuit drives the external circuit breaker OS to disconnect the target detection circuit.

[0059] See attached Figure 2 As a specific implementation of a high-precision anti-interference leakage protection circuit provided by an embodiment of the present invention, the fully differential wide common-mode input operational amplifier AMP1 includes a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, a ninth switch K9, a tenth switch K10, an eleventh switch K11, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first operational amplifier AMP0+, a second operational amplifier AMP0-, a first resistor R1, a second resistor R2 and a third resistor R3;

[0060] One end of the first switch K1 and one end of the second switch K2 are connected to the external target detection circuit, the other end of the first switch K1 is respectively connected to one end of the third switch K3 and one end of the first capacitor C1, the other end of the first capacitor C1 is respectively connected to one end of the fourth switch K4 and one end of the second capacitor C2, the other end of the second capacitor C2 is respectively connected to the other end of the second switch K2 and one end of the fifth switch K5, the other end of the third switch K3 is respectively connected to one end of the sixth switch K6, one end of the third capacitor C3, and the non-inverting input end of the first operational amplifier AMP0+, one end of the eighth switch K8 is respectively connected to the common-mode voltage output end of the reference voltage source, the other end of the sixth switch K6, and the other end of the third capacitor C3, the other end of the eighth switch K8 is respectively connected to one end of the fifth capacitor C5, one end of the first resistor R1, and one end of the second resistor R2, the other end of the fifth capacitor is respectively connected to the inverting input end of the first operational amplifier AMP0+ and one end of the tenth switch K10 The other end of the tenth switch K10 is respectively connected to the output end of the first operational amplifier AMP0+, the other end of the first resistor R1, and the first input end of the sampler; one end of the ninth switch K9 is respectively connected to the other end of the fourth switch K4, one end of the seventh switch K7, one end of the fourth capacitor C4, and the common-mode voltage output end of the reference voltage source; the other end of the ninth switch K9 is respectively connected to one end of the sixth capacitor C6, the other end of the second resistor R2, and one end of the third resistor R3; the other end of the seventh switch K7 is respectively connected to the other end of the fifth switch K5, the other end of the fourth capacitor C4, and the non-inverting input end of the second operational amplifier AMP0-; the other end of the sixth capacitor C6 is respectively connected to the inverting input end of the second operational amplifier AMP0- and one end of the eleventh switch K11; the other end of the eleventh switch K11 is respectively connected to the other end of the third resistor R3, the output end of the second operational amplifier AMP0-, and the second input end of the sampler.

[0061] See attached Figure 1, as a specific implementation of a high-precision anti-interference leakage protection circuit provided by an embodiment of the present invention, the high-precision anti-interference leakage protection circuit also includes a voltage stabilizer, which provides a stable power supply voltage for the high-precision anti-interference leakage protection circuit;

[0062] The voltage regulator includes a fourth resistor R4, a fifth resistor R5, a first NMOS transistor P1 and a third operational amplifier AMP3;

[0063] One end of the fourth resistor R4 is respectively connected to the external power supply VDD and the drain of the first NMOS tube P1, the other end of the fourth resistor R4 is respectively connected to one end of the fifth resistor R5 and the non-inverting input end of the third operational amplifier AMP3, the other end of the fifth resistor R5 is grounded, the inverting input end of the third operational amplifier AMP3 is connected to the reference voltage output end of the reference voltage source, the output end of the third operational amplifier AMP3 is connected to the gate of the first NMOS tube P1, and the source of the first NMOS tube P1 is grounded.

[0064] See attached Figure 3 As a specific implementation of a high-precision anti-interference leakage protection circuit provided by an embodiment of the present invention, the sampler includes a third comparator CMP3, a fourth comparator CMP4, a twelfth switch K12, a thirteenth switch K13, a fourteenth switch K14 and a seventh capacitor C7;

[0065] A first end of the twelfth switch K12 is respectively connected to the first output end of the fully differential wide common mode input operational amplifier AMP1 and the non-inverting input end of the third comparator CMP3, a second end of the twelfth switch K12 is respectively connected to the output end of the third comparator CMP3, a first end of the thirteenth switch K13 is respectively connected to the second output end of the fully differential wide common mode input operational amplifier AMP1 and the non-inverting input end of the fourth comparator CMP3, a second end of the thirteenth switch K13 is connected to the output end of the third comparator CMP3, one end of the fourteenth switch K14 is respectively connected to the third end of the twelfth switch K12, the third end of the thirteenth switch K13, one end of the seventh capacitor C7, and the non-inverting input end of the single-ended output amplifier AMP2, the other end of the fourteenth switch K14 is respectively connected to the inverting input end of the third comparator CMP3, the inverting input end of the fourth comparator CMP4, and the common mode voltage output end of the reference voltage source, and the other end of the seventh capacitor C7 is grounded.

[0066] See attached Figure 1 As a specific implementation of a high-precision anti-interference leakage protection circuit provided by an embodiment of the present invention, the thyristor driving circuit includes a second PMOS tube P2, a third NMOS tube P3 and a sixth resistor R6;

[0067] The source of the second PMOS tube P2 is connected to the external power supply VDD, the gate of the second PMOS tube P2 is respectively connected to the output end of the digital logic unit and the gate of the third NMOS tube P3, one end of the sixth resistor R6 is connected to the drain of the second PMOS tube P2, and the other end of the sixth resistor R6 is respectively connected to the drain of the third NMOS tube P3 and the external circuit breaker OS.

[0068] See attached Figure 1 and attached Figure 4 As a specific implementation method of a high-precision anti-interference leakage protection circuit provided by an embodiment of the present invention, the operation steps of a high-precision anti-interference leakage protection circuit are as follows:

[0069] Step S1: The fully differential wide common-mode input operational amplifier AMP1 collects the first differential signal OP1 and the second differential signal OP2 of the target detection circuit respectively and amplifies the signals to obtain the first detection level signal OUT1+ and the second detection level signal OUT1-, and sends them to the sampler;

[0070] Step S2: the sampler samples the amplified first detection level signal OUT1+, the amplified second detection level signal OUT1-, and the reference common mode voltage COM to obtain the leakage test voltage OUT1 and sends it to the single-ended output amplifier AMP2;

[0071] Step S3: the leakage detection voltage OUT1 is amplified by the single-ended output amplifier AMP2 and filtered by the filter capacitor C0, and then transmitted to the first comparator CMP1 and the power-on reset device POR, and the power-on reset device resets the clock unit and the digital logic unit;

[0072] Step S4: the first comparator CMP1 compares the leakage check voltage OUT1 with the reference voltage VREF. If the leakage check voltage OUT1 is greater than the reference voltage VREF, the first comparator CMP1 controls the integrator to charge the integration capacitor CAP.

[0073] Step S5: The second comparator CMP2 compares the voltage of the charged integral capacitor CAP with the reference voltage VREF. If the voltage of the charged integral capacitor CAP is greater than the reference voltage VREF, the second comparator CMP2 controls the digital logic unit to generate a pulse signal to control the conduction of the thyristor drive circuit and the timing of the clock unit. The thyristor drive circuit drives the external circuit breaker OS to disconnect the target detection circuit.

[0074] See attached Figure 2 As a specific implementation of a high-precision anti-interference leakage protection circuit provided by an embodiment of the present invention, the operation mode of step S1 is:

[0075] Extracting the first differential signal OP1 and the second differential signal OP2 includes: closing the first switch K1 and the second switch K2, opening the third switch K3, the fourth switch K4, and the fifth switch K5, storing the first differential signal OP1 in the first capacitor C1, and storing the second differential signal OP2 in the second capacitor C2;

[0076] Eliminating the bias voltage of the fully differential wide common-mode input amplifier AMP1 includes: closing the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, the tenth switch K10, and the eleventh switch K11, discharging the voltages of the third capacitor C3 and the fourth capacitor C4 to 0V, storing the bias voltage of the first operational amplifier AMP0+ in the fifth capacitor C5, storing the bias voltage of the second operational amplifier AMP0- in the sixth capacitor C6, and disconnecting the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, the tenth switch K10, and the eleventh switch K11, so that the output end of the first operational amplifier AMP0+, the output end of the second operational amplifier AMP0-, and both ends of the second resistor R2 are all the reference common-mode voltage COM;

[0077] Amplifying the first differential signal OP1 and the second differential signal OP2 to obtain the first detection level signal OUT1+ and the second detection level signal OUT1- includes: disconnecting the first switch K1, the second switch K2, the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, the tenth switch K10 and the eleventh switch K11, closing the third switch K3, the fourth switch K4 and the fifth switch K5, so that the first differential signal OP1 stored in the first capacitor C1 is transmitted to the third capacitor C3, and the second differential signal OP2 stored in the second capacitor C2 is transmitted to the fourth capacitor C4, the first operational amplifier AMP0+ amplifies the first differential signal OP1 to obtain the first detection level signal OUT1+, and the second operational amplifier AMP0- amplifies the second differential signal OP2 to obtain the second detection level signal OUT1-.

[0078] In this embodiment, since the initial voltage of the third capacitor C3 and the fourth capacitor C4 is 0V, and the capacitance of the first capacitor C1 and the second capacitor C2 are equal, the voltage stored on the first capacitor C1 and the second capacitor C2 are equal, and the common-mode output level of the first detection level signal OUT1+ and the second detection level signal OUT1- is ensured to be the reference common-mode voltage COM. When the signal is amplified, the voltage on the third capacitor C3 and the fourth capacitor C4 is k / (1+k)*Vin, k is a constant, Vin is an adjustable variable, and the amplification factors of the first operational amplifier AMP0+ and the second operational amplifier AMP0- are both (r1+r2+r3) / r2, r1 is the resistance value of the first resistor R1, r2 is the resistance value of the second resistor R2, and r3 is the resistance value of the third resistor R3, so the amplification factor of the fully differential wide common-mode input amplifier AMP1 is k*(r1+r2+r3) / r2*(1+k).

[0079] See attached Figure 3 As a specific implementation of a high-precision anti-interference leakage protection circuit provided by an embodiment of the present invention, the operation mode of step S2 is:

[0080] Step S2 is divided into a sampling phase and a holding phase;

[0081] The sampling stage must be performed when the first differential signal OP1 and the second differential signal OP2 are amplified by the fully differential wide common mode input operational amplifier AMP1, and the first detection level signal OUT1+ and the second detection level signal OUT1- are stable, and the amplified signal generated by AMP1 is stored in the seventh capacitor C7; the voltage of the seventh capacitor C7 in the sampling stage is divided into the following three conditions:

[0082] First, the first detection level signal OUT1+ is subtracted from the reference common mode voltage COM. If the difference is greater than a preset threshold, the first detection level signal OUT1+ is sampled to the seventh capacitor C7 through the twelfth switch K12;

[0083] Second, the second detection level signal OUT1- is subtracted from the reference common mode voltage COM. If the difference is greater than a preset threshold, the second detection level signal OUT1- is sampled to the seventh capacitor C7 through the thirteenth switch K13;

[0084] Third, if the difference between the first detection level signal OUT1+ and the reference common mode voltage COM, and the difference between the second detection level signal OUT1- and the reference common mode voltage COM are not greater than the preset threshold, the reference common mode voltage COM is sampled to the seventh capacitor C7 through the fourteenth switch K14;

[0085] Holding stage: except for the sampling stage, the seventh capacitor C7 maintains the original voltage during the rest of the time;

[0086] The seventh capacitor C7 sends the leakage detection voltage OUT1 to the single-ended output amplifier AMP2.

[0087] The beneficial effects of the present invention compared with the prior art are:

[0088] The present invention provides a high-precision anti-interference leakage protection circuit, comprising a fully differential wide common-mode input operational amplifier AMP1, a sampler, a single-ended output amplifier AMP2, a first comparator CMP1, a second comparator CMP2, an integrator, a reference voltage source, a clock unit, a digital logic unit, a power-on reset POR, and a thyristor drive circuit. The high-precision anti-interference leakage protection circuit provided by the present invention effectively solves the problem of low stability of the voltage leakage protection circuit due to the common-mode level being easily affected by interference.

[0089] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A high-precision anti-interference leakage protection circuit, characterized in that: It includes a fully differential wide common-mode input operational amplifier AMP1, a sampler, a single-ended output amplifier AMP2, a first comparator CMP1, a second comparator CMP2, an integrator, a reference voltage source, a clock unit, a digital logic unit, a power-on reset POR, and a thyristor drive circuit; The first input terminal and the second input terminal of the fully differential wide common mode input operational amplifier AMP1 are externally connected to the target detection circuit, the third input terminal of the fully differential wide common mode input operational amplifier AMP1 is connected to the common mode voltage output terminal of the reference voltage source, the first output terminal of the fully differential wide common mode input operational amplifier AMP1 is connected to the first input terminal of the sampler, and the second output terminal of the fully differential wide common mode input operational amplifier AMP1 is connected to the second input terminal of the sampler; the fully differential wide common mode input operational amplifier AMP1 acquires two differential signals of the target detection circuit and amplifies them to obtain two detection level signals, and sends the two detection level signals to the first input terminal and the second input terminal of the sampler respectively; The third input terminal of the sampler is connected to the common mode voltage output terminal of the reference voltage source, and the output terminal of the sampler is connected to the non-inverting input terminal of the single-ended output amplifier AMP2; The inverting input terminal of the single-ended output amplifier AMP2 is connected to the common-mode voltage output terminal of the reference voltage source, and the output terminal of the single-ended output amplifier AMP2 is respectively connected to one end of the filter capacitor CO, the non-inverting input terminal of the first comparator CMP1, and the input terminal of the power-on reset device POR; the other end of the filter capacitor C0 is grounded; the common-mode voltage output terminal of the reference voltage source outputs a reference common-mode voltage COM; The inverting input terminal of the first comparator CMP1 is used to be connected to the reference voltage output terminal of the reference voltage source, and the output terminal of the first comparator CMP1 is connected to the input terminal of the integrator; A first output end of the power-on reset device POR is connected to a first input end of the digital logic unit, a second output end of the power-on reset device POR is connected to a first input end of the clock unit, and a second input end of the clock unit is connected to a first output end of the digital logic unit; The output end of the integrator is connected to one end of the integration capacitor CAP and the non-inverting input end of the second comparator CMP2 respectively, and the other end of the integration capacitor CAP is grounded; The inverting input terminal of the second comparator CMP2 is connected to the reference voltage output terminal of the reference voltage source, and the output terminal of the second comparator CMP2 is connected to the second input terminal of the digital logic unit; the reference voltage output terminal of the reference voltage source outputs the reference reference voltage VREF; The second output terminal of the digital logic unit is used to drive the controllable drive circuit to turn on, and the thyristor drive circuit drives the external circuit breaker OS to disconnect the target detection circuit.

2. A high-precision anti-interference leakage protection circuit according to claim 1, characterized in that: The fully differential wide common-mode input operational amplifier AMP1 includes a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, a ninth switch K9, a tenth switch K10, an eleventh switch K11, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first operational amplifier AMP0+, a second operational amplifier AMP0-, a first resistor R1, a second resistor R2 and a third resistor R3; One end of the first switch K1 and one end of the second switch K2 are connected to the external target detection circuit, the other end of the first switch K1 is respectively connected to one end of the third switch K3 and one end of the first capacitor C1, the other end of the first capacitor C1 is respectively connected to one end of the fourth switch K4 and one end of the second capacitor C2, the other end of the second capacitor C2 is respectively connected to the other end of the second switch K2 and one end of the fifth switch K5, the other end of the third switch K3 is respectively connected to one end of the sixth switch K6, one end of the third capacitor C3, and the non-inverting input end of the first operational amplifier AMP0+, one end of the eighth switch K8 is respectively connected to the common-mode voltage output end of the reference voltage source, the other end of the sixth switch K6, and the other end of the third capacitor C3, the other end of the eighth switch K8 is respectively connected to one end of the fifth capacitor C5, one end of the first resistor R1, and one end of the second resistor R2, the other end of the fifth capacitor is respectively connected to the inverting input end of the first operational amplifier AMP0+ and one end of the tenth switch K10 The other end of the tenth switch K10 is respectively connected to the output end of the first operational amplifier AMP0+, the other end of the first resistor R1, and the first input end of the sampler; one end of the ninth switch K9 is respectively connected to the other end of the fourth switch K4, one end of the seventh switch K7, one end of the fourth capacitor C4, and the common-mode voltage output end of the reference voltage source; the other end of the ninth switch K9 is respectively connected to one end of the sixth capacitor C6, the other end of the second resistor R2, and one end of the third resistor R3; the other end of the seventh switch K7 is respectively connected to the other end of the fifth switch K5, the other end of the fourth capacitor C4, and the non-inverting input end of the second operational amplifier AMP0-; the other end of the sixth capacitor C6 is respectively connected to the inverting input end of the second operational amplifier AMP0- and one end of the eleventh switch K11; the other end of the eleventh switch K11 is respectively connected to the other end of the third resistor R3, the output end of the second operational amplifier AMP0-, and the second input end of the sampler.

3. A high-precision anti-interference leakage protection circuit according to claim 2, characterized in that: It also includes a voltage stabilizer, which provides a stable power supply voltage for the high-precision anti-interference leakage protection circuit; The voltage regulator includes a fourth resistor R4, a fifth resistor R5, a first NMOS transistor P1 and a third operational amplifier AMP3; One end of the fourth resistor R4 is respectively connected to the external power supply VDD and the drain of the first NMOS tube P1, the other end of the fourth resistor R4 is respectively connected to one end of the fifth resistor R5 and the non-inverting input end of the third operational amplifier AMP3, the other end of the fifth resistor R5 is grounded, the inverting input end of the third operational amplifier AMP3 is connected to the reference voltage output end of the reference voltage source, the output end of the third operational amplifier AMP3 is connected to the gate of the first NMOS tube P1, and the source of the first NMOS tube P1 is grounded.

4. A high-precision anti-interference leakage protection circuit according to claim 3, characterized in that: The sampler includes a third comparator CMP3, a fourth comparator CMP4, a twelfth switch K12, a thirteenth switch K13, a fourteenth switch K14 and a seventh capacitor C7; A first end of the twelfth switch K12 is respectively connected to the first output end of the fully differential wide common-mode input operational amplifier AMP1 and the non-inverting input end of the third comparator CMP3, a second end of the twelfth switch K12 is respectively connected to the output end of the third comparator CMP3, a first end of the thirteenth switch K13 is respectively connected to the second output end of the fully differential wide common-mode input operational amplifier AMP1 and the non-inverting input end of the fourth comparator CMP3, a second end of the thirteenth switch K13 is connected to the output end of the third comparator CMP3, one end of the fourteenth switch K14 is respectively connected to the third end of the twelfth switch K12, the third end of the thirteenth switch K13, one end of the seventh capacitor C7, and the non-inverting input end of the single-ended output amplifier AMP2, the other end of the fourteenth switch K14 is respectively connected to the inverting input end of the third comparator CMP3, the inverting input end of the fourth comparator CMP4, and the common-mode voltage output end of the reference voltage source, and the other end of the seventh capacitor C7 is grounded.

5. A high-precision anti-interference leakage protection circuit according to claim 4, characterized in that: The thyristor driving circuit includes a second PMOS transistor P2, a third NMOS transistor P3 and a sixth resistor R6; The source of the second PMOS tube P2 is connected to the external power supply VDD, the gate of the second PMOS tube P2 is respectively connected to the output end of the digital logic unit and the gate of the third NMOS tube P3, one end of the sixth resistor R6 is connected to the drain of the second PMOS tube P2, and the other end of the sixth resistor R6 is respectively connected to the drain of the third NMOS tube P3 and the external circuit breaker OS.

6. A high-precision anti-interference leakage protection circuit according to claim 5, wherein the operation steps of the high-precision anti-interference leakage protection circuit are: Step S1: the fully differential wide common-mode input operational amplifier AMP1 collects the first differential signal OP1 and the second differential signal OP2 of the target detection circuit respectively, amplifies the signals to obtain the first detection level signal OUT1+ and the second detection level signal OUT1-, and sends them to the sampler; Step S2: the sampler samples the amplified first detection level signal OUT1+, the amplified second detection level signal OUT1-, and the reference common mode voltage COM to obtain a leakage test voltage OUT1 and sends it to the single-ended output amplifier AMP2; Step S3: the leakage detection voltage OUT1 is transmitted to the first comparator CMP1 and the power-on reset device POR after being amplified by the signal of the single-ended output amplifier AMP2 and filtered by the filter capacitor C0, and the power-on reset device resets the clock unit and the digital logic unit; Step S4: the first comparator CMP1 compares the leakage check voltage OUT1 with the reference voltage VREF. If the leakage check voltage OUT1 is greater than the reference voltage VREF, the first comparator CMP1 controls the integrator to charge the integration capacitor CAP. Step S5: The second comparator CMP2 compares the voltage of the charged integration capacitor CAP with the reference voltage VREF. If the voltage of the charged integration capacitor CAP is greater than the reference voltage VREF, the second comparator CMP2 controls the digital logic unit to generate a pulse signal to control the conduction of the thyristor drive circuit and the timing of the clock unit, and the thyristor drive circuit drives the external circuit breaker OS to disconnect the target detection circuit.

7. A high-precision anti-interference leakage protection circuit according to claim 6, characterized in that: The operation mode of step S1 is: Extracting the first differential signal OP1 and the second differential signal OP2 includes: closing the first switch K1 and the second switch K2, opening the third switch K3, the fourth switch K4, and the fifth switch K5, storing the first differential signal OP1 in the first capacitor C1, and storing the second differential signal OP2 in the second capacitor C2; Eliminating the bias voltage of the fully differential wide common-mode input operational amplifier AMP1 includes: closing the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, the tenth switch K10, and the eleventh switch K11, discharging the voltages of the third capacitor C3 and the fourth capacitor C4 to 0V, storing the bias voltage of the first operational amplifier AMP0+ in the fifth capacitor C5, storing the bias voltage of the second operational amplifier AMP0- in the sixth capacitor C6, and disconnecting the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, the tenth switch K10, and the eleventh switch K11, so that the output end of the first operational amplifier AMP0+, the output end of the second operational amplifier AMP0-, and both ends of the second resistor R2 are all the reference common-mode voltage COM; Amplifying the first differential signal OP1 and the second differential signal OP2 to obtain the first detection level signal OUT1+ and the second detection level signal OUT1- includes: disconnecting the first switch K1, the second switch K2, the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, the tenth switch K10 and the eleventh switch K11, closing the third switch K3, the fourth switch K4 and the fifth switch K5, so that the first differential signal OP1 stored in the first capacitor C1 is transmitted to the third capacitor C3, and the second differential signal OP2 stored in the second capacitor C2 is transmitted to the fourth capacitor C4, the first operational amplifier AMP0+ amplifies the first differential signal OP1 to obtain the first detection level signal OUT1+, and the second operational amplifier AMP0- amplifies the second differential signal OP2 to obtain the second detection level signal OUT1-.

8. According to the high-precision anti-interference leakage protection circuit of claim 6, the operation mode of step S2 is: Step S2 is divided into a sampling phase and a holding phase; The sampling stage must be performed when the first differential signal OP1 and the second differential signal OP2 are amplified by the fully differential wide common mode input operational amplifier AMP1, and the first detection level signal OUT1+ and the second detection level signal OUT1- are stable, and the amplified signal generated by AMP1 is stored in the seventh capacitor C7; the voltage of the seventh capacitor C7 in the sampling stage is divided into the following three conditions: First, the first detection level signal OUT1+ is subtracted from the reference common mode voltage COM. If the difference is greater than a preset threshold, the first detection level signal OUT1+ is sampled to the seventh capacitor C7 through the twelfth switch K12; Second, the second detection level signal OUT1- is subtracted from the reference common mode voltage COM. If the difference is greater than a preset threshold, the second detection level signal OUT1- is sampled to the seventh capacitor C7 through the thirteenth switch K13; Third, if the difference between the first detection level signal OUT1+ and the reference common mode voltage COM, and the difference between the second detection level signal OUT1- and the reference common mode voltage COM are both not greater than the preset threshold, the reference common mode voltage COM is sampled to the seventh capacitor C7 through the fourteenth switch K14; Holding stage: except for the sampling stage, the seventh capacitor C7 maintains the original voltage during the rest of the time; The seventh capacitor C7 sends the leakage detection voltage OUT1 to the single-ended output amplifier AMP2.

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