Level conversion circuit

Abstract

The present application relates to a level conversion circuit. The level conversion circuit of the present application includes: an input module; an isolation module; an output module, including at least one of the following: a third high-voltage transistor; a fourth high-voltage transistor; wherein the output module is used to implement at least one of the following when the first output terminal of the input module outputs a first low-bit signal: the source of the fourth high-voltage transistor obtains a high-voltage power supply signal, and the fourth high-voltage transistor is turned on under the control of an inverted input signal that is inverted to the input signal so that the second output terminal of the level conversion circuit connected to the drain of the fourth high-voltage transistor outputs a second output signal determined according to the high-voltage power supply signal; the substrate and source of the third high-voltage transistor respectively obtain a first voltage-limiting signal to reduce the voltage difference between the substrate and drain of the third high-voltage transistor. The present application can reduce tube leakage, prevent tube breakdown, and improve circuit reliability.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a level conversion circuit. Background Art

[0002] In the design of EFLASH (called NAND Flash or NOR Flash, a non-volatile memory), bitcell (basic storage unit) is the basic unit for storing data. Due to the particularity of bitcell, high voltage is required during programming or erasing operations. Then, a level conversion circuit is usually used to achieve the conversion output of the required high voltage under the control of the logic signal.

[0003] However, due to process limitations, the breakdown voltage of the CMOS tube used in the level conversion circuit cannot reach the high voltage, so the tube is prone to breakdown, causing the chip to fail and fail to work.

[0004] Therefore, how to prevent tube breakdown is an important aspect of improving the reliability of level conversion circuits. Summary of the invention

[0005] In view of this, an embodiment of the present application provides a level conversion circuit to solve at least one problem existing in the background technology.

[0006] An embodiment of the present application provides a level conversion circuit, the level conversion circuit comprising:

[0007] An input module, used for outputting a first low-bit signal at a first output terminal of the input module or a second low-bit signal at a second output terminal of the input module under the control of an input signal; wherein the first low-bit signal and the second low-bit signal are respectively determined according to a ground signal;

[0008] The isolation module is used for, based on the control of the low-voltage power supply signal, when the first output end of the input module outputs the first low-bit signal, turning on the output of the first output end of the isolation module so that the first output end of the level conversion circuit connected to the first output end of the isolation module outputs the first output signal determined according to the first low-bit signal; when the second output end of the input module outputs the second low-bit signal, turning on the output of the second output end of the isolation module so that the second output end of the level conversion circuit connected to the second output end of the isolation module outputs the second output signal determined according to the second low-bit signal;

[0009] The output module comprises at least one of the following: a third high-voltage transistor; a fourth high-voltage transistor;

[0010] Wherein, the output module is used to implement at least one of the following when the first low-bit signal is output at the first output end of the input module:

[0011] The source of the fourth high-voltage transistor obtains a high-voltage power signal, and the fourth high-voltage transistor is turned on under the control of an inverted input signal that is inverted with respect to the input signal so that the second output terminal of the level conversion circuit connected to the drain of the fourth high-voltage transistor outputs a second output signal determined according to the high-voltage power signal;

[0012] The substrate electrode and the source electrode of the third high-voltage transistor respectively obtain the first voltage limiting signal to reduce the voltage difference between the substrate electrode and the drain electrode of the third high-voltage transistor;

[0013] In a case where the second output terminal of the input module outputs the second low-bit signal, at least one of the following is implemented:

[0014] The source of the third high-voltage transistor obtains a high-voltage power signal, and the third high-voltage transistor is turned on under the control of the input signal so that the first output terminal of the level conversion circuit connected to the drain of the third high-voltage transistor outputs a first output signal determined according to the high-voltage power signal;

[0015] The substrate electrode and the source electrode of the fourth high-voltage transistor respectively obtain the second voltage limiting signal to reduce the voltage difference between the substrate electrode and the drain electrode of the fourth high-voltage transistor.

[0016] In an optional implementation, the isolation module includes at least one of the following: a first high-voltage transistor; a second high-voltage transistor;

[0017] Wherein, the isolation module is used to implement at least one of the following when the first output terminal of the input module outputs the first low-bit signal:

[0018] The source of the first high-voltage transistor obtains the first low-bit signal, and the first high-voltage transistor is turned on under the control of the low-voltage power supply signal so that the first output end of the level conversion circuit connected to the drain of the first high-voltage transistor outputs a first output signal determined according to the first low-bit signal;

[0019] The source of the second high-voltage transistor obtains a second voltage reduction signal to reduce the drain-source voltage of the second high-voltage transistor; wherein the second voltage reduction signal is determined according to the low-voltage power supply signal;

[0020] In a case where the second output terminal of the input module outputs the second low-bit signal, at least one of the following is implemented:

[0021] The source of the second high-voltage transistor obtains the second low-bit signal, and the second high-voltage transistor is turned on under the control of the low-voltage power supply signal so that the second output terminal of the level conversion circuit connected to the drain of the second high-voltage transistor outputs a second output signal determined according to the second low-bit signal;

[0022] The source of the first high-voltage transistor obtains a first voltage reduction signal to reduce the drain-source voltage of the first high-voltage transistor; wherein the first voltage reduction signal is determined according to the low-voltage power supply signal.

[0023] In an optional implementation, the third high-voltage transistor and the fourth high-voltage transistor are both high-voltage PMOS transistors.

[0024] In an optional implementation, both the first high-voltage transistor and the second high-voltage transistor are high-voltage NMOS transistors.

[0025] In an optional implementation manner, the level conversion circuit further includes at least one of the following:

[0026] A first voltage limiting module, comprising a seventh high-voltage transistor, configured to provide the first voltage limiting signal, and to be turned on under the control of a low-voltage power supply signal to limit a voltage value of the first voltage limiting signal by utilizing a threshold voltage of the seventh high-voltage transistor;

[0027] The second voltage limiting module includes an eighth high-voltage transistor, which is used to provide the second voltage limiting signal and is turned on under the control of the low-voltage power supply signal to limit the voltage value of the second voltage limiting signal using the threshold voltage of the eighth high-voltage transistor.

[0028] In an optional implementation, the seventh high-voltage transistor and the eighth high-voltage transistor are both high-voltage NMOS transistors.

[0029] In an optional implementation manner, the level conversion circuit further includes at least one of the following:

[0030] A first voltage reduction module, used for turning on or off the first voltage reduction signal determined according to the low-voltage power supply signal under the control of the input signal;

[0031] The second step-down module is used to turn on or off the second step-down signal determined according to the low-voltage power supply signal under the control of the inverted input signal.

[0032] In an optional implementation, the first step-down module includes a third low-voltage transistor, and the second step-down module includes a fourth low-voltage transistor;

[0033] And / or, the third low-voltage transistor used in the first step-down module and the fourth low-voltage transistor used in the second step-down module are both low-voltage PMOS transistors.

[0034] In an optional implementation, the input module includes at least one of the following:

[0035] A first switch circuit, configured to be turned on or off under the control of the input signal, so as to turn on or off the output of the first low-bit signal at the first output end of the input module;

[0036] An inverter and a second switch circuit; the inverter is used to invert the input signal to obtain and output an inverted input signal; the second switch circuit is used to turn on or off under the control of the inverted input signal to open or close the output of the second low-order signal at the second output end of the input module.

[0037] In an optional implementation, the first switch circuit includes a first low-voltage transistor, and the second switch circuit includes a second low-voltage transistor;

[0038] And / or, the first low-voltage transistor used in the first switch circuit and the second low-voltage transistor used in the second switch circuit are both low-voltage NMOS transistors.

[0039] In an optional embodiment, the level conversion circuit also includes a high voltage providing module, which is used to transmit the high voltage power supply signal to the source of the fourth high voltage transistor when the first low-order signal is output at the first output end of the input module based on the control of the first output signal and the second output signal; and transmit the high voltage power supply signal to the source of the third high voltage transistor when the second low-order signal is output at the second output end of the input module.

[0040] In an optional implementation, the high voltage providing module includes at least one of the following: a fifth high voltage transistor; a sixth high voltage transistor; the fifth high voltage transistor is used to provide a high voltage power supply signal to the source of the third high voltage transistor, and the sixth high voltage transistor is used to provide a high voltage power supply signal to the source of the fourth high voltage transistor;

[0041] And / or, the high voltage providing module adopts a fifth high voltage transistor of a high voltage PMOS tube to provide a high voltage power supply signal to the source of the third high voltage transistor; and adopts a sixth high voltage transistor of a high voltage PMOS tube to provide a high voltage power supply signal to the source of the fourth high voltage transistor.

[0042] The beneficial effects of the technical solution provided by the embodiment of the present application include: applying a first voltage-limiting signal to the substrate and source of the third high-voltage transistor respectively to reduce the voltage difference between the substrate and drain of the third high-voltage transistor; and applying a second voltage-limiting signal to the substrate and source of the fourth high-voltage transistor respectively to reduce the voltage difference between the substrate and drain of the fourth high-voltage transistor, thereby avoiding the voltage difference from exceeding the breakdown voltage of the tube, so that the level conversion circuit can work normally when the breakdown voltage of the tube is lower than the circuit use voltage, and can reduce the leakage of the tube, effectively prevent the tube from breaking down, and improve the circuit reliability. And through the input module, the isolation module and the output module, it is realized that under the control of input signals of different level values, the first output signal and the second output signal, which are mutually inverted and determined based on the ground signal and the high-voltage power supply signal, are generated and output, and the high-voltage conversion output is realized.

[0043] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0045] Figure 1 A circuit diagram of a specific example of a level conversion circuit;

[0046] Figure 2 A schematic circuit block diagram of Example 1 of a level conversion circuit provided in an embodiment of the present application;

[0047] Figure 3 A schematic circuit block diagram of Example 2 of a level conversion circuit provided in an embodiment of the present application;

[0048] Figure 4 A circuit diagram of a specific example of a level conversion circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the technical solutions and beneficial effects of the present invention more clearly understandable, the following is a detailed description by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0050] The embodiments of the present application are not exhaustive, but are only illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present application. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, in a certain embodiment, the solution after removing some steps can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementations in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined, for example, some or all of the steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementations of other embodiments.

[0051] In each embodiment of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.

[0052] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0053] In the embodiments of the present application, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.

[0054] In the embodiments of the present application, "plurality" refers to two or more.

[0055] In some embodiments, the terms “at least one”, “one or more”, “a plurality of”, “multiple”, etc. can be used interchangeably.

[0056] The prefixes such as "first" and "second" in the embodiments of the present application are only used to distinguish different description objects, and do not constitute restrictions on the position, order, priority, value or content of the description objects. The statement of the description object refers to the description in the context of the claims or embodiments, and should not constitute unnecessary restrictions due to the use of prefixes. For example, the numerical value of the description object is not limited by the ordinal number, and can be one or more. Take "first device" as an example, where the numerical value of "device" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the description object is "device", the "first device" and the "second device" can be the same device or different devices, and their types can be the same or different.

[0057] In some embodiments, the term "connection" may indicate that an electrical signal or data is transmitted between a connected end and a connected end, and may be understood as "electrical connection", "communication connection", etc. "Connection" may be a direct connection between two components, an indirect connection established through other components, internal communication between two components, or any other possible connection form.

[0058] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not less than", "above", and "exceed" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "no more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.

[0059] In some embodiments, high voltage and low voltage, or high voltage and low voltage, may be relative values ​​and are not limited to absolute values.

[0060] In some embodiments, the high-voltage transistor may have a higher voltage resistance than the low-voltage transistor. For example, the breakdown voltage of the high-voltage transistor may be 12V, and the breakdown voltage may be adjusted by adjusting the process. The high-voltage transistor may be a high-voltage MOSFET (metal oxide semiconductor field effect transistor, MOS tube for short). Similarly, the low-voltage transistor may be a low-voltage MOS tube. MOS tubes may include P-type MOS tubes (PMOS tubes for short) and N-type MOS tubes (NMOS tubes for short).

[0061] In some embodiments, the high-voltage transistor and the low-voltage transistor can both be a single transistor; or they can be multiple transistors connected in series and / or in parallel, and have a gate G, source S, drain D and substrate B corresponding to the gate G, source S, drain D and substrate B of a single transistor, respectively, and also have the same working state as a single transistor, such as an on state and an off state.

[0062] In the process of implementing this application, the inventor found that the related technology has the following problems:

[0063] Figure 1 A circuit diagram of a specific example of a level conversion circuit is shown. As shown in the figure, the level conversion circuit includes an input module, an isolation module, an output module and a high voltage supply module;

[0064] The input module includes an inverter W, a first low-voltage transistor NM1, and a second low-voltage transistor NM2; the input end of the inverter W is connected to the gate of the first low-voltage transistor NM1 and is configured to obtain an input signal IN, and the output end of the inverter W is connected to the gate of the second low-voltage transistor NM2 and is configured to provide an inverted input signal IN_N that is inverted to the input signal IN; the source of the first low-voltage transistor NM1, the substrate of the first low-voltage transistor NM1, the source of the second low-voltage transistor NM2, and the substrate of the second low-voltage transistor NM2 are respectively configured to obtain a ground signal GND;

[0065] The isolation module includes a first high-voltage transistor NH1 and a second high-voltage transistor NH2; the gate of the first high-voltage transistor NH1 and the gate of the second high-voltage transistor NH2 are respectively configured to obtain a low-voltage power supply signal VDD; the source of the first high-voltage transistor NH1 is connected to the drain of the first low-voltage transistor NM1, and the source of the second high-voltage transistor NH2 is connected to the drain of the second low-voltage transistor NM2; the substrate of the first high-voltage transistor NH1 and the substrate of the second high-voltage transistor NH2 are respectively configured to obtain a ground signal GND;

[0066] The output module includes a third high-voltage transistor PH3 and a fourth high-voltage transistor PH4; the gate of the fourth high-voltage transistor PH4 is configured to obtain an inverted input signal IN_N, the drain of the fourth high-voltage transistor PH4 is connected to the drain of the second high-voltage transistor NH2 and is configured to provide a second output signal HVO; the gate of the third high-voltage transistor PH3 is configured to obtain an input signal IN, the drain of the third high-voltage transistor PH3 is connected to the drain of the first high-voltage transistor NH1 and is configured to provide a first output signal HVO_N which is inverted to the second output signal HVO; the substrate of the third high-voltage transistor PH3 and the substrate of the fourth high-voltage transistor PH4 are respectively configured to obtain a high-voltage power supply signal VDDHV;

[0067] The high voltage providing module includes a fifth high voltage transistor PH5 and a sixth high voltage transistor PH6; the gate of the fifth high voltage transistor PH5 is configured to obtain the second output signal HVO, the drain of the fifth high voltage transistor PH5 is connected to the source of the third high voltage transistor PH3, and the source and substrate of the fifth high voltage transistor PH5 are respectively configured to obtain the high voltage power supply signal VDDHV; the gate of the sixth high voltage transistor PH6 is configured to obtain the first output signal HVO_N, the drain of the sixth high voltage transistor PH6 is connected to the source of the fourth high voltage transistor PH4, and the source and substrate of the sixth high voltage transistor PH6 are respectively configured to obtain the high voltage power supply signal VDDHV.

[0068] Exemplarily, the first low voltage transistor NM1 and the second low voltage transistor NM2 are low voltage NMOS transistors, the first high voltage transistor NH1 and the second high voltage transistor NH2 are high voltage NMOS transistors, and the third high voltage transistor PH3, the fourth high voltage transistor PH4, the fifth high voltage transistor PH5 and the sixth high voltage transistor PH6 are high voltage PMOS transistors.

[0069] Table 1

[0070]

[0071] like Figure 1 The level conversion circuit shown can be controlled by an input signal IN of a 0V / 5V voltage domain to generate a second output signal HVO of 0V / 15V as shown in Table 1. The working principle of the level conversion circuit can be referred to as follows:

[0072] When the input signal IN is 5V, the first low voltage transistor NM1 is turned on, and the first high voltage transistor NH1 is turned on, so that the 0V ground signal GND is transmitted to the drain of the first high voltage transistor NH1 through the first low voltage transistor NM1 and the first high voltage transistor NH1 in sequence, and at the same time, the drain voltage of the third high voltage transistor PH3 is also 0V and the first output signal HVO_N of 0V is obtained, and the sixth high voltage transistor PH6 can be controlled to be turned on to provide the 15V high voltage power supply signal VDDHV to the source of the fourth high voltage transistor PH4. At this time, since the inverted input signal IN_N is 0V, the fourth high voltage transistor PH4 is turned on, thereby obtaining the second output signal HVO of 15V.

[0073] However, since the substrate of the third high-voltage transistor PH3 is connected to the high-voltage power supply terminal (i.e., obtaining the 15V high-voltage power supply signal VDDHV), its gate voltage is 5V, which makes it cut off, and its drain voltage is 0V, so that there is a voltage difference Vbd of 15V between its substrate and drain, which is greater than the breakdown voltage of 12V. At this time, the second high-voltage transistor NH2 realizes the isolation between the drain of the fourth high-voltage transistor PH4 and the drain of the second low-voltage transistor NM2; the drain voltage of the second high-voltage transistor NH2 is 15V, and its gate voltage is 5V; and the second low-voltage transistor NM2 is in the cut-off state under the control of the 0V inverting input signal IN_N, so that its drain is in a high-resistance state, and the source of the second high-voltage transistor NH2 does not obtain a 0V ground signal, so that the drain-source voltage Vds of the second high-voltage transistor NH2 is 15V-Vth (threshold voltage), which is approximately equal to 14.2V.

[0074] When the input signal IN is 0V, the inverted input signal IN_N is 5V, the second low voltage transistor NM2 is turned on, and the second high voltage transistor NH2 is turned on, so that the 0V ground signal GND is transmitted to the drain of the second high voltage transistor NH2 via the second low voltage transistor NM2 and the second high voltage transistor NH2 in sequence, and at the same time, the drain voltage of the fourth high voltage transistor PH4 is also 0V and the second output signal HVO of 0V is obtained, and the fifth high voltage transistor PH5 can be controlled to be turned on to provide the 15V high voltage power supply signal VDDHV to the source of the third high voltage transistor PH3. At this time, since the input signal IN is 0V, the third high voltage transistor PH3 is turned on, so as to obtain the first output signal HVO_N of 15V.

[0075] However, since the substrate of the fourth high-voltage transistor PH4 is connected to the high-voltage power supply terminal (i.e., obtaining the 15V high-voltage power supply signal VDDHV), its gate voltage is 5V and is cut off, and its drain voltage is 0V, so that the voltage difference Vbd between its substrate and drain is 15V, which is greater than the breakdown voltage 12V. At this time, the first high-voltage transistor NH1 implements the isolation between the drain of the third high-voltage transistor PH3 and the drain of the first low-voltage transistor NM1; the drain voltage of the first high-voltage transistor NH1 is 15V, and its gate voltage is 5V; and the first low-voltage transistor NM1 is in the cut-off state under the control of the 0V input signal IN, so that its drain is in a high-impedance state, and the source of the first high-voltage transistor NH1 does not obtain the 0V ground signal, so that the drain-source voltage Vds of the first high-voltage transistor NH1 is 15V-Vth (threshold voltage), which is approximately equal to 14.2V.

[0076] Then it can be seen that Figure 1When the level conversion circuit shown in FIG. 1 works normally, the Vbd of one of the third high-voltage transistor PH3 and the fourth high-voltage transistor PH4 is always 15V, which is greater than the breakdown voltage 12V. The Vds of one of the first high-voltage transistor NH1 and the second high-voltage transistor NH2 is always equal to about 14.2V. Therefore, such usage may cause leakage of the tube, affect the circuit function, and even break down the tube after a period of time, causing the chip to fail and fail to work.

[0077] To this end, an embodiment of the present application provides a level conversion circuit. Figure 2 The circuit block diagram of Example 1 of the level conversion circuit provided in the embodiment of the present application is shown. As shown in the figure, the level conversion circuit includes:

[0078] An input module 100, configured to output a first low-bit signal NV_R at a first output terminal of the input module 100 or output a second low-bit signal HV_L at a second output terminal of the input module 100 under the control of an input signal IN; wherein the first low-bit signal NV_R and the second low-bit signal HV_L are respectively determined according to a ground signal GND;

[0079] The isolation module 200 is used for, based on the control of the low-voltage power supply signal VDD, when the first output end of the input module 100 outputs the first low-bit signal NV_R, opening the output of the first output end of the isolation module 200 so that the first output end of the level conversion circuit connected to the first output end of the isolation module 200 outputs the first output signal HVO_N determined according to the first low-bit signal NV_R; and when the second output end of the input module 100 outputs the second low-bit signal HV_L, opening the output of the second output end of the isolation module 200 so that the second output end of the level conversion circuit connected to the second output end of the isolation module 200 outputs the second output signal HVO determined according to the second low-bit signal HV_L;

[0080] The output module 300 includes at least one of the following: a third high-voltage transistor PH3; a fourth high-voltage transistor PH4;

[0081] The output module 300 is used to implement at least one of the following when the first output terminal of the input module 100 outputs the first low-bit signal NV_R:

[0082] The source of the fourth high-voltage transistor PH4 obtains the high-voltage power signal VDDHV, and the fourth high-voltage transistor PH4 is turned on under the control of the inverted input signal IN_N which is inverted with the input signal IN so that the second output terminal of the level conversion circuit connected to the drain of the fourth high-voltage transistor PH4 outputs the second output signal HVO determined according to the high-voltage power signal VDDHV;

[0083] The substrate electrode and the source electrode of the third high-voltage transistor PH3 respectively obtain the first voltage limiting signal PCAS_R to reduce the voltage difference between the substrate electrode and the drain electrode of the third high-voltage transistor PH3;

[0084] When the second output terminal of the input module 100 outputs the second low-bit signal HV_L, at least one of the following is implemented:

[0085] The source of the third high-voltage transistor PH3 obtains the high-voltage power signal VDDHV, and the third high-voltage transistor PH3 is turned on under the control of the input signal IN so that the first output terminal of the level conversion circuit connected to the drain of the third high-voltage transistor PH3 outputs the first output signal HVO_N determined according to the high-voltage power signal VDDHV;

[0086] The substrate electrode and the source electrode of the fourth high-voltage transistor PH4 respectively obtain the second voltage limiting signal PCAS_L to reduce the voltage difference between the substrate electrode and the drain electrode of the fourth high-voltage transistor PH4.

[0087] Thus, the embodiment of the present application applies the first voltage limiting signal to the substrate and source of the third high-voltage transistor respectively to reduce the voltage difference between the substrate and drain of the third high-voltage transistor; and applies the second voltage limiting signal to the substrate and source of the fourth high-voltage transistor respectively to reduce the voltage difference between the substrate and drain of the fourth high-voltage transistor, thereby avoiding the voltage difference from exceeding the breakdown voltage of the tube, so that the level conversion circuit can work normally when the breakdown voltage of the tube is lower than the circuit use voltage, and can reduce the leakage of the tube, effectively prevent the tube from breaking down, and improve the circuit reliability. And through the input module, the isolation module and the output module, it is realized that under the control of the input signal of different level values, the first output signal and the second output signal that are mutually inverted and determined based on the ground signal and the high-voltage power supply signal are generated and output, respectively, to achieve the conversion output of high voltage.

[0088] In the embodiment of the present application, the ground signal GND can be provided by the circuit ground terminal, for example, it can be 0 V. The low voltage power signal VDD can be provided by the circuit low voltage power terminal, for example, it can be 5 V. The high voltage power signal VDDHV can be provided by the circuit high voltage power terminal, for example, it can be 15 V.

[0089] The first low-bit signal NV_R output from the first output terminal of the input module 100 and the second low-bit signal HV_L output from the second output terminal may not overlap, that is, when one is output, the output of the other is turned off, and are respectively determined according to the ground signal GND, and may be derived from the ground signal GND, for example, may be 0V.

[0090] In some possible implementations, the way to realize the controlled output of the first low-bit signal NV_R and the second low-bit signal HV_L in the input module 100 may include at least one of the following: using a controllable switch device, such as a MOS tube, etc.; using a circuit with signal processing capabilities, such as a CPU (Central Processing Unit), a GPU (graphics processing unit), etc., a circuit with instruction reading and running capabilities, a circuit such as an FPGA that realizes certain functions through a fixed or reconfigurable logical relationship of a hardware circuit, etc. The specific circuit structure of the input module 100 can be set according to actual needs.

[0091] The isolation module 200 can achieve isolation between the drain of the third high-voltage transistor PH3 and the first output terminal of the input module 100, so that when the first output terminal of the level conversion circuit outputs the high-level first output signal HVO_N through the third high-voltage transistor PH3, it can avoid being affected by the first output terminal of the input module 100, thereby improving the output stability of the first output signal HVO_N. And it can achieve isolation between the drain of the fourth high-voltage transistor PH4 and the second output terminal of the input module 100, so that when the second output terminal of the level conversion circuit outputs the high-level second output signal HVO through the fourth high-voltage transistor PH4, it can avoid being affected by the second output terminal of the input module 100, thereby improving the output stability of the second output signal HVO.

[0092] The first output signal HVO_N is determined according to the high voltage power signal VDDHV, which may be derived from the high voltage power signal VDDHV, for example, 15 V. The first output signal HVO_N is determined according to the first low bit signal NV_R, which may be derived from the ground signal GND, for example, 0 V.

[0093] The second output signal HVO is determined according to the high voltage power signal VDDHV, which may be derived from the high voltage power signal VDDHV, for example, 15 V. The second output signal HVO is determined according to the second low bit signal NV_L, which may be derived from the ground signal GND, for example, 0 V.

[0094] In some possible implementations, the isolation module 200 may implement the isolation function in at least one of the following ways: using a controllable switch device, such as a MOS tube, etc.; using different logic operations (AND, OR, NOT, etc.) of a gate circuit to directly implement, such as a tri-state gate circuit, etc. The specific circuit structure of the isolation module 200 may be set according to actual needs.

[0095] Exemplarily, the third high-voltage transistor PH3 and the fourth high-voltage transistor PH4 are both high-voltage PMOS transistors.

[0096] The source and substrate of the third high-voltage transistor PH3 are respectively configured to obtain the high-voltage power supply signal VDDHV or the first voltage-limiting signal PCAS_R, the gate of the third high-voltage transistor PH3 is configured to obtain the input signal IN, and the drain of the third high-voltage transistor PH3 is connected to the first output terminal HVO_N of the level conversion circuit;

[0097] The source and substrate of the fourth high-voltage transistor PH4 are respectively configured to obtain the high-voltage power supply signal VDDHV or the second voltage limiting signal PCAS_L, the gate of the fourth high-voltage transistor PH4 is configured to obtain the inverting input signal IN_N, and the drain of the fourth high-voltage transistor PH4 is connected to the second output terminal HVO of the level conversion circuit.

[0098] When the first output terminal of the input module 100 outputs the first low-bit signal NV_R of 0V, the first output terminal of the isolation module 200 can output 0V, so that the drain voltage of the third high-voltage transistor PH3 is also 0V and the first output signal HVO_N of 0V is obtained; at this time, the gate voltage of the third high-voltage transistor PH3 can be 5V to cut off it, and the substrate and source of the third high-voltage transistor PH3 can respectively obtain the first voltage-limiting signal PCAS_R, which changes the Figure 1 The connection of the substrate electrode of the third high-voltage transistor PH3 makes the voltage difference between the substrate electrode and the drain electrode equal to the voltage value of the first voltage limiting signal PCAS_R, which can be less than the breakdown voltage (such as 12V); at the same time, the fourth high-voltage transistor PH4 can be turned on to obtain the second output signal HVO of 15V.

[0099] When the second output terminal of the input module 100 outputs the second low-bit signal NV_L of 0V, the second output terminal of the isolation module 200 can output 0V, so that the drain voltage of the fourth high-voltage transistor PH4 is also 0V and the second output signal HVO of 0V is obtained; at this time, the gate voltage of the fourth high-voltage transistor PH4 can be 5V to cut off, and the substrate and source of the fourth high-voltage transistor PH4 can respectively obtain the second voltage-limiting signal PCAS_L, which changes the Figure 1The connection of the substrate electrode of the fourth high-voltage transistor PH4 makes the voltage difference between the substrate electrode and the drain electrode equal to the voltage value of the second voltage limiting signal PCAS_L, which can be less than the breakdown voltage (such as 12V); at the same time, the third high-voltage transistor PH3 can be turned on to obtain the first output signal HVO_N of 15V.

[0100] In the embodiment of the present application, the voltage values ​​of the first voltage limiting signal PCAS_R and the second voltage limiting signal PCAS_L can be configured according to actual needs. For example, they can be reduced and stabilized as much as possible to achieve a voltage difference between the substrate and the drain of the third high-voltage transistor PH3 and the fourth high-voltage transistor PH4 that is stably much smaller than the breakdown voltage (e.g., 12V).

[0101] Figure 3 The circuit block diagram of Example 2 of the level conversion circuit provided in the embodiment of the present application is shown. As shown in the figure, in an optional implementation, the isolation module 200 includes at least one of the following: a first high-voltage transistor NH1; a second high-voltage transistor NH2;

[0102] The isolation module 200 is used to implement at least one of the following when the first output terminal of the input module 100 outputs the first low-bit signal NV_R:

[0103] The source of the first high-voltage transistor NH1 obtains the first low-bit signal NV_R, and the first high-voltage transistor NH1 is turned on under the control of the low-voltage power supply signal VDD so that the first output terminal of the level conversion circuit connected to the drain of the first high-voltage transistor NH1 outputs the first output signal HVO_N determined according to the first low-bit signal NV_R;

[0104] The source of the second high-voltage transistor NH2 obtains a second voltage reduction signal NCAS_L to reduce the drain-source voltage of the second high-voltage transistor NH2; wherein the second voltage reduction signal NCAS_L is determined according to the low-voltage power supply signal VDD;

[0105] When the second output terminal of the input module 100 outputs the second low-bit signal HV_L, at least one of the following is implemented:

[0106] The source of the second high-voltage transistor NH2 obtains the second low-bit signal HV_L, and the second high-voltage transistor NH2 is turned on under the control of the low-voltage power supply signal VDD so that the second output terminal of the level conversion circuit connected to the drain of the second high-voltage transistor NH2 outputs a second output signal HVO determined according to the second low-bit signal HV_L;

[0107] The source of the first high-voltage transistor NH1 obtains a first voltage reduction signal NCAS_R to reduce the drain-source voltage of the first high-voltage transistor NH1 ; wherein the first voltage reduction signal NCAS_R is determined according to the low-voltage power signal VDD.

[0108] In the embodiment of the present application, the first step-down signal NCAS_R and the second step-down signal NCAS_L are respectively determined according to the low-voltage power supply signal VDD, and may be derived from the low-voltage power supply signal VDD, for example, may be the same as the voltage value of the low-voltage power supply signal VDD (such as 5V), so that there is no voltage difference between the gate voltage and the source voltage of the first high-voltage transistor NH1, thereby ensuring that the first high-voltage transistor NH1 is cut off; and there is no voltage difference between the gate voltage and the source voltage of the second high-voltage transistor NH2, thereby ensuring that the second high-voltage transistor NH2 is cut off.

[0109] Exemplarily, the first high-voltage transistor NH1 and the second high-voltage transistor NH2 are both high-voltage NMOS transistors.

[0110] The drain of the first high-voltage transistor NH1 may be used as the first output terminal of the isolation module 200 , and the drain of the second high-voltage transistor NH2 may be used as the second output terminal of the isolation module 200 .

[0111] The source of the first high-voltage transistor NH1 is configured to obtain the first low-bit signal NV_R or the first step-down signal NCAS_R, the gate of the first high-voltage transistor NH1 is configured to obtain the low-voltage power supply signal VDD, the drain of the first high-voltage transistor NH1 is connected to the second output terminal HVO_N of the level conversion circuit, and the substrate of the first high-voltage transistor NH1 is configured to obtain the ground signal GND;

[0112] The source of the second high-voltage transistor NH2 is configured to obtain the second low-bit signal NV_L or the second step-down signal NCAS_L, the gate of the second high-voltage transistor NH2 is configured to obtain the low-voltage power supply signal VDD, the drain of the second high-voltage transistor NH2 is connected to the first output terminal HVO of the level conversion circuit, and the substrate of the second high-voltage transistor NH2 is configured to obtain the ground signal GND.

[0113] When the first output terminal of the input module 100 outputs the first low-bit signal NV_R of 0V, the source voltage of the first high-voltage transistor NH1 may be 0V, and the gate voltage of the first high-voltage transistor NH1 may be 5V to turn it on, so that the first output signal HVO_N is 0V, so that the fourth high-voltage transistor PH4 can be turned on, so that the drain voltage of the second high-voltage transistor NH2 is 15V; and at this time, the source of the second high-voltage transistor NH2 may be the second step-down signal NCAS_L applied with 5V, and its gate voltage is 5V, so that it is guaranteed to be cut off and the drain-source voltage Vds is 15V-5V=10V, which is lower than Figure 114.2V in.

[0114] When the second output terminal of the input module 100 outputs the second low-bit signal NV_L of 0V, the source voltage of the second high-voltage transistor NH2 may be 0V, and the gate voltage of the second high-voltage transistor NH2 may be 5V to turn it on, so that the second output signal HVO is 0V, so that the third high-voltage transistor PH3 can be turned on, so that the drain voltage of the first high-voltage transistor NH1 is 15V; and at this time, the source of the first high-voltage transistor NH1 may be the first step-down signal NCAS_R applied with 5V, and its gate voltage is 5V, so that it is guaranteed to be cut off and the drain-source voltage Vds is 15V-5V=10V, which is lower than Figure 1 14.2V in.

[0115] In this way, the embodiment of the present application applies a first step-down signal determined according to a low-voltage power supply signal to the source of the first high-voltage transistor to ensure that the first high-voltage transistor is cut off and the drain-source voltage is reduced; and applies a second step-down signal determined according to the low-voltage power supply signal to the source of the second high-voltage transistor to ensure that the second high-voltage transistor is cut off and the drain-source voltage is reduced, thereby further reducing tube leakage, effectively preventing tube breakdown, and improving circuit reliability.

[0116] In the embodiment of the present application, the source of the first high-voltage transistor NH1 may obtain the first low-bit signal NV_R by connecting the source of the first high-voltage transistor NH1 to the first output terminal of the input module 100, and the second high-voltage transistor NH2 may obtain the second low-bit signal NV_L by connecting the source of the second high-voltage transistor NH2 to the second output terminal of the input module 100, but the present invention is not limited thereto. Other circuits may be connected between the source of the first high-voltage transistor NH1 and the first output terminal of the input module 100, or between the source of the second high-voltage transistor NH2 and the second output terminal of the input module 100, so that the first low-bit signal NV_R or the second low-bit signal NV_L may be processed to improve signal quality, perform buffering, etc.

[0117] Figure 4 A circuit diagram of a specific example of a level conversion circuit provided in an embodiment of the present application is shown. As shown in the figure, the level conversion circuit also includes at least one of the following:

[0118] The first voltage limiting module 10 includes a seventh high-voltage transistor NH7, which is used to provide the first voltage limiting signal PCAS_R and is turned on under the control of the low-voltage power supply signal VDD to limit the voltage value of the first voltage limiting signal PCAS_R by using the threshold voltage of the seventh high-voltage transistor NH7;

[0119] The second voltage limiting module 20 includes an eighth high voltage transistor NH8, which is used to provide the second voltage limiting signal PCAS_L and is turned on under the control of the low voltage power signal VDD to limit the voltage value of the second voltage limiting signal PCAS_L using the threshold voltage of the eighth high voltage transistor NH8.

[0120] Exemplarily, the seventh high-voltage transistor NH7 and the eighth high-voltage transistor NH8 are both high-voltage NMOS transistors.

[0121] The gate and drain of the seventh high-voltage transistor NH7 are respectively configured to obtain the low-voltage power supply signal VDD, the substrate of the seventh high-voltage transistor NH7 is configured to obtain the ground signal GND, and the source of the seventh high-voltage transistor NH7 is respectively connected to the source and substrate of the third high-voltage transistor PH3. The seventh high-voltage transistor NH7 is turned on under the control of the low-voltage power supply signal VDD so that the source of the seventh high-voltage transistor NH7 outputs the first voltage limiting signal PCAS_R (for example, 5V-Vth≈4.2V) determined according to the low-voltage power supply signal VDD and the threshold voltage.

[0122] The gate and drain of the eighth high-voltage transistor NH8 are respectively configured to obtain the low-voltage power supply signal VDD, the substrate of the eighth high-voltage transistor NH8 is configured to obtain the ground signal GND, and the source of the eighth high-voltage transistor NH8 is respectively connected to the source and substrate of the fourth high-voltage transistor PH4. The eighth high-voltage transistor NH8 is turned on under the control of the low-voltage power supply signal VDD so that the source of the eighth high-voltage transistor NH8 outputs the second voltage limiting signal PCAS_L (for example, 5V-Vth≈4.2V) determined according to the low-voltage power supply signal VDD and the threshold voltage.

[0123] When the first output terminal of the input module 100 outputs the first low-bit signal NV_R of 0V, the voltage value of the first voltage-limiting signal PCAS_R is 5V-Vth, which is approximately equal to 4.2V, so that the voltage difference between the substrate and the drain of the third high-voltage transistor PH3 is 4.2V. At this time, the voltage value of the second voltage-limiting signal PCAS_L will reach 15V, which is the source voltage of the fourth high-voltage transistor PH4, so the seventh high-voltage transistor NH7 with high voltage resistance is used.

[0124] When the second output terminal of the input module 100 outputs the second low-bit signal NV_L of 0V, the voltage value of the second voltage-limiting signal PCAS_L is 5V-Vth, which is approximately equal to 4.2V, so that the voltage difference between the substrate and the drain of the fourth high-voltage transistor PH4 is 4.2V. At this time, the voltage value of the first voltage-limiting signal PCAS_R will reach 15V, which is the source voltage of the third high-voltage transistor PH3, so the eighth high-voltage transistor NH8 with high voltage resistance is used.

[0125] Thus, the embodiment of the present application changes the connection between the substrate electrodes of the third high-voltage transistor and the fourth high-voltage transistor through the seventh high-voltage transistor NH7 and the eighth high-voltage transistor NH8, thereby reducing the voltage difference between the substrate electrode and the drain electrode of the third high-voltage transistor and the fourth high-voltage transistor (for example, the voltage difference is 4.2V) to be lower than the breakdown voltage, thereby improving the circuit reliability. Furthermore, by adopting the seventh high-voltage transistor NH7 and the eighth high-voltage transistor NH8 that are resistant to high voltage, the source voltage can reach the voltage value of the high-voltage power supply signal, thereby also improving the circuit reliability.

[0126] In an optional implementation manner, the level conversion circuit further includes at least one of the following:

[0127] A first voltage reduction module 30, configured to turn on or off the output of the first voltage reduction signal NCAS_R determined according to the low voltage power supply signal VDD under the control of the input signal IN;

[0128] The second step-down module 40 is used for turning on or off the output of the second step-down signal NCAS_L determined according to the low-voltage power supply signal VDD under the control of the inverted input signal IN_N.

[0129] Exemplarily, the first buck module 30 includes a third low-voltage transistor PM3, and the second buck module 40 includes a fourth low-voltage transistor PM4;

[0130] And / or, the third low-voltage transistor PM3 used in the first step-down module 30 and the fourth low-voltage transistor PM4 used in the second step-down module 40 are both low-voltage PMOS transistors.

[0131] The source and substrate of the third low voltage transistor PM3 are respectively configured to obtain the low voltage power signal VDD, the gate of the third low voltage transistor PM3 is configured to obtain the input signal IN, and the drain of the third low voltage transistor PM3 is connected to the source of the first high voltage transistor NH1.

[0132] The source and substrate of the fourth low voltage transistor PM4 are respectively configured to obtain the low voltage power supply signal VDD, the gate of the fourth low voltage transistor PM4 is configured to obtain the inverted input signal IN_N, and the drain of the fourth low voltage transistor PM4 is connected to the source of the second high voltage transistor NH2.

[0133] When the first output terminal of the input module 100 outputs the first low-bit signal NV_R of 0V, the fourth low-voltage transistor PM4 is turned on, and its drain outputs the second step-down signal NCAS_L of 5V to the source of the second high-voltage transistor NH2, so as to ensure that the second high-voltage transistor NH2 is cut off and reduce its drain-source voltage.

[0134] When the second output terminal of the input module 100 outputs the second low-bit signal NV_L of 0V, the third low-voltage transistor PM3 is turned on, and its drain outputs the first step-down signal NCAS_R of 5V to the source of the first high-voltage transistor NH1, so as to ensure that the first high-voltage transistor NH1 is cut off and reduce its drain-source voltage.

[0135] In this way, the embodiment of the present application reduces the drain-source voltage of the first high-voltage transistor NH1 and the second high-voltage transistor NH2 through the third low-voltage transistor PM3 and the fourth low-voltage transistor PM4, thereby improving circuit reliability.

[0136] In some possible implementations, the third low-voltage transistor PM3 and the fourth low-voltage transistor PM4 are not limited to low-voltage PMOS transistors, and other controllable switching circuits may also be used to achieve controllable output of the voltage value of the low-voltage power supply signal, such as gate circuits.

[0137] In an optional implementation, the input module 100 includes at least one of the following:

[0138] A first switch circuit, configured to be turned on or off under the control of the input signal IN, so as to turn on or off the output of the first low-bit signal NV_R at the first output terminal of the input module 100;

[0139] Inverter W and a second switch circuit; the inverter W is used to invert the input signal IN to obtain and output an inverted input signal IN_N; the second switch circuit is used to be turned on or off under the control of the inverted input signal IN_N to open or close the output of the second low-bit signal NV_L at the second output end of the input module 100.

[0140] Exemplarily, the first switch circuit includes a first low-voltage transistor NM1, and the second switch circuit includes a second low-voltage transistor NM2;

[0141] And / or, the first low-voltage transistor NM1 used in the first switch circuit and the second low-voltage transistor NM2 used in the second switch circuit are both low-voltage NMOS transistors;

[0142] The gate of the first low voltage transistor NM1 is configured to obtain the input signal IN, the source and substrate of the first low voltage transistor NM1 are respectively configured to obtain the ground signal GND, and the drain of the first low voltage transistor NM1 serves as the first output terminal of the input module 100;

[0143] The gate of the second low voltage transistor NM2 is configured to obtain the inverted input signal IN_N, the source and substrate of the second low voltage transistor NM2 are respectively configured to obtain the ground signal GND, and the drain of the second low voltage transistor NM2 serves as the second output terminal of the input module 100 .

[0144] When the input signal IN is 5V, the control input module 100 is in the first working state, the inverted output signal IN_N is 0V, the first low-voltage transistor NM1 is turned on to turn on the output of the 0V first low-bit signal NV_R at the first output terminal of the input module 100, and the second low-voltage transistor NM2 is turned off to turn off the output of the 0V second low-bit signal NV_L at the second output terminal of the input module 100.

[0145] When the input signal IN is 0V, the control input module 100 is in the second working state, the inverted output signal IN_N is 5V, the first low-voltage transistor NM1 is turned off to turn off the output of the 0V first low-bit signal NV_R at the first output terminal of the input module 100, and the second low-voltage transistor NM2 is turned on to turn on the output of the 0V second low-bit signal NV_L at the second output terminal of the input module 100.

[0146] In this way, the switching of the working state of the input module 100 based on the control of the input signal IN is achieved, and one of the first low-bit signal NV_R and the second low-bit signal NV_L is turned off during the period when the output of the other is turned on.

[0147] In some possible implementations, the first low voltage transistor NM1 and the second low voltage transistor NM2 are not limited to low voltage NMOS transistors, and other controllable switch circuits may be used to achieve controllable output of the voltage value of the ground signal, such as a gate circuit.

[0148] In an optional embodiment, the level conversion circuit also includes a high voltage providing module 400, which is used to transmit the high voltage power supply signal VDDHV to the source of the fourth high voltage transistor PH4 when the first output terminal of the input module 100 outputs the first low signal NV_R based on the control of the first output signal HVO_N and the second output signal HVO; and transmit the high voltage power supply signal VDDHV to the source of the third high voltage transistor PH3 when the second output terminal of the input module 100 outputs the second low signal NV_L.

[0149] Exemplarily, the high voltage providing module 400 includes at least one of the following: a fifth high voltage transistor PH5; a sixth high voltage transistor PH6; the fifth high voltage transistor PH5 is used to provide a high voltage power supply signal VDDHV to the source of the third high voltage transistor PH3, and the sixth high voltage transistor PH6 is used to provide a high voltage power supply signal VDDHV to the source of the fourth high voltage transistor PH4;

[0150] And / or, the high voltage providing module 400 adopts a fifth high voltage transistor PH5 of a high voltage PMOS tube to provide a high voltage power supply signal VDDHV to the source of the third high voltage transistor PH3; and adopts a sixth high voltage transistor PH6 of a high voltage PMOS tube to provide a high voltage power supply signal VDDHV to the source of the fourth high voltage transistor PH4.

[0151] The source and substrate of the fifth high-voltage transistor PH5 are respectively configured to obtain the high-voltage power supply signal VDDHV, the gate of the fifth high-voltage transistor PH5 is configured to obtain the second output signal HVO, and the drain of the fifth high-voltage transistor PH5 is connected to the source of the third high-voltage transistor PH3;

[0152] The source and substrate of the sixth high-voltage transistor PH6 are respectively configured to obtain the high-voltage power supply signal VDDHV, the gate of the sixth high-voltage transistor PH6 is configured to obtain the first output signal HVO_N, and the drain of the sixth high-voltage transistor PH6 is connected to the source of the fourth high-voltage transistor PH4.

[0153] When the second output signal HVO is 0V, the first output signal HVO_N is 15V, the sixth high-voltage transistor PH6 is turned on to make the source voltage of the fourth high-voltage transistor PH4 15V, and the fifth high-voltage transistor PH5 is turned off.

[0154] When the first output signal HVO_N is 0V, the second output signal HVO is 15V, the fifth high-voltage transistor PH5 is turned on to make the source voltage of the third high-voltage transistor PH3 15V, and the sixth high-voltage transistor PH6 is turned off.

[0155] In this way, control based on the first output signal HVO_N and the second output signal HVO is implemented, and one of the high voltage power signal VDDHV provided to the source of the third high voltage transistor PH3 and the high voltage power signal VDDHV provided to the source of the fourth high voltage transistor PH4 is turned off during the output opening period of the other.

[0156] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A level conversion circuit, characterized in that: The level conversion circuit comprises: An input module, used for outputting a first low-bit signal at a first output terminal of the input module or a second low-bit signal at a second output terminal of the input module under the control of an input signal; wherein the first low-bit signal and the second low-bit signal are respectively determined according to a ground signal; The isolation module is used for, based on the control of the low-voltage power supply signal, when the first output end of the input module outputs the first low-bit signal, turning on the output of the first output end of the isolation module so that the first output end of the level conversion circuit connected to the first output end of the isolation module outputs the first output signal determined according to the first low-bit signal; when the second output end of the input module outputs the second low-bit signal, turning on the output of the second output end of the isolation module so that the second output end of the level conversion circuit connected to the second output end of the isolation module outputs the second output signal determined according to the second low-bit signal; The output module comprises at least one of the following: a third high-voltage transistor; a fourth high-voltage transistor; Wherein, the output module is used to implement at least one of the following when the first low-bit signal is output at the first output end of the input module: The source of the fourth high-voltage transistor obtains a high-voltage power signal, and the fourth high-voltage transistor is turned on under the control of an inverted input signal that is inverted with respect to the input signal so that the second output terminal of the level conversion circuit connected to the drain of the fourth high-voltage transistor outputs a second output signal determined according to the high-voltage power signal; The substrate electrode and the source electrode of the third high-voltage transistor respectively obtain the first voltage limiting signal to reduce the voltage difference between the substrate electrode and the drain electrode of the third high-voltage transistor; In a case where the second output terminal of the input module outputs the second low-bit signal, at least one of the following is implemented: The source of the third high-voltage transistor obtains a high-voltage power signal, and the third high-voltage transistor is turned on under the control of the input signal so that the first output terminal of the level conversion circuit connected to the drain of the third high-voltage transistor outputs a first output signal determined according to the high-voltage power signal; The substrate electrode and the source electrode of the fourth high-voltage transistor respectively obtain the second voltage limiting signal to reduce the voltage difference between the substrate electrode and the drain electrode of the fourth high-voltage transistor.

2. The level conversion circuit according to claim 1, characterized in that: The isolation module includes at least one of the following: a first high-voltage transistor; a second high-voltage transistor; Wherein, the isolation module is used to implement at least one of the following when the first output terminal of the input module outputs the first low-bit signal: The source of the first high-voltage transistor obtains the first low-bit signal, and the first high-voltage transistor is turned on under the control of the low-voltage power supply signal so that the first output end of the level conversion circuit connected to the drain of the first high-voltage transistor outputs a first output signal determined according to the first low-bit signal; The source of the second high-voltage transistor obtains a second voltage reduction signal to reduce the drain-source voltage of the second high-voltage transistor; wherein the second voltage reduction signal is determined according to the low-voltage power supply signal; In a case where the second output terminal of the input module outputs the second low-bit signal, at least one of the following is implemented: The source of the second high-voltage transistor obtains the second low-bit signal, and the second high-voltage transistor is turned on under the control of the low-voltage power supply signal so that the second output terminal of the level conversion circuit connected to the drain of the second high-voltage transistor outputs a second output signal determined according to the second low-bit signal; The source of the first high-voltage transistor obtains a first voltage reduction signal to reduce the drain-source voltage of the first high-voltage transistor; wherein the first voltage reduction signal is determined according to the low-voltage power supply signal.

3. The level conversion circuit according to claim 1, characterized in that: The third high-voltage transistor and the fourth high-voltage transistor are both high-voltage PMOS transistors.

4. The level conversion circuit according to claim 2, characterized in that: The first high-voltage transistor and the second high-voltage transistor are both high-voltage NMOS transistors.

5. The level conversion circuit according to claim 1, characterized in that: The level conversion circuit further includes at least one of the following: A first voltage limiting module, comprising a seventh high-voltage transistor, configured to provide the first voltage limiting signal, and to be turned on under the control of a low-voltage power supply signal to limit a voltage value of the first voltage limiting signal by utilizing a threshold voltage of the seventh high-voltage transistor; The second voltage limiting module includes an eighth high-voltage transistor, which is used to provide the second voltage limiting signal and is turned on under the control of the low-voltage power supply signal to limit the voltage value of the second voltage limiting signal using the threshold voltage of the eighth high-voltage transistor.

6. The level conversion circuit according to claim 5, characterized in that: The seventh high-voltage transistor and the eighth high-voltage transistor are both high-voltage NMOS transistors.

7. The level conversion circuit according to claim 2, characterized in that: The level conversion circuit further includes at least one of the following: A first voltage reduction module, used for turning on or off the output of the first voltage reduction signal determined according to the low-voltage power supply signal under the control of the input signal; The second step-down module is used to open or close the output of the second step-down signal determined according to the low-voltage power supply signal under the control of the inverted input signal.

8. The level conversion circuit according to claim 7, characterized in that: The first step-down module includes a third low-voltage transistor, and the second step-down module includes a fourth low-voltage transistor; And / or, the third low-voltage transistor used in the first step-down module and the fourth low-voltage transistor used in the second step-down module are both low-voltage PMOS transistors.

9. The level conversion circuit according to claim 1, characterized in that: The input module includes at least one of the following: A first switch circuit, configured to be turned on or off under the control of the input signal, so as to turn on or off the output of the first low-bit signal at the first output end of the input module; An inverter and a second switching circuit; The inverter is used to invert the input signal to obtain and output an inverted input signal; The second switch circuit is used to be turned on or off under the control of the inverted input signal to open or close the output of the second low-bit signal at the second output end of the input module.

10. The level conversion circuit according to claim 9, characterized in that: The first switch circuit includes a first low voltage transistor, and the second switch circuit includes a second low voltage transistor; And / or, the first low-voltage transistor used in the first switch circuit and the second low-voltage transistor used in the second switch circuit are both low-voltage NMOS transistors.

11. The level conversion circuit according to any one of claims 1 to 10, characterized in that: The level conversion circuit further includes a high voltage providing module, which is used to transmit a high voltage power supply signal to a source of a fourth high voltage transistor when the first output terminal of the input module outputs the first low-bit signal based on the control of the first output signal and the second output signal; In a case where the second output terminal of the input module outputs the second low-bit signal, the high-voltage power supply signal is transmitted to the source of the third high-voltage transistor.

12. The level conversion circuit according to claim 11, characterized in that: The high voltage providing module includes at least one of the following: a fifth high voltage transistor; a sixth high voltage transistor; the fifth high voltage transistor is used to provide a high voltage power supply signal to the source of the third high voltage transistor, and the sixth high voltage transistor is used to provide a high voltage power supply signal to the source of the fourth high voltage transistor; And / or, the high voltage providing module adopts a fifth high voltage transistor of a high voltage PMOS tube to provide a high voltage power supply signal to the source of the third high voltage transistor; and adopts a sixth high voltage transistor of a high voltage PMOS tube to provide a high voltage power supply signal to the source of the fourth high voltage transistor.

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