Method and system for adaptive memory error detection and correction

Abstract

It is possible to monitor the error detection and correction (EDAC) logic of a memory subsystem for error correction, where the EDAC logic is configured to use a first EDAC level. It is possible to determine the number of error corrections performed by the EDAC logic when using the first EDAC level during a time interval. When the number of error corrections using the first EDAC level during the time interval exceeds a threshold, the EDAC logic can switch from using the first EDAC level to using a second EDAC level.

Description

[0001] Description of Related Art

[0002] A computing device may include multiple subsystems, cores, or other components. Such a computing device can be, for example, a portable computing device (″PCD″), such as a laptop or palmtop computer, a cellular phone or smartphone, a portable digital assistant, a portable game console, etc. The multiple subsystems, cores, or other components of the computing device may be included within the same integrated circuit chip or in different chips. A ″system-on-a-chip″ or ″SoC″ is an example of such a chip that integrates numerous components to provide system-level functionality. For example, an SoC may include one or more types of processors, such as a central processing unit (″CPU″), a graphics processing unit (″GPU″), a digital signal processor (″DSP″), and a neural processing unit (″NPU″). The SoC may include other processing subsystems, such as a transceiver or ″modem″ subsystem that provides wireless connectivity, a memory subsystem, etc.

[0003] The reliability of data communication and storage may be adversely affected by environmental influences. Data stored in memory may be damaged by environmental conditions such as radiation, cosmic rays, high temperature, etc. The development of high-reliability, safety-critical computing systems (such as automotive control systems) may require more reliable data storage.

[0004] Error detection and correction (″EDAC″) techniques have been used in memory systems to improve reliability. Error detection involves detecting errors and providing notification of the occurrence of errors, while error correction involves transforming error data into corrected data. It is desirable to provide a more robust but efficient use of EDAC in safety-critical and other computing systems. Summary of the Invention

[0005] Systems, methods, computer-readable media, and other examples for adaptive memory error detection and correction (EDAC) in a computing device are disclosed.

[0006] An exemplary method for adaptive memory EDAC may include monitoring the EDAC logic of a memory subsystem for error correction, where the EDAC logic is configured to use a first EDAC level. The method may further include determining the number of error corrections using the first EDAC level during a time interval. The method may further include determining whether the number of error corrections using the first EDAC level during the time interval exceeds a first threshold. The method may further include switching the EDAC logic from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the time interval exceeds the first threshold.

[0007] An exemplary system for adaptive memory EDAC may include EDAC logic and EDAC level control logic in a memory subsystem. The EDAC level control logic may be configured to monitor the EDAC logic for error correction, where the EDAC logic is configured to use a first EDAC level. The EDAC level control logic may be further configured to determine a number of error corrections using the first EDAC level during a time interval. The EDAC level control logic may also be configured to determine whether the number of error corrections using the first EDAC level during the time interval exceeds a first threshold. The EDAC level control logic may also be further configured to switch the EDAC logic from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the time interval exceeds the first threshold.

[0008] An exemplary system for adaptive memory EDAC may include means for monitoring EDAC logic of a memory subsystem for error correction, where the EDAC logic is configured to use a first EDAC level. The system may also include means for determining a number of error corrections using the first EDAC level during a time interval. The system may also include means for determining whether the number of error corrections using the first EDAC level during the time interval exceeds a first threshold. The system may also include means for switching the EDAC logic from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the time interval exceeds the first threshold.

[0009] An exemplary computer-readable medium for adaptive memory EDAC may include a non-transitory computer-readable medium having instructions stored thereon in computer-executable form. The instructions, when executed by a processing system of a computing device, may configure the processing system to control monitoring of EDAC logic of a memory subsystem for error correction, where the EDAC logic is configured to use a first EDAC level. The instructions may further configure the processing system to control determination of a number of error corrections using the first EDAC level during a time interval. The instructions may also configure the processing system to control determination of whether the number of error corrections using the first EDAC level during the time interval exceeds a first threshold. The instructions may also further configure the processing system to control switching of the EDAC logic from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the time interval exceeds the first threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, unless otherwise specified, like reference numerals refer to like components throughout the views. For reference numerals with alphabetic character names, such as "102A" or "102B", the alphabetic character name can distinguish two like components or elements in the same figure. When it is intended that a reference numeral covers all components with the same reference numeral in all figures, the alphabetic character name of the reference numeral can be omitted.

[0011] Figure 1 is a block diagram of a system for adaptive memory error detection and correction (EDAC) according to an exemplary embodiment.

[0012] Figure 2 is a flowchart illustrating a method for adaptive memory EDAC according to an exemplary embodiment.

[0013] Figure 3 is a flowchart illustrating a method for adaptive memory EDAC according to an exemplary embodiment.

[0014] Figure 4A is a flowchart illustrating a method for adaptive memory EDAC according to an exemplary embodiment.

[0015] Figure 4B is Figure 4A a continuation of the flowchart.

[0016] Figure 5A is a flowchart illustrating another method for adaptive memory EDAC according to an exemplary embodiment.

[0017] Figure 5B is Figure 5A a continuation of the flowchart.

[0018] Figure 6 is a block diagram of a vehicle computing system according to an exemplary embodiment. Detailed Description

[0019] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration". The word "illustrative" may be used synonymously with "exemplary" herein. Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or having an advantage over other aspects.

[0020] In general, error detection and correction (″EDAC″) techniques apply a hash function or algorithm to original (i.e., correct) data to produce a result that includes a certain number of bits. Various types of EDAC algorithms are known. Depending on the type of algorithm, the resulting bits may be referred to as parity bits, checksum bits, cyclic redundancy check (″CRC″) bits, error correction code (″ECC″), syndrome bits, or another term, but may be generically referred to as tags in this disclosure. When a data word is stored in memory, the computed tag corresponding to the data word is stored in memory in association with the data word. When the data word and the associated tag are later read from memory, another algorithm can then use the tag as an additional input to detect, correct, or detect and correct errors in the data word. The number of bits that can be detected or corrected depends on the algorithm. An EDAC algorithm that can detect up to two error bits and correct up to one error bit may be referred to as single error correction / double error detection (″SECDED″). An EDAC algorithm that can detect up to three error bits and correct up to two error bits may be referred to as double error correction / triple error detection (″DECTED″). An EDAC algorithm that can detect up to four error bits and correct up to three error bits may be referred to as triple error correction / quadruple error detection (″TECQED″).

[0021] The length of the tag and the complexity of the EDAC algorithm can be directly related to the number of error bits that can be detected and corrected. For example, for a 256-bit data word, a 10-bit tag may be necessary to perform SECDED, and a 28-bit tag may be used to perform TECQED. A 10-bit tag may require two bytes of storage space (with the remaining six bits filled with zeros), while a 28-bit tag may require four bytes of storage space (with the remaining four bits filled with zeros). To save storage space, maintain high memory system performance, or provide other performance advantages, it may not be desirable to use a more robust EDAC algorithm or a longer tag than necessary to detect and correct errors that may occur. The solution described below involves switching from a less robust or lower-level EDAC (e.g., SECDED) to a more robust or higher-level EDAC (e.g., DECTED or TECQED) when the number of errors exceeds a threshold. The solution described herein can be provided in a safety-critical computing system or any other computing system.

[0022] As Figure 1 shown, in an illustrative or exemplary embodiment, a memory system 100 may include a memory controller 102 and a memory 104. The memory system 100 may be included in any type of computing device or system ( Figure 1 not shown). The memory 104 can be of any type, such as dynamic random access memory (″DRAM″) or static RAM (″SRAM″). For clarity, the memory 104 is shown in Figure 1depicted as a single element in the figure, but may include any number of subunits, modules, chips, arrays, etc. In an example, the memory 104 may include a double data rate synchronous DRAM or "DDR-SDRAM", sometimes referred to as "DDR" for brevity. Although not shown in Figure 1 for clarity, the memory system 100 may be coupled (e.g., via one or more buses or other data interconnects) to one or more processing systems of the computing device ( Figure 1 not shown in

[0023] The memory controller 102 may include logic that configures the memory controller 102 to perform various functions related to storing data in the memory 104 (also referred to as writing data to the memory 104) and retrieving data from the memory 104 (also referred to as reading data from the memory 104). The memory controller 102 may perform such writing and reading of data in response to write and read requests received from the processing system. Since the manner in which the memory controller 102 controls the writing and reading of data is well known to those of ordinary skill in the art, such aspects are not described herein. However, it can be understood that the memory controller 102 may include memory control logic 106 that configures the memory controller 102 to perform such conventional writing, reading, and other functions. The memory controller 102 may also include EDAC logic 108 that configures the memory controller 102 to detect and correct errors in data read from the memory 104 and otherwise operate in the manner described below.

[0024] The memory controller 102 may receive a data word 110 from the processing system or other source associated with the write request. In response to the write request, the EDAC logic 108 may apply an EDAC algorithm to the data word 110 to be written to the memory 104. The tag 112 is the result of the EDAC algorithm (computation). The memory controller 102 may then cause the data word 110 to be stored in the memory 104 and also cause the computed tag 112 to be stored in the memory 104 in association with the data word 110, as Figure 1 shown. Although only one exemplary data word 110 and associated tag 112 are shown in Figure 1 for clarity, the memory 104 may be sized and otherwise configured to store any number of data words 110 and associated tags 112, as understood by those of ordinary skill in the art.

[0025] When the memory controller 102 later reads the data word 110 and the associated tag 112 from the memory 104 in response to a read request, the EDAC logic 108 can apply an EDAC algorithm to the data word 110 and the tag 112 to produce a result. The result can be no error detected or an error detected. No error means that all bits of the data word 110 read from the memory 104 match the corresponding bits of the original data word 110 written to the memory 104. In contrast, an error result means that one or more bits of the data word 110 read from the memory 104 do not match the corresponding bits of the original data word 110 written to the memory 104. The EDAC logic 108 can be configured to operate according to multiple selectable EDAC levels. Depending on which EDAC level in the selected EDAC levels is chosen and the severity of the error (i.e., the number of error bits in the data word 110), the EDAC logic 108 can detect an error or correct an error.

[0026] For example, a first EDAC level can be SECDED, which can detect up to two error bits and correct up to one error bit. A second EDAC level can be TECQED, which can detect up to four error bits and correct up to three error bits. Although in the examples of operations described below, the EDAC logic 108 is configured to operate in a selected EDAC level among two EDAC levels, in other examples, such EDAC logic can be configured to operate in a selected EDAC level among more than two EDAC levels. In such other examples, another selectable mode or EDAC level can be DECTED, which can detect up to three error bits and correct up to two error bits. Since SECDED, DECTED, TECQED, and other EDAC algorithms are well known to those of ordinary skill in the art, they are not described herein.

[0027] The EDAC level controller 114 can select an EDAC level. The EDAC logic 108 can be configured to receive a selection indication from the EDAC level controller 114, which indicates which EDAC level among two or more EDAC levels is selected, and thus indicates which of two or more corresponding EDAC algorithms the EDAC logic 108 is to apply when data is written to or read from the memory 104. Although not shown for clarity, the memory controller 102 can be similarly configured with other logic (not shown) to perform various conventional memory controller functions in addition to the functions specifically described herein. The memory control logic 106, the EDAC logic 108, the EDAC level controller 114, and any other logic of the configurable memory controller 102 can include hardware (e.g., a finite state machine), software (including firmware), or any combination of hardware and software.

[0028] As Figure 2 shown, a method 200 for adaptive memory error detection and correction may include the following. As indicated by block 202, the method 200 may include initializing the EDAC logic of a memory system or subsystem to use a first EDAC level (such as SECDED). As indicated by block 204, the method 200 may further include monitoring the EDAC logic for error correction, where the EDAC logic is configured to use the first EDAC level. For example, the number of error corrections performed by the EDAC logic during a periodic time interval may be counted. The time interval may be, for example, a few milliseconds. As indicated by block 206, the method 200 may further include determining whether the number of error corrections performed by the EDAC logic during the time interval is greater than a first threshold. If it is determined that the number of error corrections performed by the EDAC logic during the time interval is not greater than the first threshold, the method 200 may continue as described above with respect to block 204, where the EDAC logic is continued to be monitored (i.e., within the next time interval). As indicated by block 208, if it is determined that the number of error corrections performed by the EDAC logic during the time interval is greater than the first threshold, the EDAC logic may be switched from using the first EDAC level to using a second EDAC level (such as TECQED). The steps or actions described above with respect to blocks 202 - 208 may be performed or controlled by, for example, the aforementioned EDAC level controller 114( Figure 1 ). Although not shown for clarity in Figure 2 , this method may further include switching the EDAC logic back from the second EDAC level to the first EDAC level based on an additional condition (such as the number of errors dropping below a threshold).

[0029] As Figure 3As shown, method 300 for adaptive memory error detection and correction may include the following. As indicated by block 302, method 300 may include initializing the EDAC logic of a memory system or subsystem to use SECDED and thus correct up to 1-bit errors. As indicated by block 304, method 300 may further include monitoring the EDAC logic for 1-bit error correction, including determining the number of 1-bit error corrections within a first time interval. As indicated by block 306, method 300 may further include determining whether the number of 1-bit error corrections performed by the EDAC logic during the first time interval is greater than a first threshold. If it is determined that the number of error corrections performed by the EDAC logic during the first time interval is not greater than the first threshold, method 300 may continue as described above with respect to block 304, where the EDAC logic is continuously monitored for 1-bit error correction. As indicated by block 308, if it is determined that the number of 1-bit error corrections performed by the EDAC logic during the first time interval is greater than the first threshold, the EDAC logic may switch from using SECDED to using TECQED and thus correct up to 3-bit errors.

[0030] As indicated by block 310, method 300 may then (i.e., after switching from SECDED to TECQED) include monitoring the EDAC logic to detect 1-bit, 2-bit, and 3-bit errors, including determining the number of 1-bit, 2-bit, and 3-bit errors detected within a second time interval. As indicated by block 312, method 300 may further include determining whether the number of 1-bit errors detected during the second time interval is greater than a second threshold, or whether the number of 2-bit errors detected during the second time interval is greater than a third threshold, or whether the number of 3-bit errors detected during the second time interval is greater than a fourth threshold. If it is determined that the number of 1-bit errors detected during the second time interval is greater than the second threshold, or the number of 2-bit errors detected during the second time interval is greater than the third threshold, or the number of 3-bit errors detected during the second time interval is greater than the fourth threshold, method 300 may continue as described above with respect to block 310, where the EDAC logic is continuously monitored for 1-bit error detection, 2-bit error detection, and 3-bit error detection. For example, the third threshold may be zero. That is, if the number of 2-bit errors detected is greater than zero, method 300 may continue at block 310. For example, the fourth threshold may be zero. That is, if the number of 3-bit errors detected is greater than zero, method 300 may continue at block 310. In general, the third threshold and the fourth threshold may each be lower than the first threshold.

[0031] If it is determined (block 312) that the number of 1-bit errors detected during a second time interval is not greater than a second threshold, and the number of 2-bit errors detected during the second time interval is not greater than a third threshold, and the number of 3-bit errors detected during the second time interval is not greater than a fourth threshold, then the EDAC logic can switch back from using TECQED to using SECDED, as indicated by block 314. To prevent toggling back and forth, a hysteresis form can be provided. If the conditions indicated in block 312 are met for a time interval longer than the conditions indicated in block 306, then a decision to switch back from TECQED to SECDED can be made (block 312). That is, the second time interval (block 310) can be longer than the first time interval (block 304). Additionally, the threshold for switching from TECQED to SECDED (i.e., the second threshold of block 312) can be lower than the threshold for switching from SECDED to TECQED (i.e., the first threshold of block 306), or it can even be made zero. Method 300 can then continue as described above with respect to block 304, where the EDAC logic is again monitored for 1-bit error correction.

[0032] As Figures 4A to 4B shown, a method 400 for adaptive memory error detection and correction can include the following. As indicated by block 402, method 400 can include initializing the EDAC logic of a memory system or subsystem to use SECDED and thus correct up to 1-bit errors. As indicated by block 404, method 400 can also include monitoring the EDAC logic for 1-bit error correction, including determining the number of 1-bit error corrections within a first time interval. As indicated by block 406, method 400 can also include determining whether the number of 1-bit error corrections made by the EDAC logic during the first time interval is greater than a first threshold. If it is determined that the number of error corrections made by the EDAC logic during the first time interval is not greater than the first threshold, then method 400 can continue as described above with respect to block 404, where the EDAC logic is continued to be monitored for 1-bit error correction.

[0033] As indicated by block 408, if it is determined that the number of 1-bit error corrections made by the EDAC logic during the first time interval is greater than the first threshold, then a warning can be issued to an operator or user. For example, an operator of a vehicle in which the computing system controls driving or other safety-critical functions can be warned to slow down or stop the vehicle in an attempt to reduce reliance on the computing system.

[0034] As indicated by block 410, a reboot may then be performed. The reboot may include the memory system. In some examples, the reboot may include other systems or subsystems in addition to the memory system, if such a reboot of the other such systems or subsystems is necessary to return them to a state where they can continue to interoperate with the memory system. In some examples, the reboot may include the entire SoC. After this reboot, the EDAC logic may switch from using SECDED to using TECQED and thus correct up to 3-bit errors, as indicated by block 412. Although not shown in method 400, the computing system and its memory system may return to their normal operating mode (e.g., controlling a vehicle) after the EDAC logic is switched to TECQED. Switching to TECQED may provide additional protection against reading incorrect data from the memory and adversely affecting the operation of the computing system. Similarly, although not shown in method 400, after switching to TECQED, the operator may be informed that it is safe to resume operation of the vehicle.

[0035] As indicated by block 414, method 400 may then (i.e., after switching from SECDED to TECQED) include monitoring the EDAC logic to detect 1-bit errors, 2-bit errors, and 3-bit errors, including determining the number of 1-bit errors, 2-bit errors, and 3-bit errors detected within a second time interval. As indicated by block 416, method 400 may further include determining whether the number of 1-bit errors detected during the second time interval is greater than a second threshold, or whether the number of 2-bit errors detected during the second time interval is greater than a third threshold, or whether the number of 3-bit errors detected during the second time interval is greater than a fourth threshold. The first threshold, second threshold, third threshold, and fourth threshold may be as described above with respect to blocks 306 and 312( Figure 3 )). If it is determined (block 414) that the number of 1-bit errors detected during the second time interval is greater than the second threshold, or that the number of 2-bit errors detected during the second time interval is greater than the third threshold, or that the number of 3-bit errors detected during the second time interval is greater than the fourth threshold, then method 400 may continue as described above with respect to block 414, where the EDAC logic is continued to be monitored for 1-bit error detection, 2-bit error detection, and 3-bit error detection.

[0036] If it is determined (block 414) that the number of 1-bit errors detected during the second time interval is not greater than the second threshold, and that the number of 2-bit errors detected during the second time interval is not greater than the third threshold, and that the number of 3-bit errors detected during the second time interval is not greater than the fourth threshold, then another warning similar to the above warning may be issued to the operator or user, as indicated by block 418( Figure 4B)as indicated. As indicated by block 420, a reboot similar to the above reboot (block 410) may be performed. After this reboot, the EDAC logic may switch back from using TECQED to using SECDED, as indicated by block 422. To prevent back-and-forth switching, if the condition indicated in block 416 is satisfied for a time interval longer than the condition indicated in block 406, a decision to switch back from TECQED to SECDED may be made (block 416). That is, the second time interval (i.e., the block 414 time interval) may be longer than the first time interval (i.e., the block 404 time interval). Additionally, the threshold for switching from TECQED to SECDED (i.e., the block 416 second threshold) may be lower than the threshold for switching from SECDED to TECQED (i.e., the block 406 first threshold), or it may even be made zero. Method 400 may then continue as described above with respect to block 404( Figure 4A )wherein the EDAC logic is again monitored for 1-bit error correction.

[0037] As Figures 5A to 5B shown, a method 500 for adaptive memory error detection and correction may include the following. As indicated by block 502, method 500 may include initializing the EDAC logic of a memory system or subsystem to use SECDED and thus correct up to 1-bit errors. As indicated by block 504, method 500 may also include monitoring the EDAC logic for 1-bit error correction, including determining the number of 1-bit error corrections within a first time interval. As indicated by block 506, method 500 may also include determining whether the number of 1-bit error corrections performed by the EDAC logic during the first time interval is greater than a first threshold. If it is determined that the number of error corrections performed by the EDAC logic during the first time interval is not greater than the first threshold, method 500 may continue as described above with respect to block 504, wherein the EDAC logic is continued to be monitored for 1-bit error correction.

[0038] If it is determined that the number of 1-bit error corrections performed by the EDAC logic during the first time interval is greater than the first threshold, a sub-method that may be referred to as a memory "erase" may be performed. Memory erase refers to pausing the operation of the memory system and attempting to correct errors in the data stored in the memory (or a portion thereof) during the resulting memory downtime. During the memory downtime, the memory controller may not authorize write or read requests from the processor.

[0039] As indicated by block 508, the memory system downtime can be initiated. Then, during the downtime, data words and associated tags can be read from the memory or a portion thereof to be erased. As indicated by block 510, data words and associated tags can be read from the memory. As indicated by block 512, the error type can be determined. The error type can be one of no error, a 1-bit error, or a 2-bit error. If the error type is a 1-bit error, the 1-bit error can be corrected and the corrected data can be written back to the memory, as indicated by block 514. However, after correcting the 1-bit error, the tag associated with the data word is not written back to the memory. Instead, a new tag for the data word is calculated using TECQED and written to the memory in association with the corrected data word, as indicated by block 516. Similarly, if it is determined that the error type is no error, then according to block 516, a new tag for the data word is calculated using TECQED and written to the memory in association with the data word.

[0040] If it is determined (block 512) that the error type is a 2-bit error, the computing system can be rebooted, as indicated by block 518( Figure 5B )). Since SECDED cannot correct a 2-bit error, rebooting the computing system (including the memory subsystem and other subsystems of the computing system) prevents the error data from adversely affecting the operation of the computing system. When the reboot has been completed, the EDAC logic can be initialized to use TECQED, as indicated by block 520. Rebooting to this initial state, the computing system and its memory system can return to their normal operating mode (e.g., controlling a vehicle). For clarity, this return to the normal operating mode is not shown in FIG. 5, but the EDAC logic uses TECQED.

[0041] Returning to the case of a 1-bit error or no error, after a new tag has been calculated and written to the memory (block 516), it can be determined whether the erasure has been completed, as indicated by block 522. That is, it can be determined whether all data words in the portion of the memory being erased have been read, any correctable 1-bit errors have been corrected, and new tags have been calculated and stored in the memory according to TECQED. If it is determined (block 522) that the erasure has not been completed, i.e., more data words are to be erased, the method 500 can continue as described above with respect to block 510.

[0042] If it is determined (block 522) that the erasure has been completed, the EDAC logic can switch from using SECDED to using TECQED, as indicated by block 524. After switching from SECDED to TECQED, the memory system or subsystem can be released from the downtime, as indicated by block 526. In the case where the EDAC logic uses TECQED, the computing system and its memory system can return to their normal operating mode (e.g., controlling a vehicle). Although not shown for clarity in Figures 5A to 5B , the switch back from TECQED to SECDED can be conditioned in the same manner as described above with respect to block 312 ( Figure 3 ) and block 416 ( Figure 4A ). That is, the switch back from TECQED to SECDED can be conditioned on determining that the number of 1-bit errors detected during a second time interval is not greater than a second threshold, and the number of 2-bit errors detected during the second time interval is not greater than a third threshold, and the number of 3-bit errors detected during the second time interval is not greater than a fourth threshold. To prevent toggling back and forth, a decision to switch back from TECQED to SECDED can be made if the above conditions are met within a time interval longer than the time interval indicated in block 504. Additionally, the second threshold for switching from TECQED to SECDED can be lower than the first threshold for switching from SECDED to TECQED, or it can even be made zero.

[0043] The EDAC level controller 114 can be configured to control any of the exemplary methods 200 ( Figure 2 ), 300 ( Figure 3 ), 400 ( Figures 4A to 4B ), or 500 ( Figures 5A to 5B ) described above. In an example where the EDAC level controller 114 includes a processor and a memory, the firmware or software that configures such a processor in operation can be stored in the memory. Execution of such firmware or software can control aspects of any of the above methods or configure aspects of any of the above systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware can be an example of a "computer-readable medium" as understood in a patent dictionary.

[0044] As Figure 6 shown, the vehicle-based computing system 600 can include a memory subsystem 602. The vehicle-based computing system 600 can be the one in the above methods 200 ( Figure 2 ), 300 ( Figure 3 ), 400 ( Figures 4A to 4B ), or 500 ( Figures 5A to 5B)Examples of computing systems referenced in any of the methods in. The memory subsystem 602 may be an example of the memory system 100 described above ( Figure 1 ).

[0045] During its operation, the vehicle 601 on which the vehicle-based computing system 600 is located may sometimes be subjected to harsh environmental conditions or effects, such as radiation from solar flares or other sources, cosmic rays, etc. Such environmental conditions or effects may cause data bits stored in the memory to flip from the correct state to an incorrect state. According to the above solutions, such bit flips or errors can be corrected or their adverse effects can be mitigated in other ways. It is contemplated that a more robust EDAC level can be applied when the vehicle 601 experiences such environmental conditions, and a less robust but more efficient (e.g., lower computational intensity, more efficient use of memory space, etc.) EDAC level can be restored when the vehicle 601 no longer experiences such conditions. However, the above methods and other solutions are not limited to mitigating the effects of bit errors caused by environmental conditions and can be applied regardless of the cause of the bit errors. In addition, the methods and other solutions described herein are not limited to vehicles or other safety-critical systems and can be applied in any other scenario.

[0046] The vehicle-based computing system 600 may also include other subsystems, such as a vehicle control subsystem 604, a navigation subsystem 606, an entertainment subsystem 608, etc. The vehicle-based computing system 600 may also include an alarm or warning indicator 610, such as a feature of a display on the vehicle dashboard. A bus or other data interconnect 612 may provide data communication between the various subsystems and other components. Some of the subsystems may have one or more processors (not shown separately), and the one or more processors may initiate the above types of memory transactions (i.e., writes, reads, etc.) with the memory subsystem 602. Thus, the various subsystems and their processors can use the data stored in the memory subsystem 602 to perform their normal operations, such as controlling the operation of the vehicle in the case of the vehicle control subsystem 604 and assisting vehicle navigation in the case of the navigation subsystem 606, etc.

[0047] Some of the subsystems may be involved in safety-critical functions, while other subsystems may not be involved in safety-critical functions. For example, the vehicle control system 604 may control various aspects of vehicle power, braking, or steering, as Figure 6 conceptually indicated by the dashed arrows in. It can be understood that incorrect operation of the vehicle control subsystem 604 or the navigation subsystem 606 due to corrupted data read from the memory subsystem 602 may adversely affect safety. Therefore, in some examples, as described above regarding Figures 5A to 5BThe described erase feature can target memory regions in which security-critical data is stored. In some examples, only memory regions in which security-critical data or other important data is stored can be erased, while memory regions in which non-security-critical data or data whose corruption would not be harmful is stored may not be erased. However, in other examples, the erase feature can target any region or amount of the memory, including the entire memory.

[0048] Specific implementation examples are described in the following numbered clauses:

[0049] 1. A method for adaptive memory error detection and correction (EDAC), comprising:

[0050] Monitoring the EDAC logic of a memory subsystem for error correction, wherein the EDAC logic is configured to use a first EDAC level;

[0051] Determining the number of error corrections using the first EDAC level during a first time interval;

[0052] Determining whether the number of error corrections using the first EDAC level during the first time interval exceeds a first threshold; and

[0053] When the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold, switching the EDAC logic from using the first EDAC level to using a second EDAC level.

[0054] 2. The method according to clause 1, wherein:

[0055] The first EDAC level includes error correction for up to a first number of error bits, and determining the number of error corrections using the first EDAC level includes determining the number of error corrections for the first number of error bits; and

[0056] The second EDAC level includes error correction for a second number of error bits that is greater than the first number of error bits.

[0057] 3. The method according to clause 2, further comprising:

[0058] After switching the EDAC logic from using the first EDAC level to using the second EDAC level, monitoring the EDAC logic for error correction, wherein the EDAC logic is configured to use the second EDAC level;

[0059] Determining the number of error corrections using the second EDAC level during a second time interval, including determining the number of error corrections for the second number of error bits;

[0060] Determining whether the number of error corrections for the first number of error bits during the second time interval is greater than a second threshold, where the second threshold is less than the first threshold;

[0061] Determining whether the number of error corrections for the second number of error bits during the second time interval is greater than a third threshold, where the third threshold is less than the second threshold; and

[0062] When the number of error corrections for the first number of error bits during the second time interval does not exceed the second threshold, and the number of error corrections for the second number of error bits during the second time interval does not exceed the third threshold, switching the EDAC logic from using the second EDAC level to using the first EDAC level.

[0063] 4. The method according to clause 3, wherein the second threshold and the third threshold are zero error bits, and the first threshold is greater than zero error bits.

[0064] 5. The method according to any one of clauses 2 to 4, wherein the second time interval is greater than the first time interval.

[0065] 6. The method according to clause 3 or 4, wherein:

[0066] Determining the number of error corrections using the second EDAC level during the second time interval further includes determining the number of error corrections for a third number of error bits greater than the second number of error bits;

[0067] Determining whether the number of error corrections for the third number of error bits during the second time interval is greater than a fourth threshold; and

[0068] Switching the EDAC logic from using the second EDAC level to using the first EDAC level further includes: when the number of error corrections for the first number of error bits during the second time interval does not exceed the second threshold, and the number of error corrections for the second number of error bits during the second time interval does not exceed the third threshold, and the number of error corrections for the third number of error bits during the second time interval does not exceed the fourth threshold, switching the EDAC logic from using the second EDAC level to using the first EDAC level.

[0069] 7. The method according to any one of clauses 1 to 6, wherein the first EDAC level is single error correction / double error detection (SECDED), and the second EDAC level is triple error correction / quadruple error detection (TECQED).

[0070] 8. The method according to any one of clauses 1 to 7, further comprising: performing a reboot when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold.

[0071] 9. The method according to any one of clauses 1 to 8, further comprising: when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold:

[0072] reading data from the memory subsystem during a memory subsystem downtime, wherein the EDAC logic is configured to use the first EDAC level; and

[0073] writing the data back to the memory subsystem during the memory subsystem downtime, wherein the EDAC logic is configured to use the second EDAC level.

[0074] 10. A system for adaptive memory error detection and correction (EDAC), comprising:

[0075] EDAC logic in a memory subsystem; and

[0076] EDAC level control logic configured to:

[0077] monitor the EDAC logic for error correction, wherein the EDAC logic is configured to use a first EDAC level;

[0078] determine the number of error corrections using the first EDAC level during a first time interval;

[0079] determine whether the number of error corrections using the first EDAC level during the first time interval exceeds a first threshold; and

[0080] when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold, switch the EDAC logic from using the first EDAC level to using a second EDAC level.

[0081] 11. The system according to clause 10, wherein:

[0082] The first EDAC level includes error correction for up to a first number of error bits, wherein the EDAC level control logic is configured to determine the number of error corrections using the first EDAC level by determining the number of error corrections of the error correction configured to determine the first number of error bits; and

[0083] The second EDAC level includes error correction for up to a second number of error bits greater than the first number of error bits.

[0084] 12. The system according to clause 11, wherein the EDAC level control logic is further configured to:

[0085] After switching the EDAC logic from using the first EDAC level to using the second EDAC level, monitor the EDAC logic for error correction, wherein the EDAC logic is configured to use the second EDAC level;

[0086] Determine the number of error corrections using the second EDAC level during a second time interval, including determining the number of error corrections of the second number of error bits;

[0087] Determine whether the number of error corrections of the first number of error bits during the second time interval is greater than a second threshold, wherein the second threshold is less than the first threshold;

[0088] Determine whether the number of error corrections of the second number of error bits during the second time interval is greater than a third threshold, wherein the third threshold is less than the second threshold; and

[0089] When the number of error corrections of the first number of error bits during the second time interval does not exceed the second threshold, and the number of error corrections of the second number of error bits during the second time interval does not exceed the third threshold, switch the EDAC logic from using the second EDAC level to using the first EDAC level.

[0090] 13. The system according to clause 12, wherein the second threshold and the third threshold are zero error bits, and the first threshold is greater than zero error bits.

[0091] 14. The system according to clause 12 or 13, wherein the second time interval is greater than the first time interval.

[0092] 15. The system according to any one of clauses 12 to 14, wherein:

[0093] The EDAC level control logic is configured to further determine the number of error corrections using the second EDAC level during the second time interval by the number of error corrections of a third number of error bits configured to determine more error bits than the second number of error bits;

[0094] The EDAC level control logic is configured to determine whether the number of error corrections of the third number of error bits during the second time interval is greater than a fourth threshold; and

[0095] The EDAC level control logic is configured to switch the EDAC logic from using the second EDAC level to using the first EDAC level by being configured to switch the EDAC logic from using the second EDAC level to using the first EDAC level when the number of error corrections of the first number of error bits during the second time interval does not exceed the second threshold, and the number of error corrections of the second number of error bits during the second time interval does not exceed the third threshold, and the number of error corrections of the third number of error bits during the second time interval does not exceed the fourth threshold.

[0096] 16. The system according to any one of clauses 10 to 15, wherein the first EDAC level is single error correction / double error detection (SECDED), and the second EDAC level is triple error correction / quadruple error detection (TECQED).

[0097] 17. The system according to any one of clauses 10 to 16, wherein the EDAC level control logic is further configured to: perform a reboot when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold.

[0098] 18. The system according to any one of clauses 10 to 17, wherein the EDAC level control logic is further configured to: when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold:

[0099] Read data from the memory subsystem during a memory subsystem downtime, wherein the EDAC logic is configured to use the first EDAC level; and

[0100] Write the data back to the memory subsystem during the memory subsystem downtime, wherein the EDAC logic is configured to use the second EDAC level.

[0101] 19. The system according to any one of clauses 10 to 18, wherein the EDAC level control logic and the EDAC logic are included in a vehicle.

[0102] 20. A system for adaptive memory error detection and correction (EDAC), comprising:

[0103] means for monitoring EDAC logic of a memory subsystem for error correction, wherein the EDAC logic is configured to use a first EDAC level;

[0104] means for determining a number of error corrections using the first EDAC level during a first time interval;

[0105] means for determining whether the number of error corrections using the first EDAC level during the first time interval exceeds a first threshold; and

[0106] means for switching the EDAC logic from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold.

[0107] 21. The system according to clause 20, wherein:

[0108] the first EDAC level includes error correction for up to a first number of error bits, and the means for determining the number of error corrections using the first EDAC level includes means for determining the number of error corrections for the first number of error bits; and

[0109] the second EDAC level includes error correction for up to a second number of error bits greater than the first number of error bits.

[0110] 22. The system according to clause 21, further comprising:

[0111] means for monitoring the EDAC logic for error correction after switching the EDAC logic from using the first EDAC level to using the second EDAC level, wherein the EDAC logic is configured to use the second EDAC level;

[0112] means for determining the number of error corrections using the second EDAC level during a second time interval, including determining the number of error corrections for the second number of error bits;

[0113] A component for determining whether the number of error corrections for the first number of error bits during the second time interval is greater than a second threshold, where the second threshold is less than the first threshold;

[0114] A component for determining whether the number of error corrections for the second number of error bits during the second time interval is greater than a third threshold, where the third threshold is less than the second threshold; and

[0115] A component for switching the EDAC logic from using the second EDAC level to using the first EDAC level when the number of error corrections for the first number of error bits during the second time interval does not exceed the second threshold and the number of error corrections for the second number of error bits during the second time interval does not exceed the third threshold.

[0116] 23. The system according to clause 20, wherein the second threshold and the third threshold are zero error bits, and the first threshold is greater than zero error bits.

[0117] 24. The system according to clause 22 or 23, wherein the second time interval is greater than the first time interval.

[0118] 25. The system according to any one of clauses 22 to 24, wherein:

[0119] The component for determining the number of error corrections for using the second EDAC level during the second time interval further includes a component for determining the number of error corrections for a third number of error bits greater than the second number of error bits; the system further includes a component for determining whether the number of error corrections for the third number of error bits during the second time interval is greater than a fourth threshold; and

[0120] The component for switching the EDAC logic from using the second EDAC level to using the first EDAC level further includes a component for switching the EDAC logic from using the second EDAC level to using the first EDAC level when the number of error corrections for the first number of error bits during the second time interval does not exceed the second threshold, the number of error corrections for the second number of error bits during the second time interval does not exceed the third threshold, and the number of error corrections for the third number of error bits during the second time interval does not exceed the fourth threshold.

[0121] 26. The system according to any one of clauses 20 to 25, wherein the first EDAC level is single error correction / double error detection (SECDED), and the second EDAC level is triple error correction / quadruple error detection (TECQED).

[0122] 27. The system according to any one of clauses 20 to 26, further comprising: a component for performing a reboot when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold.

[0123] 28. The system according to any one of clauses 20 to 27, further comprising: a component for performing the following operations when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold:

[0124] Reading data from the memory subsystem during a memory subsystem downtime period, wherein the EDAC logic is configured to use the first EDAC level; and

[0125] Writing the data back to the memory subsystem during the memory subsystem downtime period, wherein the EDAC logic is configured to use the second EDAC level.

[0126] 29. A computer-readable medium for adaptive memory error detection and correction (EDAC), the computer-readable medium comprising a non-transitory computer-readable medium having instructions stored thereon in a computer-executable form, the instructions configuring the processing system to control, when executed by a processing system of a computing device:

[0127] Monitoring the EDAC logic of a memory subsystem for error correction, wherein the EDAC logic is configured to use a first EDAC level;

[0128] Determining the number of error corrections using the first EDAC level during a first time interval;

[0129] Determining whether the number of error corrections using the first EDAC level during the first time interval exceeds a first threshold; and

[0130] When the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold, switching the EDAC logic from using the first EDAC level to using a second EDAC level.

[0131] 30. The computer-readable medium according to clause 29, wherein:

[0132] The first EDAC level includes error correction for up to a first number of error bits, where determining the number of error corrections using the first EDAC level includes determining the number of error corrections for the first number of error bits; and

[0133] The second EDAC level includes error correction for a second number of error bits that is greater than the first number of error bits and up to a second number of error bits.

[0134] 31. The computer-readable medium according to clause 30, wherein the instructions further configure the processing system to control:

[0135] After switching the EDAC logic from using the first EDAC level to using the second EDAC level, monitor the EDAC logic for error correction, where the EDAC logic is configured to use the second EDAC level;

[0136] Determine the number of error corrections using the second EDAC level during a second time interval, including determining the number of error corrections for the second number of error bits;

[0137] Determine whether the number of error corrections for the first number of error bits during the second time interval is greater than a second threshold, where the second threshold is less than the first threshold;

[0138] Determine whether the number of error corrections for the second number of error bits during the second time interval is greater than a third threshold, where the third threshold is less than the second threshold; and

[0139] When the number of error corrections for the first number of error bits during the second time interval does not exceed the second threshold and the number of error corrections for the second number of error bits during the second time interval does not exceed the third threshold, switch the EDAC logic from using the second EDAC level to using the first EDAC level.

[0140] 32. The computer-readable medium according to clause 31, wherein the second threshold and the third threshold are zero error bits, and the first threshold is greater than zero error bits.

[0141] 33. The computer-readable medium according to clause 31 or 32, wherein the second time interval is greater than the first time interval.

[0142] 34. The computer-readable medium according to any one of clauses 31 to 33, wherein:

[0143] The instructions for configuring the processing system to control the determination of the number of error corrections using the second EDAC level during the second time interval include instructions for configuring the processing system to control the determination of the number of error corrections for a third number of error bits that is greater than the second number of error bits;

[0144] The instructions further configure the processing system to control the determination of whether the number of error corrections for the third number of error bits during the second time interval is greater than a fourth threshold; and

[0145] The instructions for further configuring the processing system to switch the EDAC logic from using the second EDAC level to using the first EDAC level further include:

[0146] When the number of error corrections for the first number of error bits during the second time interval does not exceed the second threshold, and the number of error corrections for the second number of error bits during the second time interval does not exceed the third threshold, and the number of error corrections for the third number of error bits during the second time interval does not exceed the fourth threshold, switch the EDAC logic from using the second EDAC level to using the first EDAC level.

[0147] Alternative embodiments will become apparent to those of ordinary skill in the art to which the present invention pertains. Accordingly, although the selected aspects have been illustrated and described in detail, it should be understood that various substitutions and alterations can be made therein.

Claims

1. A method for adaptive memory error detection and correction (EDAC), comprising: Monitor the EDAC logic of the memory subsystem for error correction, wherein the EDAC logic is configured to use a first EDAC level; Determine the number of error corrections using the first EDAC level during a first time interval; Determine whether the number of error corrections using the first EDAC level during the first time interval exceeds a first threshold; When the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold, switch the EDAC logic from using the first EDAC level to using a second EDAC level; And Based on additional conditions, switch the EDAC logic back from the second EDAC level to the first EDAC level.

2. The method according to claim 1, wherein: The first EDAC level includes error correction for up to a first number of error bits, wherein determining the number of error corrections using the first EDAC level includes determining the number of error corrections for the first number of error bits; and The second EDAC level includes error correction for a second number of error bits that is greater than the first number of error bits.

3. The method according to claim 2, further comprising: After switching the EDAC logic from using the first EDAC level to using the second EDAC level, monitor the EDAC logic for error correction, wherein the EDAC logic is configured to use the second EDAC level; Determine the number of error corrections using the second EDAC level during a second time interval, including determining the number of error corrections for the first number of error bits and the second number of error bits; Determine whether the number of error corrections for the first number of error bits during the second time interval is greater than a second threshold, wherein the second threshold is less than the first threshold; Determine whether the number of error corrections for the second number of error bits during the second time interval is greater than a third threshold, wherein the third threshold is less than the second threshold; And When the number of error corrections for the first number of error bits during the second time interval does not exceed the second threshold, and the number of error corrections for the second number of error bits during the second time interval does not exceed the third threshold, switch the EDAC logic from using the second EDAC level to using the first EDAC level.

4. The method according to claim 3, wherein the second threshold and the third threshold are zero error bits, and the first threshold is greater than zero error bits.

5. The method according to claim 3, wherein the second time interval is greater than the first time interval.

6. The method according to claim 3, wherein: Determining the number of error corrections using the second EDAC level during the second time interval further includes determining the number of error corrections for a third number of error bits that is greater than the second number of error bits; Determine whether the number of error corrections for the third number of error bits during the second time interval is greater than a fourth threshold; And Switching the EDAC logic from using the second EDAC level to using the first EDAC level further includes: when the number of error corrections of the first number of error bits during the second time interval does not exceed the second threshold, and the number of error corrections of the second number of error bits during the second time interval does not exceed the third threshold, and the number of error corrections of the third number of error bits during the second time interval does not exceed the fourth threshold, switching the EDAC logic from using the second EDAC level to using the first EDAC level.

7. The method according to claim 6, wherein the first EDAC level is single error correction / double error detection (SECDED), and the second EDAC level is triple error correction / quadruple error detection (TECQED).

8. The method according to claim 1, further comprising: Perform a reboot when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold.

9. The method according to claim 1, further comprising: When the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold: Read data from the memory subsystem during the memory subsystem downtime, where the EDAC logic is configured to use the first EDAC level; And Write the data back to the memory subsystem during the memory subsystem downtime, where the EDAC logic is configured to use the second EDAC level.

10. A system for adaptive memory error detection and correction (EDAC), comprising: EDAC logic in the memory subsystem; And EDAC level control logic, the EDAC level control logic is configured to: Monitor the EDAC logic for error correction, where the EDAC logic is configured to use the first EDAC level; Determine the number of error corrections using the first EDAC level during the first time interval; Determine whether the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold; When the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold, switch the EDAC logic from using the first EDAC level to using the second EDAC level; And Switch the EDAC logic back from the second EDAC level to the first EDAC level based on additional conditions.

11. The system according to claim 10, wherein: The first EDAC level includes error correction for up to a first number of error bits, where the EDAC level control logic is configured to determine the number of error corrections using the first EDAC level by being configured to determine the number of error corrections of the first number of error bits; and The second EDAC level includes error correction for a second number of error bits that is greater than the first number of error bits.

12. The system according to claim 11, wherein the EDAC level control logic is further configured to: After switching the EDAC logic from using the first EDAC level to using the second EDAC level, monitor the EDAC logic for error correction, wherein the EDAC logic is configured to use the second EDAC level; Determine the number of error corrections using the second EDAC level during a second time interval, including determining the number of error corrections for the second number of error bits; Determine whether the number of error corrections of the first number of error bits during the second time interval is greater than a second threshold, where the second threshold is less than the first threshold; Determine whether the number of error corrections of the second number of error bits during the second time interval is greater than a third threshold, where the third threshold is less than the second threshold; And When the number of error corrections of the first number of error bits during the second time interval does not exceed the second threshold, and the number of error corrections of the second number of error bits during the second time interval does not exceed the third threshold, switch the EDAC logic from using the second EDAC level to using the first EDAC level.

13. The system according to claim 12, wherein the second threshold and the third threshold are zero error bits, and the first threshold is greater than zero error bits.

14. The system according to claim 12, wherein the second time interval is greater than the first time interval.

15. The system according to claim 12, wherein: The EDAC level control logic is configured to further determine the number of error corrections using the second EDAC level during the second time interval by being configured to determine the number of error corrections of a third number of error bits greater than the second number of error bits; The EDAC level control logic is configured to determine whether the number of error corrections of the third number of error bits during the second time interval is greater than a fourth threshold; and The EDAC level control logic is configured to switch the EDAC logic from using the second EDAC level to using the first EDAC level by being configured to switch the EDAC logic from using the second EDAC level to using the first EDAC level when the number of error corrections of the first number of error bits during the second time interval does not exceed the second threshold, the number of error corrections of the second number of error bits during the second time interval does not exceed the third threshold, and the number of error corrections of the third number of error bits during the second time interval does not exceed the fourth threshold.

16. The system according to claim 15, wherein the first EDAC level is single error correction / double error detection (SECDED), and the second EDAC level is triple error correction / quadruple error detection (TECQED).

17. The system according to claim 10, wherein the EDAC level control logic is further configured to: perform a reboot when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold.

18. The system according to claim 10, wherein the EDAC level control logic is further configured to: when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold: read data from the memory subsystem during a memory subsystem downtime period, wherein the EDAC logic is configured to use the first EDAC level; and write the data back to the memory subsystem during the memory subsystem downtime period, wherein the EDAC logic is configured to use the second EDAC level.

19. The system according to claim 10, wherein the EDAC level control logic and the EDAC logic are included in a vehicle.

20. A system for adaptive memory error detection and correction (EDAC), comprising: A component for monitoring the EDAC logic of a memory subsystem for error correction, wherein the EDAC logic is configured to use a first EDAC level; A component for determining the number of error corrections using the first EDAC level during a first time interval; A component for determining whether the number of error corrections using the first EDAC level during the first time interval exceeds a first threshold; A component for switching the EDAC logic from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold; And A component for switching the EDAC logic from the second EDAC level back to the first EDAC level based on an additional condition.

21. The system according to claim 20, wherein: The first EDAC level includes error correction for up to a first number of error bits, wherein the component for determining the number of error corrections using the first EDAC level includes a component for determining the number of error corrections of the first number of error bits; and The second EDAC level includes error correction for up to a second number of error bits greater than the first number of error bits.

22. The system according to claim 21, further comprising: Components for monitoring the EDAC logic for error correction after switching the EDAC logic from using the first EDAC level to using the second EDAC level, wherein the EDAC logic is configured to use the second EDAC level; Components for determining the number of error corrections using the second EDAC level during a second time interval, including determining the number of error corrections for the second number of error bits; Components for determining whether the number of error corrections for the first number of error bits during the second time interval is greater than a second threshold, wherein the second threshold is less than the first threshold; Components for determining whether the number of error corrections for the second number of error bits during the second time interval is greater than a third threshold, wherein the third threshold is less than the second threshold; And Components for switching the EDAC logic from using the second EDAC level to using the first EDAC level when the number of error corrections for the first number of error bits during the second time interval does not exceed the second threshold and the number of error corrections for the second number of error bits during the second time interval does not exceed the third threshold.

23. The system according to claim 22, wherein the second threshold and the third threshold are zero error bits, and the first threshold is greater than zero error bits.

24. The system according to claim 22, wherein the second time interval is greater than the first time interval.

25. The system according to claim 22, wherein: The components for determining the number of error corrections using the second EDAC level during the second time interval further include components for determining the number of error corrections for a third number of error bits greater than the second number of error bits; The system further includes components for determining whether the number of error corrections for the third number of error bits during the second time interval is greater than a fourth threshold; and The components for switching the EDAC logic from using the second EDAC level to using the first EDAC level further include components for switching the EDAC logic from using the second EDAC level to using the first EDAC level when the number of error corrections for the first number of error bits during the second time interval does not exceed the second threshold, the number of error corrections for the second number of error bits during the second time interval does not exceed the third threshold, and the number of error corrections for the third number of error bits during the second time interval does not exceed the fourth threshold.

26. The system according to claim 25, wherein the first EDAC level is single error correction / double error detection (SECDED), and the second EDAC level is triple error correction / quadruple error detection (TECQED).

27. The system according to claim 20, further comprising: Components for performing a reboot when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold.

28. The system according to claim 20, further comprising: Components for performing the following operations when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold: Reading data from the memory subsystem during a memory subsystem downtime, wherein the EDAC logic is configured to use the first EDAC level; And Writing the data back to the memory subsystem during the memory subsystem downtime, wherein the EDAC logic is configured to use the second EDAC level.

29. A computer-readable medium for adaptive memory error detection and correction (EDAC), the computer-readable medium comprising a non-transitory computer-readable medium having instructions stored thereon in a computer-executable form, the instructions configuring the processing system to control, when executed by a processing system of a computing device: Monitoring the EDAC logic of a memory subsystem for error correction, wherein the EDAC logic is configured to use a first EDAC level; Determining the number of error corrections using the first EDAC level during a first time interval; Determining whether the number of error corrections using the first EDAC level during the first time interval exceeds a first threshold; When the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold, switching the EDAC logic from using the first EDAC level to using a second EDAC level; and Switching the EDAC logic back from the second EDAC level to the first EDAC level based on an additional condition.

30. The computer-readable medium according to claim 29, wherein: The first EDAC level includes error correction for up to a first number of error bits, where determining the number of error corrections using the error correction of the first EDAC level includes determining the number of error corrections for the first number of error bits; and The second EDAC level includes error correction for up to a second number of error bits that is greater than the first number of error bits.

31. The computer-readable medium according to claim 30, wherein the instructions further configure the processing system to control: After switching the EDAC logic from using the first EDAC level to using the second EDAC level, monitor the EDAC logic for error correction, where the EDAC logic is configured to use the second EDAC level; Determine the number of error corrections using the second EDAC level during a second time interval, including determining the number of error corrections for the second number of error bits; Determine whether the number of error corrections for the first number of error bits during the second time interval is greater than a second threshold, where the second threshold is less than the first threshold; Determine whether the number of error corrections for the second number of error bits during the second time interval is greater than a third threshold, where the third threshold is less than the second threshold; And When the number of error corrections for the first number of error bits during the second time interval does not exceed the second threshold and the number of error corrections for the second number of error bits during the second time interval does not exceed the third threshold, switch the EDAC logic from using the second EDAC level to using the first EDAC level.

32. The computer-readable medium according to claim 31, wherein the second threshold and the third threshold are zero error bits, and the first threshold is greater than zero error bits.

33. The computer-readable medium according to claim 31, wherein the second time interval is greater than the first time interval.

34. The computer-readable medium according to claim 31, wherein: The instructions that configure the processing system to control determining the number of error corrections using the second EDAC level during the second time interval include instructions that configure the processing system to control determining the number of error corrections for a third number of error bits that is greater than the second number of error bits; The instructions further configure the processing system to control determining whether the number of error corrections for the third number of error bits during the second time interval is greater than a fourth threshold; and The instructions that further configure the processing system to switch the EDAC logic from using the second EDAC level to using the first EDAC level further include: when the number of error corrections for the first number of error bits during the second time interval does not exceed the second threshold, and the number of error corrections for the second number of error bits during the second time interval does not exceed the third threshold, and the number of error corrections for the third number of error bits during the second time interval does not exceed the fourth threshold, switch the EDAC logic from using the second EDAC level to using the first EDAC level.

Images