Temperature compensation level conversion driver

Abstract

The invention relates to the field of level conversion drivers applied to phased array circuits and systems, in particular to a temperature compensation level conversion driver which comprises a logic level positive-to-negative unit and a driving shaping unit connected with the logic level positive-to-negative unit. The logic level positive-to-negative unit comprises a feedback enhanced transistor voltage drop unit formed by connecting P Schottky diodes and transistors in series, an enhanced transistor voltage drop unit formed by short-circuiting drain electrodes and grid electrodes of M transistors, and positive temperature coefficient resistors RB1 and RB2; through introduction of a feedback enhanced transistor voltage drop unit formed by series connection of P Schottky diodes and transistors, an enhanced transistor voltage drop unit formed by short circuit of drain electrodes and grid electrodes of M transistors, and positive temperature coefficient resistors RB1 and RB2, temperature compensation is realized while conversion from a positive logic level to a negative logic level is realized. According to the invention, the temperature sensitivity of the flip level is improved, and the flip level can be applied to a complex working environment with an anti-interference requirement.

Description

Technical Field

[0001] The present invention relates to the field of level conversion drivers applied to phased array circuits and systems, and particularly to a temperature compensation level conversion driver. Background Art

[0002] In the application of existing phased array radar systems, there are high requirements for radio frequency performance indicators such as noise, power, and linearity of transceiver components. Compared with semiconductor processes such as CMOS and SiGe, although the integrated circuits manufactured based on processes such as GaAs and GaN have deficiencies in integration, they have obvious advantages in radio frequency index characteristics. Therefore, in order to meet the high-performance requirements, integrated circuit products using compound semiconductor processes such as GaAs and GaN are widely used in phased array radar systems. With the continuous improvement of system integration, radio frequency circuits, analog circuits, digital and control circuits, etc. in the transceiver component have been integrated on the same motherboard. Due to the high integration of the antenna system and the complex working environment of the array surface, when the current or voltage changes violently, both the power supply and the ground wire will introduce noise sources, and the impedance mismatch of the transmission line will also introduce reflection noise. Signal coupling in the multilayer board and electromagnetic induction between wires will cause crosstalk. These factors make the requirements for the anti-interference performance of the circuit increasingly strict.

[0003] Integrated circuits using GaAs and GaN processes, such as digital control attenuators, digital control phase shifters, transceiver amplifier circuit switches, amplitude-phase control multifunctional circuits, etc., are common circuits inside transceiver components. In the phased array system, these modules can realize functions such as amplitude weighting, changing the beam direction, and receiving and transmitting pulse switching, and play an irreplaceable role. These circuits all need to be controlled by an external digital circuit. The most common control signals in radar systems include the TTL mode (+5V / 0V) and the LVTTL mode (+3.3V / 0V). However, the switching crystals in compound semiconductor processes such as GaAs and GaN often require negative logic control, so a level conversion driver is needed.

[0004] Currently, for the level conversion driver using the voltage division method of resistors and Schottky diodes, its flip level is stable at room temperature, but it is easily affected by temperature fluctuations in high and low temperature environments. Taking the digital control phase shifter product HMC649A as an example, its circuit application requires an input low level range of 0 to 0.2V and a high level range of Vdd±0.2V (Vdd is the power supply voltage); for related products such as NC13165C-618PD, etc., when applied in circuits, the required input low level range is 0 to 0.4V and the high level range is 3.0 to 5.0V. The required input low level range and high level range are significantly smaller, and there are risks in working environments with high anti-interference requirements.

[0005] In the level conversion drivers disclosed in the invention patents of CN110247651B, CN111682866B, CN104682967B, CN114567151B and CN119171903A, the temperature drift effect of temperature on the switching level is not mentioned. The Schottky diodes used inside are connected in series in the level conversion branch, and the temperature drift characteristics of the Schottky diodes themselves will affect the switching level value of the input port of the level conversion circuit, so it is prone to instability after being disturbed under high and low temperature conditions. Summary of the Invention

[0006] The purpose of the present invention is to: aiming at the above problem of temperature drift of the switching level at the input end of the level conversion driver itself under high and low temperature conditions, a temperature compensation level conversion driver is proposed, which is applicable to field effect transistor processes without insulated gate complementary logic such as GaAs and low voltage GaN. The internal circuit structure uses a series circuit of multiple devices such as a positive temperature coefficient resistor, an enhancement transistor with Schottky diode feedback, and a gate-drain shorted enhancement transistor. Temperature compensation can be achieved in a relatively wide temperature range, and then the switching level of the input port of the level conversion circuit is less affected by temperature, and it has stronger anti-noise signal and crosstalk signal interference capabilities.

[0007] To achieve the above purpose, the present invention adopts the following technical solutions: A temperature compensation level conversion driver is used to compatibly convert the input positive logic levels +5V / 0V or +3.3V / 0V into negative logic level signals 0V / -5V, and includes: a logic level positive-to-negative conversion unit and a driving and shaping unit connected thereto; The logic level positive-to-negative conversion unit includes: two enhancement transistor voltage drop units: a first enhancement transistor voltage drop unit and a second enhancement transistor voltage drop unit; four resistors: resistor RB1, resistor RB2, resistor RB3 and resistor RD1; two transistors: enhancement transistor E13 and depletion transistor D01; where: One end of the resistor RB1 is the signal input terminal connected to the input signal VCI, and the other end is connected to the input of the first enhanced transistor voltage drop unit. The first enhanced transistor voltage drop unit is a feedback enhanced transistor voltage drop unit composed of P Schottky diodes and P transistors connected in series. Its output terminal is connected to the input terminal of the first enhanced transistor voltage drop unit. The second enhanced transistor voltage drop unit is an enhanced transistor voltage drop unit composed of M enhanced transistors with their gates and drains short-circuited and connected in series. Its output terminal is respectively connected to one end of the resistor RB2 and one end of the resistor RB3. The other end of the resistor RB2 is connected to the negative power supply VSS, and the other end of the resistor RB3 is connected to the gate of the transistor E13. The source of the transistor E13 is connected to the negative power supply VSS, and the drain is simultaneously connected to one end of the resistor RD1 and the gate of the transistor D01, and serves as the output terminal of the logic level positive-to-negative conversion unit to output the signal VCO. The drain of the transistor D01 is grounded. The other end of the resistor RD1 is connected to the source of the transistor D01. The driving and shaping unit includes: a first inverting driving circuit, a second inverting driving circuit, a third inverting driving circuit, and a fourth inverting driving circuit. The input terminal of the first inverting driving circuit is the input terminal of the driving and shaping unit, which is connected to the output terminal of the logic level positive-to-negative conversion unit. The output terminal is respectively connected to the input terminals of the second inverting driving circuit and the third inverting driving circuit. The output terminal of the second inverting driving circuit outputs the signal VON, and the output terminal of the third inverting driving circuit is connected to the input terminal of the fourth inverting driving circuit and then outputs the signal VOP. The signals VON and VOP are complementary logic signals of 0V / -5V.

[0008] Further, the first enhanced transistor voltage drop unit is a feedback enhanced transistor voltage drop unit composed of five Schottky diodes and five enhanced transistors connected in series. The five Schottky diodes are: Schottky diode SD1, Schottky diode SD2, diode SD3, Schottky diode SD4, and Schottky diode SD5. The five enhanced transistors are: transistor E01, transistor E02, transistor E03, transistor E04, and transistor E05. Among them: the positive terminal of the Schottky diode SD1 is connected to the resistor RB1 and the drain of the transistor E01, and the negative terminal is connected to the gate of the transistor E01. The positive terminal of the Schottky diode SD2 is connected to the source of the transistor E01 and the drain of the transistor E02, and the negative terminal is connected to the gate of the transistor E02. The positive terminal of the Schottky diode SD3 is connected to the source of the transistor E02 and the drain of the transistor E03, and the negative terminal is connected to the gate of the transistor E03. The positive terminal of the Schottky diode SD4 is connected to the source of the transistor E03 and the drain of the transistor E04, and the negative terminal is connected to the gate of the transistor E04. The positive terminal of the Schottky diode SD5 is connected to the source of the transistor E04 and the drain of the transistor E05, and the negative terminal is connected to the gate of the transistor E05. The second enhanced transistor voltage drop unit is composed of seven enhanced transistors with their gates and drains short - circuited. The seven enhanced transistors are: transistor E06, transistor E07, transistor E08, transistor E09, transistor E10, transistor E11, and transistor E12. Among them: the drain of transistor E06 is connected to its gate and then connected to the source of transistor E05; the drain and gate of transistor E07 are connected and then connected to the source of transistor E06; the drain and gate of transistor E08 are connected and then connected to the source of transistor E07; the drain and gate of transistor E09 are connected and then connected to the source of transistor E08; the drain and gate of transistor E10 are connected and then connected to the source of transistor E09; the drain and gate of transistor E11 are connected and then connected to the source of transistor E10; the drain and gate of transistor E12 are connected and then connected to the source of transistor E11. The source is the output of the second enhanced transistor voltage drop unit and is connected to the common connection point of the second resistor RB2 and the third resistor RB3.

[0009] Further, the drive shaping unit specifically includes: eight transistors: enhanced transistor E14, enhanced transistor E15, enhanced transistor E16, enhanced transistor E17, depletion transistor D02, depletion transistor D03, depletion transistor D04, and depletion transistor D05; four resistors: resistor RD2, resistor RD3, resistor RD4, and resistor RD5. Among them: the gate of transistor E14 is used as the input of the drive shaping unit and is connected to signal VCO; the sources of transistor E14, transistor E15, transistor E16, and transistor E17 are all connected to VSS; the drains of transistor D02, transistor D03, transistor D04, and transistor D05 are all grounded; one end of resistor RD2 is connected to the source of transistor D02, and the other end is connected to the drain of transistor E14, forming a first inverting drive circuit; one end of resistor RD3 is connected to the source of transistor D03, and the other end is connected to the drain of transistor E15, forming a second inverting drive circuit; one end of resistor RD4 is connected to the source of transistor D04, and the other end is connected to the drain of transistor E16, forming a third inverting drive circuit; one end of resistor RD5 is connected to the source of transistor D05, and the other end is connected to the drain of E17, forming a fourth inverting drive circuit; the gates of the enhanced transistors in each inverting drive circuit are all used as input terminals, and the drains are all used as output terminals.

[0010] Furthermore, the five Schottky diodes have the same size.

[0011] Furthermore, the transistors E01, E02, E03, E04, E05, E06, E07, E08, E09, E10, E11, E12, and E13 have the same size.

[0012] Further, the resistors RB1, RB2, RB3, RD1, RD2, RD3, RD4, and RD5 are all positive temperature coefficient resistors with a sheet resistance greater than 400 ohms.

[0013] The temperature-compensated level conversion driver of the present invention, based on the combined action of the feedback-enhanced transistor voltage drop unit composed of P Schottky diodes and transistors in series, the enhanced transistor voltage drop unit composed of short-circuiting the drains and gates of M transistors, and multiple positive temperature coefficient resistors RB1 and RB2, realizes the temperature compensation function while realizing the conversion from positive logic level to negative logic level, and improves the temperature sensitivity of the switching level.

[0014] Compared with the level conversion driver composed of the direct series structure of traditional resistors and Schottky diodes, the present invention can achieve the cancellation of positive and negative temperature coefficients, and realizes the temperature compensation of the switching level in the temperature range of -55°C to +125°C. It can be applied to complex working environments with anti-interference requirements, such as in the scenarios of controlling the conduction and cutoff of negative voltage logic control switching transistors using GaAs process and GaN process, and can be applied to fields such as switches, numerically controlled attenuators, numerically controlled phase shifters, and amplitude-phase control multifunctional circuits. Description of the Drawings

[0015] Figure 1 is the circuit schematic diagram of a temperature-compensated level conversion driver of the present invention; Figure 2 is the simplified principle block diagram of a temperature-compensated level conversion driver of the present invention; Figure 3 is the circuit schematic diagram of the level conversion driver of the existing solution; Figure 4 is the temperature characteristic curve diagram of the Schottky diode of the present invention; Figure 5 is the temperature characteristic curve diagram of the enhanced transistor gate-drain short-circuit unit of the present invention; Figure 6 is the comparison of the temperature influence curves of the switching level of the present invention and the traditional solution based on the 0.25um GaAs process; Figure 7 is the comparison of the temperature influence curves of the switching level of the present invention and the traditional solution based on the 0.15um GaAs process. Detailed Description of the Invention

[0016] The technical solution of the present invention will be described in detail below in combination with the embodiments and the drawings.

[0017] Refer to Figure 1 - Figure 2, a temperature compensation level conversion driver provided in this embodiment includes: a logic level positive-to-negative conversion unit and a driving and shaping unit. The specific functions and connection relationships of each unit are described as follows: The logic level positive-to-negative conversion unit includes: two enhanced transistor voltage drop units: a first enhanced transistor voltage drop unit and a second enhanced transistor voltage drop unit; four resistors: resistor RB1, resistor RB2, resistor RB3, and resistor RD1; two transistors: enhanced transistor E13 and depletion transistor D01. The first enhanced transistor voltage drop unit is a feedback enhanced transistor voltage drop unit composed of five Schottky diodes and five enhanced transistors connected in series. The five Schottky diodes are: Schottky diode SD1, Schottky diode SD2, diode SD3, Schottky diode SD4, and Schottky diode SD5; the five enhanced transistors are: transistor E01, transistor E02, transistor E03, transistor E04, and transistor E05. The second enhanced transistor voltage drop unit is composed of seven enhanced transistors with their gates and drains short-circuited. The seven enhanced transistors are respectively: transistor E06, transistor E07, transistor E08, transistor E09, transistor E10, transistor E11, and transistor E12. Their connection relationships are as follows: The resistor RB1 is a current-limiting protection resistor for the input port. One end of it is the signal input terminal connected to the input signal VCI, and the other end is connected to the positive terminal of the Schottky diode SD1 and the drain of the transistor E01. The negative terminal of the Schottky diode SD1 is connected to the gate of the transistor E01. The positive terminal of the Schottky diode SD2 is connected to the source of the transistor E01 and the drain of the transistor E02, and the negative terminal is connected to the gate of the transistor E02. The positive terminal of the Schottky diode SD3 is connected to the source of the transistor E02 and the drain of the transistor E03, and the negative terminal is connected to the gate of the transistor E03. The positive terminal of the Schottky diode SD4 is connected to the source of the transistor E03 and the drain of the transistor E04, and the negative terminal is connected to the gate of the transistor E04. The positive terminal of the Schottky diode SD5 is connected to the source of the transistor E04 and the drain of the transistor E05, and the negative terminal is connected to the gate of the transistor E05. The drain and gate of the transistor E06 are connected and then connected to the source of the transistor E05. The drain and gate of the transistor E07 are connected and then connected to the source of the transistor E06. The drain and gate of the transistor E08 are connected and then connected to the source of the transistor E07. The drain and gate of the transistor E09 are connected and then connected to the source of the transistor E08. The drain and gate of the transistor E10 are connected and then connected to the source of the transistor E09. The drain and gate of the transistor E11 are connected and then connected to the source of the transistor E10. The drain and gate of the transistor E12 are connected and then connected to the source of the transistor E11. The source is the output of the second enhancement-type transistor voltage drop unit and is connected to one end of the second resistor RB2 and one end of the third resistor RB3. The resistor RB2 is a positive temperature-dividing resistor, and its other end is connected to the negative power supply VSS. The other end of the resistor RB3 is connected to the gate of the transistor E13, which plays a role in limiting the gate current when the transistor E13 is conducting, thereby reducing the power consumption of VSS. The source of the transistor E13 is connected to the negative power supply VSS, and the drain is simultaneously connected to one end of the resistor RD1 and the gate of the transistor D01, and serves as the output terminal of the logic level positive-to-negative conversion unit to output the signal VCO. The drain of the transistor D01 is grounded; the other end of the resistor RD1 is connected to the source of the transistor D01. In this embodiment, the resistor RD1 is used to limit the static current to reduce the static power consumption. The transistor D01 and the resistor RD1 together serve as the logic load of the transistor E13 and have the function of initially inverting the signal. Therefore, under their combined action, a single-ended signal VCO is formed and sent to the drive shaping unit.

[0018] The driving shaping unit includes: a first inverting driving circuit, a second inverting driving circuit, a third inverting driving circuit, and a fourth inverting driving circuit; the input end of the first inverting driving circuit is the input end of the driving shaping unit, which is connected to the output end of the logic level positive-to-negative unit, and the output end is respectively connected to the input ends of the second inverting driving circuit and the third inverting driving circuit; the output end of the second inverting driving circuit outputs a signal VON, and the output end of the third inverting driving circuit is connected to the input end of the fourth inverting driving circuit and then outputs a signal VOP; the signals VON and VOP output complementary logic signals of 0V / -5V. The specific structure and connection relationship are as follows: Eight transistors of the driving shaping unit: enhancement transistor E14, enhancement transistor E15, enhancement transistor E16, enhancement transistor E17, depletion transistor D02, depletion transistor D03, depletion transistor D04, and depletion transistor D05; four resistors: resistor RD2, resistor RD3, resistor RD4, and resistor RD5; where: the gate of transistor E14 is used as the input of the driving shaping unit to receive the signal VCO; the sources of transistors E14, E15, E16, and E17 are all connected to VSS; the drains of transistors D02, D03, D04, and D05 are all grounded; one end of resistor RD2 is connected to the source of transistor D02, and the other end is connected to the drain of transistor E14 to form the first inverting driving circuit; one end of resistor RD3 is connected to the source of transistor D03, and the other end is connected to the drain of transistor E15 to form the second inverting driving circuit; one end of resistor RD4 is connected to the source of transistor D04, and the other end is connected to the drain of transistor E16 to form the third inverting driving circuit; one end of resistor RD5 is connected to the source of transistor D05, and the other end is connected to the drain of E17 to form the fourth inverting driving circuit; the gates of the enhancement transistors in each inverting driving circuit are all used as input ends, and the drains are all used as output ends. In this embodiment, the negative power supply VSS is a power supply of -5V.

[0019] When the input control signal VH (such as a signal higher than the flip level Vs, such as +5V, +3.3V, etc.) is input, VOP outputs a high level of 0V, and VON outputs a low level of -5V; when the input control signal VL (such as 0V, etc., a signal lower than the flip level Vs) is input, VOP outputs a low level of -5V, and VON outputs a high level of 0V. Transistor E13 is an enhancement transistor, and its on and off states are determined by the threshold voltage Vth and the gate-source voltage Vgs. Among them, the threshold voltage Vth is positive and fluctuates with temperature. When the gate-source voltage Vgs > Vth, transistor E13 is turned on, and at this time VOP outputs 0V and VON outputs -5V; conversely, when Vgs < Vth, transistor E13 is turned off, and at this time VOP outputs -5V and VON outputs 0V.

[0020] For a more intuitive descriptionFigure 1 Embodiment of a medium temperature compensation level converter Figure 2 A simplified principle block diagram of a temperature compensation level conversion driver is given. The structure replaces the series structure of five enhanced transistor voltage drop units based on Schottky diode feedback in Figure 1 with a "P series" structure, replaces the series structure of seven enhanced transistor gate-drain short-circuit voltage drop units with an "M series" structure, and directly replaces the inverter unit circuit in the drive shaping unit with four "inverter drive circuits". Due to differences in semiconductor processes, the on-voltage and current curves of the first enhanced transistor voltage drop unit and the second enhanced transistor voltage drop unit vary with voltage. During implementation, the values of P and M can be flexibly adjusted according to process parameters to achieve temperature compensation.

[0021] Figure 3 Fig. is the circuit schematic diagram of a typical existing scheme level conversion driver, and its structure can be seen in the public contents of Chinese patents CN110247651B, CN111682866B, CN104682967B and CN119171903A. Different from the temperature compensation level conversion driver of this embodiment, this structure uses the method of voltage division by N Schottky diodes and resistors. During the level conversion process, the switching level of this structure fluctuates greatly affected by temperature.

[0022] Figure 4 Fig. gives the temperature characteristic curve of the Schottky diode. The three curves in the figure respectively represent the relationship between current and voltage under different conditions of high temperature HT, medium temperature MT, and low temperature LT. From Figure 4 it can be seen that the higher the temperature, the lower its on-voltage.

[0023] Figure 5 Fig. gives the temperature characteristic curve of the enhanced transistor gate-drain short-circuit unit. The three curves in the figure respectively represent the relationship between current and voltage under different conditions of high temperature HT, medium temperature MT, and low temperature LT. From Figure 5 it can be seen that the higher the temperature, the lower its on-voltage, but the curvature of the current varying with voltage has an obvious difference from Figure 4 the temperature characteristic of the Schottky diode.

[0024] Combining Figure 4 and Figure 5 , the enhanced transistor voltage drop unit based on Schottky diode feedback will form a temperature feedback characteristic. This structure combined with the enhanced transistor gate-drain short-circuit voltage drop unit and the positive temperature coefficient resistor forms a complex temperature compensation effect.

[0025] To verify the practicability of the present invention, a 0.25um GaAs process model is used for verification. Figure 6 For the switching level of the present invention and Figure 3Comparison graph of the temperature - affected curve of the flip - level of the traditional scheme shown Figure 6 The existing scheme in Figure 3 is the traditional resistor and Schottky - diode voltage - dividing structure shown. From Figure 6 it can be seen that, compared with the existing scheme, after introducing the first enhanced - transistor voltage - drop unit, the second enhanced - transistor voltage - drop unit, the positive - temperature - coefficient voltage - dividing resistors RB1 and RB2, the input low - level range VL of this embodiment is 0 - 1.5V, and the high - level range VH is 2.3 - 5.0V. Under the same conditions, the input low - level range VL of the existing scheme is 0 - 0.5V, and the high - level range VH is 3.0 - 5.0V. In comparison, the fluctuation of the flip - level Vs of the temperature - compensated level - conversion driver in this embodiment affected by temperature is smaller, and it has stronger compatibility with the TTL mode (+5V / 0V) and the LVTTL mode (+3.3V / 0V), and has the more stable advantage in applications with stronger interference signals.

[0026] In order to further verify the process adaptability of the present invention, the principle simulation verification was carried out again using the 0.15um GaAs process model Figure 7 is the comparison graph of the temperature - affected curve of the flip - level of the present invention and Figure 3 the temperature - affected curve of the flip - level of the traditional scheme shown Figure 7 The existing scheme in Figure 3 is the traditional resistor and Schottky - diode voltage - dividing structure shown. From Figure 7 it can be seen that, compared with the existing scheme, after introducing the first enhanced - transistor voltage - drop unit, the second enhanced - transistor voltage - drop unit, the positive - temperature - coefficient voltage - dividing resistors RB1 and RB2, the input low - level range VL of this embodiment is 0 - 1.7V, and the high - level range VH is 2.0 - 5.0V. Under the same conditions, the input low - level range VL of the existing scheme is 0 - 1.1V, and the high - level range VH is 2.8 - 5.0V. When comparing under the same conditions, the fluctuation of the flip - level Vs of the temperature - compensated level - conversion driver in this embodiment affected by temperature is still smaller, indicating that when using the circuit structure of the present invention with different process - parameter values, there is a temperature - compensation effect.

[0027] The above - mentioned embodiments only illustrate the principles and effects of the present invention, rather than limiting the present invention. Any person familiar with this technology can modify or change the above - mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A temperature-compensated level conversion driver for compatibly converting an input positive logic level of +5V / 0V or +3.3V / 0V into a negative logic level signal of 0V / -5V, comprising: A logic level positive-to-negative conversion unit and a driving and shaping unit connected thereto; characterized in that: The logic level positive-to-negative conversion unit includes: two enhanced transistor voltage drop units: a first enhanced transistor voltage drop unit and a second enhanced transistor voltage drop unit; four resistors: resistor RB1, resistor RB2, resistor RB3, and resistor RD1; two transistors: an enhanced transistor E13 and a depletion transistor D01; where: One end of resistor RB1 is the signal input terminal connected to the input signal VCI, and the other end is connected to the input of the first enhanced transistor voltage drop unit; the first enhanced transistor voltage drop unit is a feedback enhanced transistor voltage drop unit composed of P Schottky diodes and P transistors connected in series, and its output terminal is connected to the input terminal of the second enhanced transistor voltage drop unit; the second enhanced transistor voltage drop unit is an enhanced transistor voltage drop unit composed of M enhanced transistors with their gates and drains short-circuited and connected in series, and its output terminal is respectively connected to one end of resistor RB2 and one end of resistor RB3; the other end of resistor RB2 is connected to the negative power supply VSS, and the other end of resistor RB3 is connected to the gate of transistor E13; the source of transistor E13 is connected to the negative power supply VSS, the drain is simultaneously connected to one end of resistor RD1 and the gate of transistor D01, and is used as the output terminal of the logic level positive-to-negative conversion unit to output the signal VCO; the drain of transistor D01 is grounded; the other end of resistor RD1 is connected to the source of transistor D01; The driving and shaping unit includes: a first inverting driving circuit, a second inverting driving circuit, a third inverting driving circuit, and a fourth inverting driving circuit; the input terminal of the first inverting driving circuit is the input terminal of the driving and shaping unit, which is connected to the output terminal of the logic level positive-to-negative conversion unit, and the output terminal is respectively connected to the input terminals of the second inverting driving circuit and the third inverting driving circuit; the output terminal of the second inverting driving circuit outputs the signal VON, and the output terminal of the third inverting driving circuit is connected to the input terminal of the fourth inverting driving circuit and then outputs the signal VOP; the signals VON and VOP output complementary logic signals of 0V / -5V.

2. The temperature-compensated level conversion driver according to claim 1, wherein: The first enhanced transistor voltage drop unit is a feedback enhanced transistor voltage drop unit composed of five Schottky diodes and five enhanced transistors connected in series. The five Schottky diodes are: Schottky diode SD1, Schottky diode SD2, diode SD3, Schottky diode SD4, and Schottky diode SD5; the five enhanced transistors are: transistor E01, transistor E02, transistor E03, transistor E04, and transistor E05; where: The positive terminal of Schottky diode SD1 is connected to the drain of resistor RB1 and transistor E01, and the negative terminal is connected to the gate of transistor E01; the positive terminal of Schottky diode SD2 is connected to the source of transistor E01 and the drain of transistor E02, and the negative terminal is connected to the gate of transistor E02; the positive terminal of Schottky diode SD3 is connected to the source of transistor E02 and the drain of transistor E03, and the negative terminal is connected to the gate of transistor E03; the positive terminal of Schottky diode SD4 is connected to the source of transistor E03 and the drain of transistor E04, and the negative terminal is connected to the gate of transistor E04; the positive terminal of Schottky diode SD5 is connected to the source of transistor E04 and the drain of transistor E05, and the negative terminal is connected to the gate of transistor E05; The second enhancement transistor voltage drop unit is composed of seven enhancement transistors with their gates and drains shorted. The seven enhancement transistors are: transistor E06, transistor E07, transistor E08, transistor E09, transistor E10, transistor E11 and transistor E12; among them: The drain and gate of transistor E06 are connected and then connected to the source of transistor E05. The drain and gate of transistor E07 are connected and then connected to the source of transistor E06. The drain and gate of transistor E08 are connected and then connected to the source of transistor E07; the drain and gate of transistor E09 are connected and then connected to the source of transistor E08. The drain and gate of transistor E10 are connected and then connected to the source of transistor E09. The drain and gate of transistor E11 are connected and then connected to the source of transistor E10; the drain and gate of transistor E12 are connected and then connected to the source of transistor E11. The source is the output of the second enhancement transistor voltage drop unit and is connected to the common connection point of the second resistor RB2 and the third resistor RB3.

3. The temperature compensation level conversion driver according to claim 2, characterized in that: The drive shaping unit specifically includes: eight transistors: enhancement transistor E14, enhancement transistor E15, enhancement transistor E16, enhancement transistor E17, depletion transistor D02, depletion transistor D03, depletion transistor D04 and depletion transistor D05; four resistors: resistor RD2, resistor RD3, resistor RD4 and resistor RD5; among them: the gate of transistor E14 is used as the input of the drive shaping unit to receive signal VCO; the sources of transistors E14, E15, E16 and E17 are all connected to VSS; the drains of transistors D02, D03, D04 and D05 are all grounded; one end of resistor RD2 is connected to the source of transistor D02, and the other end is connected to the drain of transistor E14 to form a first inverting drive circuit; one end of resistor RD3 is connected to the source of transistor D03, and the other end is connected to the drain of transistor E15 to form a second inverting drive circuit; one end of resistor RD4 is connected to the source of transistor D04, and the other end is connected to the drain of transistor E16 to form a third inverting drive circuit; one end of resistor RD5 is connected to the source of transistor D05, and the other end is connected to the drain of E17 to form a fourth inverting drive circuit; the gates of the enhancement transistors in each inverting drive circuit are all used as input terminals, and the drains are all used as output terminals.

4. A temperature-compensated level conversion driver according to claim 3, characterized in that: The five Schottky diodes have the same size; the transistors E01, E02, E03, E04, E05, E06, E07, E08, E09, E10, E11, E12, and E13 have the same size.

5. The temperature compensation level conversion driver according to claim 3, wherein: The resistors RB1, RB2, RB3, RD1, RD2, RD3, RD4, and RD5 are all positive temperature coefficient resistors with a sheet resistance greater than 400 ohms.

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