Pixel driving circuit and driving method thereof, display device

Abstract

A pixel driving circuit and a driving method thereof, and a display device, wherein the pixel driving circuit is configured to drive a light emitting device (L) to emit light, the light emitting device (L) comprising a first electrode and a second electrode, the pixel driving circuit comprising a current control sub-circuit and a time length control sub-circuit; the time length control sub-circuit is configured to provide a control signal to a first node (N1) under the control of signals of a first scan signal line (Gate1), a first reset signal line (Reset1), a first light emitting signal line (EM1), a control signal line (SWP), a data signal line (Data), an initial signal line (INT) and a first power supply line (VDD1); the current control sub-circuit is configured to provide a driving current to the first electrode of the light emitting device (L) under the control of signals of the first node (N1), a second scan signal line (Gate2), a second reset signal line (Reset2), a second light emitting signal line (EM2), the data signal line (Data) and a second power supply line (VDD2).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a pixel driving circuit and a driving method thereof, and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED), Quantum-dot Light Emitting Diodes (QLED) and micro light emitting diode are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices with OLED, QLED or micro light emitting diode as light emitting elements and signal control by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0004] In a first aspect, the present disclosure provides a pixel driving circuit configured to drive a light emitting device to emit light, the light emitting device comprising a first electrode and a second electrode, the pixel driving circuit comprising a current control sub-circuit and a time length control sub-circuit.

[0005] The time length control sub-circuit is electrically connected with a first scan signal line, a first reset signal line, a first light emitting signal line, a control signal line, a data signal line, an initial signal line, a first power supply line and a first node respectively, and is configured to provide a control signal to the first node under the control of signals of the first scan signal line, the first reset signal line, the first light emitting signal line, the control signal line, the data signal line, the initial signal line and the first power supply line.

[0006] The current control sub-circuit is electrically connected with a second scan signal line, a third scan signal line, a second light emitting signal line, a data signal line, a second power supply line, the first node and the first electrode of the light emitting device respectively, and is configured to provide a driving current to the first electrode of the light emitting device under the control of signals of the first node, the second scan signal line, the third scan signal line, the second light emitting signal line, the data signal line and the second power supply line.

[0007] The second electrode of the light emitting device is electrically connected with a third power supply line.

[0008] In an example embodiment, the time length control sub-circuit comprises a first node control sub-circuit, a first driving sub-circuit, a first output control sub-circuit, and a first storage sub-circuit.

[0009] The first node control sub-circuit is electrically connected with a first scan signal line, a first reset signal line, an initial signal line, a data signal line, a first node, a second node, a third node, and a fourth node respectively, and is configured to drive a signal of the second node under control of signals of the first scan signal line and the data signal line, and provide a signal of the initial signal line to the first node and the second node under control of a signal of the first reset signal line.

[0010] The first driving sub-circuit is electrically connected with the second node, the third node, and the fourth node respectively, and is configured to provide a driving signal to the fourth node under control of signals of the second node and the third node.

[0011] The first output control sub-circuit is electrically connected with a first light-emitting signal line, the first node, the third node, the fourth node, and a first power supply line respectively, and is configured to provide a signal of the first power supply line to the third node and a signal of the fourth node to the first node under control of a signal of the first light-emitting signal line.

[0012] The first storage sub-circuit is electrically connected with the second node and a control signal line respectively, and is configured to store a voltage difference between signals of the second node and the control signal line.

[0013] In an example embodiment, the current control sub-circuit comprises a second node control sub-circuit, a second driving sub-circuit, a second output control sub-circuit, and a second storage sub-circuit.

[0014] The second node control sub-circuit is electrically connected with a second scan signal line, a third scan signal line, a data signal line, a first node, a fifth node, and a sixth node respectively, and is configured to drive a signal of the first node under control of signals of the second scan signal line, the third scan signal line, the data signal line, the fifth node, and the sixth node.

[0015] The second driving sub-circuit is electrically connected with the first node, the fifth node, and the sixth node respectively, and is configured to provide a driving current to the sixth node under control of signals of the first node and the fifth node.

[0016] The second output control sub-circuit is electrically connected with a second light-emitting signal line, a second power supply line, the fifth node, the sixth node, and a first electrode of a light-emitting device respectively, and is configured to provide a signal of the second power supply line to the fifth node and a driving current to the first electrode of the light-emitting device under control of a signal of the second light-emitting signal line.

[0017] The second storage sub-circuit is electrically connected with the first node, the second power supply line and the first electrode of the light emitting device respectively, and is configured to store a voltage difference between signals of the first node and the second power supply line and a voltage difference between signals of the first node and the first electrode of the light emitting device.

[0018] In an exemplary embodiment, further comprising: a reset sub-circuit;

[0019] The reset sub-circuit is electrically connected with the second reset signal line, the first electrode of the light emitting device and the second electrode of the light emitting device respectively, and is configured to provide, under control of a signal of the second reset signal line, the signal of the second electrode of the light emitting device to the first electrode of the light emitting device.

[0020] In an exemplary embodiment, the first node control sub-circuit comprises: a first transistor, a second transistor, a fourth transistor and a seventh transistor, the first drive sub-circuit comprises: a third transistor, the first output control sub-circuit comprises: a fifth transistor and a sixth transistor;

[0021] The control electrode of the first transistor is electrically connected with the first reset signal line, the first electrode of the first transistor is electrically connected with the initial signal line, and the second electrode of the first transistor is electrically connected with the second node;

[0022] The control electrode of the second transistor is electrically connected with the first scan signal line, the first electrode of the second transistor is electrically connected with the second node, and the second electrode of the second transistor is electrically connected with the fourth node;

[0023] The control electrode of the third transistor is electrically connected with the second node, the first electrode of the third transistor is electrically connected with the third node, and the second electrode of the third transistor is electrically connected with the fourth node;

[0024] The control electrode of the fourth transistor is electrically connected with the first scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the third node;

[0025] The control electrode of the fifth transistor is electrically connected with the first light emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the third node;

[0026] The control electrode of the sixth transistor is electrically connected with the first light emitting signal line, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first node;

[0027] The control electrode of the seventh transistor is electrically connected with the first reset signal line, the first electrode of the seventh transistor is electrically connected with the initial signal line, and the second electrode of the seventh transistor is electrically connected with the first node.

[0028] In an exemplary embodiment, the first storage sub-circuit comprises: a first capacitor;

[0029] The first end of the first capacitor is electrically connected with the control signal line, and the second end of the first capacitor is electrically connected with the second node.

[0030] In an exemplary embodiment, the second node control sub-circuit comprises an eighth transistor, a ninth transistor and an eleventh transistor.

[0031] The control electrode of the eighth transistor is electrically connected with the third scan signal line, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the fifth node.

[0032] The control electrode of the ninth transistor is electrically connected with the second scan signal line, the first electrode of the ninth transistor is electrically connected with the first node, and the second electrode of the ninth transistor is electrically connected with the sixth node.

[0033] The control electrode of the eleventh transistor is electrically connected with the second scan signal line, the first electrode of the eleventh transistor is electrically connected with the data signal line, and the second electrode of the eleventh transistor is electrically connected with the fifth node.

[0034] In an exemplary embodiment, the second drive sub-circuit comprises a tenth transistor, and the second output control sub-circuit comprises a twelfth transistor and a thirteenth transistor.

[0035] The control electrode of the tenth transistor is electrically connected with the first node, the first electrode of the tenth transistor is electrically connected with the fifth node, and the second electrode of the tenth transistor is electrically connected with the sixth node.

[0036] The control electrode of the twelfth transistor is electrically connected with the second emission signal line, the first electrode of the twelfth transistor is electrically connected with the second power supply line, and the second electrode of the twelfth transistor is electrically connected with the fifth node.

[0037] The control electrode of the thirteenth transistor is electrically connected with the second emission signal line, the first electrode of the thirteenth transistor is electrically connected with the sixth node, and the second electrode of the thirteenth transistor is electrically connected with the first electrode of the light emitting device.

[0038] In an exemplary embodiment, the second storage sub-circuit comprises a second capacitor and a third capacitor.

[0039] The first end of the second capacitor is electrically connected with the second power supply line, and the second end of the second capacitor is electrically connected with the first node.

[0040] The first end of the third capacitor is electrically connected with the first node, and the second end of the third capacitor is electrically connected with the first electrode of the light emitting device.

[0041] In an exemplary embodiment, the reset sub-circuit comprises a fourteenth transistor.

[0042] The control electrode of the fourteenth transistor is electrically connected with a second reset signal line, the first electrode of the fourteenth transistor is electrically connected with the first electrode of the light emitting device, and the second electrode of the fourteenth transistor is electrically connected with the second electrode of the light emitting device.

[0043] In the example embodiment, a reset sub-circuit is further included, the time length control sub-circuit includes a first transistor to a seventh transistor and a first capacitor, the current control sub-circuit includes an eighth transistor to a thirteenth transistor, a second capacitor and a third capacitor, and the reset sub-circuit includes a fourteenth transistor.

[0044] The control electrode of the first transistor is electrically connected with a first reset signal line, the first electrode of the first transistor is electrically connected with an initial signal line, and the second electrode of the first transistor is electrically connected with a second node.

[0045] The control electrode of the second transistor is electrically connected with a first scan signal line, the first electrode of the second transistor is electrically connected with the second node, and the second electrode of the second transistor is electrically connected with a fourth node.

[0046] The control electrode of the third transistor is electrically connected with the second node, the first electrode of the third transistor is electrically connected with a third node, and the second electrode of the third transistor is electrically connected with the fourth node.

[0047] The control electrode of the fourth transistor is electrically connected with the first scan signal line, the first electrode of the fourth transistor is electrically connected with a data signal line, and the second electrode of the fourth transistor is electrically connected with the third node.

[0048] The control electrode of the fifth transistor is electrically connected with a first light emitting signal line, the first electrode of the fifth transistor is electrically connected with a first power supply line, and the second electrode of the fifth transistor is electrically connected with the third node.

[0049] The control electrode of the sixth transistor is electrically connected with the first light emitting signal line, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with a first node.

[0050] The control electrode of the seventh transistor is electrically connected with the first reset signal line, the first electrode of the seventh transistor is electrically connected with the initial signal line, and the second electrode of the seventh transistor is electrically connected with the first node.

[0051] The control electrode of the eighth transistor is electrically connected with a third scan signal line, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with a fifth node.

[0052] The control electrode of the ninth transistor is electrically connected with a second scan signal line, the first electrode of the ninth transistor is electrically connected with the first node, and the second electrode of the ninth transistor is electrically connected with a sixth node.

[0053] The control electrode of the tenth transistor is electrically connected with the first node, the first electrode of the tenth transistor is electrically connected with the fifth node, and the second electrode of the tenth transistor is electrically connected with the sixth node;

[0054] The control electrode of the eleventh transistor is electrically connected with the second scan signal line, the first electrode of the eleventh transistor is electrically connected with the data signal line, and the second electrode of the eleventh transistor is electrically connected with the fifth node;

[0055] The control electrode of the twelfth transistor is electrically connected with the second emission signal line, the first electrode of the twelfth transistor is electrically connected with the second power supply line, and the second electrode of the twelfth transistor is electrically connected with the fifth node;

[0056] The control electrode of the thirteenth transistor is electrically connected with the second emission signal line, the first electrode of the thirteenth transistor is electrically connected with the sixth node, and the second electrode of the thirteenth transistor is electrically connected with the first electrode of the light emitting device;

[0057] The control electrode of the fourteenth transistor is electrically connected with the second reset signal line, the first electrode of the fourteenth transistor is electrically connected with the first electrode of the light emitting device, and the second electrode of the fourteenth transistor is electrically connected with the second electrode of the light emitting device;

[0058] The first end of the first capacitor is electrically connected with the control signal end, and the second end of the first capacitor is electrically connected with the second node;

[0059] The first end of the second capacitor is electrically connected with the second power supply line, and the second end of the second capacitor is electrically connected with the first node;

[0060] The first end of the third capacitor is electrically connected with the first node, and the second end of the third capacitor is electrically connected with the first electrode of the light emitting device.

[0061] In the example embodiment, the transistor types of the third transistor and the eighth transistor are opposite, the transistor types of the fifth transistor and the sixth transistor are opposite to the transistor types of the twelfth transistor and the thirteenth transistor, and the transistor types of the eighth transistor and the ninth transistor are opposite.

[0062] In the example embodiment, the first transistor to the seventh transistor, the ninth transistor, the eleventh transistor and the fourteenth transistor are P-type transistors, and the eighth transistor, the tenth transistor, the twelfth transistor and the thirteenth transistor are N-type transistors.

[0063] In the example embodiment, when the signal of the first reset signal line is an effective level signal, the signals of the first scan signal line, the second scan signal line, the first emission signal line, the second emission signal line, the third scan signal line and the second reset signal line are invalid level signals.

[0064] The signal of the second scan signal line is an effective level signal, the signal of the third scan signal line is an effective level signal, and the signals of the first reset signal line, the first scan signal line, the first light-emitting signal line, the second light-emitting signal line and the second reset signal line are invalid level signals.

[0065] The signal of the second scan signal line is an effective level signal, the signal of the third scan signal line is an effective level signal, and the signals of the first reset signal line, the first scan signal line, the first light-emitting signal line, the second light-emitting signal line and the second reset signal line are invalid level signals.

[0066] The signal of the first light-emitting signal line and the signal of the second light-emitting signal line are inverse signals of each other, the signal of the first light-emitting signal line is an effective level signal, the signal of the second light-emitting signal line is an effective level signal, and the signals of the first scan signal line, the second scan signal line, the first reset signal line, the third scan signal line and the second reset signal line are invalid level signals.

[0067] The signal of the second reset signal line is an effective level signal, the signal of the third scan signal line is an effective level signal, and the signals of the first reset signal line, the first scan signal line, the second scan signal line, the first light-emitting signal line and the second light-emitting signal line are invalid level signals.

[0068] In an example embodiment, when the signal of the first light-emitting signal line is an effective level signal, the signal of the control signal line is a ramp signal, and the voltage value gradually decreases.

[0069] The occurrence time of the signal of the first scan signal line being an effective level signal is earlier than the occurrence time of the signal of the second scan signal line being an effective level signal, and the duration of the signal of the first scan signal line being an effective level signal is less than the duration of the signal of the second scan signal line being an effective level signal.

[0070] In a second aspect, the present disclosure also provides a display device, comprising: a plurality of sub-modules, at least one of the sub-modules comprising: a plurality of rows of sub-pixels, at least one of the sub-pixels comprising: the pixel driving circuit and the light-emitting device driven by the pixel driving circuit.

[0071] In an example embodiment, the signals of any one of the first reset signal line, the third scan signal line, the second reset signal line, the second scan signal line, the first light-emitting signal line and the second light-emitting signal line connected to the pixel driving circuits of all the sub-pixels in the same sub-module are the same.

[0072] The first time corresponding to the pixel driving circuit of different row sub-pixels in the same sub-module does not overlap, and the first time corresponding to the pixel driving circuit is the time when the signal of the first scanning signal line connected to the pixel driving circuit is the effective level signal;

[0073] The latest time in the first time corresponding to the pixel driving circuit of all sub-pixels in the same sub-module is the second time, and the time when the signal of the second scanning signal line connected to the pixel driving circuit of any sub-pixel in the same sub-module is the effective level signal is the third time;

[0074] The second time and the third time do not overlap, and the second time is earlier than the third time.

[0075] In a third aspect, the present disclosure further provides a driving method of a pixel driving circuit configured to drive the pixel driving circuit described above.

[0076] The time length control sub-circuit is configured to provide a control signal to the first node under the control of the signals of the first scanning signal line, the first reset signal line, the first light-emitting signal line, the control signal line, the data signal line, the initial signal line and the first power supply line.

[0077] The current control sub-circuit is configured to provide a driving current to the first electrode of the light-emitting device under the control of the signals of the first node, the second scanning signal line, the third scanning signal line, the second light-emitting signal line, the data signal line and the second power supply line.

[0078] Other aspects can be appreciated upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0079] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0080] Figure 1 The pixel driving circuit provided for the embodiments of the present disclosure;

[0081] Figure 2 The structural schematic diagram of a time length control sub-circuit;

[0082] Figure 3 The structural schematic diagram of a current control sub-circuit;

[0083] Figure 4 The structural schematic diagram of a pixel driving circuit provided for an exemplary embodiment;

[0084] Figure 5 is an equivalent circuit diagram of a time length control sub-circuit;

[0085] Figure 6 is an equivalent circuit diagram of a current control sub-circuit;

[0086] Figure 7 is an equivalent circuit diagram of a reset sub-circuit;

[0087] Figure 8 is an equivalent circuit diagram of a pixel driving circuit;

[0088] Figure 9 is a working timing diagram of a pixel driving circuit;

[0089] Figure 10 is a curve of voltage value of a signal of a second node of a pixel driving circuit under different voltage values of a first data signal changing with time;

[0090] Figure 11 is a curve of voltage value of a signal of a first node of a pixel driving circuit under different voltage values of a first data signal changing with time;

[0091] Figure 12 is a curve of current value of a generated driving current of a pixel driving circuit under different voltage values of a first data signal changing with time;

[0092] Figure 13 is a working timing diagram of a sub-module. DETAILED DESCRIPTION

[0093] In order to make the objects, technical solutions and advantages of the present disclosure clearer, below the embodiments of the present disclosure will be described in detail with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. One skilled in the art can easily understand that the manners and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0094] The scale of the drawings in this disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted as needed. The number of pixels in the display device and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in this disclosure are only schematic diagrams, and one embodiment of this disclosure is not limited to the shapes or values shown in the drawings.

[0095] In this specification, ordinal terms such as "first", "second", and "third" are used to avoid confusion among components, and are not intended to limit in terms of numbers.

[0096] In this specification, words of "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the orientation or positional relationship are used to describe the positional relationship of components with reference to the drawings, and are only for convenience of description of this specification and simplification of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on this disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0097] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements. For those skilled in the art, the specific meaning of the above terms in this disclosure can be understood according to the specific circumstances.

[0098] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode line, drain region, or drain electrode) and the source electrode (source electrode line, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0099] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0100] In the present specification, "electrically connected" includes a case where components are connected through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can transmit and receive an electrical signal between the components to be connected. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0101] In the present specification, "parallel" means a state where two straight lines form an angle of -10° or more and 10° or less, and thus, a state where the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where two straight lines form an angle of 80° or more and 100° or less, and thus, a state where the angle is 85° or more and 95° or less is also included.

[0102] In the present specification, "film" and "layer" can be replaced with each other. For example, "a conductive layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0103] In the present specification, "disposed in the same layer" means that two (or more) structures are patterned by the same patterning process, and the materials thereof can be the same or different. For example, the materials of the precursors for forming the plurality of structures disposed in the same layer are the same, and the finally formed materials can be the same or different.

[0104] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximate triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, an arc edge, and deformation, and the like.

[0105] In the present disclosure, "about" means not strictly limited to the boundary, and allows values within a range of process and measurement errors.

[0106] A display device includes a plurality of sub-modules, each of the sub-modules includes a plurality of sub-pixels, each of the sub-pixels includes a plurality of pixel driving circuits. Each of the pixel driving circuits includes two parts, one of which determines the light-emitting time length, and the other of which generates a constant current. The response time of the constant current generated by the pixel driving circuit is relatively long, so that the pixel driving circuit cannot finely control the gray scale performance.

[0107] Figure 1 A structure schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the pixel driving circuit provided by the embodiment of the present disclosure can be configured to drive a light-emitting device to emit light. The light-emitting device can include a first electrode and a second electrode. The pixel driving circuit can include a current control sub-circuit and a time length control sub-circuit. Figure 1 The pixel driving circuit provided by the embodiment of the present disclosure can be configured to drive a light-emitting device to emit light. The light-emitting device can include a first electrode and a second electrode. The pixel driving circuit can include a current control sub-circuit and a time length control sub-circuit.

[0108] As shown in Figure 1 , the time length control sub-circuit is electrically connected with the first scan signal line Gate1, the first reset signal line Reset1, the first light-emitting signal line EM1, the control signal line SWP, the data signal line Data, the initial signal line INIT, the first power supply line VDD1 and the first node N1 respectively, and is configured to provide a control signal to the first node N1 under the control of signals of the first scan signal line Gate1, the first reset signal line Reset1, the first light-emitting signal line EM1, the control signal line SWP, the data signal line Data, the initial signal line INIT and the first power supply line VDD1. The current control sub-circuit is electrically connected with the second scan signal line Gate2, the third scan signal line Gate3, the second light-emitting signal line EM2, the data signal line Data, the second power supply line VDD2, the first node N1 and the first electrode of the light-emitting device L respectively, and is configured to provide a driving current to the first electrode of the light-emitting device L under the control of signals of the first node N1, the second scan signal line Gate2, the third scan signal line Gate3, the second light-emitting signal line EM2, the data signal line Data and the second power supply line VDD2.

[0109] In an example embodiment, as shown in Figure 1 , the second electrode of the light-emitting device L is electrically connected with the third power supply line VSS.

[0110] In an example embodiment, the first power supply line VDD1 can continuously provide a high-voltage power supply signal, and the second power supply line VDD2 can continuously provide a high-voltage power supply signal. The voltage value of the signal of the first power supply line VDD1 and the voltage value of the signal of the second power supply line VDD2 can be the same or can be different.

[0111] In an example embodiment, the voltage value of the signal of the first power supply line VDD1 or the second power supply line VDD2 can be about 2.5 volts (V) to 3 volts (V), and exemplarily, the voltage value of the signal of the first power supply line VDD1 or the second power supply line VDD2 can be about 2.8 volts (V).

[0112] In an example embodiment, the third power supply line VSS can continuously provide a low-voltage power supply signal.

[0113] In an example embodiment, the voltage value of the signal of the third power supply line VSS can be about -3 volts (V) to -3.5 volts (V), and exemplarily, the voltage value of the signal of the second power supply line VSS can be about -3.2 volts (V).

[0114] In an example embodiment, the light emitting device comprises a current driven device, which can employ a current type light emitting diode, such as a Micro Light Emitting Diode (Micro LED) or a Mini Light Emitting Diode (Mini LED) or an Organic Light Emitting Diode (OLED) or a Quantum Light Emitting Diode (QLED). A typical size (e.g. length) of a Micro LED can be less than 100 pm, such as 10 pm to 50 pm. A typical size (e.g. length) of a Mini LED can be about 100 pm to 300 pm, such as 120 pm to 260 pm.

[0115] In an example embodiment, the light emitting device L can further comprise an organic light emitting layer between the first electrode and the second electrode.

[0116] In an example embodiment, the organic light emitting layer can comprise a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Block Layer (EBL), an Emitting Layer (EML), a Hole Block Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) stacked. In an example embodiment, the HIL of all sub-pixels can be a common layer connected together, the EIL of all sub-pixels can be a common layer connected together, the HTL of all sub-pixels can be a common layer connected together, the ETL of all sub-pixels can be a common layer connected together, the HBL of all sub-pixels can be a common layer connected together, the EML of adjacent sub-pixels can have a small amount of overlap or can be isolated, and the EBL of adjacent sub-pixels can have a small amount of overlap or can be isolated.

[0117] The pixel driving circuit provided by the present disclosure is configured to drive the light emitting device to emit light, and the light emitting device comprises a first electrode and a second electrode. The pixel driving circuit comprises a current control sub-circuit and a time length control sub-circuit. The time length control sub-circuit is electrically connected with a first scan signal line, a first reset signal line, a first light emitting signal line, a control signal line, a data signal line, an initial signal line, a first power supply line and a first node respectively, and is configured to provide a control signal to the first node under the control of signals of the first scan signal line, the first reset signal line, the first light emitting signal line, the control signal line, the data signal line, the initial signal line and the first power supply line. The current control sub-circuit is electrically connected with a second scan signal line, a third scan signal line, a second light emitting signal line, a data signal line, a second power supply line, the first node and the first electrode of the light emitting device respectively, and is configured to provide a driving current to the first electrode of the light emitting device under the control of signals of the first node, the second scan signal line, the third scan signal line, the second light emitting signal line, the data signal line and the second power supply line. The second electrode of the light emitting device is electrically connected with a third power supply line. The current control sub-circuit in the present disclosure can reduce the response time of the driving current generated by the pixel driving circuit through the control of multiple signal lines, and is suitable for high-resolution display products.

[0118] In an example embodiment, Figure 2 is a structural schematic diagram of a time length control sub-circuit. As Figure 2 shown, the time length control sub-circuit can comprise a first node control sub-circuit, a first driving sub-circuit, a first output control sub-circuit and a first storage sub-circuit.

[0119] As Figure 2As shown, the first node control sub-circuit is electrically connected to the first scan signal line Gate1, the first reset signal line Reset1, the initial signal line INIT, the data signal line Data, the first node N1, the second node N2, the third node N3, and the fourth node N4, respectively. It is configured to, under the control of the signals from the first scan signal line Gate1 and the data signal line Data, drive the signal of the second node N2, and under the control of the signal from the first reset signal line Reset1, provide the initial signal line INIT signal to the first node N1 and the second node N2. The first drive sub-circuit is electrically connected to the second node N2, the third node N3, and the fourth node N4, respectively. The circuit is configured to provide a drive signal to the fourth node N4 under the control of the signals of the second node N2 and the third node N3; the first output control sub-circuit is electrically connected to the first light-emitting signal line EM1, the first node N1, the third node N3, the fourth node N4 and the first power line VDD1 respectively, and is configured to provide the signal of the first power line VDD1 to the third node N3 and the signal of the fourth node N4 to the first node N1 under the control of the signal of the first light-emitting signal line EM1; the first storage sub-circuit is electrically connected to the second node N2 and the control signal line SWP respectively, and is configured to store the voltage difference between the signals of the second node N2 and the control signal line SWP.

[0120] In an exemplary embodiment, Figure 3 This is a schematic diagram of a current-controlled sub-circuit. (Example) Figure 3 As shown, the current control sub-circuit may include: a second node control sub-circuit, a second drive sub-circuit, a second output control sub-circuit, and a second storage sub-circuit.

[0121] like Figure 3The second node control sub-circuit is electrically connected with the second scan signal line Gate2, the third scan signal line Gate3, the data signal line Data, the first node N1, the fifth node N5 and the sixth node N6 respectively, and is configured to drive the signal of the first node N1 under the control of the signals of the second scan signal line Gate2, the third scan signal line Gate3, the data signal line Data, the fifth node N5 and the sixth node N6; the second drive sub-circuit is electrically connected with the first node N1, the fifth node N5 and the sixth node N6 respectively, and is configured to provide a drive current to the sixth node N6 under the control of the signals of the first node N1 and the fifth node N5; the second output control sub-circuit is electrically connected with the second light-emitting signal line EM2, the second power supply line VDD2, the fifth node N5, the sixth node N6 and the first electrode of the light-emitting device L respectively, and is configured to provide the signal of the second power supply line VDD2 to the fifth node N5 and provide the drive current to the first electrode of the light-emitting device L under the control of the signal of the second light-emitting signal line EM2; and the second storage sub-circuit is electrically connected with the first node N1, the second power supply line VDD2 and the first electrode of the light-emitting device L respectively, and is configured to store the voltage difference between the signals of the first node N1 and the second power supply line VDD2 and the voltage difference between the signals of the first node N1 and the first electrode of the light-emitting device L.

[0122] In an example embodiment, Figure 4 A structural schematic diagram of a pixel driving circuit is provided for an example embodiment. As Figure 4 The pixel driving circuit can further include a reset sub-circuit. The reset sub-circuit is electrically connected with the second reset signal line Reset2, the first electrode of the light-emitting device L and the second electrode of the light-emitting device L respectively, and is configured to provide the signal of the second electrode of the light-emitting device L to the first electrode of the light-emitting device L under the control of the signal of the second reset signal line Reset2.

[0123] In an example embodiment, Figure 5 An equivalent circuit diagram of a time length control sub-circuit is provided. As Figure 5 The first node control sub-circuit includes the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7, the first drive sub-circuit includes the third transistor T3, and the first output control sub-circuit includes the fifth transistor T5 and the sixth transistor T6.

[0124] As Figure 5As shown, the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the initial signal line INIT, and the second electrode of the first transistor T1 is electrically connected to the second node N2; the control electrode of the second transistor T2 is electrically connected to the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected to the second node N2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the second node N2, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, and the first electrode of the fourth transistor T4 is electrically connected to the first reset signal line Reset1. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD1, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3; the control electrode of the sixth transistor T6 is electrically connected to the first light-emitting signal line EM1, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1; the control electrode of the seventh transistor T7 is electrically connected to the first reset signal line Reset1, the first electrode of the seventh transistor T7 is electrically connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1.

[0125] In an exemplary implementation, such as Figure 5 As shown, the first storage sub-circuit may include a first capacitor C1. The first terminal of the first capacitor C1 is electrically connected to the control signal line SWP, and the second terminal of the first capacitor C1 is electrically connected to the second node N2.

[0126] Figure 5 An exemplary structure of the duration control subcircuit is shown. It will be readily understood by those skilled in the art that the implementation of the duration control subcircuit is not limited to this.

[0127] In an exemplary embodiment, Figure 6 This is an equivalent circuit diagram of a current-controlled sub-circuit. For example... Figure 6 As shown, the second node control sub-circuit may include: the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11.

[0128] like Figure 6As shown in the figure, the control electrode of the eighth transistor T8 is electrically connected with the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fifth node N5; the control electrode of the ninth transistor T9 is electrically connected with the second scan signal line Gate2, the first electrode of the ninth transistor T9 is electrically connected with the first node N1, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6; the control electrode of the eleventh transistor T11 is electrically connected with the second scan signal line Gate2, the first electrode of the eleventh transistor T11 is electrically connected with the data signal line Data, and the second electrode of the eleventh transistor T11 is electrically connected with the fifth node N5.

[0129] In an example embodiment, as Figure 6 shown in the figure, the second driving sub-circuit can include the tenth transistor T10, and the second output control sub-circuit can include the twelfth transistor T12 and the thirteenth transistor T13.

[0130] As Figure 6 shown in the figure, the control electrode of the tenth transistor T10 is electrically connected with the first node N1, the first electrode of the tenth transistor T10 is electrically connected with the fifth node N5, and the second electrode of the tenth transistor T10 is electrically connected with the sixth node N6; the control electrode of the twelfth transistor T12 is electrically connected with the second emission signal line EM2, the first electrode of the twelfth transistor T12 is electrically connected with the second power supply line VDD2, and the second electrode of the twelfth transistor T12 is electrically connected with the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected with the second emission signal line EM2, the first electrode of the thirteenth transistor T13 is electrically connected with the sixth node N6, and the second electrode of the thirteenth transistor T13 is electrically connected with the first electrode of the light emitting device.

[0131] In an example embodiment, as Figure 6 shown in the figure, the second storage sub-circuit can include the second capacitor C2 and the third capacitor C3.

[0132] As Figure 6 shown in the figure, the first end of the second capacitor C2 is electrically connected with the second power supply line VDD2, and the second end of the second capacitor C2 is electrically connected with the first node N1; the first end of the third capacitor C3 is electrically connected with the first node N1, and the second end of the third capacitor C3 is electrically connected with the first electrode of the light emitting device.

[0133] Figure 6 An example structure of the current control sub-circuit is shown in the figure. It is easy for those skilled in the art to understand that the implementation of the current control sub-circuit is not limited to this.

[0134] In an example embodiment, Figure 7 is an equivalent circuit diagram of a reset sub-circuit. As Figure 7As shown in the figure, the reset sub-circuit comprises a fourteenth transistor T14. The control electrode of the fourteenth transistor T14 is electrically connected with the second reset signal line Reset2, the first electrode of the fourteenth transistor T14 is electrically connected with the first electrode of the light emitting device, and the second electrode of the fourteenth transistor T14 is electrically connected with the second electrode of the light emitting device.

[0135] Figure 7 An exemplary structure of the reset sub-circuit is shown in the figure. It is easily understood by those skilled in the art that the implementation of the reset sub-circuit is not limited to this.

[0136] Figure 8 An equivalent circuit diagram of a pixel driving circuit is shown in the figure. As shown in the figure, Figure 8 As shown in the figure, the time length control sub-circuit in the pixel driving circuit comprises the first transistor T1 to the seventh transistor T7 and the first capacitor C1, the current control sub-circuit comprises the eighth transistor T8 to the thirteenth transistor T13, the second capacitor C2 and the third capacitor C3, and the reset sub-circuit comprises the fourteenth transistor T14.

[0137] As shown in the figure, Figure 8As shown, the control electrode of the first transistor T1 is electrically connected with the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected with the initial signal line INIT, and the second electrode of the first transistor T1 is electrically connected with the second node N2; the control electrode of the second transistor T2 is electrically connected with the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected with the second node N2, and the second electrode of the second transistor T2 is electrically connected with the fourth node N4; the control electrode of the third transistor T3 is electrically connected with the second node N2, the first electrode of the third transistor T3 is electrically connected with the third node N3, and the second electrode of the third transistor T3 is electrically connected with the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected with the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the third node N3; the control electrode of the fifth transistor T5 is electrically connected with the first emission signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the first power supply line VDD1, and the second electrode of the fifth transistor T5 is electrically connected with the third node N3; the control electrode of the sixth transistor T6 is electrically connected with the first emission signal line EM1, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first node N1; the control electrode of the seventh transistor T7 is electrically connected with the first reset signal line Reset1, the first electrode of the seventh transistor T7 is electrically connected with the initial signal line INIT, and the second electrode of the seventh transistor T7 is electrically connected with the first node N1; the control electrode of the eighth transistor T8 is electrically connected with the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fifth node N5; the control electrode of the ninth transistor T9 is electrically connected with the second scan signal line Gate2, the first electrode of the ninth transistor T9 is electrically connected with the first node N1, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6; the control electrode of the tenth transistor T10 is electrically connected with the first node N1, the first electrode of the tenth transistor T10 is electrically connected with the fifth node N5, and the second electrode of the tenth transistor T10 is electrically connected with the sixth node N6; the control electrode of the eleventh transistor T11 is electrically connected with the second scan signal line Gate2, the first electrode of the eleventh transistor T11 is electrically connected with the data signal line Data, and the second electrode of the eleventh transistor T11 is electrically connected with the fifth node N5; the control electrode of the twelfth transistor T12 is electrically connected with the second emission signal line EM2, the first electrode of the twelfth transistor T12 is electrically connected with the second power supply line VDD2, and the second electrode of the twelfth transistor T12 is electrically connected with the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected with the second emission signal line EM2, the first electrode of the thirteenth transistor T13 is electrically connected with the sixth node N6, and the second electrode of the thirteenth transistor T13 is electrically connected with the first electrode of the light emitting device.A fourteenth transistor T14 has a control electrode electrically connected to a second reset signal line Reset2, a first electrode electrically connected to the first electrode of the light emitting device, and a second electrode electrically connected to the second electrode of the light emitting device; a first terminal of a first capacitor C1 is electrically connected to the control signal terminal, and a second terminal of the first capacitor C1 is electrically connected to the second node N2; a first terminal of a second capacitor C2 is electrically connected to the second power supply line VDD2, and a second terminal of the second capacitor C2 is electrically connected to the first node N1; a first terminal of a third capacitor C3 is electrically connected to the first node N1, and a second terminal of the third capacitor C3 is electrically connected to the first electrode of the light emitting device.

[0138] In an exemplary embodiment, the first transistor T1 can be referred to as a second node reset transistor. When the signal of the first reset signal line Reset1 is an active level signal, the signal of the initial signal line INIT is written into the second node N2.

[0139] In an exemplary embodiment, the second transistor T2 can be referred to as a first compensation transistor. When the signal of the first scan signal line Gate1 is an active level signal, the signal of the fourth node N4 is written into the second node N2 to compensate the second node N2.

[0140] In an exemplary embodiment, the third transistor T3 can be referred to as a first driving transistor. The third transistor T3 determines the control signal flowing between the first power supply line VDD1 and the first node N1 according to the potential difference between the gate electrode and the first electrode thereof.

[0141] In an exemplary embodiment, the fourth transistor T4 can be referred to as a first write transistor. When the signal of the first scan signal line Gate1 is an active level signal, the signal of the data signal line Data is written into the third node N3.

[0142] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 can be referred to as output transistors. When the signal of the first emitting signal line EM1 is an active level signal, the fifth transistor T5 and the sixth transistor T6 form a path between the first power supply line VDD1 and the first node N1.

[0143] In an exemplary embodiment, the seventh transistor T7 can be referred to as a first node reset transistor. When the signal of the first reset signal line Reset1 is an active level signal, the signal of the initial signal line INIT is written into the first node N1.

[0144] In an exemplary embodiment, the eighth transistor T8 can be referred to as a second compensation transistor. When the signal of the third scan signal line Gate3 is an active level signal, the signal of the fifth node N5 is written into the first node N1 to compensate the first node N1.

[0145] In an example embodiment, the ninth transistor T9 can be referred to as a third compensation transistor. When the signal of the second scan signal line Gate2 is an active level signal, the signal of the sixth node N6 is written to the first node N1 to compensate the first node N1.

[0146] In an example embodiment, the tenth transistor T10 can be referred to as a second drive transistor. The tenth transistor T10 determines a drive current flowing between the second power supply line VDD2 and the third power supply line VSS according to a potential difference between its gate electrode and the first electrode.

[0147] In an example embodiment, the eleventh transistor T11 can be referred to as a second write transistor. When the signal of the second scan signal line Gate2 is an active level signal, the signal of the data signal line Data is written to the fifth node N5.

[0148] In an example embodiment, the twelfth transistor T12 and the thirteenth transistor T13 can be referred to as light emitting transistors. When the signal of the second emission signal line EM2 is an active level signal, the twelfth transistor T12 and the thirteenth transistor T13 drive the light emitting device L to emit light by forming a current path of a drive current between the second power supply line VDD2 and the third power supply line VDD.

[0149] In an example embodiment, the fourteenth transistor T14 can be referred to as an anode reset transistor. When the signal of the second reset signal line Reset2 is an active level signal, the signal of the third power supply line VSS is written to the first electrode (anode) of the light emitting device L.

[0150] According to the characteristics of transistors, the transistors can be classified into N-type transistors and P-type transistors. When a transistor is a P-type transistor, the on voltage is a low level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the off voltage is a high level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the on voltage is a high level voltage (e.g., 5V, 10V, or other suitable voltage), and the off voltage is a low level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0151] In an example embodiment, the first transistor T1 to the fourteenth transistor T14 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the fourteenth transistor T14 can include P-type transistors and N-type transistors.

[0152] In an example embodiment, the first transistor T1 to the fourteenth transistor T14 can adopt a low temperature poly-silicon thin film transistor, or can adopt an oxide thin film transistor, or can adopt a low temperature poly-silicon thin film transistor and an oxide thin film transistor. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display device forms a low temperature polycrystalline oxide (LTPO) display device, which can take advantage of both and can achieve low frequency driving, reduce power consumption, and improve display quality.

[0153] In an example embodiment, the third transistor T3 and the eighth transistor T8 are of opposite transistor types.

[0154] In an example embodiment, the fifth transistor T5 and the sixth transistor T6 are of opposite transistor types to the twelfth transistor T12 and the thirteenth transistor T13.

[0155] In an example embodiment, the eighth transistor T8 and the ninth transistor T9 are of opposite transistor types.

[0156] In an example embodiment, the first transistor T1 to the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11, and the fourteenth transistor T14 can be P-type transistors.

[0157] In an example embodiment, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12, and the thirteenth transistor T13 are N-type transistors. The N-type transistors can be oxide thin film transistors or low temperature poly-silicon thin film transistors.

[0158] In an example embodiment, when the signal of the first reset signal line Reset1 is a valid level signal, the signals of the first scan signal line Gate1, the second scan signal line Gate2, the first emission signal line EM1, the second emission signal line EM2, the third scan signal line Gate3, and the second reset signal line Reset2 are invalid level signals.

[0159] In the exemplary embodiment, when the signal of the first scan signal line Gate1 is the active level signal, the signals of the second scan signal line Gate2, the first reset signal line Reset1, the third scan signal line Gate3, the first emission signal line EM1, the second emission signal line EM2, and the second reset signal line Reset2 are the inactive level signals.

[0160] In the exemplary embodiment, when the signal of the second scan signal line Gate2 is the active level signal, the signal of the third scan signal line Gate3 is the active level signal, and the signals of the first scan signal line Gate1, the first reset signal line Reset1, the first emission signal line EM1, the second emission signal line EM2, and the second reset signal line Reset2 are the inactive level signals.

[0161] In the exemplary embodiment, the signals of the first emission signal line EM1 and the second emission signal line EM2 are inverse signals of each other, and when the signal of the first emission signal line EM1 is the active level signal, the signal of the second emission signal line EM2 is the active level signal, and the signals of the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, the third scan signal line Gate3, and the second reset signal line Reset2 are the inactive level signals.

[0162] In the exemplary embodiment, when the signal of the second reset signal line Reset2 is the active level signal, the signal of the third scan signal line Gate3 is the active level signal, and the signals of the first reset signal line Reset1, the first scan signal line Gate1, the second scan signal line Gate2, the first emission signal line EM1, and the second emission signal line EM2 are the inactive level signals.

[0163] In the exemplary embodiment, the occurrence time of the signal of the first scan signal line Gate1 being the active level signal is earlier than the occurrence time of the signal of the second scan signal line Gate2 being the active level signal, and the duration of the signal of the first scan signal line Gate1 being the active level signal is shorter than the duration of the signal of the second scan signal line Gate2 being the active level signal.

[0164] In the exemplary embodiment, when the signal of the first reset signal line Reset1 is the active level signal, the signal of the initial signal line INIT is a first initial signal, and the voltage value of the first initial signal can be equal to the voltage value of the signal of the third power supply line. When the signal of the first reset signal line Reset1 is the inactive level signal, the signal of the initial signal line INIT is a second initial signal, and the voltage value of the second initial signal can be equal to the voltage value of the signal of the first power supply line VDD1.

[0165] In the exemplary embodiment, before the signal of the first light-emitting signal line EM1 is the active level signal, the signal of the control signal line SWP is the first control signal, and the first control signal is a constant voltage signal, the voltage value of the first control signal can be 5 volts to 7 volts, and exemplarily, the voltage value of the first control signal can be 6 volts. When the signal of the first light-emitting signal line EM1 is the active level signal, the signal of the control signal line SWP is the second control signal, and the second control signal is a ramp signal, the voltage value of the second control signal gradually decreases until it decreases to 0 volt. After the signal of the first light-emitting signal line EM1 is the active level signal, the signal of the control signal line SWP returns to the first control signal.

[0166] Figure 9 is a timing diagram of a pixel driving circuit. The working process of the exemplary pixel driving circuit is described below, Figure 8 the exemplary pixel driving circuit of the present disclosure, Figure 8 The pixel driving circuit in the exemplary embodiment includes fourteen transistors (first transistor T1 to fourteenth transistor T14) and three capacitors (first capacitor C1, second capacitor C2 and third capacitor C3), the first transistor T1 to the ninth transistor T9 and the fourteenth transistor T14 are P-type transistors, and the tenth transistor T10 to the thirteenth transistor T13 are N-type transistors.

[0167] In the exemplary embodiment, the working process of the pixel driving circuit can include:

[0168] In the first stage P1, referred to as an initialization stage, the signals of the first reset signal line Reset1, the third scan signal line Gate3 and the second emission signal line EM are low signals, and the signals of the first scan signal line Gate1, the second scan signal line Gate2, the first emission signal line EM1 and the second reset signal line Reset2 are high signals. The signal of the first reset signal line Reset1 is a low signal, the first transistor T1 and the seventh transistor T7 are turned on, the initial signal of the initial signal line INIT is written to the second node N2 through the turned-on first transistor T1, the second node N2 is initialized (reset), the pre-stored voltage in the second node N2 is emptied, the initialization is completed, the initial signal of the initial signal line INIT is written to the first node N1 through the turned-on seventh transistor T7, the first node N1 is initialized (reset), the pre-stored voltage in the first node N1 is emptied, and the initialization is completed. The signals of the first scan signal line Gate1 and the first emission signal line EM1 are high signals, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off, the signal of the second scan signal line Gate2 is a high signal, the ninth transistor T9 and the eleventh transistor T11 are turned off, the signals of the third scan signal line Gate3 and the second emission signal line EM are low signals, the eighth transistor T8, the twelfth transistor T12 and the thirteenth transistor T13 are turned off. At this time, the difference between the voltage values of the signals between the second node N2 and the third node N3 is less than the threshold voltage of the third transistor T3, and the third transistor T3 is turned on. The voltage value of the signal between the first node N1 and the fifth node N5 is greater than the threshold voltage of the tenth transistor T10, and the tenth transistor T10 is turned on. The signal of the second reset signal line Reset2 is a high signal, and the fourteenth transistor T14 is turned off. In this stage, the light emitting device L does not emit light.

[0169] In the second stage P2, referred to as a first data writing stage or a first threshold compensation stage, the signals of the third scan signal line Gate3 and the second emission signal line EM are low signals, and the signals of the first reset signal line Reset1, the second scan signal line Gate2, the first emission signal line EM1 and the second reset signal line Reset2 are high signals. The second stage P2 includes a first sub-stage P21 and a second sub-stage P22, the time of the first sub-stage P21 can be located before, in or after the time of the second sub-stage P22, depending on the position of the pixel driving circuit, Figure 9 The first sub-stage P21 is described by taking the case that the time of the first sub-stage P21 is located before the time of the second sub-stage P22 as an example.

[0170] In the first sub stage P21, the data signal line Data writes a first data signal, the signal of the first scan signal line Gate1 is a low level signal, the second transistor T2 and the fourth transistor T4 are turned on, the first data signal charges to the second node N2 through the turned-on fourth transistor T4, the third node N3, the turned-on third transistor T3, the fourth node N4 and the turned-on second transistor T2, until the voltage value of the signal of the second node N2 meets V2=Vdata1-Vth3, Vdata1 is the voltage value of the first data signal, Vth3 is the threshold voltage of the third transistor, the signals of the first reset signal line Reset1 and the first emitting signal line EM1 are high level signals, the first transistor T1, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. The signal of the second scan signal line Gate2 is a high level signal, the ninth transistor T9 and the eleventh transistor T11 are turned off, the signals of the third scan signal line Gate3 and the second emitting signal line EM are low level signals, the eighth transistor T8, the twelfth transistor T12 and the thirteenth transistor T13 are turned off. The signal of the second reset signal line Reset2 is a high level signal, the fourteenth transistor T14 is turned off. In this stage, the light emitting device L does not emit light.

[0171] In the second sub stage P22, the signal of the first scan signal line Gate1 is a low level signal, the second transistor T2 and the fourth transistor T4 are turned off, the second node N2 keeps the signal of the last stage under the action of the first capacitor C1, the signals of the first reset signal line Reset1 and the first emitting signal line EM1 are high level signals, the first transistor T1, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. The signal of the second scan signal line Gate2 is a high level signal, the ninth transistor T9 and the eleventh transistor T11 are turned off, the signals of the third scan signal line Gate3 and the second emitting signal line EM are low level signals, the eighth transistor T8, the twelfth transistor T12 and the thirteenth transistor T13 are turned off. The signal of the second reset signal line Reset2 is a high level signal, the fourteenth transistor T14 is turned off. In this stage, the light emitting device L does not emit light.

[0172] In the third stage P3, referred to as the second data writing stage or the second threshold compensation stage, the signals of the second scan signal line Gate2 and the second emission signal line EM2 are low level signals, the signals of the first scan signal line Gate1, the first reset signal line Reset1, the third scan signal line Gate3, the first emission signal line EM1 and the second reset signal line Reset2 are high level signals, and the data signal line Data writes the second data signal. The signal of the third scan signal line Gate3 is a high level signal, the eighth transistor T8 is turned on, the signal of the second scan signal line Gate2 is a low level signal, the ninth transistor T9 and the eleventh transistor T11 are turned on, the second data signal is written to the fifth node N5 through the turned-on eleventh transistor T11, and the signal of the fifth node N5 is charged to the first node N1 through the turned-on eighth transistor T8, the turned-on tenth transistor T10, the sixth node N6 and the turned-on ninth transistor T9, until the voltage value of the signal of the first node N1 meets V1=Vdata2+Vth10, wherein Vdata2 is the voltage value of the second data signal, and Vth10 is the threshold voltage of the tenth transistor. The signal of the first scan signal line Gate1 is a high level signal, the second transistor T2 and the fourth transistor T4 are disconnected, the signals of the first reset signal line Reset1 and the first emission signal line EM1 are high level signals, the first transistor T1, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are disconnected. The signal of the second emission signal line EM2 is a low level signal, the twelfth transistor T12 and the thirteenth transistor T13 are disconnected. The signal of the second reset signal line Reset2 is a high level signal, and the fourteenth transistor T14 is disconnected. In this stage, the light emitting device L does not emit light.

[0173] In the fourth stage P4, referred to as the light emitting stage, the signals of the first light emitting signal line EM1 and the third scan signal line Gate3 are low level signals, the signals of the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, the second light emitting signal line EM2 and the second reset signal line Reset2 are high level signals, the signal of the control signal terminal SWP is a ramp signal, and the voltage value of the signal gradually decreases. The signal of the first light emitting signal line EM1 is a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply signal output by the first high level power supply line VDD1 is provided to the first node N1 through the turned-on fifth transistor T5, the third node N3, the third transistor T3, the fourth node N4 and the sixth transistor T6 to provide a driving signal, at this time, the signal of the first node N1 is changed under the action of the second capacitor C2 and the third capacitor C3, so that the voltage value of the signal of the first node N1 satisfies V1=Vdata2+Vth10+ΔV, ΔV is the voltage value of the change, the signal of the second light emitting signal line EM2 is a high level signal, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, and the power supply signal output by the second high level power supply line VDD2 is provided to the seventh node N7 through the turned-on twelfth transistor T12, the fifth node N5, the tenth transistor T10, the sixth node N6 and the thirteenth transistor T13 to provide a driving current, so as to drive the light emitting device L to emit light, the signal of the second reset signal line Reset2 is a high level signal, and the fourteenth transistor T14 is turned off, which does not affect the normal light emission of the light emitting device. Due to the gradual decrease of the signal voltage value of the control signal terminal SWP, the voltage value of the signal of the second node N2 also gradually decreases under the action of the first capacitor C1, and the turn-on degree of the third transistor T3 decreases until it is completely turned off. After the third transistor T3 is completely turned off, the light emitting device L does not emit light.

[0174] In the fifth stage P5, referred to as the reset stage, the signals of the second light emitting signal line EM2 and the second reset signal line Reset2 are low level signals, and the signals of the first scan signal line Gate1, the second scan signal line Gate2, the first light emitting signal line EM1 and the first reset signal line Reset1, and the third scan signal line Gate3 are high level signals. At this time, the first transistor T1 to the seventh transistor T7 and the ninth transistor T9 to the thirteenth transistor T13 are turned off. The signal of the third scan signal line Gate3 is a high level signal, the eighth transistor T8 is turned on, the signal of the second reset signal line Reset2 is a low level signal, the fourteenth transistor T14 is turned on, and the signal of the third power supply line VSS is written to the first electrode of the light emitting device L through the turned-on fourteenth transistor T14 to reset the first electrode of the light emitting device L and empty the internal pre-stored voltage of the light emitting device L.

[0175] In the driving process of the pixel driving circuit, the driving current flowing through the tenth transistor T10 (second driving transistor) is determined by the voltage difference between the gate electrode and the first electrode of the tenth transistor T10. Since the voltage of the first node N1 is Vdata2+Vth10+ΔV, the voltage value V5 of the signal of the fifth node N5 is Vdd2, and Vdd2 is the voltage value of the signal of the second high-level power supply line, the driving current of the tenth transistor T10 is:

[0176] I=K*(Vgs-Vth)2=K*(Vdata2+Vth10+ΔV-Vdd2-Vth10)2=K*(Vdata2+ΔV-Vdd2)2

[0177] wherein I is the driving current flowing through the tenth transistor T10, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the tenth transistor T10.

[0178] In the exemplary embodiment, the display frame displayed by the display substrate where the pixel driving circuit is located includes a plurality of display frames, and the time length of at least one display frame is 8200 microseconds to 8400 microseconds, and exemplarily can be 8300 microseconds.

[0179] In the exemplary embodiment, in one display frame, the time length of the first stage can be 2450 microseconds to 2500 microseconds, and exemplarily can be 2470 microseconds.

[0180] In the exemplary embodiment, in one display frame, the time length of the second stage can be 15 microseconds to 25 microseconds, and exemplarily can be 20 microseconds.

[0181] In the exemplary embodiment, in one display frame, the time length of the third stage can be 15 microseconds to 25 microseconds, and exemplarily can be 20 microseconds.

[0182] In the exemplary embodiment, in one display frame, the time length of the fourth stage can be 5750 microseconds to 5800 microseconds, and exemplarily can be 5770 microseconds.

[0183] In the exemplary embodiment, in one display frame, the time length of the fifth stage can be 15 microseconds to 25 microseconds, and exemplarily can be 20 microseconds.

[0184] As can be seen from the derivation result of the above current formula, in the light emitting stage, the driving current of the tenth transistor T10 is not affected by the threshold voltage of the tenth transistor T10, thereby eliminating the influence of the threshold voltage of the tenth transistor T10 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0185] The present disclosure can quickly charge the first node N1 in the third stage by setting the eighth transistor T8, reduce the response time of the pixel driving circuit to generate a driving current, and be applicable to high-resolution display products. In the present disclosure, all transistors in the time length control sub-circuit are P-type transistors, and the tenth transistor (second driving transistor), the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 in the current control sub-circuit are N-type transistors, which can make the maximum driving current value of the pixel driving circuit stable regardless of the change of the first data signal, and the driving current maintenance rate is greater than 99.99%. A high driving current maintenance rate means that the pixel driving circuit can easily achieve low-frequency driving. Therefore, the pixel driving circuit provided by the present disclosure can not only achieve high-frequency driving, but also achieve low-frequency driving, has a wide range of adaptation, and can also achieve accurate driving.

[0186] Table 1

[0187]

[0188]

[0189] Table 1 is data obtained by simulating and testing the pixel driving circuit provided by the present disclosure. Imax is the maximum driving current value, CHR is the driving current maintenance rate, and Vdata1 is the voltage value of the first data signal. As shown in Table 1, the voltage value of the first data signal is 5.6V, 7.6V, 9.6V, or after initialization, the IMax of the pixel driving circuit has little deviation and is basically stable at 249.99uA, and the CHR is 100%.

[0190] In an exemplary embodiment, the response time of the pixel driving circuit to generate a driving current is 220 microseconds to 270 microseconds, and exemplarily can be 250 microseconds.

[0191] Figure 10 The voltage value of the signal of the second node of the pixel driving circuit changes with time under different voltage values of the first data signal. As shown in FIG. 6, Figure 10 N2_1 is the voltage value of the signal of the second node N2 of the pixel driving circuit when the voltage value of the first data signal is 9.6 volts, N2_2 is the voltage value of the signal of the second node N2 of the pixel driving circuit when the voltage value of the first data signal is 7.6 volts, and N2_3 is the voltage value of the signal of the second node N2 of the pixel driving circuit when the voltage value of the first data signal is 5.6 volts. As shown in FIG. 6, Figure 10 The lower the voltage value of the first data signal of the pixel driving circuit, the lower the voltage value of the signal of the second node N2 of the pixel driving circuit.

[0192] Figure 11This is a curve showing the voltage change over time of the first node signal in the pixel driving circuit under different voltage values ​​of the first data signal. (Example:) Figure 11 As shown, N1_1 is the voltage value of the signal at the first node N1 of the pixel driving circuit when the voltage value of the first data signal is 9.6 volts; N1_2 is the voltage value of the signal at the first node N1 of the pixel driving circuit when the voltage value of the first data signal is 7.6 volts; and N1_3 is the voltage value of the signal at the first node N1 of the pixel driving circuit when the voltage value of the first data signal is 5.6 volts. Figure 11 As shown, the lower the voltage value of the first data signal of the pixel driving circuit, the earlier the voltage value of the signal of the first node N1 of the pixel driving circuit changes.

[0193] Figure 12 The curves show the change in the driving current generated by the pixel driving circuit over time under different voltage values ​​of the first data signal. For example... Figure 12 As shown, I_1 is the driving current value generated by the pixel driving circuit when the voltage value of the first data signal is 9.6 volts, I_2 is the driving current value generated by the pixel driving circuit when the voltage value of the first data signal is 7.6 volts, and I_3 is the driving current value generated by the pixel driving circuit when the voltage value of the first data signal is 5.6 volts. Figure 12 As shown, the lower the voltage value of the first data signal of the pixel driving circuit, the earlier the current value of the driving current generated by the pixel driving circuit is, and the longer the light emission time of the light-emitting device L is. Figure 10 This is a diagram showing partial signal variations in the pixel driving circuit under different first data signals. For example... Figure 10 As shown, N2_1 is the voltage value of the signal at the second node N2 of the pixel driving circuit when the voltage value of the first data signal is 9.6 volts; N2_2 is the voltage value of the signal at the second node N2 of the pixel driving circuit when the voltage value of the first data signal is 7.6 volts; N2_3 is the voltage value of the signal at the second node N2 of the pixel driving circuit when the voltage value of the first data signal is 5.6 volts; N1_1 is the voltage value of the signal at the first node N1 of the pixel driving circuit when the voltage value of the first data signal is 9.6 volts; and N1_2 is the voltage value of the signal at the first node N1 when the voltage value of the first data signal is 7.6 volts. The voltage value of the signal at the first node N1 of the pixel driving circuit at 6 volts; N1_3 is the voltage value of the signal at the first node N1 of the pixel driving circuit at 5.6 volts; I_1 is the current value of the driving current generated by the pixel driving circuit at 9.6 volts; I_2 is the current value of the driving current generated by the pixel driving circuit at 7.6 volts; I_3 is the current value of the driving current generated by the pixel driving circuit at 5.6 volts. Figure 10As shown, the lower the voltage value of the first data signal of the pixel driving circuit, the lower the voltage value of the second node N2 of the pixel driving circuit, the earlier the voltage value of the first node N1 of the pixel driving circuit changes, the earlier the current value of the driving current of the generated dynamic current of the pixel driving circuit, and the longer the light emitting time of the light emitting device L.

[0194] The display device can include a plurality of sub-modules, at least one of the sub-modules including a plurality of rows of sub-pixels, at least one of the sub-pixels including a pixel driving circuit and a light emitting device driven by the pixel driving circuit.

[0195] The pixel driving circuit is the pixel driving circuit provided by any one of the preceding embodiments, and has similar implementation principles and implementation effects, which will not be described here again.

[0196] In exemplary embodiments, the display device can be any device that displays both motion (e.g., video) and still (e.g., still images) and both text and graphics. More specifically, the display device can be one of, implemented in, or associated with a variety of electronic devices such as, but not limited to, mobile phones, VR devices, AR devices, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projections, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry), and the like. Embodiments of the present disclosure are not limited in this respect.

[0197] In exemplary embodiments, FIG. 1113 is a timing diagram of the operation of a sub-module. FIG. 1113 is described by way of example with the sub-module including M rows of sub-pixels, where i = 1, 2, …, M. As shown in FIG. 1113, the signals of any one of the first reset signal line Reset1, the second reset signal line Reset2, the second scan signal line Gate2, the third scan signal line Gate3, the first light emitting signal line EM1, and the second light emitting signal line EM2 connected to the pixel driving circuits of all the sub-pixels in the same sub-module are the same, i.e., the sub-pixels in the same sub-module emit light at the same time.

[0198] As shown in FIG. 1113, the first time t1 corresponding to the pixel driving circuit of different row sub-pixels in the same sub-module does not overlap, and the first time t1 corresponding to the pixel driving circuit is the time when the signal of the first scan signal line connected to the pixel driving circuit is the active level signal.

[0199] As shown in FIG. 1113, the latest time in the first time corresponding to the pixel driving circuit of all sub-pixels in the same sub-module is the second time t2, and the time when the signal of the second scan signal line connected to the pixel driving circuit of any sub-pixel in the same sub-module is the active level signal is the third time t3; the second time t2 and the third time t3 do not overlap, and the second time t2 is earlier than the third time t3.

[0200] In an exemplary embodiment, the sum of the first time corresponding to the pixel driving circuit of all row sub-pixels in the same sub-module is the length of the second stage of any pixel driving circuit.

[0201] The pixel driving circuit provided by the embodiment of the present disclosure also provides a driving method of the pixel driving circuit, which is configured to drive the pixel driving circuit. The driving method of the pixel driving circuit can include:

[0202] The time length control sub-circuit is configured to provide a control signal to the first node under the control of the signals of the first scan signal line, the first reset signal line, the first light-emitting signal line, the control signal line, the data signal line, the initial signal line and the first power supply line.

[0203] The current control sub-circuit is configured to provide a driving current to the first electrode of the light-emitting device under the control of the signals of the first node, the second scan signal line, the second reset signal line, the second light-emitting signal line, the data signal line and the second power supply line.

[0204] The pixel driving circuit provided by any one of the foregoing embodiments has similar implementation principles and effects, and thus will not be described here.

[0205] The drawings in the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the general design.

[0206] Although the embodiments of the present disclosure are as described above, the content described above is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A pixel driving circuit configured to drive a light emitting device to emit light, the light emitting device comprising: The first electrode and the second electrode, the pixel driving circuit comprises: a current control sub-circuit and a time length control sub-circuit, the current control sub-circuit comprises: a second node control sub-circuit; The time length control sub-circuit is electrically connected with a first scan signal line, a first reset signal line, a first light-emitting signal line, a control signal line, a data signal line, an initial signal line, a first power supply line and a first node respectively, and is configured to provide a control signal to the first node under the control of signals of the first scan signal line, the first reset signal line, the first light-emitting signal line, the control signal line, the data signal line, the initial signal line and the first power supply line; The current control sub-circuit is electrically connected with a second scan signal line, a third scan signal line, a second light-emitting signal line, a data signal line, a second power supply line, the first node and a first electrode of the light-emitting device respectively, and is configured to provide a driving current to the first electrode of the light-emitting device under the control of signals of the first node, the second scan signal line, the third scan signal line, the second light-emitting signal line, the data signal line and the second power supply line; The second electrode of the light-emitting device is electrically connected with a third power supply line; The second node control sub-circuit is electrically connected with the second scan signal line, the third scan signal line, the data signal line, the first node, a fifth node and a sixth node respectively, and is configured to drive a signal of the first node under the control of signals of the second scan signal line, the third scan signal line, the data signal line, the fifth node and the sixth node; The second node control sub-circuit comprises: an eighth transistor, a ninth transistor and an eleventh transistor; The control electrode of the eighth transistor is electrically connected with the third scan signal line, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the fifth node; The control electrode of the ninth transistor is electrically connected with the second scan signal line, the first electrode of the ninth transistor is electrically connected with the first node, and the second electrode of the ninth transistor is electrically connected with the sixth node; The control electrode of the eleventh transistor is electrically connected with the second scan signal line, the first electrode of the eleventh transistor is electrically connected with the data signal line, and the second electrode of the eleventh transistor is electrically connected with the fifth node.

2. The pixel driving circuit according to claim 1, wherein The time length control sub-circuit comprises: a first node control sub-circuit, a first driving sub-circuit, a first output control sub-circuit and a first storage sub-circuit; The first node control sub-circuit is electrically connected with a first scan signal line, a first reset signal line, an initial signal line, a data signal line, a first node, a second node, a third node and a fourth node respectively, and is configured to drive a signal of the second node under the control of signals of the first scan signal line and the data signal line, and provide a signal of the initial signal line to the first node and the second node under the control of a signal of the first reset signal line; The first driving sub-circuit is electrically connected with the second node, the third node and the fourth node respectively, and is configured to provide a driving signal to the fourth node under the control of signals of the second node and the third node; The first output control sub-circuit is electrically connected with the first light-emitting signal line, the first node, the third node, the fourth node and the first power supply line respectively, and is configured to provide the signal of the first power supply line to the third node and provide the signal of the fourth node to the first node under the control of the signal of the first light-emitting signal line. The first storage sub-circuit is electrically connected with the second node and the control signal line respectively, and is configured to store the voltage difference between the signals of the second node and the control signal line.

3. The pixel driving circuit according to claim 1 or 2, wherein The current control sub-circuit further comprises a second driving sub-circuit, a second output control sub-circuit and a second storage sub-circuit. The second driving sub-circuit is electrically connected with the first node, the fifth node and the sixth node respectively, and is configured to provide the driving current to the sixth node under the control of the signals of the first node and the fifth node. The second output control sub-circuit is electrically connected with the second light-emitting signal line, the second power supply line, the fifth node, the sixth node and the first electrode of the light-emitting device respectively, and is configured to provide the signal of the second power supply line to the fifth node and provide the driving current to the first electrode of the light-emitting device under the control of the signal of the second light-emitting signal line. The second storage sub-circuit is electrically connected with the first node, the second power supply line and the first electrode of the light-emitting device respectively, and is configured to store the voltage difference between the signal of the first node and the signal of the second power supply line and the voltage difference between the signal of the first node and the signal of the first electrode of the light-emitting device.

4. The pixel driving circuit of claim 1, further comprising: The reset sub-circuit is electrically connected with the second reset signal line, the first electrode of the light-emitting device and the second electrode of the light-emitting device respectively, and is configured to provide the signal of the second electrode of the light-emitting device to the first electrode of the light-emitting device under the control of the signal of the second reset signal line. The first node control sub-circuit comprises a first transistor, a second transistor, a fourth transistor and a seventh transistor, the first driving sub-circuit comprises a third transistor, the first output control sub-circuit comprises a fifth transistor and a sixth transistor.

5. The pixel driving circuit of claim 2, wherein, The control electrode of the first transistor is electrically connected with the first reset signal line, the first electrode of the first transistor is electrically connected with the initial signal line, and the second electrode of the first transistor is electrically connected with the second node. The control electrode of the second transistor is electrically connected with the first scan signal line, the first electrode of the second transistor is electrically connected with the second node, and the second electrode of the second transistor is electrically connected with the fourth node. The control electrode of the third transistor is electrically connected with the second node, the first electrode of the third transistor is electrically connected with the third node, and the second electrode of the third transistor is electrically connected with the fourth node. The control electrode of the fourth transistor is electrically connected with the first scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the third node. The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the third node. The control electrode of the sixth transistor is electrically connected with the first light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first node. ​ The control electrode of the seventh transistor is electrically connected with the first reset signal line, the first electrode of the seventh transistor is electrically connected with the initial signal line, and the second electrode of the seventh transistor is electrically connected with the first node.

6. The pixel driving circuit of claim 2, wherein, The first storage sub-circuit comprises a first capacitor; The first end of the first capacitor is electrically connected with the control signal line, and the second end of the first capacitor is electrically connected with the second node.

7. The pixel driving circuit of claim 3, wherein, The second driving sub-circuit comprises a tenth transistor, and the second output control sub-circuit comprises a twelfth transistor and a thirteenth transistor; The control electrode of the tenth transistor is electrically connected with the first node, the first electrode of the tenth transistor is electrically connected with the fifth node, and the second electrode of the tenth transistor is electrically connected with the sixth node; The control electrode of the twelfth transistor is electrically connected with the second light-emitting signal line, the first electrode of the twelfth transistor is electrically connected with the second power supply line, and the second electrode of the twelfth transistor is electrically connected with the fifth node; The control electrode of the thirteenth transistor is electrically connected with the second light-emitting signal line, the first electrode of the thirteenth transistor is electrically connected with the sixth node, and the second electrode of the thirteenth transistor is electrically connected with the first electrode of the light-emitting device.

8. The pixel driving circuit of claim 3, wherein, The second storage sub-circuit comprises a second capacitor and a third capacitor; The first end of the second capacitor is electrically connected with the second power supply line, and the second end of the second capacitor is electrically connected with the first node. The first end of the third capacitor is electrically connected with the first node, and the second end of the third capacitor is electrically connected with the first electrode of the light-emitting device.

9. The pixel driving circuit of claim 4, wherein, The reset sub-circuit comprises a fourteenth transistor; The control electrode of the fourteenth transistor is electrically connected with the second reset signal line, the first electrode of the fourteenth transistor is electrically connected with the first electrode of the light-emitting device, and the second electrode of the fourteenth transistor is electrically connected with the second electrode of the light-emitting device.

10. The pixel driving circuit of claim 1, further comprising: The reset sub-circuit, the time length control sub-circuit comprises a first transistor to a seventh transistor and a first capacitor, the current control sub-circuit comprises an eighth transistor to a thirteenth transistor, a second capacitor and a third capacitor, and the reset sub-circuit comprises a fourteenth transistor; The control electrode of the first transistor is electrically connected with the first reset signal line, the first electrode of the first transistor is electrically connected with the initial signal line, and the second electrode of the first transistor is electrically connected with the second node. The control electrode of the second transistor is electrically connected with the first scan signal line, the first electrode of the second transistor is electrically connected with the second node, and the second electrode of the second transistor is electrically connected with the fourth node. The control electrode of the third transistor is electrically connected with the second node, the first electrode of the third transistor is electrically connected with the third node, and the second electrode of the third transistor is electrically connected with the fourth node. The control electrode of the fourth transistor is electrically connected with the first scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the third node. The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the third node. The control electrode of the sixth transistor is electrically connected with the first light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first node. A control electrode of the seventh transistor is electrically connected with the first reset signal line, a first electrode of the seventh transistor is electrically connected with the initial signal line, and a second electrode of the seventh transistor is electrically connected with the first node; A control electrode of the eighth transistor is electrically connected with the third scan signal line, a first electrode of the eighth transistor is electrically connected with the first node, and a second electrode of the eighth transistor is electrically connected with the fifth node; A control electrode of the ninth transistor is electrically connected with the second scan signal line, a first electrode of the ninth transistor is electrically connected with the first node, and a second electrode of the ninth transistor is electrically connected with the sixth node; A control electrode of the tenth transistor is electrically connected with the first node, a first electrode of the tenth transistor is electrically connected with the fifth node, and a second electrode of the tenth transistor is electrically connected with the sixth node; A control electrode of the eleventh transistor is electrically connected with the second scan signal line, a first electrode of the eleventh transistor is electrically connected with the data signal line, and a second electrode of the eleventh transistor is electrically connected with the fifth node; A control electrode of the twelfth transistor is electrically connected with the second emitting signal line, a first electrode of the twelfth transistor is electrically connected with the second power supply line, and a second electrode of the twelfth transistor is electrically connected with the fifth node; A control electrode of the thirteenth transistor is electrically connected with the second emitting signal line, a first electrode of the thirteenth transistor is electrically connected with the sixth node, and a second electrode of the thirteenth transistor is electrically connected with the first electrode of the light emitting device; A control electrode of the fourteenth transistor is electrically connected with the second reset signal line, a first electrode of the fourteenth transistor is electrically connected with the first electrode of the light emitting device, and a second electrode of the fourteenth transistor is electrically connected with the second electrode of the light emitting device; A first end of the first capacitor is electrically connected with the control signal end, and a second end of the first capacitor is electrically connected with the second node; A first end of the second capacitor is electrically connected with the second power supply line, and a second end of the second capacitor is electrically connected with the first node; A first end of the third capacitor is electrically connected with the first node, and a second end of the third capacitor is electrically connected with the first electrode of the light emitting device.

11. The pixel driving circuit of claim 10, wherein, The transistor types of the third transistor and the eighth transistor are opposite, the transistor types of the fifth transistor and the sixth transistor are opposite to the transistor types of the twelfth transistor and the thirteenth transistor, and the transistor types of the eighth transistor and the ninth transistor are opposite.

12. The pixel driving circuit according to claim 10 or 11, wherein, The first transistor to the seventh transistor, the ninth transistor, the eleventh transistor and the fourteenth transistor are P-type transistors, and the eighth transistor, the tenth transistor, the twelfth transistor and the thirteenth transistor are N-type transistors.

13. The pixel driving circuit of claim 10, wherein, When the signal of the first reset signal line is an effective level signal, the signals of the first scan signal line, the second scan signal line, the first emitting signal line, the second emitting signal line, the third scan signal line and the second reset signal line are invalid level signals; When the signal of the first scan signal line is an effective level signal, the signals of the second scan signal line, the first reset signal line, the third scan signal line, the first emitting signal line, the second emitting signal line and the second reset signal line are invalid level signals; a signal of the third scan signal line is an effective level signal when a signal of the second reset signal line is an effective level signal, and signals of the first reset signal line, the first scan signal line, the second scan signal line, the first light-emitting signal line, and the second light-emitting signal line are invalid level signals. a signal of the first light-emitting signal line is an effective level signal when a signal of the control signal line is a ramp signal and a voltage value gradually decreases; a signal of the first scan signal line is an effective level signal when a signal of the second scan signal line is an effective level signal, and a duration of the signal of the first scan signal line being the effective level signal is less than a duration of the signal of the second scan signal line being the effective level signal.

14. The pixel driving circuit of claim 13, wherein, a plurality of sub-modules, at least one of the sub-modules comprising: a plurality of rows of sub-pixels, at least one of the sub-pixels comprising: the pixel driving circuit according to any one of claims 1 to 14 and the light-emitting device driven by the pixel driving circuit. signals of any one of the first reset signal line, the third scan signal line, the second reset signal line, the second scan signal line, the first light-emitting signal line, and the second light-emitting signal line connected to the pixel driving circuit of all the sub-pixels in the same sub-module are the same; 15. A display device comprising: corresponding first times of the pixel driving circuits of different rows of sub-pixels in the same sub-module do not overlap, the corresponding first time of the pixel driving circuit being a time when a signal of the first scan signal line connected to the pixel driving circuit is an effective level signal; 16. The display device of claim 15, wherein, a latest time in the corresponding first times of the pixel driving circuits of all the sub-pixels in the same sub-module is a second time, and a time when a signal of the second scan signal line connected to the pixel driving circuit of any one of the sub-pixels in the same sub-module is an effective level signal is a third time; the second time and the third time do not overlap, and the second time is earlier than the third time.

17. A driving method of a pixel driving circuit, configured to drive the pixel driving circuit according to any one of claims 1 to 14; the time length control sub-circuit is configured to provide a control signal to the first node under control of signals of the first scan signal line, the first reset signal line, the first light-emitting signal line, the control signal line, the data signal line, the initial signal line, and the first power supply line. ​ ​ The current control sub-circuit is configured to provide a driving current to the first electrode of the light emitting device under the control of signals of the first node, the second scan signal line, the third scan signal line, the second light emitting signal line, the data signal line, and the second power supply line.

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