Charging unit and charging pile

Abstract

This application relates to the field of charging pile technology, disclosing a charging host and a charging pile. The charging host includes a power output unit, a switch matrix unit, a control unit, and a switch interlocking unit. Each switch in the switch matrix unit is configured with a switch number. The switch interlocking unit includes at least two interlocking circuits. Interlocking circuits anchored to the same switch number but belonging to different switch interlocking units are electrically connected on the same locking bus. The target interlocking circuit responds to an action signal, controls the target switch to act, and transmits the interlocking signal through the locking bus. The reference interlocking circuit responds to the interlocking signal and controls the reference switch not to act. This embodiment avoids the short circuit phenomenon caused by different switches belonging to different switch matrix units but anchored to the same power output unit acting simultaneously, and uses a hardware circuit to complete the above interlocking operation, resulting in high interlocking efficiency.

Description

Technical Field

[0001] This application relates to the field of charging pile technology, and in particular to a charging host and a charging pile. Background Technology

[0002] With the development of new energy technologies, more and more charging piles are being deployed on city streets. These charging piles have power distribution capabilities, supporting multiple outputs. Related technologies flexibly select multiple switches within the charging pile to couple the outputs of multiple power output units, thus achieving flexible power distribution. However, to accommodate this power distribution flexibility, the charging piles provided by these technologies require an increasing number of switches. Furthermore, when a charging pile supports multiple outputs, at least two switches belonging to different power output terminals but anchored to the same power output unit are prone to closing simultaneously, leading to short circuits and potentially causing safety accidents. Summary of the Invention

[0003] To address the aforementioned technical problems, this application provides a charging host and a charging pile to solve the technical problem that short circuits are prone to occur in related technologies.

[0004] In a first aspect, embodiments of this application provide a charging host, comprising:

[0005] At least two power output units;

[0006] At least two switch matrix units, each of the switch matrix units includes at least two switches connected in parallel with each other, each switch in the switch matrix unit is configured with a switch number, and switches with the same switch number but belonging to different switch matrix units are electrically connected to the bus of the same power output unit;

[0007] The control unit is used to send action signals;

[0008] At least two switch interlocking units are provided, each switch interlocking unit corresponds to a switch matrix unit, each switch interlocking unit includes at least two interlocking circuits, one interlocking circuit is electrically connected to a switch and also electrically connected to the control unit, interlocking circuits anchored to the same switch number but belonging to different switch interlocking units are electrically connected on the same locking bus, the target interlocking circuit responds to the action signal, controls the target switch to act and transmits the interlocking signal through the locking bus, the reference interlocking circuit responds to the interlocking signal and controls the reference switch not to act, the target interlocking circuit is one of the interlocking circuits, the target switch is the switch electrically connected to the target interlocking circuit, the reference interlocking circuit is the interlocking circuit electrically connected to the target interlocking circuit on the same locking bus, and the reference switch is the switch electrically connected to the reference interlocking circuit.

[0009] Optionally, the interlock circuit includes:

[0010] A switch control circuit is electrically connected to the control unit.

[0011] An interlock trigger circuit is electrically connected to the switch control circuit. When the switch control circuit detects the action signal, it controls the switch electrically connected to it to operate and transmits an interlock signal through the interlock bus. The interlock trigger circuit also controls the switch control circuit to enter the working state based on the interlock signal feedback. When the interlock trigger circuit detects the interlock signal through the interlock bus, it controls the switch control circuit to enter the non-working state based on the interlock signal feedback.

[0012] Optionally, the interlock trigger circuit includes:

[0013] A signal transmission circuit includes a first node and a locking node. The signal transmission circuit is electrically connected to the switch control circuit at the first node and electrically connected to the locking bus at the locking node. When the switch control circuit detects the action signal, the switch control circuit outputs an interlock signal at the first node. The signal transmission circuit responds to the interlock signal by transmitting the interlock signal to the locking bus through the locking node. When the switch control circuit does not detect the action signal, the voltage of the first node is a first voltage.

[0014] A bias control circuit includes a second node. The bias control circuit is electrically connected to the signal transmission circuit at the first node. When the bias control circuit detects the interlock signal at the first node, the bias control circuit biases the voltage of the second node to a second voltage. When the bias control circuit detects the first voltage at the first node, the bias control circuit biases the voltage of the second node to a third voltage.

[0015] An interlocking feedback circuit includes a third node. The interlocking feedback circuit is electrically connected to the bias control circuit and the signal transmission circuit at the second node, and electrically connected to the switch control circuit at the third node. When the interlocking feedback circuit detects the second voltage at the second node, it transmits a fourth voltage through the third node, and the switch control circuit responds to the fourth voltage to maintain its operating state. When the interlocking feedback circuit detects the third voltage or an interlock signal transmitted through the interlock bus at the second node, it transmits a fifth voltage through the third node, and the switch control circuit responds to the fifth voltage to enter a non-operating state.

[0016] Optionally, the bias control circuit includes a first transistor, the base of which is used to detect the voltage of the first node, the emitter is grounded, and the collector is electrically connected to the second node. When the first transistor detects the interlock signal, the first transistor enters a conducting state to bias the voltage of the second node to a second voltage; when the first transistor detects the first voltage at the first node, the first transistor enters a turning-off state to bias the voltage of the second node to a third voltage.

[0017] Optionally, the interlock feedback circuit includes a second transistor, the base of which is used to detect the voltage of the second node, the emitter is grounded, and the collector is electrically connected to the third node. The third node is configured to receive a preset voltage. When the second transistor detects the second voltage at the second node, the second transistor enters a turn-off state and transmits a fourth voltage through the third node. The switch control circuit responds to the fourth voltage and maintains its operating state. When the second transistor detects the third voltage at the second node, the second transistor enters a turn-on state and transmits a fifth voltage through the third node. The switch control circuit responds to the fifth voltage and is in a non-operating state.

[0018] Optionally, the signal transmission circuit includes:

[0019] A signal isolation circuit is electrically connected between the first node and the locking node and is electrically connected to the switch control circuit at the first node. It is used to isolate the signals transmitted by the locking bus. When the signal isolation circuit detects the interlock signal at the first node, the signal isolation circuit transmits the interlock signal to the locking bus through the locking node.

[0020] A voltage divider circuit is electrically connected between the locking node and the second node.

[0021] Optionally, the signal isolation circuit includes a first diode and a second diode connected in parallel, with the anodes of the first diode and the second diode both electrically connected to the first node, and the cathodes of the first diode and the second diode both electrically connected to the latching node.

[0022] Optionally, the switch control circuit includes:

[0023] A switch driving circuit is electrically connected to the switch and electrically connected to the signal transmission circuit at the first node;

[0024] A switch selection circuit is electrically connected to the interlock feedback circuit and the control unit at the third node. When the switch selection circuit detects the action signal, it triggers the switch driving circuit to operate the switch and outputs an interlock signal at the first node. When the switch selection circuit does not detect the action signal, it stops triggering the switch driving circuit to operate the switch, so as to bias the voltage of the first node to a first voltage.

[0025] Optionally, the action signal includes a first switch signal and a second switch signal, the switch driving circuit includes a switch driving chip, the switch driving chip includes a first signal terminal, a second signal terminal, a first driving terminal and a second driving terminal, the switch is electrically connected between the first driving terminal and the second driving terminal, and the switch selection circuit includes a first switch circuit and a second switch circuit.

[0026] The first switching circuit is electrically connected to the switch driver chip at the first signal terminal and is also electrically connected to the control unit and the interlock feedback circuit respectively. It is used to send a first trigger signal to the switch driver chip in response to the first switching signal and the fourth voltage, or to send a first stop signal to the switch driver chip in response to the fifth voltage.

[0027] The second switching circuit is electrically connected to the switch driver chip and the control unit at the second signal terminal. It is used to send a second trigger signal to the switch driver chip in response to the second switching signal and the fifth voltage, so that the switch driver chip can operate the switch according to the first trigger signal and the second trigger signal and output an interlock signal at the first node. Alternatively, it can send a second stop signal to the switch driver chip in response to the fifth voltage, so that the switch driver chip is in a non-operating state according to the first stop signal and the second stop signal.

[0028] Optionally, the first switching circuit includes a third transistor, the base of which is used to detect the voltage of the third node, the emitter is electrically connected to the first signal terminal, and the collector is grounded;

[0029] The second switching circuit includes a fourth transistor, the base of which is used to detect the voltage of the third node, the emitter is electrically connected to the second signal terminal, and the collector is grounded.

[0030] Optionally, the interlock circuit further includes a state detection circuit, which is electrically connected to the switch control circuit and the control unit at a preset first node, and is used to detect the switching state of the switch.

[0031] Optionally, the control unit includes at least two switch controllers, one switch controller corresponding to one switch interlocking unit, and the switch controllers are electrically connected to all interlocking circuits in the switch interlocking unit respectively.

[0032] In a second aspect, embodiments of this application provide a charging pile, comprising:

[0033] Charging terminal;

[0034] The aforementioned charging host is electrically connected to the charging terminal.

[0035] Compared with the prior art, in the charging host of this application embodiment, each switch matrix unit includes at least two switches connected in parallel. Each switch in the switch matrix unit is configured with a switch number. Switches with the same switch number but belonging to different switch matrix units are electrically connected to the same bus of the power output unit. The control unit is used to send an action signal. One switch interlock unit corresponds to one switch matrix unit. Each switch interlock unit includes at least two interlock circuits. One interlock circuit is electrically connected to a switch and also electrically connected to the control unit. Interlock circuits with the same switch number but belonging to different switch interlock units are electrically connected to the same locking bus. The interlock circuit responds to the action signal, controlling the target switch to operate and transmitting the interlock signal through the interlock bus. The reference interlock circuit responds to the interlock signal, controlling the reference switch not to operate. Therefore, different switches belonging to different switch matrix units but anchored to the same power output unit will not operate simultaneously. Only the switch corresponding to receiving the action signal can operate; the switch corresponding to not receiving the action signal automatically remains inactive. Thus, the two types of switches enter an interlocked state. This avoids the simultaneous operation of different switches belonging to different switch matrix units but anchored to the same power output unit, which could lead to a short circuit, thereby improving the safety and reliability of the charging host. In addition, the embodiments of this application use hardware circuits to complete the above interlock operation. Compared with software interlocking methods, hardware interlocking is faster and more efficient. Attached Figure Description

[0036] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0037] Figure 1 This is a schematic diagram of the structure of a charging pile provided in an embodiment of this application;

[0038] Figure 2 A schematic diagram of the circuit structure of a charging host provided in an embodiment of this application;

[0039] Figure 3 A schematic diagram of the circuit structure of a charging host provided for another embodiment of this application;

[0040] Figure 4 A schematic diagram of the circuit structure of a charging host provided in another embodiment of this application;

[0041] Figure 5 A schematic diagram of the circuit structure of a charging host provided in another embodiment of this application;

[0042] Figure 6 A schematic diagram of the circuit structure of a charging host provided in another embodiment of this application;

[0043] Figure 7 A schematic diagram of the circuit structure of a charging host provided in another embodiment of this application;

[0044] Figure 8 A schematic diagram of the circuit structure of a charging host provided in another embodiment of this application;

[0045] Figure 9 A detailed circuit diagram of the signal transmission circuit, bias control circuit, and interlock feedback circuit provided in the embodiments of this application;

[0046] Figure 10 A schematic diagram of the circuit structure of a charging host provided in another embodiment of this application;

[0047] Figure 11 A schematic diagram of the circuit structure of a charging host provided in another embodiment of this application;

[0048] Figure 12 A detailed circuit diagram of the first switching circuit, the second switching circuit, and the state detection circuit provided in the embodiments of this application;

[0049] Figure 13 A schematic diagram of the circuit structure of a charging host provided in another embodiment of this application;

[0050] Figure 14 A schematic diagram of the circuit structure of a charging host provided in another embodiment of this application;

[0051] Figure 15 This is a schematic diagram of an interlock circuit provided in an embodiment of this application. Detailed Implementation

[0052] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "electrically connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0053] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. Furthermore, technical features involved in the different embodiments of this application described below may be combined with each other as long as they do not conflict with each other.

[0054] This application provides a charging pile; please refer to the embodiments therein. Figure 1 The charging pile 100 includes a charging terminal 200 and a charging host 300. The charging host 300 is electrically connected to the charging terminal 200 and can provide charging power to the charging terminal 200.

[0055] The charging terminal 200 is used to provide the charging power of the charging host 300 to the electric vehicle. The charging terminal 200 may be equipped with one charging gun or two or more charging guns.

[0056] The charging host 300 is used to convert external power into charging power and transmit the charging power to the charging terminal 200. The charging power can be AC ​​power or DC power. It is understood that the number of charging terminals electrically connected to the charging host 300 can be one or more, and there is no limit to the number of charging terminals 200.

[0057] Please see Figure 2 The charging host 300 includes at least two power output units 31, at least two switch matrix units 32, a control unit 33, and at least two switch interlock units 34.

[0058] The power output unit 31 is used to output power at a preset power supply value. Each power output unit 31 is equipped with a bus, and the power output unit 31 can output the preset power supply value through the bus. The preset power supply value can be customized by the designer according to business needs, for example, the preset power supply value is 60kW.

[0059] The switch matrix unit 32 includes at least two switches connected in parallel. In each switch matrix unit 32, one switch is electrically connected to a power output unit 31. In each switch matrix unit 32, one end of each switch is electrically connected to the bus of the corresponding power output unit 31, and the other ends of all switches are electrically connected to the same node.

[0060] Each switch in the switch matrix unit 32 is assigned a switch number. Switches with the same switch number but belonging to different switch matrix units are electrically connected to the bus of the same power output unit.

[0061] Please see Figure 3 The first switch matrix unit 321 includes a first switch K1 (switch number 1), a second switch K2 (switch number 2), and a third switch K3 (switch number 3). The second switch matrix unit 322 includes a first switch K1 (switch number 1), a second switch K2 (switch number 2), and a third switch K3 (switch number 3). The third switch matrix unit 323 includes a first switch K1 (switch number 1), a second switch K2 (switch number 2), and a third switch K3 (switch number 3).

[0062] The first switch K1 of the first switch matrix unit 321, the first switch K1 of the second switch matrix unit 322, and the first switch K1 of the third switch matrix unit 323 are all electrically connected to the bus of the first power output unit 311. Similarly, the second switches K2 of the second switch matrix unit 322 and the second switch K2 of the third switch matrix unit 323 are all electrically connected to the bus of the second power output unit 312. The third switch K3 of the third switch matrix unit 323, the third switch K3 of the second switch matrix unit 322, and the third switch K3 of the third switch matrix unit 323 are all electrically connected to the bus of the third power output unit 313.

[0063] It is understandable that the switch can be a contactor, a relay, or other type of switching device.

[0064] Control unit 33 is used to send action signals, which can be signals encoded according to preset rules, as shown in Table 1:

[0065] Table 1

[0066] Action signal / non-action signal switch status 10 closure 01 disconnect 00 No action 11 No action

[0067] As shown in Table 1, the action signal "10" is used to indicate that the switch is closed, the action signal "01" is used to indicate that the switch is open, and the non-action signals "00" and "11" are used to indicate that the switch is not activated.

[0068] The switch interlock unit 34 is used to control any two switches belonging to different switch matrix units 32 but anchored to the same power output unit 31 to prevent them from closing simultaneously. Each switch interlock unit 34 corresponds to one switch matrix unit 32. Each switch interlock unit 34 includes at least two interlock circuits. One interlock circuit is electrically connected to a switch and also electrically connected to the control unit 33. Interlock circuits anchored to the same switch number but belonging to different switch interlock units 34 are electrically connected to the same interlock bus.

[0069] Please see Figure 4 The first switch interlock unit 341 corresponds to the first switch matrix unit 321. Similarly, the second switch interlock unit 342 corresponds to the second switch matrix unit 322, and the third switch interlock unit 343 corresponds to the third switch matrix unit 323.

[0070] The first switch interlocking unit 341 includes a first interlocking circuit 3411, a second interlocking circuit 3412, and a third interlocking circuit 3413, which are electrically connected to the control unit 33 respectively. The first interlocking circuit 3411 is electrically connected to the first switch K1 of the first switch matrix unit 321, the second interlocking circuit 3412 is electrically connected to the second switch K2 of the first switch matrix unit 321, and the third interlocking circuit 3413 is electrically connected to the third switch K3 of the first switch matrix unit 321.

[0071] Similarly, the second switch interlocking unit 342 includes a fourth interlocking circuit 3421, a fifth interlocking circuit 3422, and a sixth interlocking circuit 3423, which are electrically connected to the control unit 33 respectively. The fourth interlocking circuit 3421 is electrically connected to the first switch K1 of the second switch matrix unit 322, the fifth interlocking circuit 3422 is electrically connected to the second switch K2 of the second switch matrix unit 322, and the sixth interlocking circuit 3423 is electrically connected to the third switch K3 of the second switch matrix unit 322.

[0072] The third switch interlocking unit 343 includes a seventh interlocking circuit 3431, an eighth interlocking circuit 3432, and a ninth interlocking circuit 3433, which are electrically connected to the control unit 33 respectively. The seventh interlocking circuit 3431 is electrically connected to the first switch K1 of the third switch matrix unit 323, the eighth interlocking circuit 3432 is electrically connected to the second switch K2 of the second switch matrix unit 323, and the ninth interlocking circuit 3433 is electrically connected to the third switch K3 of the second switch matrix unit 323.

[0073] The first interlock circuit 3411, the fourth interlock circuit 3421, and the seventh interlock circuit 3431 belong to different switch interlock units, but the switch numbers anchored to them are the same, all anchoring to switch number 1 in their respective switch matrix units. In addition, the first interlock circuit 3411, the fourth interlock circuit 3421, and the seventh interlock circuit 3431 are all electrically connected to the first interlock bus L1.

[0074] Similarly, the second interlock circuit 3412, the fifth interlock circuit 3422, and the eighth interlock circuit 3432 are all anchored to switch number 2 in their respective switch matrix units. Furthermore, the second interlock circuit 3412, the fifth interlock circuit 3422, and the eighth interlock circuit 3432 are all electrically connected to the second interlock bus L2.

[0075] Similarly, the third interlock circuit 3413, the sixth interlock circuit 3423, and the ninth interlock circuit 3433 are all anchored to switch number 3 in their respective switch matrix units. Furthermore, the third interlock circuit 3413, the sixth interlock circuit 3423, and the ninth interlock circuit 3433 are all electrically connected to the third interlock bus L3.

[0076] In this embodiment, the target interlock circuit responds to the action signal, controls the target switch to operate, and transmits the interlock signal through the interlock bus. The reference interlock circuit responds to the interlock signal and controls the reference switch not to operate. The target interlock circuit is one of the interlock circuits. The target switch is a switch electrically connected to the target interlock circuit. The reference interlock circuit is an interlock circuit electrically connected to the target interlock circuit on the same interlock bus. The reference switch is a switch electrically connected to the reference interlock circuit.

[0077] For example, the control unit 33 selects the first interlock circuit 3411 as the target interlock circuit among the various interlock circuits. Therefore, the first switch K1 of the first switch matrix unit 321 is the target switch. Since the fourth interlock circuit 3421 and the seventh interlock circuit 3431 are both electrically connected to the first locking bus L1, the fourth interlock circuit 3421 and the seventh interlock circuit 3431 are both reference interlock circuits. The first switch K1 of the second switch matrix unit 322 and the first switch K1 of the third switch matrix unit 323 are both reference switches.

[0078] The control unit 33 sends an action signal "10" to the first interlock circuit 3411. The first interlock circuit 3411 responds to the action signal "10" by closing the first switch K1 of the first switch matrix unit 321 and transmitting an interlock signal through the first interlock bus L1. The fourth interlock circuit 3421 and the seventh interlock circuit 3431 both respond to the interlock signal and respectively open the first switch K1 of the second switch matrix unit 322 and the first switch K1 of the third switch matrix unit 323. The first switch K1 of the first switch matrix unit 321 is in an interlocked state with the first switches K1 of the second switch matrix unit 322 and the first switches K1 of the third switch matrix unit 323. Therefore, different switches belonging to different switch matrix units but anchored to the same power output unit will not operate simultaneously. Only the switch corresponding to the action signal can operate. The switch that does not receive the action signal will automatically not operate. Therefore, the above two types of switches enter an interlocked state. This can avoid the simultaneous operation of different switches belonging to different switch matrix units but anchored to the same power output unit, which would cause a short circuit, thereby improving the safety and reliability of the charging host. In addition, the embodiments of this application use hardware circuits to complete the above-mentioned interlocking operation. Compared with software interlocking, hardware interlocking is faster and more efficient.

[0079] In some embodiments, the control unit 33 may be a chip that integrates at least the same number of control pins as the number of interlock circuits.

[0080] In some embodiments, the control unit 33 includes at least two switch controllers, one switch controller corresponding to one switch interlocking unit, and the switch controllers are electrically connected to all interlocking circuits in the switch interlocking unit respectively.

[0081] Please see Figure 5 The control unit 33 includes a first switch controller 331, a second switch controller 332, and a third switch controller 333. The first switch controller 331 corresponds to a first switch interlock unit 341 and is electrically connected to a first interlock circuit 3411, a second interlock circuit 3412, and a third interlock circuit 3413. The second switch controller 332 corresponds to a second switch interlock unit 342 and is electrically connected to a fourth interlock circuit 3421, a fifth interlock circuit 3422, and a sixth interlock circuit 3423. The third switch controller 333 corresponds to a third switch interlock unit 343 and is electrically connected to a seventh interlock circuit 3431, an eighth interlock circuit 3432, and a ninth interlock circuit 3433.

[0082] The host computer can select one of the first switch controller 331, the second switch controller 332 and the third switch controller 333 as the target switch controller, and send control information to the target switch controller. The target switch controller selects the target interlock circuit to send an action signal according to the control information. The target interlock circuit responds to the action signal to control the target switch to perform the action.

[0083] It is understood that the switch controller can be a general-purpose processor, digital signal processor, application-specific integrated circuit, field-programmable gate array, microcontroller, ARM or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. Furthermore, the switch controller 33 can also be a combination of any conventional processor, controller, microcontroller, or state machine, such as a combination of an FPGA and a microprocessor, or a combination of multiple microprocessors.

[0084] In some embodiments, please refer to Figure 6 The interlock circuit includes a switch control circuit 600 and an interlock trigger circuit 700. The switch control circuit 600 is electrically connected to the control unit 33, and the interlock trigger circuit 700 is electrically connected to the switch control circuit 600.

[0085] When the switch control circuit 600 detects an action signal, it controls the switch electrically connected to it to operate and transmits an interlock signal through the interlock bus. The interlock trigger circuit 700 then controls the switch control circuit 600 to maintain its operating state based on the interlock signal feedback. When the interlock trigger circuit 700 detects an interlock signal through the interlock bus, it controls the switch control circuit 600 to be in a non-operating state based on the interlock signal feedback.

[0086] For example, the first interlock circuit 3411 serves as the target interlock circuit, while the fourth interlock circuit 3421 and the seventh interlock circuit 3431 are both reference interlock circuits.

[0087] In the first interlock circuit 3411, when the switch control circuit 600 of the first interlock circuit 3411 detects an action signal, it controls the first switch K1 of the first switch matrix unit 321 to act (e.g., close), and transmits an interlock signal through the first interlock bus L1. The interlock trigger circuit 700 of the first interlock circuit 3411 controls the switch control circuit 600 of the first interlock circuit 3411 to enter the working state according to the feedback of the interlock signal. Since the switch control circuit 600 of the first interlock circuit 3411 is in the working state, it can maintain the control of the first switch K1 of the first switch matrix unit 321 to remain closed.

[0088] When the interlock trigger circuit of the fourth interlock circuit 3421 and the interlock trigger circuit of the seventh interlock circuit 3431 detect the interlock signal through the first locking bus L1, the interlock trigger circuit of the fourth interlock circuit 3421 controls the switch control circuit of the fourth interlock circuit 3421 to be in a non-working state according to the interlock signal, and the interlock trigger circuit of the seventh interlock circuit 3431 controls the switch control circuit of the seventh interlock circuit 3431 to be in a non-working state according to the interlock signal.

[0089] In this embodiment, when the switch needs to operate, the interlock trigger circuit can feedback-control the switch control circuit to continuously operate, ensuring the switch control circuit maintains operation. This negative feedback ensures the reliable operation of the switch requiring action. Conversely, when the switch does not need to operate, the interlock trigger circuit controls the switch control circuit to remain in a non-operating state, preventing it from operating. These two processes embody a "one moves, the others don't" interlocking state. The negative feedback mechanism ensures that no two switches belonging to different switch matrix units but anchored to the same power output unit will operate simultaneously, improving interlock reliability.

[0090] In some embodiments, please refer to Figure 7 The interlock trigger circuit 700 includes a signal transmission circuit 71, a bias control circuit 72, and an interlock feedback circuit 73.

[0091] The signal transmission circuit 71 includes a first node N1 and a locking node B0. The first node N1 is electrically connected to the switch control circuit 600, and the locking node B0 is electrically connected to the locking bus. When the switch control circuit 600 detects an action signal, it outputs an interlock signal at the first node N1. The signal transmission circuit 71 responds to the interlock signal by transmitting the interlock signal to the locking bus through the locking node B0. When the switch control circuit 600 does not detect an action signal, the voltage at the first node N1 is a first voltage, such as a low-level voltage.

[0092] The bias control circuit 72 includes a second node N2. The bias control circuit 72 is electrically connected to the signal transmission circuit 71 at the first node N1. When the bias control circuit 72 detects an interlock signal at the first node N1, it biases the voltage of the second node N2 to a second voltage, such as a low-level voltage. When the bias control circuit 72 detects a first voltage at the first node N1, it biases the voltage of the second node N2 to a third voltage, such as a high-level voltage.

[0093] The interlock feedback circuit 73 includes a third node N3. It is electrically connected to the bias control circuit 72 and the signal transmission circuit 71 at the second node N2, and to the switch control circuit 600 at the third node N3. When the interlock feedback circuit 73 detects a second voltage at the second node N2, it transmits a fourth voltage (e.g., a high-level voltage) through the third node N3. The switch control circuit 600 responds to the fourth voltage and maintains its operating state. When the interlock feedback circuit 73 detects a third voltage at the second node N2 or an interlock signal transmitted via the interlock bus, it transmits a fifth voltage (e.g., a low-level voltage) through the third node. The switch control circuit 600 responds to the fifth voltage and enters a non-operating state.

[0094] In this embodiment, through the cooperation of the signal transmission circuit 71, the bias control circuit 72, and the interlock feedback circuit 73, when a switching action is required, the switch control circuit 600 outputs an interlock signal at the first node N1. The signal transmission circuit 71 responds to the interlock signal and transmits the interlock signal to the interlock bus through the interlock node B0. Simultaneously, the switch control circuit 600 controls the switch electrically connected to it to operate. The bias control circuit 72 detects the interlock signal at the first node N1 and biases the voltage of the second node N2 to a second voltage. The interlock feedback circuit 73 detects the second voltage at the second node N2 and transmits a fourth voltage through the third node N3. The switch control circuit 600 responds to the fourth voltage to maintain its operating state. As mentioned above, when the switch control circuit 600 is in the operating state, it will maintain control of the switch to operate.

[0095] When the switch of the reference interlock circuit does not need to operate, the signal transmission circuit 71 receives the interlock signal through the interlock bus, the interlock feedback circuit 73 detects the interlock signal transmitted through the interlock bus through the second node N2, and transmits the fifth voltage through the third node. The switch control circuit 600 responds to the fifth voltage and is in a non-operating state. As mentioned above, when the switch control circuit 600 is not in an operating state, the switch control circuit 600 will not control the switch to operate.

[0096] In some embodiments, please refer to Figure 8 The signal transmission circuit 71 includes a signal isolation circuit 711 and a voltage divider circuit 712.

[0097] Signal isolation circuit 711 is electrically connected between first node N1 and latching node B0, and also electrically connected to switch control circuit 600 at first node N1. It isolates signals transmitted via the latching bus, thus preventing signals from the latching bus from flowing back into the interlocking circuit requiring switching action, thereby improving the operational reliability of the interlocking circuit requiring switching action. When signal isolation circuit 711 detects an interlock signal at first node N1, it transmits the interlock signal to the latching bus through latching node B0.

[0098] The voltage divider circuit 712 is electrically connected between the locking node B0 and the second node N2. The voltage divider circuit 712 can prevent the voltage of the locking node B0 from being directly connected to the voltage of the second node N2, and prevent the voltage of the locking node B0 from being affected by the voltage of the second node N2.

[0099] Please see Figure 9 The signal isolation circuit 711 includes a first diode D1 and a second diode D2 connected in parallel. The anodes of both diodes D1 and D2 are electrically connected to the first node N1, and the cathodes of both diodes D1 and D2 are electrically connected to the latching node B0. Because diodes D1 and D2 are unidirectional, the voltage from the latching node B0 will not flow back into the interlocking circuit requiring switching action through diodes D1 and D2.

[0100] Please continue reading. Figure 9 The voltage divider circuit 712 includes a first resistor R1, which can divide the voltage and prevent the voltage of the blocking node B0 from being directly connected to the voltage of the second node N2.

[0101] Please continue reading. Figure 9 The bias control circuit 72 includes a first transistor Q1, which is an NPN transistor. The base of the first transistor Q1 is used to detect the voltage of the first node N1, the emitter is grounded, and the collector is electrically connected to the second node N2.

[0102] When the first transistor Q1 detects the interlock signal, the first transistor Q1 enters the conduction state to bias the voltage of the second node N2 to the second voltage. For example, when the interlock signal is high level and the high level is applied to the base of the first transistor Q1, the first transistor Q1 meets the conduction condition and can pull the collector voltage down to a low level.

[0103] When the first transistor Q2 detects the first voltage at the first node N1, the first transistor Q2 enters the off state to bias the voltage at the second node N2 to the third voltage. For example, if the first voltage is a low-level voltage, and the low level is applied to the base of the first transistor Q1, the first transistor Q1 does not meet the conduction condition, and the voltage at the collector of the first transistor Q1 remains at a high level.

[0104] Please continue reading. Figure 9 The bias control circuit 72 also includes a second resistor R2, a third resistor R3, a first capacitor C1 and a second capacitor C2. The second resistor R2 serves as a voltage divider and current limiter. The third resistor R3 and the first capacitor C1 form a filter circuit, and the second capacitor C2 also forms a filter circuit.

[0105] Please continue reading. Figure 9 The interlock feedback circuit 73 includes a second transistor Q2. The base of the second transistor Q2 is used to detect the voltage of the second node N2, the emitter is grounded, and the collector is electrically connected to the third node. The third node is configured to receive a preset voltage.

[0106] When the second transistor Q2 detects the second voltage at the second node N2, the second transistor Q2 enters the off state and transmits the fourth voltage through the third node N3. The switch control circuit 600 responds to the fourth voltage to maintain the working state. For example, if the second voltage is a low level voltage, when the low level is applied to the base of the second transistor Q2, the second transistor Q2 does not meet the conduction condition, and the voltage at the collector of the second transistor Q2 remains at a high level, that is, the fourth voltage is a high level voltage.

[0107] When the second transistor Q2 detects the third voltage at the second node N2, the second transistor Q2 enters the conduction state and transmits the fifth voltage through the third node N3. The switch control circuit 600 responds to the fifth voltage and enters the non-operating state. For example, if the third voltage is a high-level voltage, when the high level is applied to the base of the second transistor Q2, the second transistor Q2 meets the conduction condition and can pull the collector voltage down to a low level.

[0108] Please continue reading. Figure 9 The interlocked feedback circuit 73 also includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a third capacitor C3, and a fourth capacitor C4. The fourth resistor R4 and the sixth resistor R6 both function as voltage dividers and current limiters. The fifth resistor R5 and the third capacitor C3 form a filter circuit, and the fourth capacitor C4 also forms a filter circuit.

[0109] In some embodiments, please refer to Figure 10 The switch control circuit 600 includes a switch drive circuit 61 and a switch selection circuit 62.

[0110] The switch drive circuit 61 is electrically connected to the switch and to the signal transmission circuit 71 at the first node N1. It is understood that the switch drive circuit 61 can be any suitable drive circuit or switch drive chip.

[0111] The switch selection circuit 62 is electrically connected to the interlock feedback circuit 73 and the control unit 33 at the third node N3. When the switch selection circuit 62 detects an action signal, it triggers the switch drive circuit 61 to operate the switch and outputs an interlock signal at the first node N1. When the switch selection circuit 62 does not detect an action signal, it stops triggering the switch drive circuit 61 to operate the switch, thus biasing the voltage at the first node N1 to a first voltage.

[0112] Please see Figure 11 The action signal includes a first switch signal RLY1S and a second switch signal RLY1R. The switch driving circuit includes a switch driving chip U1, which includes a first signal terminal A, a second signal terminal B, a first driving terminal OA, and a second driving terminal OB. The switch is electrically connected between the first driving terminal OA and the second driving terminal OB.

[0113] The switch selection circuit 62 includes a first switch circuit 621 and a second switch circuit 622. The first switch circuit 621 is electrically connected to the switch driver chip U1 at the first signal terminal A and is also electrically connected to the control unit 33 and the interlock feedback circuit 73 respectively. It is used to send a first trigger signal to the switch driver chip U1 in response to the first switch signal and the fourth voltage, or to send a first stop signal to the switch driver chip U1 in response to the fifth voltage.

[0114] The second switching circuit 622 is electrically connected to the switch driver chip U1 at the second signal terminal B and is also electrically connected to the control unit 33 and the interlock feedback circuit 73, respectively. It is used to send a second trigger signal to the switch driver chip U1 in response to the second switching signal and the fourth voltage, so that the switch driver chip U1 can operate the switch according to the first trigger signal and the second trigger signal, and output an interlock signal at the first node N1. Alternatively, it can send a second stop signal to the switch driver chip U1 in response to the fifth voltage, so that the switch driver chip U1 is in a non-working state according to the first stop signal and the second stop signal.

[0115] For example, for the target interlock circuit, the action signal is "10", where the first switch signal is high level, the second switch signal is low level, the first switch signal is applied to the first switch circuit 621, and when the interlock feedback circuit 73 outputs a high level fourth voltage through the third node N3, the first switch circuit 621 sends a high level to the switch driver chip U1, that is, the first trigger signal is high level.

[0116] When the second switch signal is applied to the second switch circuit 621, and the interlock feedback circuit 73 outputs a high-level fourth voltage through the third node N3, the second switch circuit 622 sends a low level to the switch driver chip U1, that is, the second trigger signal is high.

[0117] The switch driver chip U1 operates the switch according to the first trigger signal and the second trigger signal, and outputs an interlock signal at the first node N1.

[0118] For the reference interlock circuit, since the interlock feedback circuit 73 outputs a low-level fifth voltage through the third node N3, the first switch circuit 621 responds to the fifth voltage and sends a first stop signal to the switch driver chip U1, and the second switch circuit 621 responds to the fifth voltage and sends a second stop signal to the switch driver chip U1, so that the switch driver chip U1 is in a non-working state according to the first stop signal and the second stop signal.

[0119] Please see Figure 12 The first switching circuit 621 includes a third transistor Q3, which is a PNP transistor. The base of the third transistor Q3 is used to detect the voltage of the third node N3, the emitter is electrically connected to the first signal terminal, and the collector is grounded. As mentioned earlier, if the first switching signal is high, the third node N3 outputs a high-level fourth voltage. Since the third transistor Q3 does not meet the conduction condition, the first switching signal is directly transmitted to the first signal terminal of the switch driver chip U1, that is, the high-level first switching signal is the first trigger signal. If the third node N3 outputs a low-level fifth voltage, even if there is a timing error that causes the control unit 33 to output a high-level first switching signal when it should have output a low-level first switching signal, since the third transistor Q3 meets the conduction condition at this time, the third transistor Q3 directly pulls the voltage of its collector down to a low level, that is, pulls the voltage of the first signal terminal down to a low level. Therefore, at this time, the first switching circuit 621 is equivalent to sending a low-level first stop signal to the switch driver chip U1.

[0120] The second switching circuit 622 includes a fourth transistor Q4. The base of the fourth transistor Q4 is used to detect the voltage of the third node, the emitter is electrically connected to the second signal terminal, and the collector is grounded. The working principle of the second switching circuit 622 is similar to that of the first switching circuit 621, and will not be described in detail here.

[0121] Please continue reading. Figure 12The first switching circuit 621 also includes a seventh resistor R7 and an eighth resistor R8, both of which serve to limit current and divide voltage. The second switching circuit 622 also includes a ninth resistor R9 and a tenth resistor R10, both of which serve to limit current and divide voltage.

[0122] In some embodiments, please refer to Figure 13 The switch selection circuit 62 includes a first filter circuit 623 and a second filter circuit 624. The first filter circuit 623 is electrically connected to the first switch circuit 621 and is used to filter harmonic signals contained in the first switch signal. The second filter circuit 624 is electrically connected to the second switch circuit 622 and is used to filter harmonic signals contained in the second switch signal.

[0123] Please combine Figure 12 The first filter circuit 623 includes an eleventh resistor R11, a twelfth resistor R12 and a fifth capacitor C5, and the second filter circuit 624 includes a thirteenth resistor R13, a fourteenth resistor R14 and a sixth capacitor C6.

[0124] In some embodiments, please refer to Figure 14 The interlock circuit also includes a state detection circuit 800, which is electrically connected to the switch control circuit 600 at a preset first node N1 and also electrically connected to the control unit 33, for detecting the switching state of the switch.

[0125] For example, when the interlock signal is high, since the interlock signal is transmitted through the first node N1 and can reflect that the switch has been activated, the state detection circuit 800 samples the voltage of the first node N1. If the voltage of the first node N1 is high, it indicates that the switch is in the activated state; if the voltage of the first node N1 is low, it indicates that the switch is in the inactive state.

[0126] Please combine Figure 12 The status detection circuit 800 includes a fifteenth resistor R15, a seventh capacitor C7, and a sixteenth resistor R16. The fifteenth resistor R15, the seventh capacitor C7, and the sixteenth resistor R16 serve as filters to sample the voltage of the first node N1, filter it, and transmit the filtered voltage to the control unit 33.

[0127] Please continue reading. Figure 12 The eighth capacitor C8 and the ninth capacitor C9 are both DC blocking capacitors, and the NTC resistor is a temperature sensor.

[0128] To illustrate in detail the working principle of the charging host provided in this application regarding switch interlocking, this application embodiment combines... Figure 4 and Figure 15 This will be explained in detail, Figure 4 In this scenario, assuming the charging host needs to close the first switch K1 of the first switch matrix unit 321, to avoid simultaneously closing the first switches K1 of the second switch matrix unit 322 and the third switch matrix unit 323, the charging host needs to perform the following interlocking operation using hardware and an interlocking circuit, as follows:

[0129] The first interlock circuit 3411 of the first switch interlock unit 341 is the target interlock circuit, and the fourth interlock circuit 3421 of the second switch interlock unit 342 and the seventh interlock circuit 3431 of the third switch interlock unit 343 are both reference interlock circuits.

[0130] For the first interlock circuit 3411 that requires switching action, the control unit 33 sends an action signal "10" to the first interlock circuit 3411, where the first switch signal is "1" and the second switch signal is "0". The base of the third transistor Q3 is applied with a high level of 5V, and the voltage of the emitter is also clamped to a high level by the first switch signal. Since the third transistor Q3 is a PNP transistor, the third transistor Q3 does not meet the conduction condition. Therefore, the first switch signal "1" is filtered and directly transmitted to the first signal terminal A of the switch driver chip U1 as the first trigger signal.

[0131] The base of the fourth transistor Q4 is applied with a high level of 5V, and the voltage of the emitter is clamped to a low level by the second switch signal. Since the fourth transistor Q4 is a PNP transistor, the fourth transistor Q3 does not meet the conduction condition. Therefore, the second switch signal "0" is filtered and directly transmitted to the second signal terminal B of the switch driver chip U1 as the second trigger signal.

[0132] According to the signal combination "10", the switch driver chip U1 outputs a drive signal through the first drive terminal and the second drive terminal. This drive signal acts on the coil of the relay RLY (i.e., the switch). The coil is energized and draws the normally open contact of the relay to close. Then, the 5V voltage of the external power supply VCC is applied to the first node N1. That is, the 5V voltage of the first node N1 can be regarded as an interlock signal.

[0133] After the interlock signal is filtered by the status detection circuit consisting of the seventh capacitor C7, the fifteenth resistor R15 and the sixteenth resistor R16, it is transmitted to the control unit 33. The control unit 33 can determine that the relay RLY is closed at this time.

[0134] On one hand, the 5V voltage at the first node N1 is applied to the second transistor Q2. Since the second transistor Q2 meets the conduction condition, it pulls the voltage at the second node N2 down to a low level, meaning the second voltage is low. On the other hand, the voltage at the second node N2 is applied to the first transistor Q1. Since the first transistor Q1 does not meet the conduction condition, it maintains the voltage at the third node N3 at a high level (e.g., 5V), meaning the fourth voltage is high.

[0135] The fourth voltage feedback is applied to the third transistor Q3 of the first switching circuit and the fourth transistor Q4 of the second switching circuit. At this time, neither the third transistor Q3 nor the fourth transistor Q4 has met the conduction condition. Therefore, the action signal "10" is still transmitted to the switch driver chip U1 after filtering. The switch driver chip U1 continues to operate, and the relay RLY remains closed.

[0136] On the other hand, the 5V voltage at the first node N1 is transmitted to the latch bus LOCK at the latch node B0 through the first diode D1 and the second diode D2. For the reference interlock circuit, the fourth interlock circuit 3421 is used as an example for explanation, as follows:

[0137] Since the switch control circuit of the fourth interlock circuit 3421 did not receive the action signal "10", neither the third transistor Q3 nor the fourth transistor Q4 of the fourth interlock circuit 3421 met the conduction condition. The switch driver chip of the fourth interlock circuit 3421 did not receive the action signal "10" and would not enter the working state. The relay RLY of the fourth interlock circuit 3421 would not close, and the 5V voltage of the external power supply VCC would not be applied to the first node N1. The voltage of the first node N1 was low, that is, the first voltage was a low-level voltage.

[0138] The voltage at the first node N1 is applied to the first transistor Q1, but the first transistor Q1 does not meet the conduction condition. However, the fourth interlock circuit 3421 detects the interlock signal transmitted by the first interlock circuit 3411 through the interlock bus. At this time, the interlock signal can be applied to the second node N2. As mentioned before, since the first transistor Q1 does not meet the conduction condition, the voltage at the second node N2 will not be pulled low by the second transistor Q2, and the voltage at the second node N2 remains the voltage of the interlock signal. When the interlock signal is applied to the second transistor Q2, the second transistor Q2 conducts, directly pulling down the voltage at the third node, that is, the fifth voltage is a low-level voltage.

[0139] The fifth voltage feedback is applied to the third transistor Q3 of the first switching circuit and the fourth transistor Q4 of the second switching circuit. Regardless of the signal combination, the signal combination received by the switch driver chip U1 is "00", that is, the switch driver chip U1 is in a stopped working state, and the relay RLY of the fourth interlock circuit 3421 is still disconnected.

[0140] The embodiments of this application employ the above-described method, which ensures that any two switches belonging to different switch matrix units but anchored to the same power output unit will not close simultaneously, thereby avoiding short circuits. Furthermore, the above-described method uses hardware interlocking, resulting in fast response speed and high interlocking efficiency.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A charging host, characterized in that, include: At least two power output units; At least two switch matrix units, each of the switch matrix units includes at least two switches connected in parallel with each other, each switch in the switch matrix unit is configured with a switch number, and switches with the same switch number but belonging to different switch matrix units are electrically connected to the bus of the same power output unit; The control unit is used to send action signals; At least two switch interlocking units are provided, each switch interlocking unit corresponds to a switch matrix unit, each switch interlocking unit includes at least two interlocking circuits, one interlocking circuit is electrically connected to a switch and also electrically connected to the control unit, interlocking circuits anchored to the same switch number but belonging to different switch interlocking units are electrically connected on the same locking bus, the target interlocking circuit responds to the action signal, controls the target switch to act and transmits the interlocking signal through the locking bus, the reference interlocking circuit responds to the interlocking signal and controls the reference switch not to act, the target interlocking circuit is one of the interlocking circuits, the target switch is a switch electrically connected to the target interlocking circuit, the reference interlocking circuit is an interlocking circuit electrically connected to the target interlocking circuit on the same locking bus, and the reference switch is a switch electrically connected to the reference interlocking circuit; The interlock circuit includes: a switch control circuit and an interlock triggering circuit, wherein the interlock triggering circuit includes: The signal transmission circuit, when the switch control circuit detects the action signal, responds to the interlock signal output by the switch control circuit and transmits the interlock signal to the locking bus. The bias control circuit generates a bias voltage when the interlock signal is detected. The interlock feedback circuit outputs a voltage to keep the switch control circuit in operation when the bias voltage is detected; and outputs a voltage to keep the switch control circuit in a non-operating state when the interlock signal is detected.

2. The charging host according to claim 1, characterized in that, The switch control circuit is electrically connected to the control unit; The interlock trigger circuit is electrically connected to the switch control circuit. When the switch control circuit detects the action signal, it controls the switch electrically connected to it to operate and transmits an interlock signal through the interlock bus. The interlock trigger circuit also controls the switch control circuit to maintain its working state based on the interlock signal feedback. When the interlock trigger circuit detects the interlock signal through the interlock bus, it controls the switch control circuit to be in a non-working state based on the interlock signal feedback.

3. The charging host according to claim 2, characterized in that, The signal transmission circuit includes a first node and a locking node. The signal transmission circuit is electrically connected to the switch control circuit at the first node and electrically connected to the locking bus at the locking node. When the switch control circuit detects the action signal, the switch control circuit outputs an interlock signal at the first node. The signal transmission circuit responds to the interlock signal and transmits the interlock signal to the locking bus through the locking node. When the switch control circuit does not detect the action signal, the voltage of the first node is the first voltage; The bias control circuit includes a second node. The bias control circuit is electrically connected to the signal transmission circuit at the first node. When the bias control circuit detects the interlock signal at the first node, the bias control circuit biases the voltage of the second node to a second voltage. When the bias control circuit detects the first voltage at the first node, the bias control circuit biases the voltage of the second node to a third voltage. The interlock feedback circuit includes a third node. The interlock feedback circuit is electrically connected to the bias control circuit and the signal transmission circuit at the second node, and electrically connected to the switch control circuit at the third node. When the interlock feedback circuit detects the second voltage at the second node, it transmits a fourth voltage through the third node, and the switch control circuit responds to the fourth voltage to maintain its working state. When the interlock feedback circuit detects the third voltage or an interlock signal transmitted through the interlock bus at the second node, it transmits a fifth voltage through the third node, and the switch control circuit responds to the fifth voltage to be in a non-working state.

4. The charging host according to claim 3, characterized in that, The bias control circuit includes a first transistor. The base of the first transistor is used to detect the voltage of the first node, the emitter is grounded, and the collector is electrically connected to the second node. When the first transistor detects the interlock signal, the first transistor enters the conducting state to bias the voltage of the second node to a second voltage. When the first transistor detects the first voltage at the first node, the first transistor enters the turning-off state to bias the voltage of the second node to a third voltage.

5. The charging host according to claim 3, characterized in that, The interlock feedback circuit includes a second transistor. The base of the second transistor is used to detect the voltage of the second node, the emitter is grounded, and the collector is electrically connected to the third node. The third node is configured to receive a preset voltage. When the second transistor detects the second voltage at the second node, the second transistor enters a turn-off state and transmits a fourth voltage through the third node. The switch control circuit responds to the fourth voltage and maintains its operating state. When the second transistor detects the third voltage at the second node, the second transistor enters a turn-on state and transmits a fifth voltage through the third node. The switch control circuit responds to the fifth voltage and enters a non-operating state.

6. The charging host according to claim 3, characterized in that, The signal transmission circuit includes: A signal isolation circuit is electrically connected between the first node and the locking node and is electrically connected to the switch control circuit at the first node. It is used to isolate the signals transmitted by the locking bus. When the signal isolation circuit detects the interlock signal at the first node, the signal isolation circuit transmits the interlock signal to the locking bus through the locking node. A voltage divider circuit is electrically connected between the locking node and the second node.

7. The charging host according to claim 6, characterized in that, The signal isolation circuit includes a first diode and a second diode connected in parallel. The anodes of the first diode and the second diode are both electrically connected to the first node, and the cathodes of the first diode and the second diode are both electrically connected to the blocking node.

8. The charging host according to claim 3, characterized in that, The switch control circuit includes: A switch driving circuit is electrically connected to the switch and electrically connected to the signal transmission circuit at the first node; A switch selection circuit is electrically connected to the interlock feedback circuit and the control unit at the third node. When the switch selection circuit detects the action signal, it triggers the switch driving circuit to operate the switch and outputs an interlock signal at the first node. When the switch selection circuit does not detect the action signal, it stops triggering the switch driving circuit to operate the switch, so as to bias the voltage of the first node to a first voltage.

9. The charging host according to claim 8, characterized in that, The action signal includes a first switch signal and a second switch signal. The switch driving circuit includes a switch driving chip. The switch driving chip includes a first signal terminal, a second signal terminal, a first driving terminal, and a second driving terminal. The switch is electrically connected between the first driving terminal and the second driving terminal. The switch selection circuit includes a first switch circuit and a second switch circuit. The first switching circuit is electrically connected to the switch driver chip at the first signal terminal and is also electrically connected to the control unit and the interlock feedback circuit respectively. It is used to send a first trigger signal to the switch driver chip in response to the first switching signal and the fourth voltage, or to send a first stop signal to the switch driver chip in response to the fifth voltage. The second switching circuit is electrically connected to the switch driver chip and the control unit at the second signal terminal. It is used to send a second trigger signal to the switch driver chip in response to the second switching signal and the fifth voltage, so that the switch driver chip can operate the switch according to the first trigger signal and the second trigger signal and output an interlock signal at the first node. Alternatively, it can send a second stop signal to the switch driver chip in response to the fifth voltage, so that the switch driver chip is in a non-operating state according to the first stop signal and the second stop signal.

10. The charging host according to claim 9, characterized in that, The first switching circuit includes a third transistor, the base of which is used to detect the voltage of the third node, the emitter is electrically connected to the first signal terminal, and the collector is grounded; The second switching circuit includes a fourth transistor, the base of which is used to detect the voltage of the third node, the emitter is electrically connected to the second signal terminal, and the collector is grounded.

11. The charging host according to claim 2, characterized in that, The interlock circuit further includes a state detection circuit, which is electrically connected to the switch control circuit and the control unit at a preset first node, and is used to detect the switching state of the switch.

12. The charging host according to any one of claims 1 to 11, characterized in that, The control unit includes at least two switch controllers, each switch controller corresponding to one switch interlocking unit, and each switch controller is electrically connected to all interlocking circuits in the switch interlocking unit.

13. A charging pile, characterized in that, include: Charging terminal; The charging host as described in any one of claims 1 to 12, wherein the charging host is electrically connected to the charging terminal.

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