Memory management method and storage device

Abstract

The present invention provides a memory management method and storage device. The method includes: updating first mapping information corresponding to first data, which reflects a mapping relationship between a first logical unit to which the first data belongs and one of a plurality of physical units; updating first-type counting information corresponding to the first data in response to the first mapping information being updated; updating second-type counting information corresponding to the first data in response to a first-type data cleanup operation being performed on the first data; determining that the first data is first-type data based on the first-type counting information and the second-type counting information; and performing the second-type data cleanup operation on the first-type data. This method achieves a balance between improving the efficiency of the data cleanup operation and extending the service life of the memory module.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] After a storage device has been used for a period of time, a mixture of valid and invalid data is stored in the memory modules within the storage device, resulting in a reduction in the number of available physical blocks within the memory modules. Generally, a storage controller uses garbage collection (GC) to collect valid data from used physical blocks and store the collected valid data back in another physical block to free up available physical blocks. Specifically, to maximize the efficiency of the GC process, the storage controller often collects valid data from the physical blocks with the least valid data, hoping to reclaim the physical blocks with minimal data movement. However, in practice, more factors related to the memory module's usage history can affect the performance of subsequent GC executions. Furthermore, excessively frequent GC of unnecessary data can lead to excessive write amplification, shortening the lifespan of the memory modules.

[0003] Therefore, how to strike a balance between improving the performance of the garbage collection process and extending the service life of the memory module is a problem that needs to be solved urgently. Summary of the Invention

[0004] The present invention provides a memory management method and a storage device, which can improve the defects of traditional garbage collection programs and effectively strike a balance between improving the performance of data sorting operations and extending the service life of memory modules.

[0005] An embodiment of the present invention provides a memory management method for a storage device, wherein the storage device includes a memory module, the memory module includes multiple physical units, and the memory management method includes: updating first mapping information corresponding to first data, wherein the first mapping information reflects the mapping relationship between a first logical unit to which the first data belongs and one of the multiple physical units; in response to the first mapping information being updated, updating first-type counting information corresponding to the first data; performing a first-type data sorting operation on the first data; in response to the first-type data sorting operation being performed on the first data, updating second-type counting information corresponding to the first data; determining that the first data is first-type data based on the first-type counting information and the second-type counting information; and in response to the total data amount of the first-type data reaching a critical value, performing a second-type data sorting operation on the first-type data.

[0006] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units, and the memory controller is used to: update first mapping information corresponding to first data, wherein the first mapping information reflects the mapping relationship between the first logical unit to which the first data belongs and one of the plurality of physical units; in response to the first mapping information being updated, update first-type counting information corresponding to the first data; perform a first-type data sorting operation on the first data; in response to the first-type data sorting operation being performed on the first data, update second-type counting information corresponding to the first data; determine that the first data is first-type data based on the first-type counting information and the second-type counting information; and in response to the total data volume of the first-type data reaching a critical value, perform a second-type data sorting operation on the first-type data.

[0007] Based on the above, after updating the first mapping information corresponding to the first data, the first type of counting information corresponding to the first data can be updated. The first mapping information reflects the mapping relationship between the first logical unit to which the first data belongs and one of the multiple physical units. On the other hand, after performing the first type of data sorting operation on the first data, the second type of counting information corresponding to the first data can be updated. Based on the first type of counting information and the second type of counting information, the first data can be determined as the first type of data. Thereafter, in response to the total data volume of the first type of data reaching a critical value, the second type of data sorting operation can be performed on the first type of data. In this way, the defects of the traditional garbage collection program can be improved, thereby effectively achieving a balance between improving the efficiency of the data sorting operation and extending the service life of the memory module. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram showing recording first mapping information and first-type counting information in a logic-to-physical mapping table according to an embodiment of the present invention;

[0012] Figure 5is a schematic diagram showing storing first data and second type counting information in a first entity unit according to an embodiment of the present invention;

[0013] Figure 6 is a schematic diagram of a second type of data sorting operation according to an embodiment of the present invention;

[0014] Figure 7 FIG. 4 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] Figure 1 Schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a laptop computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to this. In addition, the storage device 12 can include a solid-state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0017] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (e.g., exchange signals, instructions, and / or data) via the connection interface 121.

[0018] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of a voltage (also known as a threshold voltage). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules having the same or similar characteristics.

[0019] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered the control core of the memory device 12 and is used to control the memory device 12. For example, the memory controller 123 can be used to control or manage all or part of the operation of the memory device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar devices or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0020] The memory controller 123 can send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, and the present invention is not limited thereto. The memory module 122 can receive the command sequence from the memory controller 123 and access the memory cells within the memory module 122 according to the command sequence.

[0021] Figure 2 FIG is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0022] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage all or part of the operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0023] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0024] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data accuracy. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits), and the present invention is not limited thereto.

[0025] Figure 3 FIG is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile data storage.

[0026] In one embodiment, a physical unit may include one or more physical programming units. A physical programming unit is the smallest unit in the memory module 122 to which data is written synchronously. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0027] In one embodiment, a physical programming unit may include one or more physical sectors. For example, the data capacity of a physical sector may be 512 bytes (B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit may be adjusted according to practical needs and are not limited by the present invention. In one embodiment, a physical programming unit may include one or more physical pages.

[0028] In one embodiment, a physical erase unit may include multiple physical programming units. Multiple physical programming units in a physical erase unit may be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to multiple physical programming units in the physical erase unit to change the threshold voltages of at least some of the memory cells in these physical programming units. By performing an erase operation on a physical erase unit, data stored in the physical erase unit may be cleared. Furthermore, in one embodiment, a virtual unit may include one or more physical erase units.

[0029] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the spare area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also known as user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the spare area 32 do not store data (e.g., valid data).

[0030] In one embodiment, if a physical unit does not store valid data, the physical unit may be associated with the idle area 32. Furthermore, the physical units in the idle area 32 may be erased to clear the data in the physical units. In one embodiment, the physical units in the idle area 32 are also referred to as idle physical units. In one embodiment, the idle area 32 is also referred to as a free pool.

[0031] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cells, the physical cells may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0032] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management unit. A logical unit may be mapped to one or more physical units.

[0033] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is currently not mapped by any logical unit, the memory control circuit 23 may determine that the physical unit does not currently store any valid data.

[0034] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical units and the physical units in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data read, write, or erase based on the information in the management table (i.e., the logical-to-physical mapping table).

[0035] In one embodiment, the memory control circuit 23 may record mapping information (also referred to as first mapping information) corresponding to a certain data (also referred to as first data). For example, the memory control circuit 23 may record the first mapping information in the logic-to-physical mapping table. The first mapping information may reflect the mapping relationship between the logical unit to which the first data belongs (also referred to as the first logical unit) and at least one physical unit. For example, assuming that the first logical unit is the logical unit 302 (1), the first mapping information may reflect the mapping relationship between the logical unit 302 (1) and one of the physical units 301 (1) to 301 (A). For example, assuming that the logical unit 302 (1) is currently mapped to the physical unit 301 (1), the first mapping information may reflect the mapping relationship between the logical unit 302 (1) and the physical unit 301 (1).

[0036] In one embodiment, the memory control circuit 23 may update the first mapping information. For example, in response to a change in the mapping relationship between the first logical unit and one of the physical units 301(1) to 301(A), the memory control circuit 23 may update the first mapping information. The updated first mapping information may reflect the new mapping relationship between the first logical unit and one of the physical units 301(1) to 301(A). For example, assuming that the first logical unit is the logical unit 302(1) and the logical unit 302(1) was originally mapped to the physical unit 301(1). If the logical unit 302(1) is changed to be mapped to the physical unit 301(2), the memory control circuit 23 may update the first mapping information to reflect the new mapping relationship between the logical unit 302(1) and the physical unit 301(2).

[0037] In one embodiment, in response to the first mapping information being updated, the memory control circuit 23 may update the count information corresponding to the first data (also referred to as first-type count information). For example, in response to the first mapping information being updated once, the memory control circuit 23 may add "1" to the first-type count information corresponding to the first data.

[0038] In one embodiment, the first type of counting information may reflect the total number of times the first mapping information has been updated. For example, the first type of counting information may include a numerical value (also referred to as a first numerical value). If the first numerical value is "N", it means that the first mapping information has been updated "N" times.

[0039] In one embodiment, the memory control circuit 23 may record the first mapping information and the first type of counting information in the logical-to-physical mapping table. In one embodiment, the memory control circuit 23 may also record the first type of counting information in other management tables, which is not limited by the present invention.

[0040] Figure 4 Schematic diagram of recording the first mapping information and the first type of counting information in the logic-to-physical mapping table according to an embodiment of the present invention. Figure 4 , assuming that the first logical unit is logical unit 401, and logical unit 401 is currently mapped to physical unit 402. The memory control circuit 23 may record the first mapping information in the logical-to-physical mapping table 41. For example, the first mapping information may reflect the mapping relationship between the logical unit 401 and the physical unit 402. In addition, the memory control circuit 23 may also record the first type of counting information C(1) corresponding to the first data in the logical-to-physical mapping table 41. For example, the first type of counting information C(1) may reflect the total number of times the first mapping information has been updated.

[0041] In one embodiment, the memory control circuit 23 may perform a data cleanup operation (also referred to as a first-type data cleanup operation) on the first data. For example, the first-type data cleanup operation may include a garbage collection operation, a wear leveling (WL) operation, or other conventional data cleanup operations for the memory module 122. For example, in the first-type data cleanup operation on the first data, the memory control circuit 23 may move or copy the first data from a certain physical unit (also referred to as a source physical unit) to another physical unit (also referred to as a target physical unit).

[0042] In one embodiment, in response to a first-type data shuffling operation being performed on the first data (e.g., the first data being moved or copied from one physical unit to another physical unit), the memory control circuit 23 may update another type of counting information corresponding to the first data (also referred to as second-type counting information). For example, in response to a first-type data shuffling operation being performed on the first data, the memory control circuit 23 may increment the second-type counting information corresponding to the first data by "1."

[0043] In one embodiment, the second type of counting information may reflect the total number of times the first type of data tidying operation has been performed on the first data. For example, the second type of counting information may include a numerical value (also referred to as a second numerical value). If the second numerical value is "M," it indicates that the first type of data tidying operation has been performed "M" times on the first data.

[0044] In one embodiment, the memory control circuit 23 may overwrite (e.g., erase) the first data. In one embodiment, in response to the first data being overwritten, the memory control circuit 23 may reset the second type of count information corresponding to the first data. For example, in resetting the second type of count information corresponding to the first data, the memory control circuit 23 may set the second type of count information (e.g., the second value) to "0."

[0045] In one embodiment, the memory control circuit 23 may store the first data and the second type of counting information corresponding to the first data in a specific physical unit (also referred to as the first physical unit). In one embodiment, the memory control circuit 23 may also record the second type of counting information in another management table, which is not limited by the present invention.

[0046] Figure 5 FIG is a schematic diagram showing how the first data and the second type of counting information are stored in the first entity unit according to an embodiment of the present invention. Figure 5 , assuming that the first physical unit is the physical unit 51. The physical unit 51 includes a data area 501 and an idle area 502. In one embodiment, the memory control circuit 23 may store the first data and the second type of counting information C(2) corresponding to the first data in the data area 501 and the idle area 502 of the physical unit 51 respectively. For example, the second type of counting information C(2) currently stored in the idle area 502 of the physical unit 51 may reflect the total number of times that the first type of data sorting operation has been performed on the first data currently stored in the data area 501 of the physical unit 51 in the past period of time. In addition, the idle area 502 of the physical unit 51 may also store an error correction code (ECC) and / or other management data related to the physical unit 51).

[0047] In one embodiment, the memory control circuit 23 may determine whether the first data is first-category data based on the first-category counting information and the second-category counting information. In one embodiment, if the first-category counting information and the second-category counting information meet a preset condition, the memory control circuit 23 may determine that the first data is first-category data based on the first-category counting information and the second-category counting information. Alternatively, in one embodiment, if the first-category counting information and the second-category counting information do not meet the preset condition, the memory control circuit 23 may determine that the first data is not first-category data based on the first-category counting information and the second-category counting information.

[0048] In one embodiment, the memory control circuit 23 may perform a logical operation on the first-type counting information and the second-type counting information to obtain an evaluation value. Based on the evaluation value, the memory control circuit 23 may determine whether the first data is first-type data. For example, if the first-type counting information and the second-type counting information meet a predetermined condition, the memory control circuit 23 may determine that the first data is first-type data based on the evaluation value. However, if the first-type counting information and the second-type counting information do not meet the predetermined condition, the memory control circuit 23 may determine that the first data is not first-type data based on the evaluation value.

[0049] In one embodiment, assuming that the first type of count information includes a first numerical value and the second type of count information includes a second numerical value, the evaluation value may reflect a ratio of the first numerical value to the second numerical value. For example, assuming that the first numerical value is "N" and the second numerical value is "M," the memory control circuit 23 may divide "M" by "N" to obtain the evaluation value. Alternatively, the memory control circuit 23 may divide "N" by "M" to obtain the evaluation value.

[0050] In one embodiment, the memory control circuit 23 may compare the evaluation value with a preset value, and then determine whether the first data is of the first type based on the comparison result.

[0051] In one embodiment, it is assumed that the memory control circuit 23 divides "M" by "N" to obtain the evaluation value. After comparing the evaluation value with a preset value (also referred to as a first preset value), the memory control circuit 23 may determine whether the evaluation value is greater than the first preset value. If the evaluation value is greater than the first preset value (i.e., the first-category counting information and the second-category counting information meet the preset conditions), the memory control circuit 23 may determine that the first data is first-category data. However, if the evaluation value is not greater than (e.g., less than or equal to) the first preset value (i.e., the first-category counting information and the second-category counting information do not meet the preset conditions), the memory control circuit 23 may determine that the first data is not first-category data.

[0052] In one embodiment, it is assumed that the memory control circuit 23 divides "N" by "M" to obtain the evaluation value. After comparing the evaluation value with a preset value (also referred to as a second preset value), the memory control circuit 23 may determine whether the evaluation value is less than the second preset value. If the evaluation value is less than the second preset value (i.e., the first-category counting information and the second-category counting information meet the preset conditions), the memory control circuit 23 may determine that the first data is first-category data. However, if the evaluation value is not less than (e.g., greater than or equal to) the second preset value (i.e., the first-category counting information and the second-category counting information do not meet the preset conditions), the memory control circuit 23 may determine that the first data is not first-category data.

[0053] In one embodiment, if certain data (e.g., first data) is determined to belong to the first category of data, it means that most of the multiple mapping information updates performed on this data in the past period were triggered by performing the first category of data sorting operations on this data. Therefore, in one embodiment, if certain data (e.g., first data) is determined to belong to the first category of data, it means that this data is cold data.

[0054] On the other hand, if certain data (e.g., first data) is determined to not belong to the first category of data, this means that of the multiple updates to mapping information performed on this data over the past period of time, only a small portion was triggered by performing the first category of data sorting operations on this data. Alternatively, from another perspective, if certain data (e.g., first data) is determined to not belong to the first category of data, this means that of the multiple updates to mapping information performed on this data over the past period of time, most were triggered by updating the data content of this data (e.g., the host system 11 frequently updates the data content of the first data belonging to the first logical unit). Therefore, in one embodiment, if certain data (e.g., first data) is determined to not belong to the first category of data, it means that this data is hot data.

[0055] In one embodiment, the first data may refer to any data in the memory module 122. In one embodiment, through the above decision mechanism, the memory control circuit 23 may determine whether any data in the memory module 122 belongs to the first category of data.

[0056] In one embodiment, the memory control circuit 23 may detect whether the total amount of the first-type data in the memory module 122 has reached (e.g., is greater than or equal to) a critical value. In response to the total amount of the first-type data in the memory module 122 reaching the critical value, the memory control circuit 23 may perform a data tidying operation (also referred to as a second-type data tidying operation) on the first-type data. However, if the total amount of the first-type data in the memory module 122 has not reached (e.g., is less than) the critical value, the memory control circuit 23 may temporarily refrain from performing the second-type data tidying operation on the first-type data.

[0057] In one embodiment, the second-type data cleanup operation only moves or copies the first-type data. That is, during the second-type data cleanup operation, only the first-type data in the memory module 122 is moved or copied to the target physical unit. Alternatively, from another perspective, during the second-type data cleanup operation, other data in the memory module 122 that does not belong to the first-type data is not moved or copied to the target physical unit.

[0058] In one embodiment, assume that first data is currently stored in a first physical unit. In response to the first data being determined to be first-category data, the memory control circuit 23 may record address information corresponding to the first physical unit (also referred to as first address information) in a specific area (also referred to as a management area). For example, the management area may include one or more physical units. However, if the first data is not determined to be first-category data, the memory control circuit 23 may not record the first address information in the management area.

[0059] In one embodiment, after recording the first address information in the management area, the memory control circuit 23 may retrieve the first address information from the management area during the second type of data shuffling operation. Based on the first address information, the memory control circuit 23 may read the first data from the first physical unit and move or copy the read first data to another physical unit (also referred to as the second physical unit) in the memory module 122.

[0060] In one embodiment, when performing the second type of data cleanup operation, the memory control circuit 23 may select the physical unit with the largest number of erases in the memory module 122 as the target physical unit. Then, based on the first address information, the memory control circuit 23 may read the first data from the first physical unit and move or copy the read first data to the target physical unit in the memory module 122.

[0061] Figure 6 Schematic diagram of the second type of data sorting operation according to an embodiment of the present invention. Figure 6Assuming that the data 601-606 currently stored in the virtual units 61-63 are all valid data, for the first type of data sorting operation, the data 601-606 are all data that can be moved or copied to the target physical unit.

[0062] exist Figure 6 In the embodiment of FIG, it is assumed that part of the address information recorded in the management area points to the current storage locations of data 601-603 in virtual units 61-63. However, the management area does not record any address information pointing to the current storage locations of data 604-606 in virtual units 61-63. In other words, in Figure 6 In the embodiment, data 601-603 are classified as first-category data, while data 604-606 are not classified as first-category data (even though data 604-606 are valid data).

[0063] exist Figure 6 In the embodiment, after the second type of data tidying operation is initiated or triggered, the memory control circuit 23 may read data 601-603 (i.e., first type data) from virtual units 61-63, respectively, based on the address information obtained from the management area. The memory control circuit 23 may then move or copy the read data 601-603 (i.e., first type data) to virtual unit 64 (i.e., centrally store the first type data dispersed in virtual units 61-63 in virtual unit 64). However, data 604-606 do not belong to the first type of data. Therefore, during the second type of data tidying operation, the memory control circuit 23 may not move or copy data 604-606 from virtual units 61-63 to virtual unit 64.

[0064] In one embodiment, the memory control circuit 23 may determine whether the total amount of the first-category data has reached a critical value based on the total amount of address information recorded in the management area. For example, in one embodiment, in response to the total amount of address information recorded in the management area reaching (e.g., greater than or equal to) a predetermined amount, the memory control circuit 23 may determine that the total amount of the first-category data has reached the critical value. However, if the total amount of address information recorded in the management area does not reach (e.g., is less than) the predetermined amount, the memory control circuit 23 may determine that the total amount of the first-category data has not reached the critical value.

[0065] In one embodiment, the total amount of the first type of data reaches a critical value, which means that by executing the second type of data sorting operation once, enough first type of data can be collected from multiple source physical units to fill at least one virtual unit. Therefore, each time the second type of data sorting operation is started or triggered, the first type of data can be moved or copied according to the address information recorded in the management area (e.g., Figure 6As shown in FIG, the first category of data is centrally stored in at least one virtual unit. This achieves the beneficial technical effect of excluding the first category of data (similar to cold data) from the remaining data (similar to hot data) and storing it independently, thereby reducing the repeated movement of the relatively rarely updated first category of data in subsequent data sorting operations.

[0066] Figure 7 FIG is a flow chart of a memory management method according to an embodiment of the present invention. Figure 7 In step S701, first mapping information corresponding to the first data is updated, wherein the first mapping information reflects a mapping relationship between a first logical unit to which the first data belongs and one of a plurality of physical units. In step S702, in response to the first mapping information being updated, first-category counting information corresponding to the first data is updated. In step S703, a first-category data sorting operation is performed on the first data. In step S704, in response to the first-category data sorting operation being performed on the first data, second-category counting information corresponding to the first data is updated. In step S705, the first data is determined to be first-category data based on the first-category counting information and the second-category counting information. In step S706, it is determined whether the total data volume of the first-category data reaches a critical value. If the total data volume of the first-category data reaches the critical value, in step S707, a second-category data sorting operation is performed on the first-category data. However, if the total data volume of the first-category data does not reach the critical value, step S706 may be repeated.

[0067] However, Figure 7 The steps have been described in detail above and will not be repeated here. Figure 7 Each step can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 7 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0068] In summary, the memory management method and storage device proposed in the embodiment of the present invention can maintain two types of counting information (i.e., first-class counting information and second-class counting information) for each piece of data in the memory module. Taking the first data as an example, the first-class counting information reflects the total number of times the first mapping information corresponding to the first data is updated, while the second-class counting information reflects the total number of times the first data is subjected to the first-class data sorting operation. Based on the first-class counting information and the second-class counting information, whether the first data is the first-class data can be accurately confirmed. In addition, after the total amount of the first-class data reaches a critical value, the second-class data sorting operation can be performed on the first-class data alone. In this way, the beneficial technical effect of excluding the first-class data (similar to cold data) from the rest of the data (similar to hot data) and storing it independently can be achieved, and reducing the repeated movement of the first-class data that is relatively rarely updated in subsequent data sorting operations. In this way, a balance can be achieved between improving the efficiency of subsequent data sorting operations and extending the service life of the memory module.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For use in a storage device, wherein the storage device includes a memory module, the memory module includes a plurality of physical units, and the memory management method includes: updating first mapping information corresponding to the first data, wherein the first mapping information reflects a mapping relationship between a first logical unit to which the first data belongs and one of the plurality of physical units; In response to the first mapping information being updated, updating first-category counting information corresponding to the first data; performing a first type of data sorting operation on the first data; In response to the first data being subjected to the first type of data sorting operation, updating the second type of counting information corresponding to the first data; determining, based on the first category counting information and the second category counting information, that the first data is first category data; and In response to the total data volume of the first category of data reaching a critical value, a second category of data sorting operation is performed on the first category of data. 2 . The memory management method according to claim 1 , wherein the first type of counting information reflects the total number of times the first mapping information is updated, and the second type of counting information reflects the total number of times the first type of data defragmentation operation is performed on the first data.

3. The memory management method according to claim 1 , wherein the step of performing the first type of data sorting operation on the first data comprises: The first data is moved or copied from a source physical unit among the plurality of physical units to a target physical unit among the plurality of physical units.

4. The memory management method according to claim 1 , further comprising: In response to the first data being overwritten, the second-type counting information is reset.

5. The memory management method according to claim 1 , wherein the step of determining that the first data is the first category data according to the first category counting information and the second category counting information comprises: performing a logical operation on the first type of counting information and the second type of counting information to obtain an evaluation value; as well as According to the evaluation value, the first data is determined to be the first category of data. 6 . The memory management method according to claim 5 , wherein the first type of count information comprises a first value, the second type of count information comprises a second value, and the evaluation value reflects a ratio of the first value to the second value.

7. The memory management method according to claim 5, wherein the step of determining, based on the evaluation value, that the first data is the first type of data comprises: comparing the evaluation value with a preset value; as well as According to the comparison result, the first data is determined to be the first category of data.

8. The memory management method according to claim 1 , wherein the first data is currently stored in a first physical unit among the plurality of physical units, and the memory management method further comprises: In response to the first data being determined as the first type of data, first address information corresponding to the first entity unit is recorded in a management area, The step of performing the second type of data sorting operation on the first type of data includes: Obtaining the first address information from the management area; and The first data is read from the first physical unit according to the first address information, and the first data is moved or copied to a second physical unit among the plurality of physical units.

9. The memory management method according to claim 8, further comprising: According to the total number of address information recorded in the management area, it is determined whether the total data volume of the first type of data reaches the critical value.

10. The memory management method according to claim 1, wherein the second type of data sorting operation is only for moving or copying the first type of data.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to: updating first mapping information corresponding to the first data, wherein the first mapping information reflects a mapping relationship between a first logical unit to which the first data belongs and one of the plurality of physical units; In response to the first mapping information being updated, updating first-category counting information corresponding to the first data; performing a first type of data sorting operation on the first data; In response to the first data being subjected to the first type of data sorting operation, updating the second type of counting information corresponding to the first data; determining, based on the first category counting information and the second category counting information, that the first data is first category data; and In response to the total data volume of the first category of data reaching a critical value, a second category of data sorting operation is performed on the first category of data. 12 . The storage device according to claim 11 , wherein the first type of counting information reflects the total number of times the first mapping information is updated, and the second type of counting information reflects the total number of times the first type of data shuffling operation is performed on the first data.

13. The storage device according to claim 11, wherein the memory controller performs the first type of data tidying operation on the first data comprises: The first data is moved or copied from a source physical unit among the plurality of physical units to a target physical unit among the plurality of physical units.

14. The storage device according to claim 11, wherein the memory controller is further configured to: In response to the first data being overwritten, the second-type counting information is reset.

15. The storage device according to claim 11 , wherein the memory controller determines, based on the first type counting information and the second type counting information, that the first data is the first type of data, comprising: performing a logical operation on the first type of counting information and the second type of counting information to obtain an evaluation value; as well as According to the evaluation value, the first data is determined to be the first category of data. 16 . The storage device according to claim 15 , wherein the first type of count information includes a first numerical value, the second type of count information includes a second numerical value, and the evaluation value reflects a ratio of the first numerical value to the second numerical value.

17. The storage device according to claim 15, wherein the memory controller determines, based on the evaluation value, that the first data is the first type of data, comprising: comparing the evaluation value with a preset value; as well as According to the comparison result, the first data is determined to be the first category of data.

18. The storage device according to claim 11, wherein the first data is currently stored in a first physical unit among the plurality of physical units, and the memory controller is further configured to: In response to the first data being determined as the first type of data, first address information corresponding to the first entity unit is recorded in a management area, The operation of the memory controller performing the second-type data sorting operation on the first-type data includes: obtaining the first address information from the management area; as well as The first data is read from the first physical unit according to the first address information, and the first data is moved or copied to a second physical unit among the plurality of physical units.

19. The storage device according to claim 18, wherein the memory controller is further configured to: According to the total number of address information recorded in the management area, it is determined whether the total data volume of the first type of data reaches the critical value.

20. The storage device according to claim 11, wherein the second type of data sorting operation only moves or copies the first type of data.

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