A dynamic graph processing method based on 1t2r memristor array

Abstract

The application discloses a dynamic graph processing method based on a 1T2R memristor array, and belongs to the technical field of in-memory computing and graph computing. The application stores the adjacency matrix of a graph on a memristor array composed of 1T2R units, stores the state of a node in the 1T2R unit at the (i, i) position, stores the information of an edge in the 1T2R unit at the (i, j) position, and represents the connection relationship between the node i and the node j; the operation on the node and the edge of the graph is mapped to the operation on the corresponding unit in the 1T2R memristor array, and the dynamic graph storage and the dynamic graph processing are efficiently performed. Through the array operation mode, the time complexity of the dynamic graph processing process is effectively reduced, the node increase, the node deletion, the edge increase and the edge deletion can be realized at the O(1) time complexity, the calculation speed of the dynamic graph processing is effectively improved, and higher storage density is realized on the storage of the dynamic graph data.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of memristor in-memory computing and the technical field of graph computing, and particularly relates to a dynamic graph computing scheme based on a memristor in-memory computing architecture. BACKGROUND

[0002] With the rapid development of the Internet of Things and artificial intelligence technology, the demand for computing and information processing of human society is rapidly growing. In the past decade, deep neural networks and large models have emerged, which have a high demand for the amount of information processing. At present, computers based on the traditional von Neumann architecture have a design of separation of computing and storage, and their computing efficiency is limited by the frequent transfer of data, which cannot meet the demand for efficient information processing of new computing. Graph processing is a widely used computing method in applications such as causal inference, molecular prediction, and social networks. The data used in graph processing has strong irregularity, and has a very high requirement for the efficiency of the processor. Therefore, graph processing urgently needs efficient special hardware for acceleration.

[0003] A dynamic graph is a special graph that represents a graph that can change over time. At a specific time point, the dynamic graph has the characteristics of a typical graph; and at different time points, the graph structure of the dynamic graph changes. Between different time points, the operations performed on the dynamic graph include adding nodes, deleting nodes, adding edges, and deleting edges.

[0004] Dynamic graphs can also be used to represent information such as social networks and material structures. Representing a social network at a certain time as a graph, the structure of the social network often evolves over time, and storing and computing such problems becomes more complex. Hardware for processing dynamic graph information needs to have a certain flexibility to adjust to changes in dynamic graphs at each time with small hardware overhead, while also having the high efficiency of a graph processor.

[0005] Emerging in-memory computing and new memory technology is a solution that can alleviate the bottleneck of the von Neumann architecture by placing storage and computing in the same location, which can reduce the hardware overhead of data access. In-memory computing based on a memristor array can realize an integrated computing architecture with high storage density, and the memristor itself can non-volatilely store information, avoiding repeated data loading and further reducing access overhead. In-memory computing technology based on a memristor array is expected to provide an effective solution for dynamic graph problems. SUMMARY

[0006] The purpose of the present application is to provide a circuit architecture and a dynamic graph computing scheme for processing dynamic graph data based on a memristor array, to realize high-parallelism hardware acceleration for dynamic graph processing.

[0007] The application is based on the existing 1T2R memristor unit and the 1T2R memristor array composed of the 1T2R memristor unit, and a scheme of mapping a dynamic graph and a processing operation of the dynamic graph to a programming operation of the 1T2R memristor array is developed to realize dynamic graph processing based on the 1T2R memristor array. In the scheme, an adjacency matrix A of the dynamic graph is mapped to the 1T2R memristor array, an operation on a node of the graph is mapped to an operation on an (i, i) unit in the 1T2R memristor array, and an operation on an edge of the graph is mapped to an operation on an (i, j) unit in the 1T2R memristor array, where i≠j.

[0008] As shown in (a) of FIG. 1, Figure 1 The 1T2R memristor unit is composed of one transistor and two memristors; one 1T2R memristor unit is connected to four lines in the array, which are BLL, WL, BLR and SL; BLL is parallel to WL, BLR is parallel to SL, and BLL and WL are perpendicular to BLR and SL. In the unit structure, the two memristors are named L-RRAM and R-RRAM, and the two memristors are commonly connected to the drain of the transistor; the other end of L-RRAM is connected to BLL; the other end of R-RRAM is connected to BLR; the gate of the transistor is connected to WL; and the source of the transistor is connected to SL.

[0009] As shown in (b) of FIG. 1, Figure 1 A 1T2R memristor array based on the 1T2R unit structure includes MxM (M rows and M columns) 1T2R memristor units; the array has M WLs, M BLLs, M BLRs and M SLs; the units in a row share the same BLL and the same WL, and the units in a column share the same BLR and the same SL.

[0010] On the 1T2R memristor array, a graph is stored using an adjacency matrix representation. For a graph with M nodes, the adjacency matrix A of the graph stores the entire graph using an MxM square matrix. In the square matrix, the element A ij stores the connection relationship between node i and node j (i.e., the edge between i and j), where i and j are integers, 0≤i ii stores the information of node i itself. For the actual deployment of the graph, A ij =A ji .

[0011] A dynamic graph is defined as a graph whose properties of nodes or edges change over time. If a dynamic graph is stored using an adjacency matrix A, then the adjacency matrix A will change over time. In a conventional processor or a traditional 1T1R memristor array, processing a dynamic graph requires a large time overhead and area cost. The dynamic graph processing scheme based on a 1T2R memristor array proposed in the present application can effectively reduce the time overhead and area cost of dynamic graph calculation. The dynamic graph processing scheme based on a 1T2R memristor array is as follows:

[0012] 1) Adjacency matrix mapping of a graph: For a graph with M nodes, there can be a directional connection between the nodes, that is, an edge between the nodes. The adjacency matrix A of the graph is an MxM square matrix, in which the element A ij stores the connection relationship between node i and node j (i.e., the edge between i and j). The size of A ij may be -1, 0, +1. When the size of A ij is 0, it means that there is no connection from node i to node j. The method proposed in the present application maps the adjacency matrix A to a 1T2R memristor array with a scale of MxM. In the memristor array, the memristor cell at position coordinate (i, i) stores the element A ii in the adjacency matrix A, that is, the node state; the memristor cell at position coordinate (i, j) stores the element A ij in the adjacency matrix, that is, the edge state.

[0013] 2) Node addition: If the i-th node is added, the operation is performed on the cell at position coordinate (i, i) in the 1T2R memristor array, and both memristors in the cell are set to the HRS (high resistance) state. This state indicates that the i-th node has been added. During data reading, the (i, i) position cell does not significantly increase the current at the BLR end. Detecting the current at the BLR end, no abnormal current is detected.

[0014] 3) Node deletion: If the i-th node is deleted, the operation is performed on the cell at position coordinate (i, i) in the 1T2R memristor array, and both memristors in the cell are set to the LRS (low resistance) state. This state indicates that the i-th node has been deleted. During data reading, the (i, i) position cell has two low resistance states, which significantly increases the current at the BLR end. Detecting the current at the BLR end, an abnormal current is detected. By the abnormal current in the i-th column, the outside can determine that the i-th node has been deleted.

[0015] 4) Edge addition: If the edge from the i-th node to the j-th node is added, the operation is performed on the cell at position coordinate (i, j) in the 1T2R memristor array, and the programming is performed according to the value of A ij . If Aij = +1, then set the two memristors L-RRAM and R-RRAM in the (i, j) cell to HRS and LRS states respectively, i.e. use the cell to represent +1. If A ij = -1, then set the two memristors L-RRAM and R-RRAM in the (i, j) cell to LRS and HRS states respectively, i.e. use the cell to represent -1.

[0016] 5) Edge deletion: if the edges from the i-th node to the j-th node are deleted, then operate on the cell with position coordinates (i, j) in the 1T2R memristor array. Set both the two memristors in the (i, j) cell to HRS state, i.e. use the cell to represent 0.

[0017] 6) Data readout: in the data readout stage, select an address i in each clock cycle, then the WL i and BLL i selected (set to high level). All the BLRs are grounded, and the current value passing through it is read out using an analog-to-digital converter (ADC). All the SLs are floating, and the voltage value it has is read out using an analog-to-digital converter (ADC). A total of M bits of data in the i-th row can be read out in one clock cycle. Among them, if the i-th bit BLR is read out as high current, it means that the node i has been deleted, and the i-th row of data read out this time is invalid; if the i-th bit BLR is read out as low current, it means that the node i has been added, and the i-th row of data read out this time is valid. By selecting the address i from 0 to M-1, the entire M rows of data of the 1T2R memristor array can be read out, i.e. the entire data of the adjacency matrix A is read out. A total of M clock cycles are spent to read out the entire adjacency matrix A.

[0018] The above processing scheme in the mapping of the adjacency matrix of a graph, for the cell with position coordinates (i, i) in the 1T2R memristor array, both the two memristors are HRS, which means that the node is valid, and both the two memristors are LRS, which means that the node is invalid. Whether the corresponding node is valid or not can be judged by reading out the current size of each BLR line in the 1T2R memristor array.

[0019] For the cell with position coordinates (i, j) in the 1T2R memristor array, the combination of L-RRAM and R-RRAM is (HRS, HRS), which means 0, i.e. an edge does not exist; the combination of L-RRAM and R-RRAM is (HRS, LRS), which means +1, i.e. the edge has a value of +1; the combination of L-RRAM and R-RRAM is (LRS, HRS), which means -1, i.e. the edge has a value of -1.

[0020] The edge addition operation is to set the two memristors L-RRAM and R-RRAM in the (i, j) cell to (HRS, LRS) or (LRS, HRS) according to A ij(HRS, HRS) to (LRS, HRS) or (HRS, LRS); and the edge deletion operation is to change the two memristors of the 1T2R memristor unit with the position coordinates (i, j) from (LRS, HRS) or (HRS, LRS) to (HRS, HRS).

[0021] In the data readout, the above processing scheme experiences M clock cycles to read out the adjacency matrix of the graph of M nodes. According to the current on the i-th BLR line, it is determined whether the i-th node is valid. If the current on the i-th BLR line is high, the i-th node is invalid; if the current on the i-th BLR line is low, the i-th node is valid.

[0022] In the 1T2R memristor array, the memristor is preferably a memristor based on a metal-insulator-insulator-metal structure or a memristor based on a metal-semiconductor-semiconductor-metal structure, which has multiple stable resistance states, wherein the highest resistance state is the high resistance state HRS and the lowest resistance state is the low resistance state LRS; and the transistor is preferably an N-type metal oxide semiconductor field effect transistor.

[0023] The present application has the following beneficial effects:

[0024] By constructing a dynamic graph processing scheme based on the 1T2R memristor array, the time complexity of the dynamic graph processing process can be effectively reduced. As shown in the following table, for a graph with M nodes, the adjacency matrix size is MxM. When using a traditional 1T1R memristor array to store dynamic graph data, increasing nodes and deleting nodes both require O(M) time complexity, i.e., the time consumed is proportional to M. Increasing edges and deleting edges require O(1) time complexity, i.e., the time consumed is a constant. When using the 1T2R memristor array proposed in the present application to store dynamic graph data, increasing nodes and deleting nodes only require O(1) time complexity, i.e., the time consumed is a constant. Increasing edges and deleting edges require O(1) time complexity, i.e., the time consumed is a constant. In practical applications, the time consumed by O(1) time complexity operation is less than that of O(M) time complexity operation, and as M increases, the advantage of O(1) time complexity operation is more obvious. Therefore, the dynamic graph mapping method based on the 1T2R array proposed in the present application can effectively improve the calculation speed of the dynamic graph processing of the memristor array.

[0025] Time complexity Conventional 1T1R memristor array 1T2R memristor array Add node O(M) O(1) Delete node O(M) O(1) Add edge O(1) O(1) Delete edge O(1) O(1)

[0026] In terms of storage density, considering that the value range of each edge is -1, 0, and +1, a traditional 1T1R memristor array requires two 1T1R cells to store the value of one edge, while the graph mapping method based on the 1T2R array in the present invention only requires one 1T2R cell to store the value of one edge. The area of ​​both the 1T1R cell and the 1T2R cell is approximately the size of a single transistor. Therefore, the graph mapping method based on the 1T2R array proposed in the present invention can effectively improve the area density of graph data storage in the memristor array.

[0027] In summary, the graph mapping method based on 1T2R array proposed in the present invention improves the dynamic graph processing speed and area density, and can perform dynamic graph calculations more efficiently in real applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of (a) a 1T2R memristor unit and (b) a 1T2R memristor array composed of 1T2R memristor units used in the present invention.

[0029] Figure 2 This is the graph data mapping solution based on the 1T2R memristor array proposed by the present invention, where the cells in the dotted box represent nodes and the other cells represent edges.

[0030] Figure 3 An example of a specific graph adjacency matrix and its mapping on a 1T2R memristor array is shown, where the cells in the dashed box represent nodes and the other cells represent edges.

[0031] Figure 4 Shows a Figure 3 An example of dynamic graph processing based on this method, and its mapping on the 1T2R memristor array, where the cells in the dotted box represent nodes and the other cells represent edges. DETAILED DESCRIPTION

[0032] The present invention will be further described below through specific embodiments in conjunction with the accompanying drawings.

[0033] The following embodiments are carried out using a memristor array with an actual 1T2R unit structure. The structure of the memristor array is as follows: Figure 1 The operations applied in the key programming steps are given, and an embodiment of the memristor storage and computing integrated architecture is given.

[0034] 1) Graph adjacency matrix mapping: such as Figure 3 As shown, for a node with M nodes (node ​​N0 to node N M-1 ) graph, there can be directed connections between its nodes, that is, edges between nodes. The adjacency matrix A of the graph is an M×M square matrix, in which the element A with coordinates (i, i)ii Element A of the representative node with coordinates (i, j) ij Stores the connection between node i and node j (i.e. the edge between i and j). A ij The size of A can be -1, 0, +1. When A ij is 0, it means there is no connection from node i to node j. In this example, there is a bidirectional connection between node N0 and node N1 with both connection sizes being +1. There is a unidirectional connection from N0 to N M-1 with size -1 between N0 and N M-1 . Node N0 is active and node N1 is inactive. The method proposed in this invention maps the adjacency matrix A into a 1T2R memristor array of size M x M. In this memristor array, the memristor cell at position (i, j) stores the element A ij of the adjacency matrix. In the memristor array, both (0, 1) and (1, 0) positions represent +1, position (0, 0) stores information that node N0 is active, and position (1, 1) stores information that node N1 is inactive.

[0035] 2) Node addition: Figure 4 shows the change of the dynamic graph at the next time instant, in which N1 node is added. The cell at position (1, 1) in the memristor array is operated to set both memristors in this cell to HRS (High Resistance State). This state indicates that N1 node has been added. In the data readout process, a low current is read out on BLR1 data line, proving that N1 node is active.

[0036] 3) Node deletion: Figure 4 shows the process of deleting node N M-1 . The cell at position (M-1, M-1) in the memristor array is operated to set both memristors in this cell to LRS (Low Resistance State). This state indicates that N M-1 node has been deleted. In the data readout process, a high current is read out on BLR M-1 data line, proving that N M-1 node is inactive.

[0037] 4) Edge addition: Figure 4 shows the change of the dynamic graph at the next time instant, in which the edge from N1 node to N M-1 node, the cell at position (1, M-1) in the memristor array is operated to set the left memristor to HRS and the right memristor to LRS, i.e. to use this cell to represent +1. This operation indicates that the edge from N1 node to N M-1 node has been added with size +1.

[0038] 5) Edge deletion: Figure 4The process of deleting the edge from N0 node to N1 node is shown. The cell at (0, 1) position in the memristor array is operated to set the two memristors in the cell to HRS, HRS, i.e. the cell represents 0. The operation represents that the edge from N0 node to N1 node has been deleted.

[0039] The above embodiments are only used to illustrate the technical solutions of the present application but not to limit the present application, and ordinary skilled in the art can modify or equivalently replace the technical solutions of the present application without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the description of the claims.

Claims

1.A dynamic graph processing method based on a 1T2R memristor array, the dynamic graph and processing operations of the dynamic graph are mapped to a 1T2R memristor array and programming operations of the 1T2R memristor array, wherein, The 1T2R memristor array comprises MxM 1T2R memristor units, each of which is connected with four lines BLL, WL, BLR and SL, wherein BLL is parallel to WL, and BLR is parallel to SL, and the two groups of parallel lines are perpendicular to each other; each 1T2R memristor unit is composed of one transistor and two memristors L-RRAM and R-RRAM, one end of L-RRAM and R-RRAM is commonly connected to the drain of the transistor, the other end of L-RRAM is connected to BLL, and the other end of R-RRAM is connected to BLR; the gate of the transistor is connected to WL; the source of the transistor is connected to SL; the 1T2R memristor array has M WLs, M BLLs, M BLRs and M SLs; the 1T2R memristor units in one row share the same BLL and the same WL, and the 1T2R memristor units in one column share the same BLR and the same SL. For a dynamic graph with M nodes, the adjacency matrix A of the graph stores the whole graph using an M x M square matrix, in which the element A ij stores the connection relationship between node i and node j, i.e., the edge between node i and j, the element A ii stores the information of node i itself; mapping the adjacency matrix A of the dynamic graph to the 1T2R memristor array, the operation on the nodes of the graph is mapped to the operation on the cell with coordinates (i, i) in the 1T2R memristor array, and the operation on the edges of the graph is mapped to the operation on the cell with coordinates (i, j) in the 1T2R memristor array, wherein, i and j are integers from 0 to M-1, and i≠j. 2.The dynamic map processing method of claim 1, wherein, It comprises: 1) Graph adjacency matrix mapping: In the 1T2R memristor array, the memristor cell with position coordinates (i, i) stores the element A ii , i.e. the node state, both memristors in the memristor cell are in HRS, i.e. high resistance state, representing the node is valid, both memristors are in LRS, i.e. low resistance state, representing the node is invalid; the memristor cell with position coordinates (i, j) stores the element A ij , i.e. the edge state, the size of element A ij is -1, 0 or +1, when the size of A ij is 0, it means there is no connection from node i to node j; in the memristor cell with position coordinates (i, j), when both L-RRAM and R-RRAM are in HRS state, it represents the number 0, when L-RRAM is in HRS state and R-RRAM is in LRS state, it represents the number +1, when L-RRAM is in LRS state and R-RRAM is in HRS state, it represents the number -1; 2) node addition: if the ith node is added, the unit with the position coordinates (i, i) in the 1T2R memristor array is operated, and both of the two memristors in the unit are set to HRS state, indicating that the ith node has been added; 3) node deletion: if the ith node is deleted, the unit with the position coordinates (i, i) in the 1T2R memristor array is operated, and both of the two memristors in the unit are set to LRS state, indicating that the ith node has been deleted; 4) Edge addition: If an edge between the ith node and the jth node is added, then the cell at position (i, j) in the 1T2R memristor array is operated according to the value of A ij : If A ij = +1, then the two memristors L-RRAM and R-RRAM of the (i, j) cell are set to HRS and LRS states respectively, i.e. the cell is used to represent +1; if A ij = -1, then the two memristors L-RRAM and R-RRAM of the (i, j) cell are set to LRS and HRS states respectively, i.e. the cell is used to represent -1. 5) edge deletion: if the edge from the ith node to the jth node is deleted, the unit with the position coordinates (i, j) in the 1T2R memristor array is operated, and both of the two memristors in the (i, j) unit are set to HRS state, i.e. using the unit to represent 0. The memristor is a memristor based on a metal-insulator-insulator-metal structure, or a memristor based on a metal-semiconductor-semiconductor-metal structure. 3.The dynamic map processing method of claim 2, wherein, In the data readout phase, an address i is selected in each clock cycle, and WL in the 1T2R memristor array i With BLL i is selected and set to a high level; all BLRs are grounded, and the analog-to-digital converter is used to read the current value passing through it; all SLs are floating, and the analog-to-digital converter is used to read the voltage value it has; one clock cycle can read out M bits of data in the i-th row, among which, if the i-th BLR reads a high current, it means that the node i has been deleted and the i-th row data read this time is invalid; if the i-th BLR reads a low current, it means that the node i has been added and the i-th row data read this time is valid; the selected address i is traversed from 0 to M-1, and all M rows of data of the 1T2R memristor array are read out, that is, all data of the adjacency matrix A is read out. 4.The dynamic map processing method of claim 1, wherein, The transistor is an N-type metal oxide semiconductor field effect transistor. 5.The dynamic map processing method of claim 1, wherein, ​

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