A semiconductor device and a process testing method

Abstract

An embodiment of the present invention discloses a semiconductor device and a process testing method, relating to the field of semiconductor technology, which can facilitate the discovery of abnormal process steps occurring in the manufacture of semiconductor devices, thereby facilitating targeted improvement of related semiconductor processes. The semiconductor device includes: at least one conductive layer and at least one dielectric layer stacked alternately; each of the conductive layers includes at least one detection pattern; each of the detection patterns includes two conductive lines arranged in parallel and spaced apart from each other, wherein two end points of each of the conductive lines are respectively led out of the semiconductor device through metal pins. The present invention can be applied to semiconductor testing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and a process testing method. Background Art

[0002] In the process of semiconductor manufacturing, various process defects may occur, resulting in the failure of the corresponding die, thus greatly reducing the die yield. For example, the abnormalities occurring in the die at the edge of the wafer during the process are significantly higher than those in other regions. In some cases, abnormalities even continuously occur at fixed positions on the edge, leading to the die yield of this part approaching 0.

[0003] In the related art, although the failed die can be found by testing the die, it is very difficult to find out which specific process is abnormal based on the test results, so it is not conducive to the further improvement of the process. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a semiconductor device and a process testing method, which can facilitate the discovery of the process steps with abnormalities in the manufacture of the semiconductor device, thereby facilitating the targeted improvement of related semiconductor processes.

[0005] In a first aspect, an embodiment of the present invention provides a semiconductor device, including: at least one conductive layer and at least one dielectric layer stacked alternately; each of the conductive layers includes at least one detection pattern; each of the detection patterns includes two conductive lines arranged in parallel and spaced apart from each other, and two end points of each of the conductive lines are respectively led out of the semiconductor device through metal pins.

[0006] In an implementation manner, each of the conductive layers further includes at least one chip pattern; there is no electrical connection between the detection pattern and the chip pattern.

[0007] In an implementation manner, each of the chip patterns has a corresponding first region in the conductive layer, each of the chip patterns is disposed in the corresponding first region, and the first regions are spaced apart from each other on the conductive layer; each of the detection patterns is disposed in one of the first regions or outside each of the first regions.

[0008] In one embodiment, a preset number of the first regions are arranged in an array on the conductive layer to form a first array; the setting position of each detection pattern includes any one of the following: being set within one of the first regions; being set between at least two adjacent first regions; being set outside the rectangular envelope corresponding to the first array and near any target position of the rectangular envelope, corresponding to the target position, and the distance between any point on the detection pattern and the target position is within a preset range; wherein, the rectangular envelope is a rectangle outlined by the outer contour line of the first array; the target position includes any vertex or any side of the rectangular envelope; the detection patterns corresponding to the respective target positions of the rectangular envelope and the first array together form a second array.

[0009] In one embodiment, one or more detection patterns are provided near each target position of the rectangular envelope.

[0010] In one embodiment, each conductive layer includes one or more second arrays; the second arrays in the same conductive layer are the same; the second arrays in different conductive layers are different; the second array in any conductive layer corresponds to the pattern on the mask used to manufacture the conductive layer.

[0011] In one embodiment, the first region is rectangular, and one or more detection patterns are correspondingly provided near each vertex of each first region, and the distance between any point on the detection pattern and the corresponding vertex is within a preset range.

[0012] In one embodiment, one or more detection patterns are also correspondingly provided near the four right-angled sides of the first region, and the distance between any point on the detection pattern and the corresponding right-angled side is within the preset range.

[0013] In one embodiment, the shape of each conductive line includes any one of the following: a line segment, a broken line formed by splicing multiple line segments.

[0014] In one embodiment, in the broken line, the included angle between two adjacent line segments is 90 degrees.

[0015] In one embodiment, the conductive layer includes a metal layer and / or a polysilicon layer.

[0016] In one embodiment, the width of the conductive line is the minimum line width under a preset process, and the spacing between two conductive lines is the minimum line spacing under the preset process.

[0017] Second aspect, an embodiment of the present invention provides a process test method, which is applied to any semiconductor device provided by the embodiment of the present invention. The method includes: obtaining a measured value of a preset electrical parameter through a metal pin corresponding to at least one of the conductive wires in the semiconductor device; determining whether there is an abnormality in the process corresponding to at least one of the conductive layers or at least one of the dielectric layers in the semiconductor device according to the measured value and the theoretical value of the preset electrical parameter.

[0018] In one implementation manner, the obtaining a measured value of a preset electrical parameter through a metal pin corresponding to at least one of the conductive wires in the semiconductor device includes at least one of the following: obtaining a measured value of a first parameter of the conductive wire through two metal pins corresponding to two end points of one conductive wire, where the first parameter includes: current flowing through the conductive wire and / or resistance of the conductive wire; obtaining a measured value of a second parameter between two conductive wires through a metal pin corresponding to one end point of one conductive wire and a metal pin corresponding to one end point of another conductive wire, where the second parameter includes at least one of the following: current between the two conductive wires, resistance between the two conductive wires, capacitance between the two conductive wires.

[0019] In one implementation manner, the determining whether there is an abnormality in the process corresponding to at least one of the conductive layers or at least one of the dielectric layers in the semiconductor device according to the measured value and the theoretical value of the preset electrical parameter includes at least one of the following: when the absolute value of the difference between the measured value and the theoretical value of the first parameter is greater than or equal to a first difference threshold, determining that there is a break in the conductive wire in the conductive layer; when the absolute value of the difference between the measured value and the theoretical value of the first parameter is less than the first difference threshold, determining that there is no break in the conductive wire in the conductive layer; when the absolute value of the difference between the measured value and the theoretical value of the current and / or resistance between the two conductive wires is greater than or equal to a second difference threshold, determining that there is a short circuit between the conductive wires in the conductive layer; when the absolute value of the difference between the measured value and the theoretical value of the current and / or resistance between the two conductive wires is less than the second difference threshold, determining that there is no short circuit between the conductive wires in the conductive layer; when the absolute value of the difference between the measured value and the theoretical value of the capacitance between the two conductive wires is greater than or equal to a third difference threshold, and there is no break in the conductive wire and no short circuit between the conductive wires in the conductive layer, determining that there is a flaw in the dielectric layer covering the conductive layer; when the absolute value of the difference between the measured value and the theoretical value of the capacitance between the two conductive wires is less than the third difference threshold, and there is no break in the conductive wire and no short circuit between the conductive wires in the conductive layer, determining that there is no flaw in the dielectric layer covering the conductive layer.

[0020] The semiconductor device and process test method provided by the embodiments of the present invention, the semiconductor device includes at least one conductive layer and at least one dielectric layer stacked alternately; each conductive layer includes at least one detection pattern; each detection pattern includes two conductive lines arranged in parallel and spaced apart from each other, wherein the two end points of each conductive line are respectively led out of the semiconductor device through metal pins. In this way, one or more electrical parameters of the detection pattern can be tested by means of the metal pins corresponding to the end points of the conductive lines in the detection pattern. When the measured values of these electrical parameters are inconsistent with the theoretical values, it can be determined that a process anomaly has occurred in the conductive layer or dielectric layer related to the detection pattern, thereby facilitating targeted improvement of the relevant semiconductor process. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 A schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0023] Figure 2 A schematic structural diagram of a detection pattern in an embodiment of the present invention;

[0024] Figure 3 Another schematic structural diagram of a detection pattern in an embodiment of the present invention;

[0025] Figure 4 Another schematic structural diagram of a detection pattern in an embodiment of the present invention;

[0026] Figure 5 Another schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0027] Figure 6 Another schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0028] Figure 7 Another schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0029] Figure 8 Another schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0030] Figure 9 Another schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0031] Figure 10 Another structural schematic diagram of the semiconductor device provided by the embodiment of the present invention;

[0032] Figure 11 A flowchart of a process test method provided by the embodiment of the present invention;

[0033] Figure 12 A connection schematic diagram of a test device in the process test method provided by the embodiment of the present invention;

[0034] Figure 13 Another connection schematic diagram of a test device in the process test method provided by the embodiment of the present invention. Detailed implementation manners

[0035] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0037] In a first aspect, the embodiment of the present invention provides a semiconductor device, which can facilitate the discovery of abnormal process steps in the manufacture of the semiconductor device, thereby facilitating the targeted improvement of related semiconductor processes.

[0038] As Figure 1 shown, the embodiment of the present invention provides a semiconductor device, including:

[0039] At least one conductive layer 1 and at least one dielectric layer (not shown) stacked alternately;

[0040] Each conductive layer 1 includes at least one detection pattern 11;

[0041] Each detection pattern 11 includes two conductive lines 12 that are parallel to each other and spaced apart, and two end points 120 of each conductive line 12 are respectively led out of the semiconductor device through metal pins (not shown).

[0042] The semiconductor device provided by the embodiment of the present invention includes at least one conductive layer 1 and at least one dielectric layer stacked alternately; each conductive layer 1 includes at least one detection pattern 11; each detection pattern includes two conductive lines 12 arranged in parallel and spaced apart from each other, wherein two end points 120 of each conductive line 12 are respectively led out of the semiconductor device through metal pins. In this way, one or more electrical parameters of the detection pattern 11 can be tested by means of the metal pins corresponding to the end points 120 of the conductive lines 12 in the detection pattern 11. When the measured values of these electrical parameters are inconsistent with the theoretical values, it can be determined that a process anomaly has occurred in the conductive layer 1 or the dielectric layer related to the detection pattern 11, thereby facilitating targeted improvement of the relevant semiconductor process.

[0043] Specifically, for the semiconductor device provided by the embodiment of the present invention, the conductive layer 1 can be a layer formed of a material with conductive properties, and the dielectric layer can be a layer formed of a material with insulating properties. Exemplarily, in one implementation, the conductive layer 1 can include a metal layer and / or a polysilicon layer.

[0044] In the embodiment of the present invention, the conductive layer 1 can include one or more detection patterns 11. Each detection pattern 11 can include two conductive lines 12 parallel to each other. Specifically, in one implementation, the two conductive lines 12 only need to be arranged parallel to each other, and the specific shape of each conductive line 12 is not limited. For example, as Figure 2 shown, in one example, the two conductive lines 12 can both be line segments. In another example, as Figure 3 shown, the two conductive lines 12 can both be broken lines formed by splicing multiple line segments, and the included angle and folding direction between adjacent line segments in the broken line are not limited. Exemplarily, as Figure 4 shown, in one embodiment of the present invention, in the broken line corresponding to the conductive line 12, the included angle between adjacent two line segments can be 90 degrees.

[0045] In each detection pattern 11, the width of the conductive line 12 and the spacing between the two conductive lines 12 can be not limited. In one example, the width of the conductive line 12 can be the minimum line width under a preset process, and the spacing between the two conductive lines 12 can be the minimum line spacing under a preset process, so as to effectively improve the sensitivity of process anomaly detection.

[0046] Furthermore, in the embodiment of the present invention, in addition to including one or more detection patterns 11, each conductive layer 1 can also include other patterns. For example, as Figure 5As shown, in one embodiment, each conductive layer 1 may further include one or more chip patterns 13, where there is no electrical connection between the detection pattern 11 and the chip pattern 13. Specifically, the chip pattern 13 may refer to the pattern for implementing the main functions of the chip, and the detection pattern 11 may refer to the pattern for implementing the process detection function, that is, the detection pattern 11 is not used to implement the main functions of the chip. In one example, the chip pattern 13 may be a more complex pattern occupying a larger area, and the detection pattern 11 may be a simpler pattern occupying a smaller area.

[0047] In the semiconductor device provided by the embodiment of the present invention, the number of chip patterns 13 and detection patterns 11 in each conductive layer 1 may be one or more. When each conductive layer 1 includes one chip pattern 13, the semiconductor device provided by the embodiment of the present invention may specifically be an independent chip, and the chip pattern 13 belongs to the independent chip; when each conductive layer 1 includes multiple chip patterns 13, each chip pattern 13 may belong to different chips respectively. In this case, the semiconductor device provided by the embodiment of the present invention may be an integration of multiple chips, such as a wafer that has been manufactured but not yet diced.

[0048] In the embodiment of the present invention, each chip pattern 13 and each detection pattern 11 may be spaced apart from each other on the conductive layer 1. Specifically, as Figure 6 shown, in one embodiment of the present invention, each chip pattern 13 may have a corresponding first region 14 in the conductive layer 1, each chip pattern 13 may be disposed within the corresponding first region 14, and the first regions 14 are spaced apart from each other on the conductive layer 1; each detection pattern 11 may be disposed within one of the first regions 14 or outside the first regions 14.

[0049] In one example, the first region 14 may be a region planned for each chip in the semiconductor device. In the same conductive layer 1, the size and shape of each first region 14 may be adapted to the contour of the corresponding chip. Based on this, the different first regions 14 in the same conductive layer 1 are spaced apart from each other, which means that different chips in the semiconductor device are spaced apart from each other, so that the different chips in the semiconductor device can be separated from each other through operations such as dicing in the later stage.

[0050] As mentioned above, each chip pattern 13 is located inside the corresponding first region 14, but the setting position of each detection pattern 11 can be more flexible. It can be set inside the first region 14 or outside the first region 14. Optionally, when the detection pattern 11 is located inside the first region 14, the detection pattern 11 is located on the corresponding chip. However, since the pattern structure of the detection pattern 11 is relatively simple, even if it is set inside the first region 14, it will not occupy too much chip area. When the detection pattern 11 is located outside the first region 14, the detection pattern 11 is actually not located on the corresponding chip, that is, the detection pattern 11 does not occupy the chip area in the semiconductor device, but effectively utilizes the area resources between the chips (such as scribe lanes) in the semiconductor device.

[0051] In an embodiment of the present invention, the first region 14 can not only have a corresponding relationship with the chip pattern 13, but also have a corresponding relationship with the detection pattern 11. For example, in one example, each first region 14 can correspond to one or more detection patterns 11. Similarly, among these detection patterns 11, there can be detection patterns 11 located inside the first region 14 and detection patterns 11 located outside the first region 14. The embodiments of the present invention do not limit this.

[0052] Specifically, as Figure 7 shown, in one implementation, the first region 14 can be rectangular, and one or more detection patterns 11 are correspondingly arranged near each vertex of each first region 14. The distance between any point on the detection pattern 11 and the corresponding vertex is within a preset range. As Figure 8 shown, in another implementation, one or more detection patterns 11 are also correspondingly arranged near the four right-angled sides of the first region 14. The distance between any point on the detection pattern 11 and the corresponding right-angled side is within a preset range. In this way, due to the corresponding relationship between the detection pattern 11 and the first region 14, the detection pattern 11 can be widely distributed on the semiconductor device along with the first region 14, so as to widely monitor process anomalies during the manufacturing process of the semiconductor device. Among them, the preset range can be set and modified as needed. Exemplarily, in one example, the preset range can be 5 to 30 times the minimum line pitch under a preset process.

[0053] Optionally, the distribution rule of the first region 14 on the conductive layer 1 is not limited. It can be evenly distributed or non-uniformly distributed, as long as they are spaced apart from each other. Exemplarily, as Figure 9As shown, in one example, the conductive layer 1 may include a plurality of first regions 14, where a preset number of first regions may be arranged in an array on the conductive layer 1 to form a first array 15. Based on this, the setting position of each detection pattern 11 may include any one of the following:

[0054] Set within one of the first regions 14 (not shown);

[0055] Set between at least two adjacent first regions 14 (not shown);

[0056] Set outside the rectangular envelope 16 corresponding to the first array 15 and near any target position 161 of the rectangular envelope 16. Corresponding to the target position 161, the distance between any point on the detection pattern 11 and the target position 161 is within a preset range; where the rectangular envelope 16 is a rectangle outlined by the outer contour line of the first array 15; the target position 161 includes any vertex or any side of the rectangular envelope 16 ( Figure 9 as shown is the upper left vertex of the rectangular envelope 16); the detection patterns 11 corresponding to the respective target positions 161 of the rectangular envelope 16 and the first array 15 together form a second array 17. Among them, the preset range can be set and modified as needed. Exemplarily, in one example, the preset range may be 5 to 30 times the minimum line pitch under a preset process.

[0057] In this embodiment, the detection pattern 11 may be set near any target position 161 of the rectangular envelope 16, but the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, corresponding detection patterns 11 may also be set near other target positions 161 of the rectangular envelope 16. For example, as Figure 10 shown, in another embodiment of the present invention, one or more detection patterns 11 may be set near each target position 161 of the rectangular envelope 16. For example, one or more detection patterns 11 may be set near the four vertices of the rectangular envelope 16. Correspondingly, the first array 15 and the detection patterns 11 near the four vertices of the rectangular envelope 16 together form a corresponding second array 17.

[0058] In specific implementation, the number of the second arrays 17 in each conductive layer 1 is not limited. Each conductive layer 1 may include one second array 17 or multiple second arrays 17. The second arrays 17 in the same conductive layer 1 may be the same; the second arrays 17 in different conductive layers 1 may be different. In one example, the second array 17 in any conductive layer 1 may correspond to the pattern on the mask used to manufacture the conductive layer 1. Since in the lithography process, the area of the wafer is large while the area of a single exposure is small, in this way, in the lithography process of the semiconductor device manufacturing process, through multiple exposures, the pattern on the mask can be replicated multiple times at different positions on the wafer, and multiple corresponding second arrays 17 are obtained. Since the second array 17 includes the detection pattern 11 disposed near the target position 161 of the rectangular envelope 16, for the second array 17 distributed near the edge of the wafer, the edge position of the second array 17 (i.e., near the vertex or edge of the rectangular envelope 16) will be closer to the edge of the wafer. Since the process uniformity and stability at the wafer edge are relatively poor, therefore, by disposing the detection pattern 11 near the vertex or edge of the rectangular envelope 16, the process anomalies at the wafer edge can be sensitively captured, so as to strengthen the detection of the weak points in the process flow.

[0059] Further, in addition to using the second array 17 near the wafer edge to detect the process anomalies at the wafer edge, the second array 17 located in the non-edge area of the wafer can also be used to detect the process conditions in its area. For example, in some cases, due to problems such as parameter settings of the process equipment, even in the central area of the wafer, the yield may be relatively low. Therefore, the detection pattern 11 in the second array 17 located in the central area of the wafer can also be used to detect the processing technology of the semiconductor device.

[0060] Corresponding to the foregoing semiconductor device, in a second aspect, an embodiment of the present invention further provides a process testing method, which is convenient for discovering the process steps with anomalies in semiconductor device manufacturing, so as to facilitate targeted improvement of relevant semiconductor processes.

[0061] As Figure 11 shown, the process testing method provided by the embodiment of the present invention is applied to the semiconductor device provided in any of the foregoing embodiments. The method may include:

[0062] S31. Obtain the measured value of a preset electrical parameter through the metal pins corresponding to at least one conductive wire 12 in the semiconductor device;

[0063] S32. Determine whether there are anomalies in the process corresponding to at least one conductive layer 1 or at least one dielectric layer in the semiconductor device according to the measured value and the theoretical value of the preset electrical parameter.

[0064] The process test method provided by an embodiment of the present invention is applied to the semiconductor device provided by any of the foregoing embodiments. It can obtain the measured value of a preset electrical parameter through the metal pins corresponding to at least one conductive line 12 in the semiconductor device, and determine whether there is an abnormality in the process corresponding to at least one conductive layer 1 or at least one dielectric layer in the semiconductor device according to the measured value and the theoretical value of the preset electrical parameter. Since the semiconductor device includes at least one conductive layer 1 and at least one dielectric layer stacked alternately; each conductive layer 1 includes at least one detection pattern 11; each detection pattern includes two conductive lines 12 arranged in parallel and spaced apart from each other, and two end points 120 of each conductive line 12 are respectively led out of the semiconductor device through metal pins. In this way, the preset electrical parameter of the detection pattern 11 can be tested by means of the metal pins corresponding to the end points 120 of the conductive lines 12 in the detection pattern 11. When the measured values of these preset electrical parameters are inconsistent with the theoretical values, it can be determined that a process abnormality has occurred in the conductive layer 1 or the dielectric layer related to the detection pattern 11, thereby facilitating targeted improvement of the relevant semiconductor process.

[0065] Specifically, step S31 of obtaining the measured value of the preset electrical parameter through the metal pins corresponding to at least one conductive line 12 in the semiconductor device may include one or more of the following:

[0066] Obtaining the measured value of the first parameter of a conductive line 12 through two metal pins corresponding to two end points 120 of the conductive line 12, where the first parameter includes: the current flowing through the conductive line 12 and / or the resistance of the conductive line 12;

[0067] Obtaining the measured value of the second parameter between two conductive lines 12 through a metal pin corresponding to one end point 120 of one conductive line 12 and a metal pin corresponding to one end point 120 of another conductive line 12, where the second parameter includes at least one of the following: the current between the two conductive lines 12, the resistance between the two conductive lines 12, and the capacitance between the two conductive lines 12.

[0068] In this step, the test equipment can be connected to the metal pins corresponding to the conductive lines 12 in the detection pattern 11, and excitation signals such as voltage and current can be applied to the detection pattern 11 through the metal pins, so as to measure the preset electrical parameters corresponding to the detection pattern 11. Specifically, in this step, the current flowing through any one of the conductive lines 12 in the detection pattern 11 and the resistance of any one of the conductive lines 12 can be measured, or the leakage current between two conductive lines 12 in the detection pattern 11, the resistance between two conductive lines 12, the capacitance between two conductive lines 12, etc. can also be measured. Optionally, when measuring the leakage current between two conductive lines 12 in the detection pattern 11, the resistance between two conductive lines 12, and the capacitance between two conductive lines 12, the measuring device can be connected to the different-side endpoints of the two conductive lines 12 (see Figure 12 ), or can be connected to the same-side endpoints of the two conductive lines 12 (see Figure 13 ). The embodiments of the present invention do not limit this.

[0069] Further, after obtaining the preset electrical parameters of the semiconductor device, in step S32, it is possible to determine whether there is an abnormality in the process corresponding to at least one conductive layer 1 or at least one dielectric layer in the semiconductor device according to the measured value and the theoretical value of the preset electrical parameters. Specifically, in an embodiment of the present invention, determining whether there is an abnormality in the process corresponding to at least one conductive layer 1 or at least one dielectric layer in the semiconductor device according to the measured value and the theoretical value of the preset electrical parameters may include one or more of the following:

[0070] When the absolute value of the difference between the measured value and the theoretical value of the first parameter is greater than or equal to the first difference threshold, it is determined that there is a break in the conductive line 12 in the conductive layer 1; when the absolute value of the difference between the measured value and the theoretical value of the first parameter is less than the first difference threshold, it is determined that there is no break in the conductive line 12 in the conductive layer 1; for example, in an embodiment of the present invention, the first difference threshold is 0.1 μA, the measured value of the first current parameter is 0.2 μA, the theoretical value of the first current parameter is 0.18 μA, and the absolute value of the difference between the measured value and the theoretical value is 0.02 μA. Since the absolute value of the difference between the two, 0.02 μA, is less than the first difference threshold of 0.1 μA, it can be determined that there is no break in the conductive line 12 in the conductive layer 1. In another embodiment of the present invention, the first difference threshold is 0.1 μA, the measured value of the first current parameter is 0 μA, the theoretical value of the first current parameter is 0.18 μA, and the absolute value of the difference between the measured value and the theoretical value is 0.18 μA. Since the absolute value of the difference between the two, 0.18 μA, is greater than the first difference threshold of 0.1 μA, it can be determined that there is a break in the conductive line 12 in the conductive layer 1.

[0071] If the absolute value of the difference between the measured value and the theoretical value of the current and / or resistance between the two conductive wires is greater than or equal to a second difference threshold, it is determined that there is a short circuit between the conductive wires 12 in the conductive layer 1; if the absolute value of the difference between the measured value and the theoretical value of the current and / or resistance between the two conductive wires is less than the second difference threshold, it is determined that there is no short circuit between the conductive wires 12 in the conductive layer 1. For example, in an embodiment of the present invention, the second difference threshold is 10,000 ohms, the measured value of the resistance between the two conductive wires 12 is 900,000,000 ohms, the theoretical value of the resistance between the two conductive wires 12 is 900,000,000 ohms, and the absolute value of the difference between the measured value and the theoretical value is 0 ohms. Since the absolute value of the difference between the two, 0 ohms, is less than the second difference threshold of 10,000 ohms, it can be determined that there is no short circuit between the conductive wires 12 in the conductive layer 1. In another embodiment of the present invention, the second difference threshold is 10,000 ohms, the measured value of the resistance between the two conductive wires 12 is 800 ohms, the theoretical value of the resistance between the two conductive wires 12 is 900,000,000 ohms, and the absolute value of the difference between the measured value and the theoretical value is 890,000,200 ohms. Since the absolute value of the difference between the two, 890,000,200 ohms, is greater than the second difference threshold of 10,000 ohms, it can be determined that there is a short circuit between the conductive wires 12 in the conductive layer 1.

[0072] If the absolute value of the difference between the measured value and the theoretical value of the capacitance between the two conductive wires 12 is greater than or equal to a third difference threshold, and there is no breakage of the conductive wires 12 and no short circuit between the conductive wires 12 in the conductive layer 1, it is determined that there are defects in the dielectric layer covering the conductive layer 1; if the absolute value of the difference between the measured value and the theoretical value of the capacitance between the two conductive wires 12 is less than the third difference threshold, and there is no breakage of the conductive wires 12 and no short circuit between the conductive wires 12 in the conductive layer 1, it is determined that the dielectric layer covering the conductive layer 1 has no defects. For example, in one example, by measuring the first parameter of the conductive wire 12 and measuring the current and resistance between the two conductive wires 12, it can be determined that there is no breakage of the conductive wires 12 and no short circuit between the conductive wires 12 in the conductive layer 1. The third difference threshold is 8 femtofarads. If the measured value of the capacitance between the two conductive wires 12 is 20 femtofarads and the theoretical value of the capacitance between the two conductive wires 12 is 25 femtofarads, and the absolute value of the difference between the two is 5 femtofarads, since the absolute value of the difference between the two, 5 femtofarads, is less than the third difference threshold of 8 femtofarads, it can be determined that the dielectric layer covering the conductive layer 1 has no defects. In another example, if the measured value of the capacitance between the two conductive wires 12 is 10 femtofarads and the theoretical value of the capacitance between the two conductive wires 12 is 25 femtofarads, and the absolute value of the difference between the two is 15 femtofarads, since the absolute value of the difference between the two, 15 femtofarads, is greater than the third difference threshold of 8 femtofarads, it can be determined that there are defects in the dielectric layer covering the conductive layer 1.

[0073] It should be noted that in the above embodiments, the theoretical values of the electrical parameters can be calculated according to the design parameters of the semiconductor device and the excitation signal applied to the test pattern 11. The first difference threshold, the second difference threshold, and the third difference threshold can be set according to the specific conditions of different electrical parameters.

[0074] It should also be noted that when performing a process test on the semiconductor device, one or more preset electrical parameters can be selected as needed to obtain their measured values, and the measurement order of each electrical parameter is not limited. Further, when determining whether there is a process anomaly in the conductive layer 1 or the dielectric layer of the semiconductor device based on the measured values and the theoretical values, it can be judged only based on the measured value and the theoretical value of one of the electrical parameters, or it can be judged according to the specific conditions of the measured values and the theoretical values of multiple electrical parameters as needed. The embodiments of the present invention do not limit this.

[0075] In this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0076] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other, and the key point of each embodiment is to illustrate the differences from other embodiments.

[0077] In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments.

[0078] For the convenience of description, the above device is described by dividing it into various units / modules according to functions. Of course, when implementing the present invention, the functions of the units / modules can be implemented in the same or multiple software and / or hardware.

[0079] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above various methods. Among them, the storage medium can be a magnetic disk, an optical disc, a read-only memory (ROM), or a random access memory (RAM), etc.

[0080] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: At least one conductive layer and at least one dielectric layer stacked alternately; Each of the conductive layers includes at least one detection pattern; Each of the detection patterns includes two conductive lines that are parallel to each other and spaced apart, wherein two end points of each of the conductive lines are respectively led out of the semiconductor device through metal pins; Each of the conductive layers further includes at least one chip pattern; there is no electrical connection between the detection pattern and the chip pattern; Each of the chip patterns has a corresponding first region in the conductive layer, each of the chip patterns is disposed within the corresponding first region, and the first regions are spaced apart from each other on the conductive layer; A preset number of the first regions are arranged in an array on the conductive layer to form a first array; The setting position of each of the detection patterns includes: Disposed outside the rectangular envelope corresponding to the first array and near any target position of the rectangular envelope, corresponding to the target position, and the distance between any point on the detection pattern and the target position is within a preset range; wherein, the rectangular envelope is a rectangle outlined by the outer contour line of the first array; the target position includes any vertex or any side of the rectangular envelope; the detection patterns corresponding to the target positions of the rectangular envelope and the first array together form a second array.

2. The semiconductor device according to claim 1, wherein, One or more of the detection patterns are disposed near each of the target positions of the rectangular envelope.

3. The semiconductor device according to claim 1, wherein Each of the conductive layers includes one or more of the second arrays; the second arrays in the same conductive layer are the same; the second arrays in different conductive layers are different; The second array in any of the conductive layers corresponds to the pattern on the mask used to manufacture the conductive layer.

4. The semiconductor device according to claim 1, wherein The shape of each of the conductive lines includes any one of the following: a line segment, a broken line formed by splicing a plurality of line segments.

5. The semiconductor device according to claim 4, wherein, In the broken line, the included angle between two adjacent line segments is 90 degrees.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The conductive layer includes a metal layer and / or a polysilicon layer.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that, The width of the conductive line is the minimum line width under a preset process, and the spacing between the two conductive lines is the minimum line spacing under the preset process.

8. A process testing method, characterized in that, Applied to the semiconductor device according to any one of claims 1 to 7, the method includes: Obtaining a measured value of a preset electrical parameter through the metal pins corresponding to at least one of the conductive lines in the semiconductor device; Determining whether there is an abnormality in the process corresponding to at least one of the conductive layers or at least one of the dielectric layers in the semiconductor device according to the measured value and the theoretical value of the preset electrical parameter.

9. The method according to claim 8, wherein The obtaining a measured value of a preset electrical parameter through the metal pins corresponding to at least one of the conductive lines in the semiconductor device includes at least one of the following: Obtaining a measured value of a first parameter of the conductive line through two metal pins corresponding to two end points of one of the conductive lines, the first parameter including: the current flowing through the conductive line and / or the resistance of the conductive line; Obtain the measured value of the second parameter between the two conductive wires through the metal pins corresponding to one end of one of the conductive wires and the metal pins corresponding to one end of the other conductive wire, where the second parameter includes at least one of the following: current between the two conductive wires, resistance between the two conductive wires, capacitance between the two conductive wires.

10. The method according to claim 9, characterized in that, Determining whether there is an abnormality in the process corresponding to at least one of the conductive layers or at least one of the dielectric layers in the semiconductor device according to the measured value and the theoretical value of the preset electrical parameter includes at least one of the following: When the absolute value of the difference between the measured value and the theoretical value of the first parameter is greater than or equal to the first difference threshold, determine that there is a break in the conductive wire in the conductive layer; when the absolute value of the difference between the measured value and the theoretical value of the first parameter is less than the first difference threshold, determine that there is no break in the conductive wire in the conductive layer; When the absolute value of the difference between the measured value of the current and / or resistance between the two conductive wires and the theoretical value is greater than or equal to the second difference threshold, determine that there is a short circuit between the conductive wires in the conductive layer; when the absolute value of the difference between the measured value of the current and / or resistance between the two conductive wires and the theoretical value is less than the second difference threshold, determine that there is no short circuit between the conductive wires in the conductive layer; When the absolute value of the difference between the measured value of the capacitance between the two conductive wires and the theoretical value is greater than or equal to the third difference threshold, and there is no break in the conductive wire and no short circuit between the conductive wires in the conductive layer, determine that there is a defect in the dielectric layer covering the conductive layer; when the absolute value of the difference between the measured value of the capacitance between the two conductive wires and the theoretical value is less than the third difference threshold, and there is no break in the conductive wire and no short circuit between the conductive wires in the conductive layer, determine that the dielectric layer covering the conductive layer is free of defects.

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