A control method and control circuit for a bridgeless four-tube Buck-Boost PFC converter

Abstract

The present invention discloses a control method and a control circuit for a bridgeless four-tube Buck-Boost PFC converter, which fully considers the characteristics of wide-range changes in the input voltage and input current of the converter and switching of the power flow direction, and can realize the control of power factor correction, ZVS of all switch tubes, minimization of the effective value of the inductor current and smooth switching of the power flow direction of the bridgeless four-tube Buck-Boost PFC converter. Compared with the four-tube Buck-Boost PFC converter, ZVS of all switch tubes can be realized at any time by superimposing a DC bias voltage at the input end. At the same time, the converter is controlled to commutate at the CLK2a moment through the commutation trigger moment control circuit, which eliminates the process of the inductor current at the zero-crossing moment of the input AC voltage and reduces the distortion of the input current.

Description

Technical Field

[0001] The invention belongs to the technical field of power converters, and in particular relates to a control method and a control circuit for a bridgeless four-tube Buck-Boost PFC converter. Background Art

[0002] Power electronics technology is a technology that uses power semiconductor devices to efficiently convert electrical energy. Power electronic converters can make electrical energy better meet the requirements of different electrical equipment to achieve the goals of high-efficiency and high-quality electricity use. They have been applied to varying degrees in almost all industries. Based on the type of electrical energy, power electronic converters can be divided into DC converters (DC-DC Converter), inverters (DC-AC Converter), rectifiers (AC-DC Converter), and AC-DC Cyclo-Converters. Rectifiers are converters that convert AC power to DC power. In daily life and industrial fields, electrical energy is usually taken from the AC power grid, and many electrical equipment requires DC power supply. Therefore, rectifiers are widely used in LED lighting power supplies, communication power supplies, battery chargers, and DC motor power supplies.

[0003] In order to improve the power factor of the rectifier, power factor correction (PFC) technology is usually used. According to whether active components such as switching tubes are used, PFC technology can be divided into passive PFC and active PFC. Active PFC is further divided into bridge PFC and bridgeless PFC according to whether there is a rectifier bridge. Common PFC converters include Buck PFC converter, Boost PFC converter, and Buck-Boost PFC converter. Among them, Buck PFC converter has an input current dead zone and a low power factor; Boost PFC converter can only be used in high-voltage output occasions due to the characteristics of the boost circuit; Buck-Boost PFC converter has a negative output voltage polarity, and the voltage stress of the power tube is high, which is the sum of the input voltage peak and the output voltage. Applying the four-tube Buck-Boost circuit to the DC-DC stage of the PFC converter can obtain a four-tube Buck-Boost PFC converter. The converter has no dead zone in the input current, can achieve unity power factor, has low voltage stress on the switch tube, and can achieve zero voltage switching (ZVS) of all switch tubes. However, the inductor current ripple of this circuit is too low when the input AC voltage passes through zero, and the ZVS of the switch tube cannot be achieved. The outputs of two four-tube Buck-Boosts are connected in parallel, and the inputs are connected to the two ends of the AC voltage source respectively, and a bridgeless four-tube Buck-Boost PFC converter is obtained. Compared with the four-tube Buck-Boost PFC converter, this converter still has a higher voltage at both ends of the Buck-Boost when the input AC voltage passes through zero, and can achieve ZVS of all switch tubes at any time; at the same time, the four diodes in the current path are replaced by switch tubes, which reduces the conduction loss.

[0004] For the four-tube Buck-Boost converter, PWM plus phase shift control can be used to achieve ZVS of all switch tubes and minimize the inductor current pulsation. The input voltage of the bridgeless four-tube Buck-Boost PFC converter is a sine wave superimposed with a DC bias, and the input current is a sine wave with a wide range of variation. At the same time, there is a switching of power flow direction at the zero-crossing point of the input AC voltage, which is different from the working mode and design method of the DC-DC converter. Therefore, for the bridgeless four-tube Buck-Boost PFC converter, how to find a simple and feasible control scheme based on the characteristics of wide-range variation of input voltage and input current combined with the control ideas of the four-tube Buck-Boost converter is an urgent problem to be solved by researchers in this field. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a control method and a control circuit for a bridgeless four-tube Buck-Boost PFC converter in view of the deficiencies in the above-mentioned prior art, which fully considers the characteristics of wide range changes in the converter input voltage and input current and switching of the power flow direction, and can realize power factor correction and ZVS of all switching tubes, while realizing smooth switching of the power flow direction.

[0006] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0007] A control method for a bridgeless four-tube Buck-Boost PFC converter, the converter comprising eight switch tubes Q A1 ~Q A4 , Q B1 ~Q B4 , filter inductor L c1 , L c2 , output filter capacitor C o , input capacitance C in1 , C in2 ; where Q A1 ~Q A4 and L c1 Composed of A module, Q B1 ~Q B4 and L c2 Composition B module; Q A1 With Q A2 , Q A3 With Q A4 , Q B1 With Q B2 , Q B3 With Q B4 Complementary conduction respectively; L c1 The two ends are respectively connected to Q A1 , Q A2 The midpoint of the bridge arm and Q A3 , Q A4 The bridge arm midpoint is connected; L c2 The two ends are respectively connected to Q B1 , Q B2 The midpoint of the bridge arm and Q B3 , Q B4 The bridge arms are connected at the midpoint; C o The two ends are respectively connected to Q A3 Drain and Q A4 The source is connected to Q B3 Drain and Q B4 Source connection; C in1 The two ends are respectively connected to Q A1 Drain and Q A2 Source connection; C in2 The two ends are respectively connected to Q B1 Drain and QB2 source connection, the method comprising:

[0008] Step 1: In the positive half cycle of the power frequency, sample the output voltage v o and input AC voltage v in , get the output voltage sampling signal v o_s With the input AC voltage sampling signal v in_s , v o_s and the reference signal V o_ref The error is amplified by the output voltage regulator, and the output signal v c With v in_s After multiplication, the input current reference signal i is obtained. g_ref ;

[0009] In the negative half cycle of the power frequency, v o and v in , v o_s and V o_ref The error is amplified by the output voltage regulator and the output voltage is c With -v in_s After multiplication, we get i g_ref ;

[0010] Step 2: In the positive half cycle of the power frequency, sample the input current i of module A ga , get the input current sampling signal i ga_s ,i ga_s and i g_ref By comparing the input current and adjusting the input current in a closed loop through the input current regulator to make it follow the reference, we get Q A1 Duty cycle D y1 ;

[0011] In the negative half cycle of the power frequency, sample the input current i of module B gb , get the input current sampling signal i gb_s ,i gb_s and i g_ref By comparing the input current and adjusting the input current in a closed loop through the input current regulator to make it follow the reference, we get Q B1 Duty cycle D y1 ;

[0012] Step 3: In the positive half cycle of the power frequency, the inductor current i of module A is Lc1 Negative current reference required for soft switching -I ZVS For comparison, when i Lc1 Linear decrease to -I ZVS When Q is turned off A3 , get Q A3 Duty cycle 1-D y2 ;

[0013] In the negative half cycle of the power frequency, the inductor current i Lc2 with -I ZVS For comparison, when i Lc2 Linear decrease to -I ZVS When Q is turned off B3 , get Q B3 Duty cycle 1-D y2 ;

[0014] Step 4: In the positive half cycle of the power frequency, according to the input voltage v of module A ga and the output voltage v o Calculate Q A1 , Q A3 The phase difference between the two at the opening time is the phase shift angle D θ_PDCM1 ;

[0015] In the negative half cycle of the power frequency, according to the input voltage v of module B gb and the output voltage v o Calculate Q B1 , Q B3 The phase difference between the two at the opening time is the phase shift angle D θ_PDCM1 ;

[0016] Step 5: In the positive half cycle of the power frequency, sample the v of module B gb , the obtained sampling signal v gb_s and the B module input voltage reference signal V g_refb By comparing the input voltage and adjusting the input voltage to follow the reference through the closed loop of the input voltage regulator, we can get Q B3 Duty cycle D y ' 1 ;

[0017] In the negative half cycle of the power frequency, sample the v of module A ga , the obtained sampling signal v ga_s and the input voltage reference signal V g_refa By comparing the input voltage and adjusting the input voltage to follow the reference through the closed loop of the input voltage regulator, we can get Q A3 Duty cycle D y ' 1 ;

[0018] Step 6: In the positive half cycle of the power frequency, the inductor current of module B is negative -i Lc2 , with -I ZVS For comparison, when -i Lc2 Linear decrease to -I ZVS When Q is turned off B1 , get Q B1 Duty cycle 1-D y ' 2 ;

[0019] In the negative half cycle of the power frequency, the negative value of the inductor current of module A is -i Lc1 , with -I ZVS For comparison, when -i Lc1 Linear decrease to -I ZVS When Q is turned off A1 , get Q A1 Duty cycle 1-D y ' 2 ;

[0020] Step 7: In the positive half cycle of the power frequency, according to the input voltage v of module B gb and the output voltage v o Calculate Q B3 , Q B1 The phase difference between the two at the opening time is the phase shift angle D θ_PDCM2 ;

[0021] In the negative half cycle of the power frequency, according to the input voltage v of module A ga and the output voltage v o Calculate the switch Q A3 , Q A1 The phase difference between the two at the opening time is the phase shift angle D θ_PDCM2 ;

[0022] Step 8: Sample the input AC voltage polarity and obtain the sampling signal V EN and clock signal CLK2a are sent to the commutation trigger timing control circuit to obtain the commutation trigger signal V TR .

[0023] To optimize the above technical solutions, the specific measures taken also include:

[0024] Step 4 above D θ_PDCM1 for:

[0025]

[0026] The D θ_PDCM1 for:

[0027]

[0028] Among them, D c_max The expression is:

[0029] D c_max =2L c1 I ZVS / (V o T s )

[0030] Among them, T s is the switching cycle duration of the switch tube;

[0031] D c_max The inductor current is from –I ZVS Rise to I ZVS Or from I ZVS Down to –I ZVS The maximum value of the duty cycle corresponding to the time.

[0032] Step 5 above V g_refb The expression is:

[0033]

[0034] The V g_refa The expression is:

[0035]

[0036] Among them, V bias is the DC bias voltage, V in is the effective value of the input AC voltage, ω in is the input AC voltage angular frequency.

[0037] Step 7 above D θ_PDCM2 for:

[0038]

[0039] The D θ_PDCM2 for:

[0040]

[0041] Among them, D c_max The expression is:

[0042] D c_max =2L c1 I ZVS / (V o T s )

[0043] Where D y ' 1 Q is the positive half cycle of the power frequency B3 Or Q of the negative half cycle of the power frequency A3 duty cycle.

[0044] A bridgeless four-tube Buck-Boost PFC converter control circuit comprises an input current reference generating circuit, a first drive signal generating circuit, a second drive signal generating circuit, a phase shift signal generating circuit a, a third drive signal generating circuit, a fourth drive signal generating circuit, a phase shift signal generating circuit b and a commutation triggering time control circuit;

[0045] Input current reference signal generation circuit, used to obtain i g_ref ;

[0046] The first drive signal generating circuit is used to generate Q in the positive half cycle of the power frequency A1 and Q A2 The driving signal generates Q in the negative half cycle of the power frequency. B1 and Q B2 The driving signal of

[0047] The second drive signal generating circuit is used to obtain Q in the positive half cycle of the power frequency. A3 and Q A4 The driving signal is Q in the negative half cycle of the power frequency. B3 and Q B4 The driving signal of

[0048] Phase shift signal generating circuit a is used to obtain clock signal CLK2a, whose phase difference with CLK1 corresponds to phase shift duty ratio D θ_PDCM1 ;

[0049] The third driving signal generating circuit is used to obtain the Q in the positive half cycle of the power frequency. B3 and Q B4 Drive signal and Q during the negative half cycle of the power frequency A3 and Q A4 ;

[0050] The fourth driving signal generating circuit is used to generate Q in the positive half cycle of the power frequency. B1 and Q B2 Drive signal and Q during the negative half cycle of the power frequency A1 and Q A2 ;

[0051] Phase shift signal generating circuit b is used to obtain clock signal CLK2b, whose phase difference with CLK1 corresponds to phase shift duty ratio D θ_PDCM2 ;

[0052] The commutation trigger timing control circuit is used to control the positive and negative signals V corresponding to the input AC voltage. EN The control converter commutates at the time CLK2a.

[0053] The input current reference signal generating circuit includes an output voltage regulator and a multiplier. The output voltage regulator includes an operational amplifier EA1 and its peripheral circuits. EA1 and its peripheral circuits are sensitive to v o_s and V o_ref The error is amplified and the output signal v c , the multiplier pair v c With v in_s The absolute value of i is multiplied by g_ref ,i g_ref With vin The waveform of the absolute value of is the same;

[0054] The phase shift signal generating circuit a comprises a subtractor based on EA3, a multiplier Mult2 and an adder based on EA4, a comparator, and a monostable circuit; in the positive half cycle of the power frequency, v ga_s and v o_s It is sent to the subtractor and then clamped by the diode to generate the y input signal y of Mult2 Mult2 ,y Mult2 With v error1 Multiply and divide by v o_s , and then through the adder and D c_max V M Add them together and get D θ_PDCM1 The modulation signal v θ_PDCM1 ,for:

[0055]

[0056] In the negative half cycle of the power frequency, v gb_s and v o_s It is sent to the subtractor and then clamped by the diode to generate the y input signal y of Mult2 Mult2 ,y Mult2 With v error1 Multiply and divide by v o_s , and then through the adder and D c_max V M Add them together and get D θ_PDCM1 The modulation signal v θ_PDCM1 ,for:

[0057]

[0058] The comparator will v θ_PDCM1 With v saw After comparison, a phase-shifted PWM signal Q is generated θ1 , whose rising edge corresponds to CLK1, and the duty cycle is D θ_PDCM1 ;Q θ1 The falling edge of the monostable circuit generates CLK2a, and the time lag of CLK2a behind CLK1 is D θ_PDCM1 T s ;

[0059] The phase shift signal generating circuit b includes a subtractor based on operational amplifier EA6, a multiplier Mult3, an adder based on operational amplifier EA7, a comparator and a monostable circuit; in the positive half cycle of the power frequency, v o_s and v gb_s It is sent to the subtractor and then clamped by the diode to generate the y input signal y of Mult3. Mult3 ,y Mult3 With verror2 Multiply and divide by v o_s , and then through the adder and D c_max V M Add them together and get D θ_PDCM2 The modulation signal v θ_PDCM2 ,for:

[0060]

[0061] In the positive half cycle of the power frequency, v o_s and v ga_s It is sent to the subtractor and then clamped by the diode to generate the y input signal y of Mult3. Mult3 ,y Mult3 With v error2 Multiply and divide by v o_s , and then through the adder and D c_max V M Add them together and get D θ_PDCM2 The modulation signal v θ_PDCM2 ,for:

[0062]

[0063] The comparator will v θ_PDCM2 With sawtooth wave v saw After comparison, a phase-shifted PWM signal Q is generated θ2 , whose rising edge corresponds to CLK1, and the duty cycle is D θ_PDCM2 , Q θ2 The falling edge of the monostable circuit generates CLK2b, so the time lag of CLK2b behind CLK1 is D θ_PDCM2 T s ;

[0064] The commutation triggering moment control circuit includes a reverse logic gate and a trigger; when the input AC voltage changes from positive to negative, V EN The signal is low potential, and the output is high potential through the reverse logic gate, waiting for the rising edge of the CLK2a signal of the next switching cycle to arrive, V EN The inverse signal of CLK2a and the v generated by the AND gate flip1 Set high, v flip1 Input trigger makes its output signal V TR When the input AC voltage changes from negative to positive, V EN The signal is high potential, and the output is low potential through the reverse logic gate, waiting for the rising edge of the CLK2a signal of the next switching cycle to arrive. flip2 Set high, v flip2 Input trigger makes its output signal V TR Set high and the converter works in the forward direction.

[0065] The first driving signal generating circuit includes an input current regulator, a comparator, and a 1#RS trigger. The input current regulator includes an operational amplifier EA2 and its peripheral circuits. In the positive half cycle of the power frequency, EA2 and its peripheral circuits sample the input current signal i ga_s and the reference signal i g_ref The error is amplified to obtain the output signal v error1 , v error1 and sawtooth wave v saw After comparison by the comparator, it is sent to the 1#RS flip-flop together with CLK1 to generate Q A1 and Q A2 The driving signal; in the negative half cycle of the power frequency, EA2 and its peripheral circuits gb_s and i g_ref The error is amplified and the output signal v error1 , v error1 and sawtooth wave v saw After comparison by the comparator, it is sent to the 1#RS flip-flop together with CLK1 to generate Q B1 and Q B2 The driving signal of

[0066] The second driving signal generating circuit includes a hysteresis comparator Comp2, an OR gate, and a 2#RS trigger; in the positive half cycle of the power frequency, i Lc1 with -I ZVS Sent to Comp2, when i Lc1 Down to -I ZVS When the output signal v comp1 is high, the OR gate generates a high signal Q A3off , Q A3off Send it to the reset terminal of RS flip-flop 2, making Q A3 Shutdown; clock signal CLK1 and v comp1 Perform an OR operation, if i Lc1 Failure to drop to -I at the end of the switching cycle ZVS , when CLK1 is high, Q A2 and Q A3 At the same time, Q A3 The opening time is determined by the clock signal CLK2a; in the negative half cycle of the power frequency, i Lc2 with -I ZVS Sent to Comp2, when i Lc2 Down to -I ZVS When the output signal v comp1 is high, the OR gate generates a high signal Q B3off , Q B3off Send it to the reset terminal of RS flip-flop 2, making Q B3 Shutdown; CLK1 and vcomp1 Perform an OR operation, if i Lc2 Failure to drop to -I at the end of the switching cycle ZVS , when CLK1 is high, Q B2 and Q B3 At the same time, Q B3 The opening time is determined by CLK2a;

[0067] The third driving signal generating circuit includes an input voltage regulator based on operational amplifier EA5, a comparator and a 3#RS trigger; in the positive half cycle of the power frequency, the input voltage regulator is gb_s and V g_refb The error is amplified, and the output signal of EA5 is v error2 and sawtooth wave v saw After comparison, it is sent to the 3#RS flip-flop together with CLK1 to generate Q B3 and Q B4 The driving signal; in the negative half cycle of the power frequency, the input voltage regulator is ga_s and V g_refa The error is amplified, and the output signal of EA5 is v error2 and sawtooth wave v saw After comparison, it is sent to the 3#RS flip-flop together with CLK1 to generate Q A3 and Q A4 The driving signal of

[0068] The fourth driving signal generating circuit includes a hysteresis comparator Comp5, an OR gate, and a reset terminal of a 4#RS trigger; in the positive half cycle of the power frequency, –i Lc2 with -I ZVS Sent to the hysteresis comparator Comp5, when –i Lc2 Down to -I ZVS When the output signal v comp2 is high, the OR gate generates a high signal Q B1off , Q B1off Send it to the reset terminal of RS flip-flop 4, making Q B1 Shutdown; CLK1 and v comp2 Perform an OR operation if –i Lc2 Failure to drop to -I at the end of the switching cycle ZVS , when CLK1 is high, Q B1 and Q B4 At the same time, Q B1 The opening time is determined by CLK2b; in the negative half cycle of the power frequency, –i Lc1 with -I ZVS Sent to the hysteresis comparator Comp5, when –i Lc1 Down to -I ZVS When the comparator output signal vcomp2 is high, the OR gate generates a high signal Q A1off , Q A1off Send it to the reset terminal of RS flip-flop 4, making Q A1 Shutdown; CLK1 and v comp2 Perform an OR operation if –i Lc1 Failure to drop to -I at the end of the switching cycle ZVS , when CLK1 is high, Q A1 and Q A4 At the same time, Q A1 The turn-on time is determined by CLK2b.

[0069] In the first driving signal generating circuit described above, v saw Synchronous with CLK1, v saw The amplitude is recorded as V M , then Q A1 Duty cycle D y1 for:

[0070]

[0071] Q B1 Duty cycle D y1 for:

[0072]

[0073] In the third driving signal generating circuit, v saw Synchronous with CLK1, v saw The amplitude is recorded as V M , then Q B3 Duty cycle D y ' 1 for:

[0074]

[0075] Q A3 Duty cycle D y ' 1 for:

[0076]

[0077] The present invention has the following beneficial effects:

[0078] The present invention can realize the power factor correction of the bridgeless four-tube Buck-Boost PFC converter, the ZVS of all switch tubes, the minimization of the effective value of the inductor current and the control of the smooth switching of the power flow. Compared with the four-tube Buck-Boost PFC converter, the ZVS of all switch tubes can be realized at any time by superimposing a DC bias voltage on the input end. At the same time, the converter is controlled to commutate at the CLK2a moment through the commutation trigger moment control circuit, which eliminates the process of the inductor current at the zero-crossing moment of the input AC voltage and reduces the distortion of the input current. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 This is the circuit structure diagram of the bridgeless four-tube Buck-Boost PFC converter.

[0080] Figure 2 The figure is an overall block diagram of the control circuit of the bridgeless four-tube Buck-Boost PFC converter in an example of the present invention.

[0081] Figure 3 It is a switching timing diagram of the converter commutation process in the present invention.

[0082] Figure 4 It is the working waveform of the converter in the present invention.

[0083] Figure 5a It is a simulation waveform diagram of module A under full load when the effective value of the input voltage is 220V in the present invention.

[0084] Figure 5b It is a simulation waveform diagram of module B under full load when the effective value of the input voltage is 220V in the present invention.

[0085] Figure 6 It is a simulation waveform diagram of the load jumping between 10% and 90% when the effective value of the input voltage is 220V in the present invention.

[0086] Figure 7a This is a simulation waveform diagram of the present invention without using a commutation trigger timing control circuit.

[0087] Figure 7b It is a simulation waveform diagram of the commutation triggering moment control circuit used in the present invention. DETAILED DESCRIPTION

[0088] The embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0089] The present invention proposes a control method for a bridgeless four-tube Buck-Boost PFC converter. Figure 1 The circuit structure diagram of the bridgeless four-tube Buck-Boost PFC converter is mainly composed of eight switch tubes Q A1~Q A4 , Q B1 ~Q B4 , two filter inductors L c1 , L c2 , an output filter capacitor C o , two input capacitors C in1 , C in2 composition.

[0090] Switching tube Q A1 With the switch tube Q A2 Complementary conduction forms a bridge arm unit, the switch tube Q A3 With the switch tube Q A4 Complementary conduction forms a bridge arm unit, the switch tube Q B1 With the switch tube Q B2 Complementary conduction forms a bridge arm unit, the switch tube Q B3 With the switch tube Q B4 Complementary conduction forms a bridge arm unit.

[0091] Inductance L c1 The two ends of the switch tube Q A1 , Q A2 The midpoint of the bridge arm and the switch tube Q A3 , Q A4 The bridge arm midpoint is connected, the inductor L c2 The two ends of the switch tube Q B1 , Q B2 The midpoint of the bridge arm and the switch tube Q B3 , Q B4 The output filter capacitor C o The two ends of the switch tube Q A3 The drain and switch tube Q A4 The source of the switch tube Q B3 The drain and switch tube Q B4 The source connection is used to filter out the switching frequency ripple.

[0092] Input Capacitor C in1 The two ends of the switch tube Q A1 The drain and switch tube Q A2 The source connection, input capacitor C in2 The two ends of the switch tube Q B1 The drain and switch tube Q B2 The source connection is used to provide bias voltage.

[0093] In order to facilitate analysis, the switch tube Q A1 ~Q A4 and filter inductor L c1The four-tube Buck-Boost circuit is named module A. The switch tube Q B1 ~Q B4 and filter inductor L c2 The four-tube Buck-Boost circuit is named B module.

[0094] In the positive half cycle of the power frequency, the bridgeless four-tube Buck-Boost PFC converter has six control variables: Q A1 Duty cycle D y1 , Q A4 Duty cycle D y2 , Q A1 and Q A3 The phase difference between the opening moments corresponds to the phase shift duty ratio D θ , Q B3 Duty cycle D y ' 1 , Q B2 Duty cycle D y ' 2 , and Q B3 and Q B1 The phase difference between the opening moments corresponds to the phase shift duty ratio D θ '; In the negative half cycle of the power frequency, Q A1 , Q A2 Bridge arm and Q B1 , Q B2 The driving signals of the bridge arms are interchanged, Q A3 , Q A4 Bridge arm and Q B3 , Q B4 The driving signals of the bridge arms are interchanged. At this time, there are still six control quantities: Q B1 Duty cycle D y1 , Q B4 Duty cycle D y2 , Q B1 and Q B3 The phase difference between the opening moments corresponds to the phase shift duty ratio D θ , Q A3 Duty cycle D y ' 1 , Q A2 Duty cycle D y ' 2 , and Q A3 and Q A1 The phase difference between the opening moments corresponds to the phase shift duty ratio D θ Among them, the duty cycle is used to control the switch action, and the phase shift duty cycle is used to control the phase difference at the opening moment.

[0095] Realize the switch tube Q A1 and Q A4Soft switching requires that the inductor current i Lc1 If the switch is too negative, the junction capacitance of the switch tube is discharged to zero, so that its reverse-parallel diode is naturally turned on, realizing the switch tube Q B1 and Q B4 Soft switching requires that the inductor current i Lc2 If the voltage is too negative, the junction capacitance of the switch tube is discharged to zero to make its reverse-parallel diode turn on naturally. The magnitude of the negative current required is defined as –I ZVS . Realize the switch tube Q A2 and Q A3 Soft switching requires that the inductor current i Lc1 is positive, discharges the junction capacitance of the switch tube to zero, making its reverse-parallel diode naturally conductive, thus realizing the switch tube Q B2 and Q B3 Soft switching requires that the inductor current i Lc2 The junction capacitance of the switch tube is discharged to zero to make its reverse-parallel diode turn on naturally. The magnitude of the positive current required is defined as I ZVS .

[0096] The present invention proposes a control method for the above four-tube Buck-Boost PFC converter, comprising:

[0097] Step 1: In the positive half cycle of the power frequency, sample the output voltage v o and input AC voltage v in , output voltage sampling signal v o_s and the reference signal V o_ref The error is amplified by the output voltage regulator, and the output signal v c With the input voltage sampling signal v in_s After multiplication, the input current reference signal i is obtained. g_ref ;

[0098] In the negative half cycle of the power frequency, the sampled output voltage v o and input AC voltage v in , output voltage sampling signal v o_s and the reference signal V o_ref The error is amplified by the output voltage regulator, and the output signal v c The negative value of the input voltage sampling signal -v in_s After multiplication, the input current reference signal i is obtained. g_ref .

[0099] Step 2: In the positive half cycle of the power frequency, sample the input current i of module A ga , input current sampling signal i ga_s and the input current reference signal ig_ref In comparison, the input current regulator is closed-loop regulated to follow the reference, and the switch tube Q is obtained. A1 Duty cycle D y1 ;

[0100] In the negative half cycle of the power frequency, sample the input current i of module B gb , input current sampling signal i gb_s and the input current reference signal i g_ref In comparison, the input current regulator is closed-loop regulated to follow the reference, and the switch tube Q is obtained. B1 Duty cycle D y1 .

[0101] Step 3: In the positive half cycle of the power frequency, sample the inductor current i of module A Lc1 , with the negative current reference required for soft switching -I ZVS For comparison, when i Lc1 Linear decrease to -I ZVS When the switch tube Q is turned off A3 , get the switch tube Q A3 Duty cycle 1-D y2 ;

[0102] In the negative half cycle of the power frequency, sample the inductor current i of module B Lc2 , with the negative current reference required for soft switching -I ZVS For comparison, when i Lc2 Linear decrease to -I ZVS When the switch tube Q is turned off B3 , get the switch tube Q B3 Duty cycle 1-D y2 .

[0103] Step 4: In the positive half cycle of the power frequency, sample the input voltage v of module A ga and the output voltage v o , the switch tube Q is approximately calculated A1 , Q A3 The phase difference between the two at the opening time is the phase shift angle D θ_PDCM1 ,Right now:

[0104]

[0105] In the negative half cycle of the power frequency, sample the input voltage v of module B gb and the output voltage v o , the switch tube Q is approximately calculated B1 , Q B3 The phase difference between the two at the opening time is the phase shift angle D θ_PDCM1 ,Right now:

[0106]

[0107] Among them, D c_max The expression is:

[0108] D c_max =2L c1 I ZVS / (V o T s )

[0109] Step 5: In the positive half cycle of the power frequency, sample the input voltage v of module B gb , the sampling signal v gb_s and B module input voltage reference signal V g_refb In comparison, the input voltage is closed-loop regulated by the input voltage regulator to follow the reference, and the switch tube Q is obtained. B3 Duty cycle D y ' 1 , V g_refb The expression is:

[0110]

[0111] In the negative half cycle of the power frequency, sample the input voltage v of module A ga , the sampling signal v ga_s and A module input voltage reference signal V g_refa In comparison, the input voltage is closed-loop regulated by the input voltage regulator to follow the reference, and the switch tube Q is obtained. A3 Duty cycle D y ' 1 , V g_refa The expression is:

[0112]

[0113] Among them, V bias is the DC bias voltage, V in is the effective value of the input AC voltage, ω in is the input AC voltage angular frequency.

[0114] Step 6: In the positive half cycle of the power frequency, sample the negative value of the inductor current of module B -i Lc2 , with the negative current reference required for soft switching -I ZVS For comparison, when -i Lc2 Linear decrease to -I ZVS When the switch tube Q is turned off B1 , get the switch tube Q B1 Duty cycle 1-D y ' 2 ;

[0115] In the negative half cycle of the power frequency, sample the negative value of the inductor current of module A -i Lc1, with the negative current reference required for soft switching -I ZVS For comparison, when -i Lc1 Linear decrease to -I ZVS When the switch tube Q is turned off A1 , get the switch tube Q A1 Duty cycle 1-D y ' 2 .

[0116] Step 7: In the positive half cycle of the power frequency, sample the input voltage v of module B gb and the output voltage v o , the switch tube Q is approximately calculated B3 , Q B1 The phase difference between the two at the opening time is the phase shift angle D θ_PDCM2 ,Right now:

[0117]

[0118] In the negative half cycle of the power frequency, sample the input voltage v of module A ga and the output voltage v o , the switch tube Q is approximately calculated A3 , Q A1 The phase difference between the two at the opening time is the phase shift angle D θ_PDCM2 ,Right now:

[0119]

[0120] Among them, D c_max The expression is:

[0121] D c_max =2L c1 I ZVS / (V o T s )

[0122] Step 8: Sample the input AC voltage polarity and sample the signal V EN and clock signal CLK2a are sent to the commutation trigger timing control circuit to obtain the commutation trigger signal V TR .

[0123] In addition, the present invention also proposes a bridgeless four-tube Buck-Boost PFC converter control circuit. The bridgeless four-tube Buck-Boost PFC converter consists of eight switch tubes Q A1 ~Q A4 , Q B1 ~Q B4 , two filter inductors L c1 , L c2 , an output filter capacitor C o , two input capacitors Cin1 , C in2 Inductor L c1 The two ends of the switch tube Q A1 , Q A2 The midpoint of the bridge arm and the switch tube Q A3 , Q A4 The bridge arm midpoint is connected, the inductor L c2 The two ends of the switch tube Q B1 , Q B2 The midpoint of the bridge arm and the switch tube Q B3 , Q B4 The bridge arm midpoint is connected, and the output filter capacitor C o The two ends of the switch tube Q A3 The drain and switch tube Q A4 The source of the switch tube Q B3 The drain and switch tube Q B4 The source connection, input capacitor C in1 The two ends of the switch tube Q A1 The drain and switch tube Q A2 The source connection, input capacitor C in2 The two ends of the switch tube Q B1 The drain and switch tube Q B2 The source of the switch tube Q A1 With the switch tube Q A2 Complementary conduction, switch tube Q A3 With the switch tube Q A4 Complementary conduction, switch tube Q B1 With the switch tube Q B2 Complementary conduction, switch tube Q B3 With the switch tube Q B4 Complementary conduction;

[0124] The implementation takes the analog control circuit as an example, and its principle diagram is as follows Figure 2 As shown in the figure, the control circuit mainly consists of eight components: input current reference generation circuit, Q A1 and Q A2 Drive signal and Q during the negative half cycle of the power frequency B1 and Q B2 Drive signal generating circuit (first drive signal generating circuit), Q in the positive half cycle of the power frequency A3 and Q A4 Drive signal and Q during the negative half cycle of the power frequency B3 and Q B4 Drive signal generating circuit (second drive signal generating circuit), phase shift signal generating circuit a, Q in the positive half cycle of the power frequency B3 and Q B4Drive signal and Q during the negative half cycle of the power frequency A3 and Q A4 Drive signal generating circuit (third drive signal generating circuit), Q in the positive half cycle of the power frequency B1 and Q B2 Drive signal and Q during the negative half cycle of the power frequency A1 and Q A2 A driving signal generating circuit (a fourth driving signal generating circuit), a phase shift signal generating circuit b, and a commutation triggering timing control circuit.

[0125] (I) Input current reference signal generation circuit

[0126] The input current reference signal generating circuit is used to obtain the input current reference signal i g_ref The operational amplifier EA1 and its peripheral circuits form an output voltage regulator, which samples the output voltage signal v o_s and the reference signal V o_ref The error is amplified. The output signal of EA1 is v c With the input AC voltage sampling signal v in_s After multiplying the absolute value of g_ref . In steady state, v c remains basically unchanged, so i g_ref With v in The waveform of the absolute value of is the same.

[0127] (ii) Q during the positive half cycle of the power frequency A1 and Q A2 Drive signal and Q during the negative half cycle of the power frequency B1 and Q B2 Driving signal generating circuit

[0128] In the positive half cycle of the power frequency, this circuit is used to obtain Q A1 and Q A2 The operational amplifier EA2 and its peripheral circuits form an input current regulator, which samples the input current signal i ga_s and the reference signal i g_ref The error is amplified. The output signal of EA2 is v error1 and sawtooth wave v saw After comparison, it is sent to RS trigger 1 together with CLK1 to generate Q A1 and Q A2 The driving signal. saw Synchronous with CLK1, v saw The amplitude is recorded as V M , then Q A1 Duty cycle D y1 for:

[0129]

[0130] In the negative half cycle of the power frequency, this circuit is used to obtain Q B1 and Q B2 The operational amplifier EA2 and its peripheral circuits form an input current regulator, which samples the input current signal i gb_s and the reference signal i g_ref The error is amplified. The output signal of EA2 is v error1 and sawtooth wave v saw After comparison, it is sent to RS trigger 1 together with CLK1 to generate Q B1 and Q B2 The driving signal. saw Synchronous with CLK1, v saw The amplitude is recorded as V M , then Q B1 Duty cycle D y1 for:

[0131]

[0132] (III) Q during the positive half cycle of the power frequency A3 and Q A4 Drive signal and Q during the negative half cycle of the power frequency B3 and Q B4 Driving signal generating circuit

[0133] In the positive half cycle of the power frequency, this circuit is used to obtain Q A3 and Q A4 The driving signal Q A3 Need to be in i Lc1 Down to -I ZVS and cannot be later than Q A2 Turn off to ensure the optimal switching timing. Lc1 with -I ZVS Sent to the hysteresis comparator Comp2, when i Lc1 Down to -I ZVS When the comparator output signal v comp1 is high, the Q generated by the OR gate A3off Also high level. Q A3off Send it to the reset terminal of RS flip-flop 2, making Q A3 To ensure the optimal switching timing, CLK1 and v comp1 Perform an OR operation. If i Lc1 Failure to drop to -I at the end of the switching cycle ZVS , when CLK1 is high, Q A2 and Q A3 At the same time, Q A3The turn-on time is determined by CLK2a.

[0134] In the negative half cycle of the power frequency, this circuit is used to obtain Q B3 and Q B4 The driving signal Q B3 Need to be in i Lc2 Down to -I ZVS and cannot be later than Q B2 Turn off to ensure the optimal switching timing. Lc2 with -I ZVS Sent to the hysteresis comparator Comp2, when i Lc2 Down to -I ZVS When the comparator output signal v comp1 is high, the Q generated by the OR gate B3off Also high level. Q B3off Send it to the reset terminal of RS flip-flop 2, making Q B3 To ensure the optimal switching timing, CLK1 and v comp1 Perform an OR operation. If i Lc2 Failure to drop to -I at the end of the switching cycle ZVS , when CLK1 is high, Q B2 and Q B3 At the same time, Q B3 The turn-on time is determined by CLK2a.

[0135] (IV) Phase shift signal generating circuit a

[0136] Phase shift signal generating circuit a is used to obtain clock signal CLK2a, whose phase difference with CLK1 corresponds to phase shift duty ratio D θ_PDCM1 Its modulation signal v θ_PDCM1 The calculation circuit is composed of a subtractor (EA3 and its peripheral circuits), a multiplier Mult2 and an adder (EA4 and its peripheral circuits).

[0137] In the positive half cycle of the power frequency, the sampling signal v ga_s and v o_s The signal is sent to the subtractor and then clamped by the diode to generate the y input signal of Mult2. Mult2 With v error1 Multiply and divide by v o_s , and then with D c_max V M Add them together to get D θ_PDCM1 The modulation signal v θ_PDCM1 ,for:

[0138]

[0139] In the negative half cycle of the power frequency, the sampling signal v gb_sand v o_s The signal is sent to the subtractor and then clamped by the diode to generate the y input signal of Mult2. Mult2 With v error1 Multiply and divide by v o_s , and then with D c_max V M Add them together to get D θ_PDCM1 The modulation signal v θ_PDCM1 ,for:

[0140]

[0141] v θ_PDCM1 With sawtooth wave v saw After comparison, a phase-shifted PWM signal Q is generated θ1 , whose rising edge corresponds to CLK1, and the duty cycle is D θ_PDCM1 .Q θ1 The falling edge of the monostable circuit generates CLK2a, so the time lag of CLK2a behind CLK1 is D θ_PDCM1 T s .

[0142] (V) Q during the positive half cycle of the power frequency B3 and Q B4 Drive signal and Q during the negative half cycle of the power frequency A3 and Q A4 Driving signal generating circuit

[0143] In the positive half cycle of the power frequency, this circuit is used to obtain Q B3 and Q B4 The operational amplifier EA5 and its peripheral circuits form an input voltage regulator, which samples the input voltage signal v gb_s and the reference signal V g_refb The error is amplified. The output signal of EA5 is v error2 and sawtooth wave v saw After comparison, it is sent to the 3#RS flip-flop together with CLK1 to generate Q B3 and Q B4 The driving signal. saw Synchronous with CLK1, v saw The amplitude is recorded as V M , then Q B3 Duty cycle D y ' 1 for:

[0144]

[0145] In the negative half cycle of the power frequency, this circuit is used to obtain Q A3 and Q A4The operational amplifier EA5 and its peripheral circuits form an input voltage regulator, which samples the input voltage signal v ga_s and the reference signal V g_refa The error is amplified. The output signal of EA5 is v error2 and sawtooth wave v saw After comparison, it is sent to the 3#RS flip-flop together with CLK1 to generate Q A3 and Q A4 The driving signal. saw Synchronous with CLK1, v saw The amplitude is recorded as V M , then Q A3 Duty cycle D y ' 1 for:

[0146]

[0147] (VI) Q during the positive half cycle of the power frequency B1 and Q B2 Drive signal and Q during the negative half cycle of the power frequency A1 and Q A2 Driving signal generating circuit

[0148] In the positive half cycle of the power frequency, this circuit is used to obtain Q B1 and Q B2 The driving signal Q B1 Need to be in –i Lc2 Down to -I ZVS and cannot be later than Q B4 Turn off to ensure the optimal switching timing. Lc2 with -I ZVS Sent to the hysteresis comparator Comp5, when –i Lc2 Down to -I ZVS When the comparator output signal v comp2 is high, the Q generated by the OR gate B1off Also high level. Q B1off Send it to the reset terminal of RS flip-flop 4, making Q B1 To ensure the optimal switching timing, CLK1 and v comp2 Perform an OR operation. If –i Lc2 Failure to drop to -I at the end of the switching cycle ZVS , when CLK1 is high, Q B1 and Q B4 At the same time, Q B1 The turn-on time is determined by CLK2b.

[0149] In the negative half cycle of the power frequency, this circuit is used to obtain Q A1 and QA2 The driving signal Q A1 Need to be in –i Lc1 Down to -I ZVS and cannot be later than Q A4 Turn off to ensure the optimal switching timing. Lc1 with -I ZVS Sent to the hysteresis comparator Comp5, when –i Lc1 Down to -I ZVS When the comparator output signal v comp2 is high, the Q generated by the OR gate A1off Also high level. Q A1off Send it to the reset terminal of RS flip-flop 4, making Q A1 To ensure the optimal switching timing, CLK1 and v comp2 Perform an OR operation. If –i Lc1 Failure to drop to -I at the end of the switching cycle ZVS , when CLK1 is high, Q A1 and Q A4 At the same time, Q A1 The turn-on time is determined by CLK2b.

[0150] (VII) Phase shift signal generating circuit b

[0151] Phase shift signal generating circuit b is used to obtain clock signal CLK2b, whose phase difference with CLK1 corresponds to phase shift duty ratio D θ_PDCM2 Its modulation signal v θ_PDCM2 The calculation circuit is composed of a subtractor (EA6 and its peripheral circuits), a multiplier Mult3 and an adder (EA7 and its peripheral circuits).

[0152] In the positive half cycle of the power frequency, the sampling signal v o_s and v gb_s The signal is sent to the subtractor and then clamped by the diode to generate the y input signal of Mult3. Mult3 With v error2 Multiply and divide by v o_s , and then with D c_max V M Add them together to get D θ_PDCM2 The modulation signal v θ_PDCM2 ,for:

[0153]

[0154] In the positive half cycle of the power frequency, the sampling signal v o_s and v ga_s The signal is sent to the subtractor and then clamped by the diode to generate the y input signal of Mult3. Mult3 With v error2Multiply and divide by v o_s , and then with D c_max V M Add them together to get D θ_PDCM2 The modulation signal v θ_PDCM2 ,for:

[0155]

[0156] v θ_PDCM2 With sawtooth wave v saw After comparison, a phase-shifted PWM signal Q is generated θ2 , whose rising edge corresponds to CLK1, and the duty cycle is D θ_PDCM2 .Q θ2 The falling edge of the monostable circuit generates CLK2b, so the time lag of CLK2b behind CLK1 is D θ_PDCM2 T s .

[0157] (8) Commutation trigger timing control circuit.

[0158] There is a change in power flow near the zero-crossing point of the input AC voltage. In order to reduce the pulsation of the inductor current at the commutation time, a commutation trigger timing control circuit is used to control the converter to commutate at the CLK2a time. The switching timing diagram of the converter commutation process is shown in Figure 3 shown.

[0159] V EN The high and low levels correspond to the positive and negative input AC voltage, V TR The signal is used as the output of the circuit. When V TR When the potential is high, the actual operation direction of the converter is forward operation; when V TR When the potential is low, the actual running direction of the converter is reverse.

[0160] When the input AC voltage changes from positive to negative, V EN The signal is low potential, and the output is high potential through the reverse logic gate, waiting for the rising edge of the CLK2a signal of the next switching cycle to arrive. flip1 Set high, the trigger is reset, V TR When the signal is low, the converter works in reverse.

[0161] When the input AC voltage changes from negative to positive, V EN The signal is high potential, and the output is low potential through the reverse logic gate, waiting for the rising edge of the CLK2a signal of the next switching cycle to arrive. flip2 Set high, trigger set, V TR When the signal is high, the converter works in the forward direction.

[0162] Through the above control circuit, the following can be achieved: Figure 4The working waveform is shown.

[0163] In order to further illustrate the advantages of the control method, a simulation example of the present invention is given below.

[0164] According to the parameters of the 500W bridgeless four-tube Buck-Boost PFC converter given in Table 1, a simulation circuit was built using the Saber simulation software. Figure 5a , Figure 5b The simulation waveform diagram of the input AC voltage effective value of 220V under full load is given, where: Figure 5a This is the simulation waveform of module A; Figure 5b This is the simulation waveform of module B. It can be seen that all switch tubes can achieve ZVS at any time and the inductor current pulsation is small. Figure 6 The simulation waveform of the load jumping between 10% and 90% when the effective value of the input voltage is 220V is given. It can be seen that the output voltage can be stabilized at 300V and has a faster dynamic response speed. Figure 7a This is the simulation waveform diagram of the circuit without using the commutation trigger moment control. Figure 7b This is a simulation waveform diagram of the commutation trigger timing control circuit. It can be seen that after using the commutation trigger timing control circuit, there is no reverse overshoot in the inductor current and the zero-crossing distortion of the input current is reduced.

[0165] Table 1 Main parameters of the bridgeless four-tube Buck-Boost PFC converter

[0166] parameter symbol Numeric parameter symbol Numeric Input voltage RMS <![CDATA[V in ]]> 220V±20％ A module filter inductor <![CDATA[L c1 ]]> 13.8μH Input voltage frequency <![CDATA[f in ]]> 50Hz B module filter inductor <![CDATA[L c2 ]]> 13.8μH Output voltage <![CDATA[V o ]]> 300V A Module input capacitance <![CDATA[C in1 ]]> 400nF Output Power <![CDATA[P o ]]> 500W B module input capacitance <![CDATA[C in2 ]]> 400nF Switching frequency <![CDATA[f s ]]> 500kHz Input filter inductor <![CDATA[L f ]]> 12μH Output filter capacitor <![CDATA[C o ]]> 360μF Input filter capacitor <![CDATA[C f ]]> 510nF

[0167] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A control method for a bridgeless four-tube Buck-Boost PFC converter, the converter comprising eight switch tubes Q A1 ~Q A4 , Q B1 ~Q B4 , filter inductor L c1 , L c2 , output filter capacitor C o , input capacitance C in1 , C in2 ; where Q A1 ~Q A4 and L c1 Composed of A module, Q B1 ~Q B4 and L c2 Composition B module; Q A1 With Q A2 , Q A3 With Q A4 , Q B1 With Q B2 , Q B3 With Q B4 Complementary conduction respectively; L c1 The two ends are respectively connected to Q A1 , Q A2 The midpoint of the bridge arm and Q A3 , Q A4 The bridge arm midpoint is connected; L c2 The two ends are respectively connected to Q B1 , Q B2 The midpoint of the bridge arm and Q B3 , Q B4 The bridge arms are connected at the midpoint; C o The two ends are respectively connected to Q A3 Drain and Q A4 The source is connected to Q B3 Drain and Q B4 Source connection; C in1 The two ends are respectively connected to Q A1 Drain and Q A2 Source connection; C in2 The two ends are respectively connected to Q B1 Drain and Q B2 The source connection is characterized in that The method comprises: Step 1: In the positive half cycle of the power frequency, sample C o The output voltage V o and Q A1 Drain and Q B1 Input AC voltage between drain and in , get the output voltage sampling signal v o_s With the input AC voltage sampling signal v in_s , v o_s and the reference signal V o_ref The error is amplified by the output voltage regulator, and the output signal v c With v in_s After multiplication, the input current reference signal i is obtained. g_ref ; In the negative half cycle of the power frequency, sample V o and v in , we get v o_s and v in_s , v o_s and V o_ref The error is amplified by the output voltage regulator, and the output voltage regulator output v c With -v in_s After multiplication, we get i g_ref ; Step 2: In the positive half cycle of the power frequency, sample the input current i of module A ga , get the input current sampling signal i ga_s ,i ga_s and i g_ref By comparing the input current and adjusting the input current in a closed loop through the input current regulator to make it follow the reference, we get Q A1 Duty cycle D y1 ; In the negative half cycle of the power frequency, sample the input current i of module B gb , get the input current sampling signal i gb_s ,i gb_s and i g_ref By comparing the input current and adjusting the input current in a closed loop through the input current regulator to make it follow the reference, we get Q B1 Duty cycle D y1 ; Step 3: In the positive half cycle of the power frequency, the inductor current i of module A is Lc1 Negative current reference required for soft switching -I ZVS For comparison, when i Lc1 Linear decrease to -I ZVS When Q is turned off A3 , get Q A3 Duty cycle 1-D y2 ; In the negative half cycle of the power frequency, the inductor current i Lc2 with -I ZVS For comparison, when i Lc2 Linear decrease to -I ZVS When Q is turned off B3 , get Q B3 Duty cycle 1-D y2 ; Step 4: In the positive half cycle of the power frequency, according to the input voltage v of module A ga The sampled signal v ga_s and v o_s Calculate Q A1 , Q A3 The phase difference between the two at the opening time is the phase shift angle D θ_PDCM1(正半) ; In the negative half cycle of the power frequency, according to the input voltage v of module B gb The sampled signal v gb_s and v o_s Calculate Q B1 , Q B3 The phase difference between the two at the opening time is the phase shift angle D θ_PDCM1(负半) ; Step 4 D θ_PDCM1(正半) for: The D θ_PDCM1(负半) for: Among them, D c_max The expression is: D c_max =2L c1 I ZVS / (V o T s ) Among them, T s is the switching cycle duration of the switch tube; D c_max The inductor current is from –I ZVS Rise to I ZVS Or from I ZVS Down to –I ZVS The maximum value of the duty cycle corresponding to the time; Step 5: In the positive half cycle of the power frequency, sample the v of module B gb , the obtained sampling signal v gb_s and the B module input voltage reference signal V g_refb By comparing the input voltage and adjusting the input voltage to follow the reference through the closed loop of the input voltage regulator, we can get Q B3 Duty cycle D′ y1 ; In the negative half cycle of the power frequency, sample the v of module A ga , the obtained sampling signal v ga_s and the input voltage reference signal V g_refa By comparing the input voltage and adjusting the input voltage to follow the reference through the closed loop of the input voltage regulator, we can get Q A3 Duty cycle D′ y1 ; Step 6: In the positive half cycle of the power frequency, the inductor current of module B is negative -i Lc2 , with -I ZVS For comparison, when -i Lc2 Linear decrease to -I ZVS When Q is turned off B1 , get Q B1 Duty cycle 1-D′ y2 ; In the negative half cycle of the power frequency, the negative value of the inductor current of module A is -i Lc1 , with -I ZVS For comparison, when -i Lc1 Linear decrease to -I ZVS When Q is turned off A1 , get Q A1 Duty cycle 1-D′ y2 ; Step 7: In the positive half cycle of the power frequency, according to v gb_s and v o_s Calculate Q B3 , Q B1 The phase difference between the two at the opening time is the phase shift angle D θ_PDCM2(正半) ; In the negative half cycle of the power frequency, according to v ga_s and v o_s Calculate the switch Q A3 , Q A1 The phase difference between the two at the opening time is the phase shift angle D θ_PDCM2(负半) ; Step 7D θ_PDCM2(正半) for: The D θ_PDCM2(负半) for: Step 8: Sample the input AC voltage polarity and obtain the sampling signal V EN The clock signal CLK2a is sent to the commutation trigger timing control circuit to obtain the commutation trigger signal V that triggers the converter to work at the power frequency. TR .

2. A control method for a bridgeless four-tube Buck-Boost PFC converter according to claim 1, characterized in that: Step 5 V g_refb The expression is: The V g_refa The expression is: Among them, V bias is the DC bias voltage, V in is the effective value of the input AC voltage, ω in is the input AC voltage angular frequency.

3. A bridgeless four-transistor Buck-Boost PFC converter control circuit implementing the method described in any one of claims 1 to 2, characterized in that: It includes an input current reference generating circuit, a first driving signal generating circuit, a second driving signal generating circuit, a phase shift signal generating circuit a, a third driving signal generating circuit, a fourth driving signal generating circuit, a phase shift signal generating circuit b and a commutation triggering time control circuit; Input current reference signal generation circuit, used to obtain i g_ref ; The first drive signal generating circuit is used to generate Q in the positive half cycle of the power frequency A1 and Q A2 The driving signal generates Q in the negative half cycle of the power frequency. B1 and Q B2 The driving signal of The second driving signal generating circuit is used to obtain Q in the positive half cycle of the power frequency A3 and Q A4 The driving signal is Q in the negative half cycle of the power frequency. B3 and Q B4 The driving signal of Phase shift signal generating circuit a is used to obtain clock signal CLK2a, whose phase difference with CLK1 corresponds to phase shift duty ratio D θ_PDCM1 , where D θ_PDCM1 In the positive half cycle of the power frequency, D θ_PDCM1(正半) , in the negative half cycle of the power frequency is D θ_PDCM1(负半) ; The third driving signal generating circuit is used to obtain the Q in the positive half cycle of the power frequency. B3 and Q B4 Drive signal and Q during the negative half cycle of the power frequency A3 and Q A4 Driving signal; The fourth driving signal generating circuit is used to generate Q in the positive half cycle of the power frequency. B1 and Q B2 Drive signal and Q during the negative half cycle of the power frequency A1 and Q A2 Driving signal; Phase shift signal generating circuit b is used to obtain clock signal CLK2b, whose phase difference with CLK1 corresponds to phase shift duty ratio D θ_PDCM2 , where D θ_PDCM2 In the positive half cycle of the power frequency, D θ_PDCM2(正半) , in the negative half cycle of the power frequency is D θ_PDCM2(负半) ; The commutation trigger timing control circuit is used to control the positive and negative signals V corresponding to the input AC voltage. EN Control the commutation trigger signal V of the converter TR The switching of high and low levels is synchronized with the rising edge of CLK2a.

4. The bridgeless four-tube Buck-Boost PFC converter control circuit according to claim 3, characterized in that: The first drive signal generating circuit includes an input current regulator, a comparator, and a 1#RS trigger. The input current regulator includes an operational amplifier EA2 and its peripheral circuits. In the positive half cycle of the power frequency, EA2 and its peripheral circuits sample the input current signal i ga_s and the reference signal i g_ref The error is amplified to obtain the output signal v error1 , v error1 and sawtooth wave v saw After comparison by the comparator, it is sent to the 1#RS flip-flop together with CLK1 to generate Q A1 and Q A2 The driving signal; in the negative half cycle of the power frequency, EA2 and its peripheral circuits gb_s and i g_ref The error is amplified and the output signal v error1 , v error1 and sawtooth wave v saw After comparison by the comparator, it is sent to the 1#RS flip-flop together with CLK1 to generate Q B1 and Q B2 The driving signal of The second driving signal generating circuit includes a hysteresis comparator Comp2, an OR gate, and a 2#RS trigger; in the positive half cycle of the power frequency, i Lc1 with -I ZVS Sent to Comp2, when i Lc1 Down to -I ZVS When Comp2 outputs a signal v comp1 is high level, v comp1 and CLK1 input OR gate, OR gate generates high level signal Q A3off , Q A3off Send it to the reset terminal of RS flip-flop 2, making Q A3 Shutdown; clock signal CLK1 and v comp1 Perform an OR operation, if i Lc1 Failure to drop to -I at the end of the switching cycle ZVS , when CLK1 is high, Q A2 and Q A3 At the same time, Q A3 The opening time is determined by the clock signal CLK2a; in the negative half cycle of the power frequency, i Lc2 with -I ZVS Sent to Comp2, when i Lc2 Down to -I ZVS When the output signal v comp1 is high, the OR gate generates a high signal Q B3off , Q B3off Send it to the reset terminal of RS flip-flop 2, making Q B3 Shutdown; CLK1 and v comp1 Perform an OR operation, if i Lc2 Failure to drop to -I at the end of the switching cycle ZVS , when CLK1 is high, Q B2 and Q B3 At the same time, Q B3 The opening time is determined by CLK2a; The third driving signal generating circuit includes an input voltage regulator based on operational amplifier EA5, a comparator and a 3#RS trigger; in the positive half cycle of the power frequency, the input voltage regulator is gb_s and V g_refb The error is amplified, and the output signal of EA5 is v error2 and sawtooth wave v saw After comparison, it is sent to the 3#RS flip-flop together with CLK1 to generate Q B3 and Q B4 The driving signal; in the negative half cycle of the power frequency, the input voltage regulator is ga_s and V g_refa The error is amplified, and the output signal of EA5 is v error2 and sawtooth wave v saw After comparison, it is sent to the 3#RS flip-flop together with CLK1 to generate Q A3 and Q A4 The driving signal of The fourth driving signal generating circuit includes a hysteresis comparator Comp5, an OR gate, and a 4#RS trigger; in the positive half cycle of the power frequency, –i Lc2 with -I ZVS Sent to the hysteresis comparator Comp5, when –i Lc2 Down to -I ZVS When Comp5 output signal v comp2 is high level, v comp2 and CLK1 input OR gate, OR gate generates high level signal Q B1off , Q B1off Send it to the reset terminal of RS flip-flop 4, making Q B1 Shutdown; CLK1 and v comp2 Perform an OR operation if –i Lc2 Failure to drop to -I at the end of the switching cycle ZVS , when CLK1 is high, Q B1 and Q B4 At the same time, Q B1 The opening time is determined by CLK2b; in the negative half cycle of the power frequency, –i Lc1 with -I ZVS Sent to the hysteresis comparator Comp5, when –i Lc1 Down to -I ZVS When the comparator output signal v comp2 is high, the OR gate generates a high signal Q A1off , Q A1off Send it to the reset terminal of RS flip-flop 4, making Q A1 Shutdown; CLK1 and v comp2 Perform an OR operation if –i Lc1 Failure to drop to -I at the end of the switching cycle ZVS , when CLK1 is high, Q A1 and Q A4 At the same time, Q A1 The turn-on time is determined by CLK2b.

5. The bridgeless four-tube Buck-Boost PFC converter control circuit according to claim 4, characterized in that: The input current reference signal generating circuit includes an output voltage regulator and a multiplier. The output voltage regulator includes an operational amplifier EA1 and its peripheral circuits. EA1 and its peripheral circuits are sensitive to v o_s and V o_ref The error is amplified and the output signal v c , the multiplier pair v c With v in_s The absolute value of i is multiplied by g_ref ,i g_ref With v in The waveform of the absolute value of is the same; The phase shift signal generating circuit a includes a subtractor based on an operational amplifier EA3, a multiplier Mult2, and an adder based on an operational amplifier EA4, a comparator, and a monostable circuit; In the positive half cycle of the power frequency, v ga_s and v o_s It is sent to the subtractor and then clamped by the diode to generate the y input signal y of Mult2 Mult2 ,y Mult2 With v error1 Multiply and divide by v o_s , and then through the adder and D c_max V M Add them together and get D θ_PDCM1 The modulation signal v θ_PDCM1(正半) ; In the negative half cycle of the power frequency, v gb_s and v o_s It is sent to the subtractor and then clamped by the diode to generate the y input signal y of Mult2 Mult2 ,y Mult2 With v error1 Multiply and divide by v o_s , and then through the adder and D c_max V M Add them together to get D θ_PDCM1 The modulation signal v θ_PDCM1(负半) ; The comparator will v θ_PDCM1 With v saw After comparison, a phase-shifted PWM signal Q is generated θ1 , Q θ1 The rising edge is synchronized with CLK1, and the duty cycle is D θ_PDCM1 ;Q θ1 It is sent to the monostable circuit, which extracts Q θ1 The falling edge of CLK1 generates a synchronous clock signal CLK2a, and the time lag of CLK2a from CLK1 is D θ_ PDCM1 T s ; where v θ_PDCM1 In the positive half cycle of the power frequency, v θ_PDCM1(正半) , in the negative half cycle of the power frequency is v θ_PDCM1(负半) ; The phase shift signal generating circuit b includes a subtractor based on operational amplifier EA6, a multiplier Mult3, an adder based on operational amplifier EA7, a comparator and a monostable circuit; in the positive half cycle of the power frequency, v o_s and v gb_s It is sent to the subtractor and then clamped by the diode to generate the y input signal y of Mult3. Mult3 ,y Mult3 With v error2 Multiply and divide by v gb_s , and then through the adder and D c_max V M Add them together to get D θ_PDCM2 The modulation signal v θ_PDCM2(正半) ; In the negative half cycle of the power frequency, v o_s and v ga_s It is sent to the subtractor and then clamped by the diode to generate the y input signal y of Mult3. Mult3 ,y Mult3 With v error2 Multiply and divide by v ga_s , and then through the adder and D c_max V M Add them together to get D θ_PDCM2 The modulation signal v θ_PDCM2(负半) ; The comparator will v θ_PDCM2 With sawtooth wave v saw After comparison, a phase-shifted PWM signal Q is generated θ2 , Q θ2 The rising edge is synchronized with CLK1, and the duty cycle is D θ_PDCM2 , Q θ2 It is sent to the monostable circuit, which extracts Q θ2 The falling edge of CLK1 generates a synchronous clock signal CLK2b, so CLK2b lags behind CLK1 by a time D θ_PDCM2 T s ; where v θ_PDCM2 In the positive half cycle of the power frequency, v θ_PDCM2(正半) , in the negative half cycle of the power frequency is v θ_PDCM2(负半) ; The commutation triggering moment control circuit includes a reverse logic gate and a trigger; when the input AC voltage changes from positive to negative, V EN The signal is low potential, and the output is high potential through the reverse logic gate, waiting for the rising edge of the CLK2a signal of the next switching cycle to arrive, V EN The inverse signal of CLK2a and the v generated by the AND gate flip1 Set high, v flip1 Input trigger makes its output signal V TR When the input AC voltage changes from negative to positive, V EN The signal is high potential, and the output is low potential through the reverse logic gate, waiting for the rising edge of the CLK2a signal of the next switching cycle to arrive, V EN The signal and CLK2a pass through another AND gate to generate v flip2 Set high, v flip2 Input trigger makes its output signal V TR Set high and the converter works in the forward direction.

6. A bridgeless four-tube Buck-Boost PFC converter control circuit according to claim 5, characterized in that: The v θ_PDCM1(正半) for: v θ_PDCM1(负半) for: v θ_PDCM2(正半) for: v θ_PDCM2(负半) for:

7. The bridgeless four-tube Buck-Boost PFC converter control circuit according to claim 4, characterized in that: In the first driving signal generating circuit, v saw Synchronous with CLK1, v saw The amplitude is recorded as V M , then Q A1 Duty cycle D y1 for: Q B1 Duty cycle D y1 for: In the third driving signal generating circuit, v saw Synchronous with CLK1, v saw The amplitude is recorded as V M , then Q B3 Duty cycle D y ′1 is: Q A3 Duty cycle D y ′1 is:

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