Display panel

Abstract

A display panel includes a substrate substrate and a plurality of sub-pixels disposed on the substrate substrate, each of at least part of the sub-pixels includes a pixel driving circuit and a light emitting device, the pixel driving circuit includes a first metal pattern, an active pattern and a second metal pattern disposed on the substrate substrate, the light emitting device includes an electrode pattern electrically connected with the second metal pattern, at least part of the sub-pixels includes a first color sub-pixel and a second color sub-pixel, the first color sub-pixel and the second color sub-pixel are configured to emit light of different colors, in the first color sub-pixel, the ratio of the overlapping area of the active pattern and the first metal pattern to the area of the electrode pattern is X1, in the second color sub-pixel, the ratio of the overlapping area of the active pattern and the first metal pattern to the area of the electrode pattern is X2, 1 / 2≤X1 / X2<1. The display panel has better display effect.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display panel. Background Technology

[0002] OLED (Organic Light Emitting Diode) displays possess a range of advantages, including self-illumination, high contrast, high definition, wide viewing angle, low power consumption, fast response time, and low manufacturing cost. As a result, they have become a key development direction for next-generation display devices and have attracted increasing attention. Currently, optimizing the structure of display devices is a subject of ongoing research in the field. Summary of the Invention

[0003] This disclosure provides at least one embodiment of a display panel, the display panel including a substrate and a plurality of sub-pixels disposed on the substrate, wherein each of at least some of the sub-pixels includes a pixel driving circuit and a light-emitting device, the pixel driving circuit including a first metal pattern, an active pattern and a second metal pattern disposed on the substrate, the light-emitting device including an electrode pattern electrically connected to the second metal pattern, the at least some of the sub-pixels including a first color sub-pixel and a second color sub-pixel, the first color sub-pixel and the second color sub-pixel being configured to emit light of different colors, in the first color sub-pixel, the ratio of the overlap area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern is X1, and in the second color sub-pixel, the ratio of the overlap area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern is X2.

[0004] 1 / 2 ≤ X1 / X2 < 1.

[0005] For example, in a display panel provided in at least one embodiment of this disclosure, the active pattern is disposed on the side of the first metal pattern close to the substrate or on the side away from the substrate, the second metal pattern is disposed on the side of the active pattern away from the substrate, and the electrode pattern is disposed on the side of the second metal pattern away from the substrate.

[0006] For example, in a display panel provided in at least one embodiment of this disclosure, the luminance of the first color sub-pixel is L1, and the luminance of the second color sub-pixel is L2.

[0007]

[0008] Where α is the expected brightness parameter, and the value range of α is -2.00 < α < 9.50; β is the capacitance compensation parameter, and the value range of β is 0.95 < β < 1.05.

[0009] For example, in a display panel provided by at least one embodiment of this disclosure, the active pattern and the second metal pattern are electrically connected through a first via, and the second metal pattern and the electrode pattern are electrically connected through a second via; in the first color sub-pixel, the distance between the center point of the first via and the center point of the second via is y1, and in the second color sub-pixel, the distance between the center point of the first via and the center point of the second via is y2.

[0010]

[0011] Where a and b are constants.

[0012] For example, in the display panel provided in at least one embodiment of this disclosure,

[0013]

[0014] γ is a light intensity control compensation parameter, and the value range of γ is: γ < -0.4 or γ > 0.3.

[0015] For example, in the display panel provided in at least one embodiment of this disclosure,

[0016]

[0017] For example, at least one embodiment of the display panel provided in this disclosure further includes: a planarization layer disposed on the side of the second metal pattern away from the substrate, wherein the second via penetrates the planarization layer, the second via has a first opening on the surface of the planarization layer away from the substrate, and a second opening on the surface of the planarization layer near the substrate, the orthographic projection of the second opening on the substrate lies within the orthographic projection of the first opening on the substrate, in the first color sub-pixel, the overlap area of ​​the orthographic projection of the first opening on the substrate and the orthographic projection of the second metal pattern on the substrate is Y1, and in the second color sub-pixel, the overlap area of ​​the orthographic projection of the first opening on the substrate and the orthographic projection of the second metal pattern on the substrate is Y2.

[0018] Y1>Y2.

[0019] For example, in a display panel provided by at least one embodiment of this disclosure, the slope angle α1 of the planarization layer at the second via ranges as follows:

[0020] 75 degrees ≥ α1 ≥ 40 degrees.

[0021] For example, in at least one embodiment of the display panel provided in this disclosure, the thickness h of the planarization layer in the direction perpendicular to the substrate ranges as follows:

[0022] h≤5.5 micrometers.

[0023] For example, at least one embodiment of the display panel provided in this disclosure further includes: a pixel defining layer disposed on the side of the electrode pattern away from the substrate, wherein the pixel defining layer includes a plurality of first barrier dams extending along a first direction and a plurality of second barrier dams extending along a second direction, the plurality of first barrier dams and the plurality of second barrier dams being configured to define sub-pixel openings of the plurality of sub-pixels, the first direction being different from the second direction; the light-emitting device further includes a light-emitting material layer disposed in the sub-pixel openings, wherein in a direction perpendicular to the substrate, the thickness of the first barrier dams is greater than the thickness of the second barrier dams, at the location of the second via, along the second direction, at the boundary of the second metal pattern, the thickness of the planarization layer is h1, at the boundary of the light-emitting material layer, the thickness of the planarization layer is h2, and at the boundary of the electrode pattern, the thickness of the planarization layer is h3.

[0024] h1 / h2 < h2 / h3.

[0025] For example, in a display panel provided in at least one embodiment of this disclosure, the diameter of the first opening is L1, and the diameter of the second opening is L2.

[0026] L1>L2+2*f*(h / tanα1),

[0027] Where f is a constant, and 1.5≤f≤3.4.

[0028] For example, in a display panel provided in at least one embodiment of this disclosure, L1 / L2 ≥ 2.5.

[0029] For example, in the display panel provided in at least one embodiment of this disclosure,

[0030] h = k * h²,

[0031] k is a constant, and 0.5 <k<1。

[0032] For example, in a display panel provided in at least one embodiment of this disclosure, in a direction perpendicular to the substrate, the second barrier dam includes a first portion overlapping with the second via and a second portion not overlapping with the second via, wherein the thickness of the first portion is greater than the thickness of the second portion.

[0033] For example, in a display panel provided in at least one embodiment of this disclosure, the slope angle of the first portion at the boundary of the second via is smaller than the slope angle α1 of the planarization layer at the second via.

[0034] For example, in a display panel provided by at least one embodiment of this disclosure, in the first direction, in at least a portion of the sub-pixels, the center of the second via is different from the shortest distance of the edge of the second barrier covering the second via.

[0035] For example, in a display panel provided in at least one embodiment of this disclosure, in the second direction, in at least some sub-pixels, the center of the second via is at a different distance from two adjacent first barrier dams.

[0036] For example, in a display panel provided in at least one embodiment of this disclosure, the first color sub-pixel is a blue sub-pixel, and the second color sub-pixel is a green sub-pixel or a red sub-pixel.

[0037] For example, in a display panel provided in at least one embodiment of this disclosure, the at least some sub-pixels further include a third color sub-pixel, and the display panel further includes a plurality of reset signal lines configured to transmit reset signals to the at least some sub-pixels, wherein the extension length of the reset signal line transmitting the reset signal to the first color sub-pixel in the second direction is D1, the extension length of the reset signal line transmitting the reset signal to the second color sub-pixel in the second direction is D2, and the extension length of the reset signal line transmitting the reset signal to the third color sub-pixel in the second direction is D3.

[0038] D3 > D2, D3 > D1.

[0039] For example, in a display panel provided in at least one embodiment of this disclosure, the first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a red sub-pixel.

[0040] For example, in a display panel provided in at least one embodiment of this disclosure, at least some of the plurality of reset signal lines include portions extending along a first direction and portions extending along a second direction, wherein the first direction is different from the second direction.

[0041] For example, in a display panel provided by at least one embodiment of this disclosure, in the second direction, signal lines extending along the first direction are respectively provided on both sides of the electrode pattern, and in the at least some sub-pixels, the signals transmitted by the signal lines extending along the first direction on both sides of the electrode pattern are different. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0043] Figure 1AA circuit diagram of a 3T1C pixel driving circuit for a display panel;

[0044] Figure 1B for Figure 1A Timing diagram of the circuit diagram in the image;

[0045] Figure 2 A partial cross-sectional schematic diagram of a sub-pixel in a display panel provided in at least one embodiment of the present disclosure;

[0046] Figure 3 A partial cross-sectional schematic diagram of a sub-pixel in another display panel provided for at least one embodiment of the present disclosure;

[0047] Figures 4A-4G This is a plan view of each functional layer in a display panel provided in at least one embodiment of the present disclosure;

[0048] Figures 5A-5D A plan view of multiple functional layers stacked in a display panel provided in at least one embodiment of the present disclosure;

[0049] Figure 6 A partial cross-sectional schematic diagram of the planarization layer of a display panel provided in at least one embodiment of the present disclosure near the second via;

[0050] Figure 7 This is a partial planar schematic diagram of the pixel delimiting layer of a display panel provided in at least one embodiment of the present disclosure;

[0051] Figure 8 for Figure 7 A schematic diagram of the cross-section of the pixel delimiting layer along line AA;

[0052] Figure 9 for Figure 7 A schematic diagram of the cross-section of the pixel delimiting layer along the BB line; and

[0053] Figure 10 This is a partial cross-sectional schematic diagram of the planarization layer and pixel defining layer in a display panel provided in at least one embodiment of the present disclosure near the second via. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0055] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0056] In some implementations, the display area of ​​the OLED display panel can employ a 3T1C pixel driving circuit to drive the light-emitting devices to emit light. For example, Figure 1A A circuit diagram of a 3T1C pixel driving circuit is shown. Figure 1B for Figure 1A Timing diagram of the pixel driving circuit.

[0057] For example, such as Figure 1A and Figure 1B As shown, the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor. The storage capacitor includes a first capacitor and a second capacitor connected in parallel. The first capacitor is composed of a first capacitor electrode ACT and a second capacitor electrode SHL, and the second capacitor is composed of a first capacitor electrode ACT and a third capacitor electrode SD. The pixel driving circuit is connected to signal lines such as a data line DT, a sensing line SN, a high-level power line VDD, and a low-level power line VSS, as well as components such as an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) connected to the sensing line SN via switches S1 and S2, respectively. It also has the following features: Figure 1A The connection relationships are shown.

[0058] During the operation of the aforementioned 3T1C pixel driving circuit, combined with Figure 1A and Figure 1B During the light-emitting stage D, at time t1, the first control signal G1 and the second control signal G2 are turn-on signals and are input to the gates of the first transistor T1 and the second transistor T2. The first transistor T1 and the second transistor T2 are turned on. The data signal dt is transmitted to the gate of the third transistor T3 through the first transistor T1. The third transistor T3 is turned on. The sensing IC writes the reset signal Vint to the first electrode (e.g., the anode) of the light-emitting device through the sensing line SN and the second transistor T2.

[0059] During time period t2, the first control signal G1 and the second control signal G2 are off signals, the voltage across the storage capacitor remains unchanged, the third transistor T3 operates in saturation and the current remains unchanged, and drives the light-emitting device to emit light.

[0060] At this point, if the pixel row where the light-emitting device is located needs compensation, the sensing phase S, i.e., the t3-t6 period, is entered.

[0061] During time period t3, the first control signal G1 and the second control signal G2 are turn-on signals and are input to the gates of the first transistor T1 and the second transistor T2. The first transistor T1 and the second transistor T2 are turned on. The data signal dt is transmitted to the gate of the third transistor T3 through the first transistor T1. The third transistor T3 is turned on. The sensing IC writes the reset signal Vint to the first electrode (e.g., the anode) of the light-emitting device through the sensing line SN and the second transistor T2.

[0062] During time period t4, the first transistor T1 is turned off, while the second transistor T2 and the third transistor T3 are turned on. The parasitic capacitance of the sensing line SN is discharged through point S until the third transistor T3's Vgs = Vth. At this time, the third transistor T3 is turned off. The sensing IC can obtain the potential of S and calculate the Vth of the third transistor. Based on the discharge curve of point S during the sensing phase, the mobility and other characteristic parameters of the third transistor can also be calculated.

[0063] During time period t5, the first transistor T1 is turned on, and the data line DT writes a data voltage to the gate of the third transistor T3. Since the pixel row where the light-emitting device is located does not emit light during the sensing phase, a dark line will appear on the display. Therefore, after the end of time period t4, a data voltage is immediately written to make the pixel row emit light, reducing the impact of the dark line on the display effect.

[0064] During time period t6, the first transistor T1 and the second transistor T2 are turned off, and the light-emitting device emits light.

[0065] The time periods t5 and t6 mentioned above are added for power-on compensation; these two stages are not needed for power-off compensation.

[0066] The pixel driving circuit described above can be implemented using various circuit layouts, and different layouts may affect the display effect of the display device.

[0067] At least one embodiment of this disclosure provides a display panel, the display panel including a substrate and a plurality of sub-pixels disposed on the substrate, wherein each of at least some of the sub-pixels includes a pixel driving circuit and a light-emitting device, the pixel driving circuit including a first metal pattern, an active pattern and a second metal pattern disposed on the substrate, the light-emitting device including an electrode pattern electrically connected to the second metal pattern, and at least some of the sub-pixels including a first color sub-pixel and a second color sub-pixel, the first color sub-pixel and the second color sub-pixel being configured to emit light of different colors, in the first color sub-pixel, the ratio of the overlapping area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern is X1, in the second color sub-pixel, the ratio of the overlapping area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern is X2, 1 / 2≤X1 / X2<1.

[0068] The display panel provided in this embodiment of the present disclosure can balance the speed and magnitude of signal transmission from the pixel driving circuit to the light-emitting device in each sub-pixel by designing the ratio of the overlapping area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern in different color sub-pixels, thereby balancing the light-emitting duration of each sub-pixel and improving the display effect of the display panel.

[0069] The display panel provided in the embodiments of this disclosure is described below through several specific examples.

[0070] At least one embodiment of this disclosure provides a display panel, Figure 2 This diagram shows a partial cross-sectional view of a sub-pixel in the display panel, as shown below. Figure 2 As shown, the display panel includes a substrate 110 and a plurality of sub-pixels disposed on the substrate 110. At least some of the sub-pixels include a pixel driving circuit and a light-emitting device EM. The pixel driving circuit includes a first metal pattern M1, an active pattern AC and a second metal pattern M2 disposed on the substrate 110. The light-emitting device EM includes an electrode pattern 1041 electrically connected to the second metal pattern M2.

[0071] At least some sub-pixels include a first color sub-pixel and a second color sub-pixel, which are configured to emit different colors of light. For example, in the first color sub-pixel, the ratio of the overlapping area of ​​the active pattern AC and the first metal pattern M1 to the area of ​​the electrode pattern 1041 is X1; in the second color sub-pixel, the ratio of the overlapping area of ​​the active pattern AC and the first metal pattern M1 to the area of ​​the electrode pattern 1041 is X2.

[0072] 1 / 2 ≤ X1 / X2 < 1.

[0073] For example, the larger the overlap area between the active pattern AC and the first metal pattern M1, the larger the amount of electricity that the storage capacitor formed by the active pattern AC and the first metal pattern M1 can store. Therefore, the signal holding function is better, and the light emission duration of the light-emitting device EM is longer. Due to differences in the size of the electrode pattern 1041 of different sub-pixels, differences in signal transmission paths, and differences in the light emission performance of the light-emitting material layer of the light-emitting device EM, the light emission performance of different sub-pixels varies. By designing the ratio of the overlap area of ​​the active pattern AC and the first metal pattern M1 to the area of ​​the electrode pattern 1041, the speed and magnitude of signal transmission from the pixel driving circuit to the light-emitting device EM in each sub-pixel can be balanced, thereby balancing the light emission duration of each sub-pixel and improving the display effect of the display panel.

[0074] For example, in some embodiments, the aforementioned at least some sub-pixels may include blue sub-pixels, green sub-pixels, and red sub-pixels. For example, the aforementioned first color sub-pixel may be a blue sub-pixel, and the second color sub-pixel may be a green sub-pixel or a red sub-pixel.

[0075] For example, in some embodiments, the pixel driving circuit includes multiple thin-film transistors. Figure 2 A cross-sectional schematic diagram of a thin-film transistor T electrically connected to a light-emitting device EM is shown. For example, when the pixel driving circuit is the aforementioned 3T1C pixel driving circuit, Figure 2 The thin-film transistor shown is Figure 1A The third transistor in the process. For example... Figure 2 As shown, the thin-film transistor T includes an active layer 1021, a gate 1022, and source and drain electrodes 1023 and 1024.

[0076] For example, in some embodiments, such as Figure 2 As shown, the active pattern AC is disposed on the side of the first metal pattern M1 away from the substrate 110. At this time, the first metal pattern M1 can be a light-shielding pattern SHL, and the light-shielding pattern SHL can be an active pattern ACT for light shielding. For example, the active pattern AC is disposed on the same layer as the active layer 1021 of the thin film transistor, or the active pattern AC is multiplexed as the active layer 1021.

[0077] Alternatively, in other embodiments, such as Figure 3 As shown, the active pattern AC is disposed on the side of the first metal pattern M1 near the substrate 110. At this time, the first metal pattern M1 can be located in the gate metal layer, that is, disposed in the same layer as the gate 1022 of the thin film transistor T, or the first metal pattern M1 can be multiplexed as the gate 1022, and the active pattern AC can be disposed in the same layer as the active layer 1021 of the thin film transistor T, or the active pattern AC can be multiplexed as the active layer 1021.

[0078] For example, such as Figure 2 and Figure 3 As shown, the second metal pattern M2 is disposed on the side of the active pattern AC away from the substrate 110. For example, the second metal pattern M2 is disposed in the same layer as the source / drain electrode 1023 of the thin-film transistor T or reused as the source / drain electrode 1023 of the thin-film transistor T. The electrode pattern 1041 is disposed on the side of the second metal pattern M2 away from the substrate 110, and the electrode pattern 1041 can serve as the anode of the light-emitting device EM.

[0079] It should be noted that in the embodiments of this disclosure, "same-layer setting" means that two (or more) functional layers or structural layers are formed on the same layer and with the same material in the layer structure of the display substrate. That is, in the manufacturing process, the two functional layers or structural layers can be formed from the same material layer and can be formed with the same patterning process to form the required pattern and structure.

[0080] For example, in a direction perpendicular to the substrate 110, the active pattern AC and the light-shielding pattern SHL at least partially overlap, so that the active pattern AC and the light-shielding pattern SHL can form the first capacitor of the storage capacitor. For example, the active pattern AC and the second metal pattern M2 at least partially overlap, so that the active pattern AC and the second metal pattern M2 can form the second capacitor of the storage capacitor, and the first capacitor and the second capacitor are connected in parallel.

[0081] For example, in some embodiments, under the same driving conditions, such as the same driving current, the luminance of the first color sub-pixel is L1, and the luminance of the second color sub-pixel is L2.

[0082]

[0083] In the above formula, α is the expected brightness parameter, and the value range of α is -2.00 < α < 9.50. For example, α can be approximately -1.00, 3.00, 4.00, 5.00, 6.00 or 8.00, etc. β is the capacitance compensation parameter, and the value range of β is 0.95 < β < 1.05. For example, β can be approximately 1.00, etc.

[0084] For example, in the above embodiment, the first color sub-pixel can be a blue sub-pixel, and the second color sub-pixel can be a green sub-pixel or a red sub-pixel. Since the luminous intensity of the blue sub-pixel is less than that of the green or red sub-pixel, the above design can balance the difference in luminous intensity between different color sub-pixels, keeping the difference in luminous intensity within an acceptable range, thereby improving the display effect of the display substrate.

[0085] For example, corresponding to Figure 2 The embodiment shown, Figures 4A-4G A plan view of each functional layer in the display panel is shown. Figures 5A-5DA planar schematic diagram of multiple functional layers stacked in a display panel is shown.

[0086] It is important to note that, Figures 4A-4G and Figures 5A-5D In the illustrated embodiment, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B constitute a pixel unit, and in the row direction, i.e., the horizontal direction in the figure, the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B are arranged sequentially to form a periodically arranged plurality of pixel units. For example, Figures 4A-4G and Figures 5A-5D Two pixel units located in the same row are shown as examples, and the display panel uses the following... Figure 1A The 3T1C pixel driving circuit shown.

[0087] For example, Figure 4A A planar schematic diagram of the first conductive layer containing the light-shielding pattern SHL of the display panel is shown.

[0088] like Figure 4A As shown, the first conductive layer includes a reset signal line 131, a power line segment 141, and a light-shielding pattern SHL (as a first metal pattern M1) that are insulated from each other. For example, the light-shielding pattern SHL can achieve the effect of light shielding and can also serve as a capacitor electrode of the storage capacitor in the pixel driving circuit.

[0089] For example, in some embodiments, in the same pixel unit, the light-blocking pattern SHL in the red sub-pixel R and the light-blocking pattern SHL in the green sub-pixel G are arranged substantially symmetrically, and the distance between the light-blocking pattern SHL in the red sub-pixel R and the light-blocking pattern SHL in the green sub-pixel G is greater than the distance between the light-blocking pattern SHL in the green sub-pixel G and the light-blocking pattern SHL in the blue sub-pixel B.

[0090] For example, in some embodiments, the display panel includes a plurality of reset signal lines 131 configured to transmit reset signals to at least a portion of the sub-pixels. For example, the at least a portion of the sub-pixels include a first color sub-pixel (e.g., blue sub-pixel B), a second color sub-pixel (e.g., green sub-pixel G), and a third color sub-pixel (e.g., red sub-pixel R), such as... Figure 4A As shown, in at least some pixel units, the length of the reset signal line transmitting the reset signal for the first color sub-pixel in the second direction (horizontal direction in the figure) is D1, the length of the reset signal line transmitting the reset signal for the second color sub-pixel in the second direction is D2, and the length of the reset signal line transmitting the reset signal for the third color sub-pixel in the second direction is D3.

[0091] D3 > D2, D3 > D1.

[0092] For example, in the above embodiment, since in the pixel driving circuit, due to the connection to the reset node S (reference) Figure 1A The reset signal line lengths of the red sub-pixels are different, so the same signal is given to different colored sub-pixels with different signal strengths. Because the red sub-pixel R has a long lifespan, its reset signal line is the longest, resulting in a low reset potential, fast charging, and high brightness.

[0093] For example, in some embodiments, at least some of the reset signal lines include a portion 131A extending along a first direction and a portion 131B extending along a second direction, the first direction being different from the second direction. For example, the portion 131B extending along the second direction is connected to the detection line SN, and the portion 131A extending along the first direction is used to connect the circuitry of each sub-pixel. For example, the width of the portion 131A extending along the first direction is greater than the width of the portion 131B extending along the second direction, to facilitate electrical connection of the portion 131A extending along the first direction to circuitry located in other layers, for example, through vias, thereby improving the reliability of the electrical connection.

[0094] For example, power line segment 141 is used to electrically connect to the first power line VDD for transmitting power signals.

[0095] For example, Figure 4B This diagram shows a planar schematic of the semiconductor material layer containing the active pattern AC of the display panel. Figure 5A A planar schematic diagram of the stacked semiconductor material layer and the first conductive layer is shown.

[0096] like Figure 4B and Figure 5A As shown, the semiconductor material layer includes active patterns T1a of a first transistor, active patterns T2a of a second transistor, and active patterns T3a of a third transistor spaced apart from each other. The semiconductor material layer also includes an active pattern AC, which is integrally connected to the active pattern T2a of the second transistor, or a portion of the active pattern AC serves as the active pattern T2a of the second transistor. The active pattern AC and the light-shielding pattern SHL at least partially overlap, thereby forming the first capacitor of the storage capacitor.

[0097] For example, Figure 4C A planar schematic diagram of the second conductive layer where the gate of the display panel is located is shown. Figure 5B A planar schematic diagram of the stacked layers of the second conductive layer, the semiconductor material layer, and the first conductive layer is shown.

[0098] like Figure 4C and Figure 5BThe second conductive layer includes a first scan line 150 and a second scan line 160 that are insulated from each other, and also includes the gates of each transistor that are insulated from each other. For example, the gate of each transistor is the portion where the first scan line 150 and the second scan line 160 overlap with the active layer, such as including the gate T1g of the first transistor, the gate T2g of the second transistor, and the gate T3g of the third transistor.

[0099] For example, the portions of the first scan line 150 and the second scan line 160 that intersect with the data line, the sensing line SN, and the first power line VDD (described later) are configured as a ring structure RIN, i.e., a dual-channel structure, which can effectively improve the yield of the device. For example, the intersection of signal lines is prone to electrostatic breakdown due to parasitic capacitance, leading to short circuit failure. During the detection process, if a short circuit failure is detected in one channel of the ring structure, that channel can be cut off (e.g., by laser cutting), and the circuit structure can still operate normally through the other channel.

[0100] For example, Figure 4D A planar schematic diagram of the third conductive layer where the source and drain electrodes of the display panel are located is shown. Figure 5C A planar schematic diagram of the stacked third conductive layer, second conductive layer, semiconductor material layer, and first conductive layer is shown.

[0101] like Figure 4D and Figure 5C As shown, the third conductive layer includes mutually insulated data lines DL1, DL2, DL3, a sensing line SN, and a first power line VDD for providing a high-level power signal, as well as the source and drain electrodes of various transistors, such as the source and drain electrodes T1d and T1s of the first transistor, the source and drain electrodes T2d and T2s of the second transistor, and the source and drain electrodes T3d and T3s of the third transistor. For example, the third conductive layer also includes a second metal pattern M2, which is integrated with the source and drain electrodes T2s of the second transistor and T3s of the third transistor; or, in other words, two opposing portions of the second metal pattern M2 serve as the source and drain electrodes T2s and T3s of the second and third transistors, respectively. For example, the second metal pattern M2 (as...) Figure 1A The SD in the first capacitor can be connected in parallel with the active pattern AC to form the second capacitor of the storage capacitor.

[0102] For example, such as Figure 2 As shown, the display panel also includes a gate insulating layer 1014 disposed on the side of the active pattern AC away from the substrate 110 and an interlayer insulating layer 1015 disposed on the side of the gate 1022 away from the substrate 110, as shown. Figure 2 and Figure 5CAs shown, the gate insulating layer 1014 and the interlayer insulating layer 1015 have a first via V1, and the active pattern AC and the second metal pattern M2 are electrically connected through the first via V1.

[0103] For example, Figure 4E A planar schematic diagram of the planarization layer of the display panel is shown. Figure 5C A planar schematic diagram of the stacked layers of planarization layer, third conductive layer, second conductive layer, semiconductor material layer, and first conductive layer is also shown.

[0104] like Figure 2 , Figure 4E and Figure 5C As shown, the display panel also includes a planarization layer 1016. The planarization layer 1016 is disposed on the side of the second metal pattern M2 (i.e., the third conductive layer mentioned above) away from the substrate 110. The planarization layer 1016 includes a second via V2, which penetrates the planarization layer 1016. The second metal pattern M2 (the source and drain electrodes 1023 of the thin film transistor) is electrically connected to the electrode pattern 1041 through the second via V2.

[0105] For example, the second via V2 is on the surface of the planarization layer 1016 away from the substrate 110 (i.e. Figure 2 The upper surface of the planarization layer 1016 has a first opening O1 on the surface near the substrate 110 (i.e., the upper surface of the planarization layer 1016). Figure 2 The lower surface of the substrate 110 has a second opening O2, the orthographic projection of the second opening O2 onto the substrate 110 being within the orthographic projection of the first opening O1 onto the substrate 110. For example, the size of the second opening O2 is smaller than the size of the first opening O1.

[0106] For example, in the first color sub-pixel (e.g., blue sub-pixel B), the overlapping area of ​​the orthographic projection of the first opening O1 onto the substrate 110 and the orthographic projection of the second metal pattern M2 onto the substrate 110 is Y1; in the second color sub-pixel (e.g., red sub-pixel R or green sub-pixel G), the overlapping area of ​​the orthographic projection of the first opening O1 onto the substrate 110 and the orthographic projection of the second metal pattern M2 onto the substrate 110 is Y2.

[0107] Y1>Y2.

[0108] For example, at the location of the second via V2, such as Figure 4DAs shown, the second metal pattern M2 of the blue sub-pixel B is slightly larger than the second metal patterns M2 of the green sub-pixel G and the red sub-pixel R, for example, by an additional BX area. Since blue is relatively weaker than red and green, the thin-film transistor T of the blue sub-pixel B needs to better reduce leakage current. Therefore, the area of ​​the second metal pattern M2 in the thin-film transistor T of the blue sub-pixel B is larger, and the overlap size between the second via V2 on the second metal pattern M2 and the second metal pattern M2 is also larger, providing a more stable environment and allowing the thin-film transistor T to operate better.

[0109] On the other hand, since the position of the thin film transistor T of the blue sub-pixel B is shifted to the right on the display panel, there may be problems with the overlap between the second metal pattern M2 and the electrode pattern 1041 at the second via V2, and the flatness below the second via V2 may also be problematic. Therefore, making the second metal pattern M2 larger is more conducive to the overlap between the second metal pattern M2 and the electrode pattern 1041. In addition, the area below the second via V2 will be flatter, which is beneficial for inkjet printing organic light-emitting materials on the electrode pattern 1041 during the fabrication process.

[0110] For example, such as Figure 5C As shown, in the first color sub-pixel (e.g., blue sub-pixel B), the distance between the center point of the first via V1 and the center point of the second via V2 is y1; in the second color sub-pixel (e.g., red sub-pixel R or green sub-pixel G), the distance between the center point of the first via V1 and the center point of the second via V2 is y2.

[0111]

[0112] Where a and b are constants. In sub-pixels of different colors, when a signal is transmitted from the active pattern AC through the first via V1 to the second metal pattern M2, and then through the second metal pattern M2 to the second via V2 to the electrode pattern 1041, the signal will suffer different losses due to the different signal transmission paths. For example, the theoretical maximum emission time of each sub-pixel is directly proportional to the ratio of the overlap area of ​​the active pattern AC and the first metal pattern M1 to the area of ​​the electrode pattern 1041, and inversely proportional to the distance between the center point of the first via V1 and the center point of the second via V2.

[0113] For example, in some embodiments,

[0114]

[0115] γ is a light intensity control compensation parameter, and its value range is: γ < -0.4 or γ > 0.3, for example, γ is approximately -0.5 or 0.4. Through the above design, the light emission duration and brightness of each sub-pixel can be further balanced, improving the display effect of the display panel.

[0116] For example, in some embodiments,

[0117]

[0118] Through the above design, the light emission duration and brightness of each sub-pixel can be adjusted more precisely, thereby balancing the light emission duration and brightness of each sub-pixel and improving the display effect of the display panel.

[0119] For example, Figure 6 A partial cross-sectional schematic diagram of the planarization layer 1016 near the second via V2 is shown, as follows. Figure 6 As shown, the planarization layer 1016 has a slope angle α1 at the second via V2. For example, the range of values ​​for the slope angle α1 is:

[0120] 75 degrees ≥ α1 ≥ 40 degrees.

[0121] For example, the slope angle α1 can be 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, or 70 degrees, etc. In the embodiments of this disclosure, the smaller the slope angle α1 of the planarization layer 1016 at the second via V2, the larger the aperture ratio of the sub-pixel. However, if the slope angle α1 of the planarization layer 1016 at the second via V2 is too large, the risk of the electrode pattern 1041 breaking at the second via V2 is also greater. Therefore, the slope angle α1 of the planarization layer 1016 at the second via V2 is designed to be within the above range. Through experiments, the above range can balance the aperture ratio of the sub-pixel and the risk of breakage of the electrode pattern 1041. That is, when the slope angle α1 of the planarization layer 1016 at the second via V2 is within the above range, it can simultaneously ensure that the aperture ratio of the sub-pixel and the electrode pattern 1041 will not break at the second via V2, thereby ensuring the reliability of the display panel.

[0122] For example, in some embodiments, such as Figure 2 and Figure 6 As shown, in the direction perpendicular to the substrate 110, that is, in the vertical direction shown in the figure, the thickness h of the planarization layer 1016 can take the following values:

[0123] h≤5.5 micrometers.

[0124] For example, 1.0 micrometers ≤ h ≤ 5.5 micrometers, where h can be 2.0 micrometers, 3.0 micrometers, 4.0 micrometers, or 5.0 micrometers, etc. The thinner the planarization layer 1016, the simpler the etching process for forming vias (e.g., second vias) in the planarization layer 1016. The thicker the planarization layer 1016, the better the planarization effect. Therefore, when the thickness of the planarization layer 1016 is within the above-mentioned size range, the effects of the two aspects can be balanced.

[0125] For example, Figure 4FA planar schematic diagram of the fourth conductive layer where the electrode pattern of the display panel is located is shown. Figure 4G A planar schematic diagram of the pixel boundary layer of the display panel is shown. Figure 5D A planar schematic diagram of the stacked layers of pixel defining layer, fourth conductive pattern, planarization layer, third conductive layer, second conductive layer, semiconductor material layer, and first conductive layer is shown.

[0126] like Figure 4F As shown, the electrode pattern 1041 is rectangular in shape, and is electrically connected to the second metal pattern M2 through the second via V2 on one side of the rectangle (e.g., the position of the square box in the figure).

[0127] For example, in some embodiments, such as Figure 4D and Figure 5D As shown, in the second direction, the electrode pattern 1041 has signal lines extending along the first direction on both sides, such as data lines DL1-DL3, a detection line SN, and a first power line VDD. In at least some sub-pixels, such as the red sub-pixel R and the blue sub-pixel B, the signals transmitted by the signal lines extending along the first direction on both sides of the electrode pattern 1041 are different. For example, in the red sub-pixel R, the signal lines extending along the first direction on both sides of the electrode pattern 1041 are the data line DL1 and the first power line VDD, respectively. In the blue sub-pixel B, the signal lines extending along the first direction on both sides of the electrode pattern 1041 are the data line DL3 and the detection line SN, respectively.

[0128] like Figure 2 and Figure 4G The display panel further includes a pixel defining layer 1017, which is disposed on the side of the electrode pattern 1041 away from the substrate 110. The pixel defining layer 1017 includes a plurality of sub-pixel openings 1017A for exposing the electrode pattern 1041 of the plurality of sub-pixels.

[0129] For example, such as Figure 2 As shown, the light-emitting device EM also includes a light-emitting material layer 1042 disposed in the sub-pixel opening 1017A and an electrode layer 1043 disposed at least partially in the sub-pixel opening 1017A. The electrode layer 1043 serves, for example, as the cathode of the light-emitting device EM. The sub-pixel opening 1017A defines the light-emitting area of ​​the sub-pixel. The portion of the light-emitting material layer 1042 located in the sub-pixel opening 1017A contacts the electrode pattern 1041, thereby being sandwiched between the electrode pattern 1041 and the electrode layer 1043. Thus, under the drive of the electrode pattern 1041 and the electrode layer 1043, it can emit light within the area defined by the sub-pixel opening 1017A.

[0130] For example, the subpixel opening 1017A can be elliptical or have curved edges. The shape and size of the subpixel opening 1017A corresponding to different color subpixels can be the same or different. Figure 4G In the illustrated embodiment, the shape and size of the subpixel opening 1017A corresponding to different color subpixels are the same, while in other embodiments, there may be different designs.

[0131] For example, Figure 7 A simplified schematic diagram of the pixel defining layer 1017 is shown, as follows: Figure 4G and Figure 7 As shown, the pixel defining layer 1017 includes a plurality of first blocking dams 1017B extending along a first direction and a plurality of second blocking dams 1017C extending along a second direction. Specifically, the first blocking dams 1017B are located between adjacent sub-pixel openings 1017A in the second direction, and the second blocking dams 1017C are located between adjacent sub-pixel openings 1017A in the first direction. The plurality of first blocking dams 1017B and the plurality of second blocking dams 1017C are configured to define sub-pixel openings 1017A for a plurality of sub-pixels. The first direction is different from the second direction; for example, the first direction is perpendicular to the second direction.

[0132] For example, in Figure 7 In the example, the first direction is the vertical direction in the image, which is the column direction of the sub-pixels, and the second direction is the horizontal direction in the image, which is the row direction of the sub-pixels. In other embodiments, the first direction can be the horizontal direction and the second direction can be the vertical direction.

[0133] For example, when a light-emitting material layer 1042 is formed in the sub-pixel opening 1017A by means of inkjet printing, the first barrier dam 1017B and the second barrier dam 1017C can block the light-emitting material, so that the light-emitting material is fully printed into the sub-pixel opening 1017A.

[0134] For example, Figure 8 It shows Figure 7 A schematic diagram of the pixel-defining layer along AA shows the cross-section of the first barrier dam 1017B. Figure 9 It shows Figure 7 A schematic cross-sectional view of the pixel-defining layer along BB shows the cross-section of the second barrier dam 1017C. In some embodiments, such as Figure 8 and Figure 9 As shown, in the direction perpendicular to the substrate 110, the thickness H1 of the first barrier dam 1017B is greater than the thickness H2 of the second barrier dam 1017C.

[0135] For example, in some embodiments, sub-pixels located in the same column emit the same color, that is, the light-emitting material layer in the light-emitting device of the sub-pixels located in the same column is the same. Therefore, by making the thickness H1 of the first barrier dam 1017B greater than the thickness H2 of the second barrier dam 1017C, when the light-emitting material layer 1042 is formed in the sub-pixel opening 1017A using methods such as inkjet printing, the first barrier dam 1017B can effectively prevent crosstalk between light-emitting materials of different colors, while the thickness H2 of the second barrier dam 1017C is lower, allowing the light-emitting materials of the light-emitting devices of the sub-pixels located in the same column to flow between each other, so that the light-emitting material is evenly distributed in the sub-pixel opening 1017A located in the same column. This helps to improve the uniformity of the light-emitting material layer 1042 formed in the sub-pixel opening 1017A after solvent evaporation, thereby improving the overall display uniformity of the display substrate.

[0136] For example, Figure 10 A partial cross-sectional schematic diagram of the planarization layer and pixel delimitation layer near the second via is shown. In some embodiments, such as Figure 10 As shown, at the location of the second via V2, along the second direction (the horizontal direction in the figure), at the boundary of the second metal pattern M2, the thickness of the planarization layer 1016 is h1; at the boundary of the light-emitting material layer 1042, the thickness of the planarization layer 1016 is h2; and at the boundary of the electrode pattern 1041, the thickness of the planarization layer 1016 is h3.

[0137] h1 / h2 < h2 / h3.

[0138] Therefore, the slope of the planarization layer 1016 at the second via V2 gradually becomes gentler in the direction away from the second via V2, thereby achieving a better planarization effect.

[0139] For example, in some embodiments, such as Figure 6 As shown, the diameter of the first opening O1 is L1, and the diameter of the second opening O2 is L2.

[0140] L1>L2+2*f*(h / tanα1),

[0141] Where f is a constant, and 1.5≤f≤3.4.

[0142] For example, the larger the slope angle α1 of the planarization layer 1016 at the second via V2, the smaller the diameter L1 of the first opening. When f is within the above-mentioned range, the size and structure of the second via V2 are within a suitable range, which helps to achieve a high opening ratio and maintain the stability of the structure.

[0143] For example, in some embodiments, L1 / L2 ≥ 2.5. When L1 / L2 is too small, there is a risk of breakage of the electrode pattern 1041 in the second via V2. Within the above-mentioned dimensional range, the structure of the display panel near the second via V2 is more stable, so as to improve the reliability of the display panel.

[0144] For example, in some embodiments, h = k*h2, where k is a constant and 0.5 < k < 1. Thus, the relationship between the thickness of the planarization layer 1016 at the boundary of the light-emitting material layer 1042 and the thickness of the planarization layer 1016 is constructed.

[0145] For example, in some embodiments, as Figure 10 shown, in the direction perpendicular to the substrate 110, the second dam 1017C includes a first part 1017D overlapping with the second via V2 and a second part 1017F not overlapping with the second via 1017C. The thickness h4 of the first part 1017D is greater than the thickness h5 of the second part 1017F. For example, the slope angle α2 of the first part 1017D at the boundary of the second via V2 is smaller than the slope angle α1 of the planarization layer 1016 at the second via V2. Thus, the second dam 1017C can at least partially fill the second via V2, or even completely fill the second via V2, so as to prevent the uneven structure at the second via V2 from affecting the display effect of the display panel.

[0146] For example, in some embodiments, in the first direction, in at least some sub-pixels, the shortest distance between the center of the second via V2 and the edge of the second dam 1017C covering the second via V2 is different. For example, as Figure 7 shown, the shortest distance between the center of the second via V2 and the lower edge of the second dam covering the second via V2 is h6, and the shortest distance between the center of the second via V2 and the upper edge of the second dam covering the second via V2 is h7. h6 is different from h7. For example, h6 is less than h7.

[0147] For example, in some embodiments, in the second direction, in at least some sub-pixels, the distances between the center of the second via V2 and two adjacent first dams 1017B are different. For example, as Figure 7 shown, the distance between the center of the second via V2 and the left adjacent first dam 1017B is h8, and the distance between the center of the second via V2 and the right adjacent first dam 1017B is h9. h8 is different from h9. For example, h8 is greater than h9.

[0148] Thus, the second via V2 is relatively shifted to the right in the area occupied by the sub-pixel. Thereby, the size of the storage capacitor in the pixel driving circuit of the sub-pixel can be reduced, and further the light-emitting time of the sub-pixel can be reduced, so as to improve the lifespan of the sub-pixel, and thus achieve the effect of making the lifespans of different color sub-pixels uniform.

[0149] The embodiments disclosed herein do not limit the materials or other structures of each functional layer. For example, the substrate 110 can be a rigid substrate such as glass or quartz, or a flexible substrate such as polyimide; the light-shielding layer SHL can be made of metals or alloys such as copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo); the gate 1022 can be made of metals or alloys such as copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), and can be formed as a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium / aluminum / titanium multi-layer metal layer structure. The source and drain electrodes 1023 and 1024 can be made of metals or alloys such as copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), and can be formed as a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium / aluminum / titanium multi-layer metal layer structure. The semiconductor material layer can be made of silicon-based materials (such as amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (such as IGZO, ZnO, AZO, IZTO, etc.) or organic materials (such as hexathiophene, polythiophene, etc.).

[0150] For example, such as Figure 2 and Figure 3 As shown, the display panel may further include a barrier layer 1112 and a buffer layer 1013 disposed on the substrate 110. The barrier layer 1112 and the buffer layer 1013 can prevent impurities in the substrate 110 from entering the multiple functional layers on the display panel 110, thereby providing protection. For example, the barrier layer 1112 and the buffer layer 1013 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. For example, the gate insulating layer 1014 and the interlayer insulating layer 1015 can also be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0151] For example, such as Figure 2 and Figure 3 As shown, the display panel may further include spacers 108 for defining the encapsulation space and an encapsulation layer EN for encapsulating the light-emitting device EM. The encapsulation layer EN may be a composite encapsulation layer, including a first inorganic encapsulation layer 1051, an organic encapsulation layer 1052, and a second inorganic encapsulation layer 1053. For example, the first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The spacers 108 and the organic encapsulation layer 1052 may be made of organic insulating materials such as polyimide or resin.

[0152] For example, the planarization layer 1016 and the pixel defining layer 1017 can be made of organic insulating materials such as polyimide and resin.

[0153] For example, the display panel may also include other structures besides those described above. For details, please refer to the relevant technologies, which will not be elaborated here.

[0154] Additionally, it should be noted that in the embodiments of this disclosure, each thin-film transistor can be a P-type thin-film transistor or an N-type thin-film transistor, and the structure can be bottom-gate, top-gate, or dual-gate. The structures shown in the accompanying drawings are merely exemplary, and the embodiments of this disclosure do not limit the specific form of each thin-film transistor.

[0155] This disclosure provides at least one embodiment of a display device, which includes any of the display panels described above. The display device can be implemented as a large-size, narrow-bezel display device. For example, the display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0156] The following points also need to be explained:

[0157] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0158] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0159] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0160] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A display panel, comprising a substrate and a plurality of sub-pixels disposed on the substrate, wherein, At least some of the sub-pixels each include a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a first metal pattern, an active pattern, and a second metal pattern disposed on the substrate, and the light-emitting device includes an electrode pattern electrically connected to the second metal pattern. The at least some sub-pixels include a first color sub-pixel and a second color sub-pixel, the first color sub-pixel and the second color sub-pixel being configured to emit different colors of light. In the first color sub-pixel, the ratio of the overlap area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern is X1. In the second color sub-pixel, the ratio of the overlap area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern is X2. 1 / 2 ≤ X1 / X2 < 1.

2. The display panel according to claim 1, wherein, The active pattern is disposed on the side of the first metal pattern closer to the substrate or on the side farther from the substrate. The second metal pattern is disposed on the side of the active pattern away from the substrate. The electrode pattern is disposed on the side of the second metal pattern away from the substrate.

3. The display panel according to claim 1 or 2, wherein, The luminance of the first color sub-pixel is L1, and the luminance of the second color sub-pixel is L2. Where α is the expected brightness parameter, and the value range of α is: -2.00 < α < 9.

50. β is the capacitor compensation parameter, and the value range of β is: 0.95 < β < 1.

05.

4. The display panel according to claim 1 or 2, wherein, The active pattern and the second metal pattern are electrically connected through a first via, and the second metal pattern and the electrode pattern are electrically connected through a second via. In the first color sub-pixel, the distance between the center point of the first via and the center point of the second via is y1. In the second color sub-pixel, the distance between the center point of the first via and the center point of the second via is y2. Where a and b are constants.

5. The display panel according to claim 3, wherein, γ is a light intensity control compensation parameter, and the value range of γ is: γ < -0.4 or γ > 0.

3.

6. The display panel according to claim 5, wherein, 7. The display panel according to claim 4, further comprising: A planarization layer is disposed on the side of the second metal pattern away from the substrate, wherein the second via penetrates the planarization layer. The second via has a first opening on the surface of the planarization layer away from the substrate, and a second opening on the surface of the planarization layer near the substrate. The orthographic projection of the second opening on the substrate lies within the orthographic projection of the first opening on the substrate. In the first color sub-pixel, the overlapping area of ​​the orthographic projection of the first opening on the substrate and the orthographic projection of the second metal pattern on the substrate is Y1. In the second color sub-pixel, the overlapping area of ​​the orthographic projection of the first opening on the substrate and the orthographic projection of the second metal pattern on the substrate is Y2. Y1>Y2.

8. The display panel according to claim 7, wherein, The slope angle α1 of the planarization layer at the second via is within the following range: 75 degrees ≥ α1 ≥ 40 degrees.

9. The display panel according to claim 7, wherein, In the direction perpendicular to the substrate, the thickness h of the planarization layer ranges as follows: h≤5.5 micrometers.

10. The display panel according to claim 9, further comprising: A pixel defining layer is disposed on the side of the electrode pattern away from the substrate, wherein the pixel defining layer includes a plurality of first blocking dams extending along a first direction and a plurality of second blocking dams extending along a second direction, the plurality of first blocking dams and the plurality of second blocking dams being configured to define sub-pixel openings of the plurality of sub-pixels, the first direction being different from the second direction; The light-emitting device further includes a light-emitting material layer disposed in the sub-pixel opening. In a direction perpendicular to the substrate, the thickness of the first barrier dam is greater than the thickness of the second barrier dam. At the location of the second via, along the second direction, at the boundary of the second metal pattern, the thickness of the planarization layer is h1; at the boundary of the luminescent material layer, the thickness of the planarization layer is h2; and at the boundary of the electrode pattern, the thickness of the planarization layer is h3. h1 / h2 < h2 / h3.

11. The display panel according to claim 10, wherein, The diameter of the first opening is L1, and the diameter of the second opening is L2. L1>L2+2*f*(h / tanα1), Where f is a constant, and 1.5≤f≤3.

4.

12. The display panel according to claim 11, wherein, L1 / L2≥2.

5.

13. The display panel according to claim 12, wherein, h = k * h², k is a constant, and 0.5 <k<1。 14. The display panel according to claim 10, wherein, In a direction perpendicular to the substrate, the second barrier dam includes a first portion overlapping the second via and a second portion not overlapping the second via. The thickness of the first part is greater than the thickness of the second part.

15. The display panel according to claim 14, wherein, The slope angle of the first portion at the boundary of the second via is smaller than the slope angle α1 of the planarization layer at the second via.

16. The display panel according to claim 10, wherein, In the first direction, in at least a portion of the sub-pixels, the center of the second via is different from the shortest distance from the edge of the second blocking dam covering the second via.

17. The display panel according to claim 10, wherein, In the second direction, in at least some sub-pixels, the center of the second via is at a different distance from the two adjacent first blocking dams.

18. The display panel according to claim 1 or 2, wherein, The first color sub-pixel is a blue sub-pixel, and the second color sub-pixel is either a green sub-pixel or a red sub-pixel.

19. The display panel according to claim 1 or 2, wherein, The at least some sub-pixels also include a third color sub-pixel, and the display panel further includes a plurality of reset signal lines configured to transmit a reset signal to the at least some sub-pixels. Wherein, the extension length of the reset signal line transmitting the reset signal for the first color sub-pixel in the second direction is D1, the extension length of the reset signal line transmitting the reset signal for the second color sub-pixel in the second direction is D2, and the extension length of the reset signal line transmitting the reset signal for the third color sub-pixel in the second direction is D3. D3 > D2, D3 > D1.

20. The display panel according to claim 19, wherein, The first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a red sub-pixel.

21. The display panel according to claim 19, wherein, At least some of the plurality of reset signal lines include portions extending along a first direction and portions extending along a second direction, respectively. The first direction is different from the second direction.

22. The display panel according to claim 21, wherein, In the second direction, signal lines extending along the first direction are respectively located on both sides of the electrode pattern. In at least some of the sub-pixels, the signals transmitted by the signal lines extending along the first direction on both sides of the electrode pattern are different.

Images