Array substrate and display device

Abstract

The array substrate and display device provided by the present disclosure comprise a substrate substrate; a plurality of pixel circuits arranged in an array on the substrate substrate; a plurality of gate lines extending along a first direction on the substrate substrate and arranged along a second direction, the gate lines being coupled with the pixel circuits; a plurality of pixel electrodes arranged in an array on the substrate substrate, the pixel electrodes comprising oppositely arranged first and second end portions, a plurality of intermediate portions connecting the first and second end portions, and a protruding portion located on one side of the second end portion, the first end portion being coupled with the pixel circuit, the intermediate portions extending obliquely with respect to the first and second directions, the protruding portion extending along a direction forming an obtuse angle with the extension direction of the intermediate portions, the slit between adjacent intermediate portions being a parallelogram, and the orthographic projection of the slit on the substrate substrate, the orthographic projection of the pixel circuit on the substrate substrate, and the orthographic projection of the gate line on the substrate substrate all being mutually non-overlapping.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to an array substrate and a display device. BACKGROUND

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high picture quality, no radiation, and convenient to carry, etc. In recent years, it has been rapidly developed, and has gradually replaced the traditional Cathode Ray Tube display (CRT), and occupies a dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various large, medium and small size products, and almost covers the main electronic products in today's information society, such as liquid crystal television, high-definition digital television, computer (desktop and notebook), mobile phone, tablet computer, navigator, vehicle display, projection display, camera, digital camera, electronic watch, calculator, electronic instrument, instrument, public display and virtual display, etc. SUMMARY

[0003] The array substrate and the display device provided by the present disclosure have the following specific solutions:

[0004] In one aspect, the present disclosure provides an array substrate, comprising:

[0005] a substrate substrate;

[0006] a plurality of pixel circuits arranged in an array on the substrate substrate;

[0007] a plurality of gate lines extending along a first direction on the substrate substrate and arranged along a second direction, the gate lines being coupled to the pixel circuits;

[0008] a plurality of pixel electrodes arranged in an array on the substrate substrate, the pixel electrodes comprising a first end portion and a second end portion opposite to each other, a plurality of intermediate portions connecting the first end portion and the second end portion, and a protruding portion located on one side of the second end portion, the first end portion being coupled to the pixel circuits, the intermediate portions extending obliquely with respect to the first direction and the second direction, the protruding portion extending in a direction forming an obtuse angle with the extending direction of the intermediate portions, the slit between adjacent intermediate portions being a parallelogram, and the orthogonal projection of the slit on the substrate substrate, the orthogonal projection of the pixel circuits on the substrate substrate, and the orthogonal projection of the gate lines on the substrate substrate all being non-overlapping.

[0009] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the convex part has a shape of a triangle in a plan view of the substrate, and the triangle includes an arc-shaped corner away from the second end, and an included angle of a boundary extension line of the arc-shaped corner is greater than or equal to 20° and less than or equal to 30°.

[0010] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the extension direction of the convex part is rotated relative to the extension direction of the middle part.

[0011] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a plan view of the convex part on the substrate is located within a plan view of the gate line on the substrate.

[0012] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the pixel circuit includes a transistor, the transistor includes a station area for supporting a spacer, and a plan view of the convex part on the substrate does not overlap with a plan view of the station area on the substrate.

[0013] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a first electrode of the transistor is coupled with the pixel electrode, and two station areas adjacent in the second direction are arranged in the first direction with a staggered arrangement, one of the station areas overlaps with a first electrode area and a second electrode area of the same transistor, and the other station area overlaps with a second electrode area of one transistor and a first electrode area of an adjacent transistor.

[0014] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the array substrate further includes a plurality of data lines extending in an inclined direction of the pixel electrode and arranged in the first direction, a line width of the data lines is substantially uniform, and a part of the data lines are multiplexed as the second electrodes of the transistors.

[0015] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the transistor is located on a side of the gate line facing the pixel electrode coupled with the gate line, a gate electrode of the transistor is integrally arranged with the gate line, and the gate electrode of the transistor is arranged with an angle missing away from a corner of the gate line and the data line.

[0016] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a plan view of an active layer of the transistor on the substrate is located within a plan view of the gate electrode of the transistor and a plan view of the gate line on the substrate, and in the second direction, an overlap width of the active layer of the transistor and the second electrode of the transistor is greater than an overlap width of the active layer of the transistor and the first electrode of the transistor.

[0017] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a projection of the protruding portion on the substrate away from one end of the second end portion is located within a projection of the data line on the substrate.

[0018] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the plurality of pixel electrodes include a plurality of first pixel electrodes and a plurality of second pixel electrodes, rows where the first pixel electrodes are located and rows where the second pixel electrodes are located are alternately arranged in the second direction, and the tilt direction of the middle portion of the first pixel electrode and the tilt direction of the middle portion of the second pixel electrode are substantially symmetrical about the first direction.

[0019] On the other hand, the present disclosure provides a display device including an array substrate and a counter substrate opposite to each other, and a liquid crystal layer between the array substrate and the counter substrate, the array substrate being the above-mentioned array substrate provided by the embodiments of the present disclosure.

[0020] In some embodiments, in the display device provided by the embodiments of the present disclosure, the pixel circuit includes a transistor including a station area for supporting a spacer, the counter substrate includes a spacer, and a projection of the spacer on the substrate substrate near an end of the array substrate is substantially coincident with a projection of the station area on the substrate substrate. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A light efficiency simulation diagram of a sub-pixel in the related art;

[0022] Figure 2 A structure schematic diagram of a sub-pixel provided by the embodiments of the present disclosure;

[0023] Figure 3 A light efficiency simulation diagram of a sub-pixel provided by the embodiments of the present disclosure;

[0024] Figure 4 A liquid crystal molecule orientation schematic diagram when the pixel electrode provided by the embodiments of the present disclosure has no protruding portion;

[0025] Figure 5 A liquid crystal molecule orientation schematic diagram when the pixel electrode provided by the embodiments of the present disclosure has a protruding portion;

[0026] Figure 6 A structure schematic diagram of a gate line in the middle layer; Figure 2

[0027] A structure schematic diagram of a gate line in the middle layer; Figure 7 Figure 2 A structure schematic diagram of an active layer in the middle layer;

[0028] ​Figure 8 FIG. 1 is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 2 FIG. 2 is a structural schematic diagram of a layer where a data line is located in the display device of FIG. 1.

[0029] Figure 9 FIG. 3 is a structural schematic diagram of a layer where a common electrode is located in the display device of FIG. 1. Figure 2

[0030] Figure 10 FIG. 4 is a structural schematic diagram of a layer where an insulating layer is located in the display device of FIG. 1. Figure 2

[0031] Figure 11 FIG. 5 is a structural schematic diagram of a layer where a pixel electrode is located in the display device of FIG. 1. Figure 2

[0032] Figure 12 FIG. 6 is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It should be noted that in order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions and the like are exaggerated for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described in the present disclosure are not to be construed as being limited to the particular shapes of regions as illustrated but are to include deviations in shapes that result from, for example, manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. A illustrated sharp angle can be rounded, etc. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and do not reflect true scales and proportions. The purpose of the figures is to illustrate concepts and principles of the present disclosure and the figures are not to be construed as being limiting in any way. Also, identical or similar elements are denoted by the same or similar reference numerals throughout the entire disclosure. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known components.

[0034] ​​​Unless otherwise defined, technical terms or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and the like, as used in the specification and claims herein, do not denote any order, quantity, or importance, but are used to identify different components. The terms "comprises", "comprising", "includes", "including", or the like, means encompassing, and the like, without excluding other elements or integers. The terms "connected", "coupled", or the like, are not limited to a physical or mechanical connection or coupling, and can include an electrical connection or coupling, whether direct or indirect. The terms "inner", "outer", "upper", "lower", and the like, are used for convenience only and are not a limitation on the scope of the disclosure.

[0035] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. When an element or layer is referred to as being "disposed on" one side of another element or layer, it can be directly on the one side of the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. However, when an element or layer is referred to as being "directly on" another element or layer, or "directly connected to" another element or layer, there is no intervening element or layer present. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] An advanced dimension switch (ADS) liquid crystal display panel has advantages of high transmittance, wide viewing angle, etc., and has been widely applied to products such as mobile phones, tablet computers, desktop displays, televisions, etc. The display principle of the ADS liquid crystal display panel is: by controlling the voltage between the pixel electrode and the common electrode, the rotation of the liquid crystal is controlled, the light transmission of the pixel is realized, and finally the target display picture is realized. In the conventional pixel design of the ADS liquid crystal display panel, in order to prevent trace mura, there is a corner design at the beginning and end of the slit of the pixel electrode, the light efficiency at the corner is poor, which will affect the overall transmittance of the pixel, as shown in Figure 1 .

[0037] In order to improve the above technical problems existing in the related art, the embodiments of the present disclosure provide an array substrate, as shown in Figure 2 .

[0038] The substrate 101 is a substrate allowing visible light to pass through, for example, a glass, quartz, plastic, etc.

[0039] a plurality of pixel circuits (including the transistor 102) arranged in an array on the substrate 101; optionally, the transistor 102 can be a P-type transistor or an N-type transistor, the transistor 102 can be a bottom-gate transistor, a top-gate transistor or a dual-gate transistor, etc., the transistor 102 can be an amorphous silicon (a-Si) transistor, a polysilicon (poly) transistor, an oxide (such as indium gallium zinc oxide IGZO) transistor, etc.

[0040] a plurality of gate lines 103 extending along a first direction X and arranged along a second direction Y on the substrate 101, the gate line 103 being coupled with the pixel circuit (including the transistor 102), for example, the gate line 103 is integrally arranged with the gate electrode 1021 of the transistor 102; optionally, the material of the gate line 103 can include molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc., the gate line 103 can be a single-layer structure or a laminated structure, for example, the gate line 103 is a single-layer structure composed of a molybdenum metal layer.

[0041] a plurality of pixel electrodes 104 arranged in an array on the substrate 101, the pixel electrode 104 including a first end portion 1041 and a second end portion 1042 opposite to each other, a plurality of intermediate portions 1043 connecting the first end portion 1041 and the second end portion 1042, and a protruding portion 1044 located on the side of the second end portion 1042, the first end portion 1041 being coupled with the pixel circuit (including the transistor 102), for example, the first end portion 1041 is coupled with the first electrode 1022 of the transistor 102 through a via hole h penetrating through an insulating layer, the intermediate portion 1043 extends obliquely with respect to the first direction X and the second direction Y, the protruding portion 1044 extends along a direction forming an obtuse angle α with the extending direction of the intermediate portion 1043, the slit 1045 between adjacent intermediate portions 1043 is a parallelogram, the orthogonal projection of the slit 1045 on the substrate 101, the orthogonal projection of the pixel circuit (including the transistor 102) on the substrate 101, and the orthogonal projection of the gate line 103 on the substrate 101 all do not overlap with each other; optionally, the material of the pixel electrode 104 includes transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0042] In the above array substrate provided by the embodiments of the present disclosure, the slit 1045 of the pixel electrode 104 is a parallelogram without corner design, which is different from the prior art Figure 1 and Figure 3It can be seen that the slit 1045 of the present disclosure has no corner design, which can reduce the dark area D and effectively improve the transmittance. Meanwhile, the present disclosure sets the orthogonal projection of the slit 1045 on the substrate 101, the orthogonal projection of the pixel circuit (including the transistor 102) on the substrate 101, and the orthogonal projection of the gate line 103 on the substrate 101 to be mutually non-overlapping, which avoids the pixel circuit (including the transistor 102) and the gate line 103 from shielding the light transmission at the slit 1045, and further improves the transmittance. However, as shown in Figure 4 , when the slit 1045 adopts the corner-free design, the liquid crystal molecules at the first end portion 1041 and the second end portion 1042 are disordered in orientation, and are not easy to restore the original orientation without external force and will appear indentation defects. Based on this, the present disclosure sets a protruding portion 1044 with an obtuse angle a with the middle portion 1043 on one side of the second end portion 1042, and combines Figure 5 It can be seen that the protruding portion 1044 can set a fixed molecular orientation for the liquid crystal molecules, prevent the liquid crystal molecules from not recovering in time after being pressed, and effectively prevent indentation defects.

[0043] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in Figure 2 and Figure 11 , the orthogonal projection shape of the protruding portion 1044 on the substrate 101 can be designed as a triangle, but due to the limitation of exposure accuracy and the like, the angle of the triangle away from the second end portion 1042 is actually made as an arc angle rather than a sharp angle, so that the orthogonal projection shape of the protruding portion 1044 on the substrate 101 in the final product is approximately a triangle. In order to ensure the effect of fixing the liquid crystal molecular orientation of the protruding portion 1044, the included angle β of the boundary extension line of the arc angle can be set to be greater than or equal to 20° and less than or equal to 30°, for example, 20°, 21°, 22°, 23°, 24°, 25°, 26°, 27°, 28°, 29°, 30°, etc. In some embodiments, in order to meet the resolution accuracy requirement of the exposure machine, the length l of the protruding portion 1044 can be set to be at least 3 μm, and correspondingly, the width w of the protruding portion 1044 is l*tanβ. Continue to refer to Figure 11 It can be seen that the obtuse angle a, the included angle β, and the inclination angle γ of the middle portion 1043 satisfy the relationship: a = 180°-r+β.

[0044] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in Figure 2 and Figure 11As shown, the plurality of pixel electrodes 104 include a plurality of first pixel electrodes 104' and a plurality of second pixel electrodes 104"; the rows where the first pixel electrodes 104' are located and the rows where the second pixel electrodes 104" are located are alternately arranged in the second direction Y; the tilt direction of the middle portion 1043 of the first pixel electrode 104' and the tilt direction of the middle portion of the second pixel electrode 104" are approximately symmetrical about the first direction X (i.e. symmetrical or within the error range caused by factors such as manufacturing and measurement), so that the present disclosure can realize a dual-domain display effect, which is beneficial to improving transmittance.

[0045] Optionally, such as Figure 5 As shown, when the extending direction of the protrusion 1044 is rotated by an obtuse angle α relative to the extending direction of the middle portion 1043, a fixed molecular orientation can be set for the liquid crystal molecules, preventing them from failing to recover promptly after being pressed, thus effectively preventing indentation defects. Based on this, to effectively improve indentation defects, such as... Figure 2 and Figure 11 As shown, in this disclosure, the extending direction of the protrusion 1044 of the first pixel electrode 104' can be rotated by an obtuse angle α relative to the extending direction of its intermediate portion 1043, and the extending direction of the protrusion 1044 of the second pixel electrode 104" can be rotated by an obtuse angle α relative to the extending direction of its intermediate portion 1043. For example, in... Figure 2 and Figure 11 The diagram shows that the middle portion 1043 of the first pixel electrode 104' is tilted to the right, and correspondingly, the protrusion 1044 of the first pixel electrode 104' is tilted to the right at an obtuse angle α relative to its middle portion 1043; the middle portion 1043 of the second pixel electrode 104" is tilted to the left, and correspondingly, the protrusion 1044 of the second pixel electrode 104" is tilted to the left at an obtuse angle α relative to its middle portion 1043.

[0046] In some embodiments, in the array substrate provided in the present disclosure, by Figure 2 , Figure 6 and Figure 11 As can be seen, the orthographic projection of the protrusion 1044 on the substrate 101 can be located within the orthographic projection of the gate line 103 on the substrate 101. Normally, to avoid reflection from the gate line 103, a black matrix (BM) is used to block the gate line 103. By placing the protrusion 1044 in the area of ​​the gate line 103, the protrusion 1044 and the gate line 103 can share the black matrix (BM), eliminating the need for an additional black matrix (BM) to block the protrusion 1044. Therefore, the product has better transmittance.

[0047] In some embodiments, in the array substrate provided in the present disclosure, such as Figure 2 , Figure 6 to Figure 8As shown, the transistor 102 includes a station area PS' for supporting a photo spacer (PS), and a projection of the protrusion 1044 on the substrate 101 does not overlap with a projection of the station area PS' on the substrate 101, so as to prevent the liquid crystal recovery effect from being affected by the poor orientation of the alignment layer caused by the film layer unevenness at the station area PS'.

[0048] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in Figure 2 、 Figure 8 to Figure 11 As shown, the first electrode 1022 of the transistor 102 is coupled with the pixel electrode 104, and optionally, the first electrode 1022 of the transistor 102 is coupled with the pixel electrode 104 through a via h penetrating through an insulating layer (for example, including a passivation layer PVX between the layer where the pixel electrode 104 is located and the layer where the common electrode 105 is located, and a planarization layer PLN between the layer where the common electrode 105 is located and the layer where the first electrode 1022 is located); and, to avoid the short circuit between the common electrode 105 and the first electrode 1022 and the pixel electrode 104, a hollow structure K exposing the via h can be arranged on the common electrode 105. In some embodiments, the material of the common electrode 105 can include indium tin oxide (ITO), indium zinc oxide (IZO), and the like transparent conductive material; the material of the passivation layer PVX includes but is not limited to inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, and the like; and the material of the planarization layer PLN can be organic insulating material such as polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, phenolic epoxy acrylic resin, and the like.

[0049] Continuing to refer to Figure 2 and Figure 8It can be known that two adjacent station areas PS' in the second direction Y are arranged staggered in the first direction X, one of which overlaps with the area where the first electrode 1022 of the same transistor 102 is located and the area where the second electrode 1023 of the same transistor 102 is located, and the other overlaps with the area where the second electrode 1023 of one transistor 102 is located and the area where the first electrode 1022 of the adjacent transistor 102 is located. By arranging the station area PS' to overlap with the area where the first electrode 1022 is located and the area where the second electrode 1023 is located, the area of the station area PS' is larger, which is conducive to stably supporting the spacers (PS); and by arranging the two adjacent station areas PS' in the second direction Y staggered in the first direction X, it is equivalent to arranging the spacers (PS) in the adjacent two rows in the adjacent columns, so that the spacers (PS) are arranged more uniformly, which is conducive to balancing the support force and maintaining the uniformity of the box thickness; at the same time, the way of arranging the spacers (PS) in the present disclosure is suitable for high-definition (WQ) screens with high resolution. Since the sub-pixels of the high-definition screen are small, if the spacers (PS) are arranged in the same row and adjacent two sub-pixels, the adjacent spacers (PS) will be connected together in actual production, which will affect the effect of supporting the box thickness. Therefore, in the present disclosure, only one of the two adjacent sub-pixels in the same row is provided with a spacer (PS). It should be understood that in a low-resolution product, the sub-pixel is large, and there is enough space to arrange the spacer, so that the spacers (PS) at the two adjacent sub-pixels in the same row are relatively independent and not connected in actual production. Therefore, a spacer (PS) can be arranged at each sub-pixel.

[0050] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in Figure 2 、 Figure 8 and Figure 11 , the array substrate can further include a plurality of data lines 106 extending along the oblique direction of the pixel electrode 104 and arranged in the first direction X. For example, when the pixel electrode 104 includes a first pixel electrode 104' and a second pixel electrode 104" with opposite oblique directions, the data line 106 extends along the oblique direction of the first pixel electrode 104' and the oblique direction of the second pixel electrode 104", and appears as a zigzag shape. In the present disclosure, the line width of the data line 106 is substantially uniform (i.e. uniform or within an error range of ±5% due to factors such as production and measurement), and the local part of the data line 106 can be reused as the second electrode 1023 of the transistor 102. In the present disclosure, the local data line 106 reused as the second electrode 1023 and the first electrode 1022 of the transistor 102 are used to support the spacers (PS) together, which can ensure effective support for the spacers (PS). In addition, considering that the data line 106 with a locally widened line width is used to support the spacers (PS) in the related art, the line width of the data line 106 in the present disclosure is uniform, has less impact on the aperture ratio, and thus can improve the aperture ratio while stably supporting the spacers (PS).

[0051] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in Figure 2 、 Figure 6 、 Figure 8 and Figure 11 , the transistor 102 is located on the side of the gate line 103 facing the pixel electrode 104 coupled with the gate line 103, the gate 1021 of the transistor 102 is integrally arranged with the gate line 103, and the gate 1021 of the transistor 102 is arranged with an angle at the corner away from the gate line 103 and the data line 106 (i.e., the corner close to the first pole 1022) (for example, the gate 1021 is arranged with an angle at the upper right corner as shown in Figure 6 ) to reduce the area occupied by the gate 1021 and improve the aperture ratio.

[0052] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in Figure 2 、 Figure 6 to Figure 8 , the active layer 1024 of the transistor 102 is located in the projection of the gate 1021 of the transistor 102 and the gate line 103 on the substrate 101, so as to shield the active layer 1024 by the gate 1021 to prevent the leakage current caused by the backlight irradiation of the active layer 1024; accordingly, due to the angle arrangement of the gate 1021 close to the first pole 1022, the overlap width w1 of the active layer 1024 of the transistor and the second pole 1023 of the transistor 102 in the second direction Y can be greater than the overlap width w2 of the active layer 1024 of the transistor and the first pole 1022 of the transistor 102, and the active layer 1024 of the transistor 102 is approximately in the shape of "convex".

[0053] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in Figure 2 、 Figure 8 and Figure 11 , the projection of the one end of the protruding portion 1044 away from the second end portion 1042 on the substrate 101 is located in the projection of the data line 106 on the substrate 101, in other words, the one end of the protruding portion 1044 away from the second end portion 1042 does not exceed the area where the data line 106 is located, so as to ensure that the distance between the protruding portion 1044 and the adjacent pixel electrode 104 is at least equal to the spacing between the data line 106 and the adjacent pixel electrode 104, effectively preventing the short circuit between the protruding portion 1044 and the adjacent pixel electrode 104.

[0054] Based on the same inventive concept, the embodiments of the present disclosure provide a display device, as shown in Figure 12As shown, the display device includes the array substrate 001 and the opposite substrate 002 opposite to each other, and the liquid crystal layer 003 between the array substrate 001 and the opposite substrate 002, wherein the array substrate 001 is the array substrate provided by the embodiment of the present disclosure. Since the principle of solving the problem of the display device is similar to the principle of solving the problem of the array substrate, the implementation of the display device can refer to the embodiments of the array substrate, and the repeated parts will not be described here.

[0055] By Figure 2 and Figure 12 It can be seen that the opposite substrate 002 provided by the present disclosure can include a spacer (PS), and the front projection of the end of the spacer (PS) on the array substrate 001 on the substrate 101 is substantially coincident with the front projection of the standing area PS' on the substrate 101 (i.e., coincident or within the error range caused by manufacturing, measurement, etc.), so as to achieve stable support of the spacer (PS) while avoiding the standing area PS' being too large to affect the aperture ratio.

[0056] In some embodiments, in the display device provided by the embodiment of the present disclosure, as Figure 12 shown, a backlight module 004 can also be located on the light-in side of the array substrate 001. The backlight module 004 can be a direct type backlight module as Figure 12 shown, or a side type backlight module. Optionally, the side type backlight module can include a lamp strip, a reflector sheet, a light guide plate, a diffusion sheet, a prism group, etc., and the lamp strip is located on one side of the light guide plate in the thickness direction. The direct type backlight module can include a matrix light source, a reflector sheet, a diffusion plate, a brightness enhancement film, etc., which are stacked on the light-out side of the matrix light source, and the reflector sheet includes openings opposite to the positions of the lamp beads in the matrix light source. The lamp beads in the lamp strip and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).

[0057] The micro light-emitting diode of sub-millimeter level or even micron level is a self-luminous device like the organic light-emitting diode (OLED). It has a series of advantages such as high brightness, ultra-low delay, and ultra-large viewing angle like the organic light-emitting diode. And since the inorganic light-emitting diode realizes light emission based on a metal semiconductor with more stable properties and lower resistance, it has the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life compared with the organic light-emitting diode which realizes light emission based on organic matter. When the micro light-emitting diode is used as a backlight source, it can realize more precise dynamic backlight effect, effectively improve the screen brightness and contrast, and solve the glare phenomenon caused by the traditional dynamic backlight between the light and dark areas of the screen, thereby optimizing the visual experience.

[0058] In some embodiments, the display device provided by the embodiments of the present disclosure can be a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any product or component having a display function. Optionally, the display device provided by the embodiments of the present disclosure includes, but is not limited to, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip, and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), or the like. For example, the control chip can further include a memory, and can further include a power module, and the like, and the power supply and signal input and output functions are realized through additionally arranged wires, signal lines, and the like. For example, the control chip can further include hardware circuitry and computer executable code, and the like. The hardware circuitry can include conventional very large scale integration (VLSI) circuitry or gate arrays, and existing semiconductors or other discrete elements such as logic chips, transistors, and the like; the hardware circuitry can also include field programmable gate arrays, programmable array logic, programmable logic devices, and the like. In addition, those skilled in the art can understand that the above structure does not constitute a limitation on the display device provided by the embodiments of the present disclosure, in other words, the display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or different component arrangements.

[0059] Although the preferred embodiments of the present disclosure have been described, it should be understood that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The application relates to a display panel, comprising: a substrate; a plurality of pixel circuits arranged in an array on the substrate; a plurality of gate lines extending along a first direction on the substrate and arranged along a second direction, the gate lines being coupled with the pixel circuits; a plurality of pixel electrodes arranged in an array on the substrate, the pixel electrodes comprising opposite first and second end portions, a plurality of intermediate portions connecting the first and second end portions, and a protruding portion located on one side of the second end portion, the first end portion being coupled with the pixel circuit, the intermediate portions extending obliquely with respect to the first and second directions, the protruding portion extending along a direction forming an obtuse angle with the extending direction of the intermediate portions, a slit between adjacent intermediate portions being a parallelogram, a normal projection of the slit on the substrate not overlapping with a normal projection of the pixel circuit on the substrate and a normal projection of the gate line on the substrate; the pixel circuit comprising a transistor, the transistor comprising a station area for supporting a spacer, a normal projection of the protruding portion on the substrate not overlapping with a normal projection of the station area on the substrate; a first pole of the transistor being coupled with the pixel electrode, two adjacent station areas in the second direction being arranged staggered along the first direction, one of the station areas overlapping with a first pole area and a second pole area of the same transistor, the other station area overlapping with a second pole area of one transistor and a first pole area of an adjacent transistor.

2. The array substrate of claim 1, wherein, a normal projection of the protruding portion on the substrate is approximately triangular, the triangle comprising an arc-shaped corner away from the second end portion, an included angle of a boundary extension line of the arc-shaped corner being greater than or equal to 20 DEG and less than or equal to 30 DEG.

3. The array substrate of claim 1 or 2, wherein, the extending direction of the protruding portion is rotated by the obtuse angle with respect to the extending direction of the intermediate portions.

4. The array substrate of claim 1 or 2, wherein, a normal projection of the protruding portion on the substrate is located within a normal projection of the gate line on the substrate.

5. The array substrate of claim 1, wherein, a plurality of data lines extending along the oblique direction of the pixel electrode and arranged along the first direction, the data lines having uniform line widths, and the data lines being locally multiplexed as the second poles of the transistors.

6. The array substrate of claim 5, wherein, the transistor is located on one side of the gate line towards the pixel electrode coupled with the gate line, a gate of the transistor being integrally arranged with the gate line, and the gate of the transistor being arranged with an angle corner away from a corner of the gate line and the data line.

7. The array substrate of claim 6, wherein, a normal projection of an active layer of the transistor on the substrate is located within a normal projection of the gate of the transistor and a normal projection of the gate line on the substrate; and in the second direction, an overlap width of the active layer of the transistor and the second pole of the transistor is greater than an overlap width of the active layer of the transistor and the first pole of the transistor.

8. The array substrate of any one of claims 5 to 7, wherein, a normal projection of one end of the protruding portion away from the second end portion on the substrate is located within a normal projection of the data line on the substrate.

9. The array substrate according to any one of claims 1, 2, 5-7, wherein, The plurality of pixel electrodes includes a plurality of first pixel electrodes and a plurality of second pixel electrodes, rows of the first pixel electrodes and rows of the second pixel electrodes are alternately arranged in the second direction, and the intermediate portion of the first pixel electrode and the intermediate portion of the second pixel electrode are symmetric about the first direction.

10. A display device, wherein, An array substrate as claimed in any one of claims 1 to 9.

11. The display device of claim 10, wherein, The pixel circuit includes a transistor including a stand area for supporting a spacer, the counter substrate includes a spacer, and a normal projection of an end portion of the spacer on the substrate substrate coincides with a normal projection of the stand area on the substrate substrate.

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