A characteristic current identification circuit and identification method for a low voltage topology module

Abstract

The present invention discloses a characteristic current identification circuit and identification method of a low-voltage topology module, wherein the characteristic current identification circuit collects characteristic current signals between live and neutral lines through a current transformer, and the characteristic current identification circuit includes a differential amplifier circuit, a bandpass filter circuit, and a reference voltage generation circuit; the differential amplifier circuit is used to input the characteristic current signal collected by the current transformer and convert the characteristic current signal into a voltage signal; the bandpass filter circuit is used to amplify the voltage signal and filter the voltage signal; the reference voltage generation circuit is used to raise the working reference level of the differential amplifier circuit and the bandpass filter circuit. When the present invention is applied, the characteristic current identification circuit is used to perform filtering processing, and the filtering effect is better, the signal distortion problem can be effectively solved, and the recognition success rate is higher.

Description

Technical Field

[0001] The present invention relates to the technical field of low-voltage power communication, and in particular to a characteristic current identification circuit and an identification method for a low-voltage topology module. Background Art

[0002] In the prior art, the low-voltage topology module uses an ordinary constant current transmission mode or a constant resistance transmission mode to transmit characteristic current, directly samples and calculates without filtering at the receiving end, and uses software to filter in the identification chip, but there is no filtering design in the hardware. In addition, the current low-voltage topology module has a low recognition success rate, cannot be recognized under complex working conditions, and has a high manufacturing cost. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a characteristic current identification circuit and identification method for a low-voltage topology module. When used, the characteristic current identification circuit performs filtering processing, has a better filtering effect, can effectively solve the signal distortion problem, and has a higher recognition success rate.

[0004] The purpose of the present invention is mainly achieved through the following technical solutions:

[0005] In the first aspect, the present application provides a characteristic current identification circuit of a low-voltage topology module, wherein the characteristic current identification circuit collects a characteristic current signal between the live and neutral lines through a current transformer, and the characteristic current identification circuit includes a differential amplifier circuit, a bandpass filter circuit and a reference voltage generation circuit; the differential amplifier circuit is used to input the characteristic current signal collected by the current transformer and convert the characteristic current signal into a voltage signal; the bandpass filter circuit is used to amplify the voltage signal and filter the voltage signal; the reference voltage generation circuit is used to raise the working reference level of the differential amplifier circuit and the bandpass filter circuit.

[0006] In a possible implementation, the differential amplifier circuit includes a second operational amplifier U3.1, a first capacitor C19, a second capacitor C15, a first resistor R15, a second resistor R23, a third resistor R13, a fourth resistor R11, a fifth resistor R16, a sixth resistor R24 ​​and a seventh resistor R29, the two ends of the first capacitor C19 are connected in parallel with a series circuit connecting the first resistor R15 and the second resistor R23, one end of the first resistor R15 and the second resistor R23 is grounded, the characteristic current signal is filtered by the first capacitor C19 and divided by the first resistor R15 and the second resistor R23, and then input into the second operational amplifier U3.1, the inverting input terminal and the output terminal of the second operational amplifier U3.1 are connected through the fourth resistor R11, and the The inverting input terminal of the second operational amplifier U3.1 is connected to the third resistor R13, and the other end of the third resistor R13 connected to the second operational amplifier U3.1 inputs the characteristic current signal. The non-inverting input terminal of the second operational amplifier U3.1 is connected to the fifth resistor R16, the sixth resistor R24 ​​and the seventh resistor R29, wherein the other end of the fifth resistor R16 connected to the second operational amplifier U3.1 inputs the characteristic current signal, the other end of the sixth resistor R24 ​​connected to the second operational amplifier U3.1 is grounded, and the other end of the seventh resistor R29 connected to the operational amplifier U3.1 is connected to the band-pass filter circuit; the positive power supply connection terminal of the second operational amplifier U3.1 is connected to the power supply and is grounded through the second capacitor C15, and the negative power supply connection terminal is grounded.

[0007] In a possible implementation, the bandpass filter circuit includes a third operational amplifier U3.2, an eighth resistor R17, a ninth resistor R30, a tenth resistor R25, an eleventh resistor R20, a third capacitor C17 and a fourth capacitor C18, the in-phase input terminal of the third operational amplifier U3.2 is connected to the in-phase input terminal of the second operational amplifier U3.1 through the ninth resistor R30 and the seventh resistor R29, the ninth resistor R30 and the seventh resistor R29 are connected in series, the inverting input terminal of the third operational amplifier U3.2 is connected to the output terminal of the second operational amplifier U3.1 through the fourth capacitor C18 and the eighth resistor R17, the fourth capacitor C 18 is connected in series with the eighth resistor R17, the inverting input terminal and the output terminal of the third operational amplifier U3.2 are connected through the fourth capacitor C18 and the third capacitor C17, the other end of the fourth capacitor C18 connected to the third operational amplifier U3.2 is connected to the eighth resistor R17, one end of the fourth capacitor C18 connected to the inverting input terminal of the third operational amplifier U3.2 is connected in parallel with the tenth resistor R25, one end of the third capacitor C17 connected to the output terminal of the third operational amplifier U3.2 is connected in parallel with the eleventh resistor R20, the tenth resistor R25 and the eleventh resistor R20 are connected in series, and the output terminal of the third operational amplifier U3.2 is connected with an RC filtering circuit.

[0008] In one possible implementation, the reference voltage generating circuit includes a first operational amplifier U4.2, the in-phase input terminal of the first operational amplifier U4.2 is connected to a twelfth resistor R44 and a thirteenth resistor R49, and is connected to a power supply through the twelfth resistor R44 and is grounded through the thirteenth resistor R49, the inverting input terminal and the output terminal of the first operational amplifier U4.2 are connected, the output terminal of the first operational amplifier U4.2 is connected to a fourteenth resistor R45 and a fourth capacitor C29, the first operational amplifier U4.2 is connected to the in-phase input terminal of the third operational amplifier U3.2 through the fourteenth resistor R45 and the ninth resistor R30, and the first operational amplifier U4.2 is grounded through the fourth capacitor C29.

[0009] In a second aspect, the present application also proposes a characteristic current identification method for a low voltage topology module, comprising the following steps:

[0010] Step 1: The signal sending end sends a voltage zero-crossing information collection instruction to the lower HPLC module of the signal receiving end through the upper HPLC module;

[0011] Step 2: The lower HPLC module at the signal receiving end receives the voltage zero-crossing point information collection instruction from the upper HPLC module at the signal sending end, collects its own voltage zero-crossing point information, and sends the voltage zero-crossing point information back to the signal sending end;

[0012] Step 3: The signal transmitting end calculates the phase information of the signal receiving end according to the voltage zero-crossing point information of the signal receiving end;

[0013] Step 4: The signal sending end sends a characteristic current trigger instruction to the signal receiving end;

[0014] Step 5: The signal receiving end sends a characteristic current signal after receiving the characteristic current trigger instruction sent by the signal sending end, and identifies the characteristic current signals sent by the remaining signal receiving ends based on the characteristic current identification circuit of a low-voltage topology module as described above.

[0015] In the prior art, in some cases where the lines are complex or special, due to the close proximity between the phases, crosstalk problems are prone to occur when identifying characteristic currents, resulting in identification errors and reducing the success rate of identification. For example, for the construction of a topological hierarchy, a node at a certain layer of phase A may receive a characteristic current signal from another node at another layer of other phases, thereby identifying the node at that layer of phase A as another node at another layer of phase A, resulting in the lack of a topological hierarchy. For example, the third-layer node of phase A recognizes the characteristic current signal of the fourth-layer node of phase B, thereby causing the original third-layer node of phase A to become the fourth-layer node of phase A, resulting in the lack of the fourth-layer node in the topological hierarchy of phase A. Since there is a certain difference in the zero-crossing time of the three-phase voltage within a cycle, the relationship between phases can be judged by the zero-crossing time of the voltage. In the present application, through the HPLC communication mode, the voltage zero-crossing information acquisition instruction is sent from the signal sending end to the lower HPLC module of each signal receiving end through the upper HPLC module. After receiving the voltage zero-crossing information acquisition instruction, the lower HPLC module of each signal receiving end collects its own voltage zero-crossing information and sends its own voltage zero-crossing information back to the signal sending end. The signal sending end calculates the phase of the signal receiving end according to the voltage zero-crossing information of the signal receiving end, thereby determining the phase of the signal receiving end. In the present application, before sending and identifying the characteristic current signal, the phase relationship is preferentially determined through the HPLC communication mode, thereby determining which phase each signal receiving end is in, and solving the problem of signal crosstalk and identification errors when performing characteristic current identification.

[0016] Furthermore, the step 1 is specifically as follows: the signal sending end sends a voltage zero-crossing information collection instruction to the lower-level HPLC module of the signal receiving end, and records the sending time t0 of sending the collection instruction, and the sending time t0 is configured as any voltage zero-crossing time of any known phase of the signal sending end.

[0017] Furthermore, the step 2 is specifically as follows:

[0018] Step 2.1: The lower HPLC module at the signal receiving end receives the voltage zero-crossing point information collection instruction sent from the signal sending end, and starts to collect its own voltage zero-crossing point information;

[0019] Step 2.2: When the signal receiving end collects the first voltage zero-crossing information since receiving the collection instruction, the first voltage zero-crossing time t1 is recorded;

[0020] Step 2.3: The signal receiving end sends the first voltage zero-crossing point information back to the signal receiving end through the lower HPLC module.

[0021] Furthermore, the step 3 is specifically as follows:

[0022] Step 3.1: After receiving the first voltage zero-crossing information from the signal receiving end, the signal sending end calculates the time difference between the first voltage zero-crossing time t1 collected by the signal receiving end and the first sending time t0, which is recorded as the first time difference :

[0023]

[0024] Step 3.2: Calculate the first time difference The remainder of the quotient with the voltage signal period T is recorded as the first remainder n:

[0025]

[0026] in, is the remainder function;

[0027] Step 3.3: The signal transmitting end determines the phase information of the signal receiving end based on the value of the first remainder n.

[0028] In summary, compared with the prior art, the present invention has the following beneficial effects: the present invention receives the voltage signal through a bandpass filter circuit and then filters it to remove unnecessary signals, so that the waveform of the voltage signal collected is smoother and the recognition success rate is higher; the present invention generates a voltage signal through a reference voltage generating circuit to raise the working reference level of the differential amplifier circuit and the bandpass filter circuit, so that the differential amplifier circuit and the bandpass filter circuit do not need to be additionally designed with a negative power supply, thereby saving manufacturing costs; the reference voltage generating circuit designed by the present invention increases the voltage value of the zero point of the sampling signal by raising the working reference level of the differential amplifier and the bandpass filter circuit, so that a negative signal can be easily simulated, thereby solving the problem of signal distortion obtained by sampling without designing a negative power supply; the present invention preferentially determines the phase relationship between each signal receiving end through an HPLC communication method, thereby solving the crosstalk problem that may occur during characteristic current identification and improving the success rate of signal identification. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0030] Figure 1 The schematic diagram of the differential amplifier circuit and the bandpass filter circuit according to the embodiment of the present invention;

[0031] Figure 2 is a schematic diagram of a reference voltage generating circuit according to an embodiment of the present invention;

[0032] Figure 3 is a schematic diagram of a characteristic current generating circuit according to an embodiment of the present invention;

[0033] Figure 4 for Figure 3 Circuit diagram of the control module;

[0034] Figure 5 for Figure 3 The circuit diagram of the full-bridge rectifier module;

[0035] Figure 6 for Figure 3 Circuit diagram of the medium voltage conversion module;

[0036] Figure 7 for Figure 3 The circuit schematic diagram of the characteristic current sending module;

[0037] Figure 8 is a flow chart of an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0039] Example:

[0040] A characteristic current identification circuit of a low-voltage topology module, wherein the characteristic current identification circuit collects a characteristic current signal between a live wire and a neutral wire through a current transformer, and comprises a differential amplifier circuit, a bandpass filter circuit and a reference voltage generation circuit; the differential amplifier circuit is used to input the characteristic current signal collected by the current transformer and convert the characteristic current signal into a voltage signal; the bandpass filter circuit is used to amplify the voltage signal and filter the voltage signal; the reference voltage generation circuit is used to raise the working reference level of the differential amplifier circuit and the bandpass filter circuit.

[0041] The present embodiment collects the characteristic current signal between the neutral and live wires through a characteristic current identification circuit, wherein the characteristic current identification circuit includes a differential amplifier circuit, a bandpass filter circuit and a reference voltage generation circuit. The characteristic current between the neutral and live wires is collected by a current transformer and then input into the differential amplifier circuit. The differential amplifier circuit converts the input AC signal into a voltage signal and outputs it to the bandpass filter circuit. The bandpass filter circuit receives the voltage signal and performs filtering processing on it to filter out unnecessary signals, so that the waveform of the voltage signal collected is more stable. At the same time, the present embodiment generates a voltage signal through a reference voltage generation circuit to raise the working reference level of the differential amplifier circuit and the bandpass filter circuit, so that the differential amplifier circuit and the bandpass filter circuit do not need to design an additional negative power supply, saving manufacturing costs. In addition, the reference voltage generation circuit designed in the present embodiment increases the voltage value of the zero point of the sampling signal by raising the working reference level of the differential amplifier and the bandpass filter circuit, so that a negative signal can be easily simulated, solving the problem of signal distortion obtained by sampling without designing a negative power supply.

[0042] In one possible implementation, Figure 1 As shown, the differential amplifier circuit includes a second operational amplifier U3.1, a first capacitor C19, a second capacitor C15, a first resistor R15, a second resistor R23, a third resistor R13, a fourth resistor R11, a fifth resistor R16, a sixth resistor R24 ​​and a seventh resistor R29, both ends of the first capacitor C19 are connected in parallel with a series circuit connecting the first resistor R15 and the second resistor R23, one end of the first resistor R15 and the second resistor R23 is connected to ground, the characteristic current signal is filtered by the first capacitor C19 and divided by the first resistor R15 and the second resistor R23 before being input into the second operational amplifier U3.1, the inverting input terminal and the output terminal of the second operational amplifier U3.1 are connected through the fourth resistor R11, and the second operational amplifier The inverting input terminal of the amplifier U3.1 is connected to the third resistor R13, and the other end of the third resistor R13 connected to the second operational amplifier U3.1 inputs the characteristic current signal. The non-inverting input terminal of the second operational amplifier U3.1 is connected to the fifth resistor R16, the sixth resistor R24 ​​and the seventh resistor R29, wherein the other end of the fifth resistor R16 connected to the second operational amplifier U3.1 inputs the characteristic current signal, the other end of the sixth resistor R24 ​​connected to the second operational amplifier U3.1 is grounded, and the other end of the seventh resistor R29 connected to the operational amplifier U3.1 is connected to a band-pass filter circuit; the positive power supply connection terminal of the second operational amplifier U3.1 is connected to the power supply and is grounded through the second capacitor C15, and the negative power supply connection terminal is grounded.

[0043] Specifically, in this embodiment, the characteristic current signal collected by the current transformer is input into the differential amplifier circuit after a preliminary filtering by the first capacitor C19, the first resistor R15 and the second resistor R23 convert the characteristic current signal into a voltage signal, and output by the second operational amplifier U3.1, wherein the third resistor R13 and the fourth resistor R11 act as voltage followers, so that the voltage signal output by the second operational amplifier U3.1 is the same as the original voltage signal, and the seventh resistor R29 is connected to the reference voltage generating circuit to increase the voltage at the in-phase input terminal of the second operational amplifier U3.1.

[0044] In one possible implementation, Figure 1 As shown, the band-pass filter circuit includes a third operational amplifier U3.2, an eighth resistor R17, a ninth resistor R30, a tenth resistor R25, an eleventh resistor R20, a third capacitor C17 and a fourth capacitor C18. The in-phase input terminal of the third operational amplifier U3.2 is connected to the in-phase input terminal of the second operational amplifier U3.1 through the ninth resistor R30 and the seventh resistor R29. The ninth resistor R30 and the seventh resistor R29 are connected in series. The inverting input terminal of the third operational amplifier U3.2 is connected to the output terminal of the second operational amplifier U3.1 through the fourth capacitor C18 and the eighth resistor R17. The fourth capacitor C18 and the seventh resistor R29 are connected in series. Eight resistors R17 are connected in series, the inverting input and output of the third operational amplifier U3.2 are connected through the fourth capacitor C18 and the third capacitor C17, the other end of the fourth capacitor C18 connected to the third operational amplifier U3.2 is connected to the eighth resistor R17, one end of the fourth capacitor C18 connected to the inverting input of the third operational amplifier U3.2 is connected in parallel with the tenth resistor R25, one end of the third capacitor C17 connected to the output of the third operational amplifier U3.2 is connected in parallel with the eleventh resistor R20, the tenth resistor R25 and the eleventh resistor R20 are connected in series, and the output of the third operational amplifier U3.2 is connected to an RC filter circuit.

[0045] In this embodiment, the bandpass filter circuit receives the voltage signal output by the differential amplifier circuit through the eighth resistor R17, and performs filtering processing through the third capacitor C17, the fourth capacitor C18, the tenth resistor R25 and the eleventh resistor R20, so that the output signal waveform is more stable, and the in-phase input terminal of the third operational amplifier U3.2 raises the working reference level through the reference voltage generation circuit. Specifically, the RC filter circuit includes the thirty-seventh resistor R31 and the fifteenth capacitor C22.

[0046] In one possible implementation, Figure 2As shown, the reference voltage generating circuit includes a first operational amplifier U4.2, the in-phase input terminal of the first operational amplifier U4.2 is connected to the twelfth resistor R44 and the thirteenth resistor R49, and is connected to the power supply through the twelfth resistor R44 and is grounded through the thirteenth resistor R49, the inverting input terminal and the output terminal of the first operational amplifier U4.2 are connected, the output terminal of the first operational amplifier U4.2 is connected to the fourteenth resistor R45 and the fourth capacitor C29, the first operational amplifier U4.2 is connected to the in-phase input terminal of the third operational amplifier U3.2 through the fourteenth resistor R45 and the ninth resistor R30, and the first operational amplifier U4.2 is grounded through the fourth capacitor C29.

[0047] In this embodiment, the power supply is input into the first operational amplifier U4.2 through the twelfth resistor R44 and the thirteenth resistor R49, and the inverting input terminal and the output terminal of the first operational amplifier U4.2 are connected, playing the role of voltage follower, thereby generating a voltage signal at the output terminal for raising the working reference level of the differential amplifier circuit and the bandpass filter circuit.

[0048] Based on this, this embodiment also proposes a characteristic current generating circuit for sending a characteristic current.

[0049] In one possible implementation, Figure 3 As shown, the characteristic current generating circuit includes a control module, a full-bridge rectifier module, a voltage conversion module and a characteristic current sending module. The control module is connected to the characteristic current sending module and is used to send a control signal to control the characteristic current sending module to generate a characteristic current. The full-bridge rectifier module is connected to the characteristic current sending module and the voltage conversion module and is used to power the characteristic current sending module and charge the voltage conversion module. The voltage conversion module is connected to the characteristic current sending module. When the power supply voltage of the full-bridge rectifier module is low, the voltage conversion module provides a constant voltage to the characteristic current sending module.

[0050] In one possible implementation, Figure 7As shown, the characteristic current sending module includes a first NPN transistor Q4, a first PNP transistor Q7, a first NMOS transistor Q3, a fifteenth resistor R57, a sixteenth resistor R66, a seventeenth resistor R71, an eighteenth resistor R62, a nineteenth resistor R61, a twentieth resistor R67, a twenty-first resistor R68, a twenty-second resistor R69, a fifth capacitor C30, a sixth capacitor C33, a seventh capacitor C34, an eighth capacitor C32, a first diode D6 and a first voltage zener diode D7; the emitter of the first NPN transistor Q4 and the first PNP transistor Q7 are connected. The collector of the first NPN transistor Q4 is connected to the output end of the control module through the sixteenth resistor R66, and the collector of the first NPN transistor Q4 is connected to the output end of the voltage conversion module, that is, the source of the second NMOS transistor Q5, through the fifteenth resistor R57; the fifth capacitor C30 is connected in parallel with the fifteenth resistor R57 and connected between the fifteenth resistor R57 and the power supply, and the other end of the fifth capacitor C30 connected to the fifteenth resistor R57 is grounded; the base of the first PNP transistor Q7 is connected to the output end of the control module, and the first PNP transistor The emitter of the transistor Q7 is connected to the output end of the control module through the seventeenth resistor R71; the nineteenth resistor R61 and the first diode D6 are connected in series to form a first series circuit, the nineteenth resistor R61 is connected to the anode of the first diode D6, the cathode of the first diode D6 is connected to the emitter of the first NPN transistor Q4, the sixth capacitor C33, the seventh capacitor C34, the twentieth resistor R67 and the first voltage regulator diode D7 are connected in parallel to form a first parallel circuit, the twenty-first resistor R68 and the twenty-second resistor R69 are connected in parallel to form a second parallel circuit, the eighth capacitor C3 2 is connected in series with the second parallel circuit to form a second series circuit, the second series circuit is connected in parallel with the first parallel circuit, the gate of the first NMOS tube Q3 is connected to the emitter of the first NPN triode Q4 through the eighteenth resistor R62, and the eighteenth resistor R62 is connected in parallel with the first series circuit, the two ends of the eighth capacitor C32 are respectively connected to the gate and source of the first NMOS tube Q3, and the gate of the first NMOS tube Q3 is connected to the other end of the second parallel circuit connected to the eighth capacitor C32, and the drain of the first NMOS tube Q3 is connected to the output end of the full-bridge rectifier module.

[0051] Specifically, in this embodiment, the full-bridge rectifier module receives an AC signal through terminal H2, and the AC signal is rectified into a DC signal through a full-bridge composed of four diodes. The DC signal is input into the characteristic current sending module and the voltage conversion module after passing through the varistor R53. More specifically, as Figure 5As shown, the full-bridge rectifier module includes a first current limiting resistor R50, a second current limiting resistor R51, a fuse F1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5 and a varistor R53. The first current limiting resistor R50 and the second current limiting resistor R51 are connected to a full-bridge circuit composed of the second diode D2, the third diode D3, the fourth diode D4 and the fifth diode D5. The first current limiting resistor R50 is connected to end 1 of the terminal H2, the second current limiting resistor R51 is connected to end 3 of the terminal H2 through the fuse F1, and the varistor R53 is connected in parallel with the full-bridge circuit.

[0052] In one possible implementation, Figure 4 As shown, the control module includes a control chip, a second NPN transistor Q2, a third NPN transistor Q6, a first PMOS tube Q1, a photocoupler U2, a twenty-third resistor R52, a twenty-fourth resistor R54, a twenty-fifth resistor R58, a twenty-sixth resistor R65, a twenty-seventh resistor R70, a twenty-eighth resistor R72, a twenty-ninth resistor R73, a ninth capacitor C31 and a tenth capacitor C35, and the photocoupler U2 includes a light emitting diode and a phototransistor; the base of the second NPN transistor Q2 is connected to the control chip through the twenty-fifth resistor R58, the emitter of the second NPN transistor Q2 is grounded, and the collector of the second NPN diode Q2 is connected to the gate of the first PMOS tube Q1; the two ends of the twenty-third resistor R52 are respectively connected to the source and drain of the first PMOS tube Q1, the two ends of the twenty-fourth resistor R54 are respectively connected to the source and gate of the first PMOS tube Q1, and the source of the first PMOS tube Q1 is connected to the electric The source of the first PMOS tube Q1 is connected to the anode of the light emitting diode; one end of the ninth capacitor C31 is connected to the anode of the light emitting diode, and the other end is grounded; the cathode of the light emitting diode is connected to the collector of the third NPN transistor Q6 through the twenty-sixth resistor R65, the collector of the phototransistor is connected to the collector of the first NPN transistor Q4, and the emitter of the phototransistor is connected to the base of the first PNP transistor Q7; the emitter of the third NPN transistor Q6 is grounded, and the base of the third NPN transistor Q6 is connected to the tenth capacitor C35, and the other end of the tenth capacitor C35 connected to the third NPN transistor Q6 is connected to the control chip through the twenty-seventh resistor R70, and the two ends of the twenty-ninth resistor R73 are respectively connected to the base and emitter of the third NPN transistor Q6; one end of the twenty-eighth resistor R72 is connected between the twenty-seventh resistor R70 and the tenth capacitor C35, and the other end thereof is connected to the emitter of the third NPN transistor Q6.

[0053] In one possible implementation, Figure 6As shown, the voltage conversion module includes a third series circuit, a fourth series circuit, a second NMOS tube Q5, a third parallel circuit and a fourth parallel circuit, the third series circuit includes a 30th resistor R55, a 31st resistor R59 and a 32nd resistor R63 in series, the fourth series circuit includes a 33rd resistor R56, a 34th resistor R60 and a 35th resistor R64 in series, the third parallel circuit includes an 11th capacitor C36, a 12th capacitor C37 and a 13th capacitor C38 in parallel, the fourth parallel circuit includes a 36th resistor R74, a 14th capacitor C39 and a second voltage zener diode D8 in parallel; the drain of the second NMOS tube Q5 is connected to the output end of the full-bridge rectifier module through the third series circuit, the gate is connected to the output end of the full-bridge rectifier circuit through the fourth series circuit, and the gate is grounded through the fourth parallel circuit, the source is grounded through the third parallel circuit, and the source is connected to the 15th resistor R57.

[0054] Specifically, the third series circuit is used for voltage division and current limiting. The current output by the full-bridge rectifier module passes through the second NMOS tube Q5 and obtains a constant voltage at the source, providing a control voltage for the characteristic current sending module and the phototransistor. When the power supply voltage of the full-bridge rectifier module is low, the fourteenth capacitor C39 discharges to provide a constant voltage for the gate of the second NMOS tube Q5, thereby controlling the on and off of the second NMOS tube Q5.

[0055] In this embodiment, the control chip sends a PWM wave to control the characteristic current sending module to generate a characteristic current. When PWM is a high-level signal, the characteristic current generating circuit generates a characteristic current. When PWM is a low-level signal, the characteristic current generating circuit stops generating a characteristic current. Specifically, when the PWM wave sent by the control chip is a high-level signal, the second NPN transistor Q2 is turned on, the third NPN transistor Q6 is turned on, and the first PMOS transistor Q1 is turned on, so that the photocoupler U2 is turned on. At this time, the first NPN transistor Q4 is turned on, the first PNP transistor Q7 is turned off, and the first NMOS transistor Q3 is turned on, so that the parallel twenty-first resistor R68 and the twenty-second resistor R69 consume electric energy to generate a characteristic current; when the PWM wave sent by the control chip is a low-level signal, the second NPN transistor Q2 is turned off, the third NPN transistor Q6 is turned off, and the first PMOS transistor Q1 is turned off, so that the photocoupler U2 is turned off. At this time, the first NPN transistor Q4 is turned off, the first PNP transistor Q7 is turned on, and the electric energy stored in the sixth capacitor C33 and the seventh capacitor C34 is released through the nineteenth resistor R61 and the first diode D6, so that the level of the gate of the first NMOS transistor Q3 is reduced, the first NMOS transistor Q3 is turned off, and the characteristic current stops being generated. In this embodiment, through the design of the first NPN transistor Q4 and the first PNP transistor Q7, with the first diode D6 and the nineteenth resistor R61, when the PWM signal is at a low level, a channel for quickly reducing the voltage is provided for the gate of the first NMOS tube Q3, so that the characteristic current waveform control is more accurate. It should be noted that UNT is a grounding symbol in the drawings of this embodiment, indicating grounding.

[0056] Based on the above characteristic current sending and identification circuit, such as Figure 8 As shown, this embodiment also proposes a characteristic current identification method for a low-voltage topology module, comprising the following steps:

[0057] Step 1: The signal sending end sends a voltage zero-crossing information collection instruction to the lower HPLC module of the signal receiving end through the upper HPLC module;

[0058] Step 2: The lower HPLC module at the signal receiving end receives the voltage zero-crossing information acquisition instruction from the upper HPLC module at the signal sending end, acquires its own voltage zero-crossing information, and sends the voltage zero-crossing information back to the signal sending end; the voltage zero-crossing information includes voltage zero-crossing time and voltage waveform information;

[0059] Step 3: The signal transmitting end calculates the phase information of the signal receiving end according to the voltage zero-crossing point information of the signal receiving end;

[0060] Step 4: The signal sending end sends a characteristic current trigger instruction to the signal receiving end;

[0061] Step 5: The signal receiving end sends a characteristic current signal after receiving the characteristic current trigger instruction sent by the signal sending end, and identifies the characteristic current signals sent by the remaining signal receiving ends based on the characteristic current identification circuit of a low-voltage topology module as described above.

[0062] In the prior art, in some cases where the lines are complex or special, since the phases are close to each other, crosstalk problems are prone to occur when identifying characteristic currents, resulting in identification errors and reducing the success rate of identification. For example, for the construction of a topological hierarchy, the construction of a certain layer of nodes of phase A may receive characteristic current signals of nodes of other phases, thereby identifying the layer node of phase A as a layer node of other phases. When the layer of phase A receives the characteristic current signal of its own correct node, it will also generate two layer nodes at the correct layer node of the layer of phase A, resulting in problems in the constructed topological hierarchy. For example, when constructing the third-layer node of phase A, the characteristic current signal of the third-layer node of phase B is identified, resulting in the original third-layer node of phase A being constructed as the third-layer node of phase B. At the same time, the characteristic current signal of the third-layer node of phase A is also identified, so that the third-layer node of phase A is also constructed here, resulting in two layer nodes appearing at this location in the topological hierarchy of phase A. Since there is a certain difference in the voltage zero-crossing time of the three-phase voltage within a cycle, the phase relationship can be judged by the voltage zero-crossing time. In the present application, through the HPLC communication mode, the signal sending end sends a voltage zero-crossing information collection instruction to the lower HPLC module of each signal receiving end through the upper HPLC module, and the lower HPLC module of each signal receiving end collects its own voltage zero-crossing information after receiving the voltage zero-crossing information collection instruction, and sends its own voltage zero-crossing information back to the signal sending end, and the signal sending end calculates the phase of the signal receiving end according to the voltage zero-crossing information of the signal receiving end, thereby determining the phase of the signal receiving end. In the present application, before sending and identifying the characteristic current signal, the phase relationship is preferentially determined by the HPLC communication method, and the device address corresponding to the signal receiving end is combined to determine which phase each signal receiving end is in. In this way, when the topology is constructed, it can be judged at the signal sending end. If a node at a certain layer of a phase receives a characteristic current signal of another phase, it can be known that the characteristic current signal does not belong to the phase according to the phase information, and then the characteristic current signal is excluded, thereby solving the problem of signal crosstalk between different phases causing identification errors when performing characteristic current identification. It should be noted that in the embodiment of the present application, the first voltage zero-crossing time is the voltage zero-crossing time in the same direction, that is, the voltage zero-crossing time is upward or downward, to prevent phase identification errors caused by different directions when the voltage crosses zero when calculating the phase. Optionally, in the embodiment of the present application, the signal sending end is a fusion terminal, and the signal receiving end is a low-voltage metering monitoring device (LTU for short), wherein the LTU includes a low-voltage topology module.

[0063] It should be noted that in the embodiment of the present application, when identifying characteristic current, the characteristic current identification circuit used can further improve the success rate of signal identification. The identification method described in the present application combines the phase relationship identification by HPLC communication and the characteristic current signal identification based on the improved characteristic current identification circuit, which can significantly improve the success rate of characteristic current signal identification and build a more accurate topological structure.

[0064] Furthermore, the step 1 is specifically as follows: the signal sending end sends a voltage zero-crossing information collection instruction to the lower-level HPLC module of the signal receiving end, and records the sending time t0 of sending the collection instruction, and the sending time t0 is configured as any voltage zero-crossing time of any known phase of the signal sending end.

[0065] Furthermore, the step 2 is specifically as follows:

[0066] Step 2.1: The lower HPLC module at the signal receiving end receives the voltage zero-crossing point information collection instruction sent from the signal sending end, and starts to collect its own voltage zero-crossing point information;

[0067] Step 2.2: When the signal receiving end collects the first voltage zero-crossing information since receiving the collection instruction, the first voltage zero-crossing time t1 is recorded;

[0068] Step 2.3: The signal receiving end sends the first voltage zero-crossing point information back to the signal receiving end through the lower HPLC module.

[0069] Furthermore, the step 3 is specifically as follows:

[0070] Step 3.1: After receiving the first voltage zero-crossing information from the signal receiving end, the signal sending end calculates the time difference between the first voltage zero-crossing time t1 collected by the signal receiving end and the first sending time t0, which is recorded as the first time difference :

[0071]

[0072] Step 3.2: Calculate the first time difference The remainder of the quotient with the voltage signal period T is recorded as the first remainder n:

[0073]

[0074] in, is the remainder function;

[0075] Step 3.3: The signal transmitting end determines the phase information of the signal receiving end based on the value of the first remainder n.

[0076] In the prior art, when performing phase identification, when the transmitting end sends the HPLC carrier signal to the receiving end, if the three phases are too close to each other, the carrier signal may be coupled to the adjacent phases, thereby affecting the phase identification accuracy of the adjacent phases. For this reason, in an embodiment of the present application, the signal transmitting end uses the voltage zero-crossing point information of the same known phase as the identification basis, and only sends the voltage zero-crossing point information collection instruction to the signal receiving end. The voltage zero-crossing point information of the known phase is stored at the signal transmitting end. Therefore, even if the carrier signal is transmitted to other phases during transmission, it belongs to the same instruction and will not interfere with the remaining phases. As for phase information identification, in an embodiment of the present application, the identification step is performed at the signal transmitting end, and only information collection is performed at the signal receiving end. Therefore, the signal receiving end does not need to receive the phase information of the signal transmitting end, which reduces the data processing amount of the signal receiving end and solves the crosstalk problem when transmitting different phase information to the signal receiving end.

[0077] It can be understood that, in the embodiment of the present application, if the phase of the signal receiving end is the same as the known phase confirmed by the signal sending end, then the first time difference is an integer multiple of the voltage signal period T, that is, the first remainder n=0; if the phase of the signal receiving end lags behind the known phase of the signal sending end , since the voltage zero-crossing time of the known phase is t0, and for the signal receiving end, in its voltage timing diagram, is the actual voltage zero-crossing time (the first voltage zero-crossing time after the signal sending end sends the acquisition instruction). Therefore, for the signal receiving end, the first remainder n= , the phase of the signal receiving end can be obtained according to the known phase and the first remainder n; if the phase of the signal receiving end lags behind the known phase of the signal sending end , since the voltage zero-crossing time of the known phase is t0, and for the signal receiving end, in its voltage timing diagram, is the actual voltage zero-crossing time (the first voltage zero-crossing time after the signal sending end sends the acquisition instruction). Therefore, for the signal receiving end, the first remainder n= , the phase of the signal receiving end can be obtained according to the known phase and the first remainder n. Taking the A phase of the signal transmitting end as the known phase, the first voltage zero crossing time collected is specified as the upward voltage zero crossing time. When performing phase identification, if the first remainder n=0, the signal receiving end is in phase A; if the first remainder n= , the signal receiving end is in phase B; if the first remainder n= , the signal receiving end is in phase C.

[0078] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A characteristic current identification circuit of a low voltage topology module, wherein the characteristic current identification circuit collects characteristic current signals between live and neutral lines through a current transformer, and is characterized in that: The characteristic current identification circuit includes a differential amplifier circuit, a bandpass filter circuit and a reference voltage generation circuit; the differential amplifier circuit is used to input the characteristic current signal collected by the current transformer and convert the characteristic current signal into a voltage signal; the bandpass filter circuit is used to amplify the voltage signal and filter the voltage signal; the reference voltage generation circuit is used to raise the working reference level of the differential amplifier circuit and the bandpass filter circuit; The differential amplifier circuit includes a second operational amplifier U3.1, a first capacitor C19, a second capacitor C15, a first resistor R15, a second resistor R23, a third resistor R13, a fourth resistor R11, a fifth resistor R16, a sixth resistor R24 ​​and a seventh resistor R29. The two ends of the first capacitor C19 are connected in parallel to a series circuit connecting the first resistor R15 and the second resistor R23. One end of the first resistor R15 and the second resistor R23 is connected to ground. The characteristic current signal is filtered by the first capacitor C19 and divided by the first resistor R15 and the second resistor R23 before being input into the second operational amplifier U3.

1. The inverting input end and the output end of the second operational amplifier U3.1 are connected through the fourth resistor R11. The second operational amplifier The inverting input terminal of the amplifier U3.1 is connected to the third resistor R13, and the other end of the third resistor R13 connected to the second operational amplifier U3.1 inputs the characteristic current signal. The non-inverting input terminal of the second operational amplifier U3.1 is connected to the fifth resistor R16, the sixth resistor R24 ​​and the seventh resistor R29, wherein the other end of the fifth resistor R16 connected to the second operational amplifier U3.1 inputs the characteristic current signal, the other end of the sixth resistor R24 ​​connected to the second operational amplifier U3.1 is grounded, and the other end of the seventh resistor R29 connected to the operational amplifier U3.1 is connected to the band-pass filter circuit; the positive power supply connection terminal of the second operational amplifier U3.1 is connected to the power supply and is grounded through the second capacitor C15, and the negative power supply connection terminal is grounded; The bandpass filter circuit includes a third operational amplifier U3.2, an eighth resistor R17, a ninth resistor R30, a tenth resistor R25, an eleventh resistor R20, a third capacitor C17 and a fourth capacitor C18. The in-phase input terminal of the third operational amplifier U3.2 is connected to the in-phase input terminal of the second operational amplifier U3.1 through the ninth resistor R30 and the seventh resistor R29. The ninth resistor R30 and the seventh resistor R29 are connected in series. The inverting input terminal of the third operational amplifier U3.2 is connected to the output terminal of the second operational amplifier U3.1 through the fourth capacitor C18 and the eighth resistor R17. The fourth capacitor C18 is connected to the third operational amplifier U3.

2. The other end of the third operational amplifier U3.2 is connected to the eighth resistor R17, the inverting input terminal and the output terminal of the third operational amplifier U3.2 are connected through the fourth capacitor C18 and the third capacitor C17, the fourth capacitor C18 and the third capacitor C17 are connected in series, one end of the fourth capacitor C18 connected to the inverting input terminal of the third operational amplifier U3.2 is connected in parallel with the tenth resistor R25, one end of the third capacitor C17 connected to the output terminal of the third operational amplifier U3.2 is connected in parallel with the eleventh resistor R20, the tenth resistor R25 and the eleventh resistor R20 are connected in series, and the output terminal of the third operational amplifier U3.2 is connected with an RC filter circuit; The reference voltage generating circuit includes a first operational amplifier U4.2, the in-phase input terminal of the first operational amplifier U4.2 is connected to a twelfth resistor R44 and a thirteenth resistor R49, and is connected to a power supply through the twelfth resistor R44 and is grounded through the thirteenth resistor R49, the inverting input terminal and the output terminal of the first operational amplifier U4.2 are connected, the output terminal of the first operational amplifier U4.2 is connected to a fourteenth resistor R45 and a fourth capacitor C29, the first operational amplifier U4.2 is connected to the in-phase input terminal of the third operational amplifier U3.2 through the fourteenth resistor R45 and the ninth resistor R30, and the first operational amplifier U4.2 is grounded through the fourth capacitor C29.

2. A method for identifying a characteristic current of a low-voltage topology module, using a characteristic current identification circuit of a low-voltage topology module as claimed in claim 1, characterized in that: The following steps are involved: Step 1: The signal sending end sends a voltage zero-crossing information collection instruction to the lower HPLC module of the signal receiving end through the upper HPLC module; Step 2: The lower HPLC module at the signal receiving end receives the voltage zero-crossing point information collection instruction from the upper HPLC module at the signal sending end, collects its own voltage zero-crossing point information, and sends the voltage zero-crossing point information back to the signal sending end; Step 3: The signal transmitting end calculates the phase information of the signal receiving end according to the voltage zero-crossing point information of the signal receiving end; Step 4: The signal sending end sends a characteristic current trigger instruction to the signal receiving end; Step 5: The signal receiving end sends a characteristic current signal after receiving the characteristic current trigger instruction sent by the signal sending end, and identifies the characteristic current signals sent by the remaining signal receiving ends based on the characteristic current identification circuit of the one low-voltage topology module.

3. The characteristic current identification method of a low voltage topology module according to claim 2 is characterized in that: The step 1 is specifically as follows: the signal sending end sends a voltage zero-crossing information collection instruction to the lower-level HPLC module of the signal receiving end, and records the sending time t0 of sending the collection instruction, wherein the sending time t0 is configured as any voltage zero-crossing time of any known phase of the signal sending end.

4. The characteristic current identification method of a low voltage topology module according to claim 3 is characterized in that: The step 2 is specifically as follows: Step 2.1: The lower HPLC module at the signal receiving end receives the voltage zero-crossing point information collection instruction sent from the signal sending end, and starts to collect its own voltage zero-crossing point information; Step 2.2: When the signal receiving end collects the first voltage zero-crossing information since receiving the collection instruction, the first voltage zero-crossing time t1 is recorded; Step 2.3: The signal receiving end sends the first voltage zero-crossing point information back to the signal receiving end through the lower HPLC module.

5. The characteristic current identification method of a low voltage topology module according to claim 4 is characterized in that: The step 3 is specifically as follows: Step 3.1: After receiving the first voltage zero-crossing information from the signal receiving end, the signal sending end calculates the time difference between the first voltage zero-crossing time t1 collected by the signal receiving end and the first sending time t0, which is recorded as the first time difference : ； Step 3.2: Calculate the first time difference The remainder of the quotient with the voltage signal period T is recorded as the first remainder n: ， in, is the remainder function; Step 3.3: The signal transmitting end determines the phase information of the signal receiving end based on the value of the first remainder n.

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