2.5-dimensional fan-out packaging structure for high-density optoelectronic integration and its preparation method

Abstract

The present invention provides a high-density optoelectronic integrated 2.5-dimensional fan-out packaging structure and a preparation method thereof. The 2.5-dimensional fan-out packaging structure includes a rewiring layer and an electrical chip and an optical chip arranged on the first main surface of the rewiring layer. The optical chip and the electrical chip with different process nodes are integrated through a back-end process, and the rewiring layer is used to realize signal connection between the optical chip and the electrical chip, thereby improving assembly compatibility, effectively shortening the transmission path of the optical chip and the electrical chip, and increasing efficiency, thereby realizing a low-cost, high-density optoelectronic co-packaging structure. At the same time, the electrical chip and the optical chip are both located on the same side of the substrate and the side away from the substrate is in flat contact with the heat dissipation cover plate, thereby improving the transmission rate and taking into account the heat dissipation requirements of the optoelectronic packaging structure.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor packaging and relates to a 2.5-dimensional fan-out packaging structure of optoelectronic integration and a preparation method thereof. Background Art

[0002] Silicon photonics devices are compatible with complementary metal oxide semiconductor (CMOS) processes and offer advantages such as minimal signal attenuation, low energy consumption, and high bandwidth. These factors directly impact I / O bandwidth and energy consumption. Therefore, the introduction of silicon photonics is essential to increase I / O bandwidth and minimize energy consumption. The integration of optical and electrical components is crucial, and the optimal combination and packaging of optical integrated circuits (PICs) and electrical integrated circuits (EICs) is a pressing issue.

[0003] Currently, optoelectronic modules are commonly integrated onto PCBs. For example, discrete electrical and optical chips are assembled onto the PCB via wire bonding or flip-chip bonding. However, as CMOS process nodes continue to shrink, further reducing the line width and spacing of PCB circuits becomes increasingly challenging. Furthermore, the process node of silicon photonics lags behind that of electronic chips. For example, the most advanced silicon photonics process nodes currently developed for monolithic integration are 45nm and 32nm, significantly lower than the sub-10nm process node for electronic chips. This mismatch in process node performance makes it unsuitable to utilize the same CMOS process for both the optical and electrical components. Existing processes also employ system-on-chip (SOC) packaging to improve chip design and packaging density. However, this SOC approach requires improvements to the optical chip in the front-end process to achieve a process node below 10nm for both the optical and electrical chips. This packaging approach undoubtedly increases process costs.

[0004] Therefore, a 2.5-dimensional fan-out packaging structure and a preparation method thereof are provided to meet the needs of high-density optoelectronic co-packaging while taking into account heat dissipation capabilities. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a high-density optoelectronic integrated 2.5-dimensional fan-out packaging structure and a preparation method thereof, which are used to solve the problems of high-density integration of photonic integrated circuits and electronic integrated circuits in the prior art, such as the difficulty in high-density integration and poor heat dissipation performance.

[0006] To achieve the above and other related objectives, the present invention provides a high-density optoelectronic integrated 2.5-dimensional fan-out packaging structure, comprising:

[0007] a substrate, wherein a carrier plate is provided on the substrate;

[0008] a redistribution layer disposed on the carrier and comprising a first main surface and a second main surface opposite to each other, the first main surface of the redistribution layer exposing the metal wiring layer, and the second main surface of the redistribution layer contacting the carrier;

[0009] an electrical chip bonded to the first main surface of the redistribution layer and electrically connected to the corresponding metal wiring layer via an electrical chip pad;

[0010] an optical fiber coupler, the optical fiber coupler being provided on the substrate and located near the carrier;

[0011] an optical chip having an optical chip bonding pad and a photosensitive area located on the same side, the optical chip being mounted on the rewiring layer and the optical fiber coupler in a state where the optical chip bonding pad is electrically connected to the corresponding metal wiring layer and the photosensitive area is optically coupled to the optical fiber coupler, and the optical chip is interconnected with the electrical chip via the rewiring layer;

[0012] an electrical connection component coupled between the first main surface of the re-distribution layer and the substrate, for achieving connection of electrical signals between the re-distribution layer and the substrate;

[0013] A heat dissipation cover plate is mounted above the substrate, covers at least the electrical chip and the optical chip, and is provided with an opening on a side adjacent to the optical chip so that one end of the optical fiber coupler passes through the opening and is optically coupled with the photosensitive area of ​​the optical chip.

[0014] Optionally, a bonding pad is provided on the first main surface of the rewiring layer, and the electrical chip and the optical chip are arranged side by side on the bonding pad and are electrically connected to the metal wiring layer through the bonding pad.

[0015] Optionally, the fiber coupler comprises a fiber body and a glass plate, and the height of the glass plate is adapted to the height of the carrier board and the redistribution layer.

[0016] Optionally, the electrical connection component includes a connection line and an electrical connector electrically connected to both ends of the connection line, and the electrical connection component is coupled between the bonding pad and the first main surface of the substrate.

[0017] Optionally, the electrical connection component includes a bridge chip and a connection bump in contact with the bridge chip, and the bridge chip is coupled between the bonding pad and the connection bump located on the first main surface of the substrate.

[0018] Optionally, the bridge chip is coupled between the bonding pad and the connection bump located on the first main surface of the substrate, and solder balls are further provided on a second main surface of the substrate opposite to the first main surface.

[0019] Optionally, the rewiring layer further includes an inorganic dielectric layer, and the rewiring layer has a line width and a line spacing as low as 0.4 μm.

[0020] Optionally, the electric chip pad is electrically connected to the metal wiring layer through bump welding, and the interface between the first main surface of the rewiring layer and the electric chip is filled with bottom filler.

[0021] Optionally, the electrical chip and the metal wiring layer are electrically connected via a hybrid bonding structure at an interface between the two.

[0022] The present invention also provides a method for preparing a high-density optoelectronic integrated 2.5-dimensional fan-out packaging structure, comprising the following steps:

[0023] Providing a carrier board, forming a redistribution layer on the carrier board, wherein the redistribution layer includes a first main surface and a second main surface opposite to each other, and the first main surface of the redistribution layer exposes the metal wiring layer;

[0024] bonding an electrical chip to the first major surface of the redistribution layer so that the electrical chip pads are electrically connected to the metal wiring layer;

[0025] Providing a substrate and an optical fiber coupler, and fixing the carrier plate and the optical fiber coupler on the substrate;

[0026] Providing an optical chip having an optical chip bonding pad and a photosensitive area located on the same side, bonding the optical chip to the first main surface of the rewiring layer so that the optical chip bonding pad is electrically connected to the metal wiring layer and the photosensitive area is optically coupled to the fiber coupler;

[0027] Disposing an electrical connection component on the substrate and the redistribution layer, wherein the electrical connection component is coupled between the first main surface of the redistribution layer and the substrate;

[0028] A heat dissipation cover is mounted above the substrate so that the heat dissipation cover at least covers the electrical chip, the optical chip and the electrical connection component. An opening is provided on a side of the heat dissipation cover adjacent to the optical chip to allow the optical fiber coupler to extend through the opening.

[0029] Optionally, a bonding pad is provided on the first main surface of the rewiring layer, and the optical chip is placed across the rewiring layer and the optical fiber coupler so that the optical chip is electrically connected to the metal wiring layer through the bonding pad, and the photosensitive area of ​​the optical chip is optically coupled to the optical fiber coupler.

[0030] Optionally, the method further includes: applying a thermally conductive adhesive material on surfaces of the electrical chip and the optical chip before attaching the heat dissipation cover plate, wherein the thermally conductive adhesive material contacts the heat dissipation cover plate.

[0031] Optionally, the step of providing an electrical connection component on the first main surface of the rewiring layer includes:

[0032] forming connection bumps on the first main surface of the substrate and disposing a bridge chip on the first main surface of the rewiring layer;

[0033] The bridge chip is coupled between the connection bump and the bonding pad to achieve connection of electrical signals between the rewiring layer and the substrate.

[0034] As described above, the 2.5-dimensional fan-out packaging structure of the present invention utilizes a fan-out packaging structure to integrate optical chips and electrical chips with different process nodes through a back-end process, and utilizes a rewiring layer to achieve signal connection between the optical chip and the electrical chip, thereby improving assembly compatibility, effectively shortening the transmission path of the optical chip and the electrical chip, and increasing efficiency; the connection of electrical signals between the rewiring layer and the substrate is achieved through electrical connection components, thereby realizing a low-cost, high-density optoelectronic co-packaging structure, while making the electrical integrated circuit package in smooth contact with the heat dissipation cover plate, and improving the heat dissipation effect of the optoelectronic packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Shown is a structural schematic diagram of a 2.5-dimensional fan-out packaging structure for high-density optoelectronic integration of the present invention.

[0036] Figure 2 Shown is a process flow chart for manufacturing a 2.5 fan-out packaging structure for high-density optoelectronic integration according to the present invention.

[0037] Figures 3 to 9 Shown are structural schematic diagrams presented at various stages of a method for preparing a 2.5-dimensional fan-out packaging structure for high-density optoelectronic integration according to an embodiment of the present invention.

[0038] Figure 10 It is a structural schematic diagram showing the method for preparing a 2.5-dimensional fan-out packaging structure of high-density optoelectronic integration according to an embodiment of the present invention after setting electrical connection components in step S5.

[0039] Figure 11 It is a schematic structural diagram showing another example of a 2.5-dimensional fan-out packaging structure for high-density optoelectronic integration according to the present invention.

[0040] Component number description:

[0041] 100 carrier board

[0042] 200 Rewiring Layer

[0043] 210 bonding pad

[0044] 211 bottom filler

[0045] 300 electrical chips

[0046] 301 chip pad

[0047] 400 optical chips

[0048] 401 Photosensitive Area

[0049] 402 optical chip pad

[0050] 410 Fiber Optic Coupler

[0051] 500 connecting wire

[0052] 501, 502 electrical connectors

[0053] 800 bridge chip

[0054] 802 connection bump

[0055] 600 heat dissipation cover

[0056] 601 Opening

[0057] 610 thermal conductive adhesive material

[0058] 700 substrate

[0059] 701 solder balls

[0060] 702 substrate pad

[0061] Steps S110 to S160 DETAILED DESCRIPTION

[0062] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0063] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0064] The terms "coupled" and "connected" and their derivatives may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended to be synonymous with each other. On the contrary, in certain embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect physical, optical, or electrical contact with each other (with other intermediate elements between them), and / or that two or more elements cooperate or interact with each other (e.g., in a causal relationship).

[0065] For ease of description, spatial relational terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers. Among them, when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or indirectly connected to the other element.

[0066] The phrases "between..." and "a plurality of" may be used herein to indicate an inclusive value, and the phrases "a plurality of" and "a plurality of" may be used to indicate two or more, unless otherwise specifically limited. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features.

[0067] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0068] like Figure 1As shown, this embodiment provides a 2.5D fan-out packaging structure for high-density optoelectronic integration. Using the fan-out packaging structure, optical chips and electrical chips with different process nodes can be integrated through back-end processes. A redistribution layer is used to achieve signal connection between the optical and electrical chips, improving assembly compatibility, effectively shortening the transmission path of the optical and electrical chips, and increasing efficiency. This allows for a low-cost, high-density optoelectronic co-packaging structure. At the same time, the electrical integrated circuit package is in smooth contact with the heat dissipation cover, taking into account the heat dissipation requirements of the optoelectronic packaging structure.

[0069] In addition, a rewiring layer is formed through the Damascus process, increasing the density of the I / O terminals, enabling high-density integrated packaging of optical and electrical chips. Signal transmission between the rewiring layer and the substrate is achieved by setting electrical connection components in subsequent processes, thereby optimizing the layout of high-density integration.

[0070] Afterwards, the attached Figure 2 and Figures 3 to 11 The process steps for making a 2.5-dimensional fan-out packaging structure for high-density optoelectronic integration are described in detail.

[0071] First, see Figure 3 , perform step S1, provide a carrier 100, and form a redistribution layer 200 on the carrier 100, wherein the redistribution layer 200 includes a first main surface and a second main surface relative to each other, and a metal wiring layer (not shown) is exposed on the first main surface of the redistribution layer 200.

[0072] Specifically, the carrier 100 may include one of a glass carrier and a silicon-based carrier. At step S1, the step of forming the rewiring layer 200 by the Damascene process includes: forming an inorganic dielectric layer (not shown) on the carrier 100 by chemical vapor deposition, physical vapor deposition or other suitable processes; photolithographically defining a through-hole pattern on the surface of the inorganic dielectric layer, and performing dry etching based on the windows defined in the through-hole pattern to form through-holes in the inorganic dielectric layer; and filling the through-holes with a metal layer to form a metal wiring layer. The rewiring layer 200 is formed by the Damascene process. The rewiring layer 200 has a line width and line spacing as low as 0.4 μm, which reduces the line spacing between metal wirings. The rewiring layer 200 enables horizontal interconnection of electrical chips and optical chips of different process nodes, improves assembly compatibility, increases I / O port density, and effectively shortens the transmission path of optical chips and electrical chips. In this embodiment, the dry etching process includes but is not limited to, for example, reactive ion etching (RIE), ion beam etching, and plasma etching.

[0073] It should be noted that multiple inorganic dielectric layers and metal wiring layers can be stacked as needed, and adjacent metal wiring layers can be electrically interconnected by forming conductive plugs in the through holes of the inorganic dielectric layer, which is not limited to this embodiment.

[0074] As an example, a metal layer is formed on the carrier 100 by combining one or more methods including but not limited to sputtering, electroplating, and chemical plating, and the metal layer is patterned to form a metal wiring layer. The material of the metal wiring layer includes but is not limited to a combination of one or more metals such as gold, silver, copper, and aluminum; preferably, the metal wiring layer is selected to be a copper layer.

[0075] As an example, before forming the inorganic dielectric layer above the carrier 100 , an etch stop layer (not shown) is further formed on the surface of the carrier 100 .

[0076] like Figure 3 As shown, step S1 also includes planarizing the structure obtained after filling the metal layer, removing the metal material located on the surface of the inorganic dielectric layer; forming a bonding pad 210 on the first main surface of the rewiring layer 200, and the bonding pad 210 is in contact with the exposed metal wiring layer.

[0077] In other examples, the rewiring layer 200 further includes an organic dielectric layer, and the rewiring layer 200 has a line width and line spacing as low as 2 μm, wherein the material of the organic dielectric layer includes but is not limited to a combination of one or more of epoxy resin, silicone, PI, PBO and BCB.

[0078] Next, continue reading Figure 4 , executing step S2, bonding the electrical chip 300 onto the rewiring layer 200 so that the electrical chip 300 is electrically connected to the metal wiring layer.

[0079] Specifically, the electrical chip pads 301 are bonded correspondingly to the bonding pads 210 on the first main surface of the redistribution layer 200 to electrically connect the electrical chip 300 to the metal wiring layer exposed on the first main surface of the redistribution layer 200 .

[0080] As an example, the electric chip 300 can be joined to the bonding pad 210 on the first main surface of the rewiring layer 200 by bump welding, so that the electric chip 300 is electrically connected to the metal wiring layer. The bump welding includes one of a flip-chip bonding process and a thermocompression bonding process.

[0081] See also Figure 5Step S2 further includes: after bonding the electrical chip pads 301 to the bonding pads 210 on the first main surface of the redistribution layer 200, forming an underfill 211 at the bonding interface between the electrical chip 300 and the first main surface of the redistribution layer 200. The underfill 211 can protect the connection between the electrical chip 300 and the bonding pads 210 from corrosion or damage, and can also improve the bonding performance between the electrical chip 300 and the bonding pads 210, thereby increasing the mechanical strength. The material of the underfill 211 can be selected as needed, and any insulating material is sufficient, and is not excessively limited herein.

[0082] As an example, the first main surface of the rewiring layer 200 is also formed with a first passivation layer (not shown), and the bonding pad 210 is embedded in the first passivation layer (not shown), and correspondingly, the electrical chip pad 301 is formed to be embedded in a second passivation layer (not shown). By bonding the bonding pad 210 to the electrical chip pad 301, a hybrid bonding structure is formed at the interface between the first main surface of the rewiring layer 200 and the electrical chip 300. Since hybrid bonding combines metal-metal bonding and dielectric-dielectric bonding, while obtaining vertical metal interconnection, the auxiliary effect of dielectric bonding is used to enhance the physical and mechanical properties between the rewiring layer 200 and the chip, thereby improving the comprehensive performance of the 2.5-dimensional packaging structure. In detail, hybrid bonding technology is different from traditional bump welding technology. Hybrid bonding technology does not have protruding bumps, and the surface of the dielectric layer is very smooth. By attaching two chips together at room temperature, raising the temperature and annealing them, the copper expands and firmly bonds together, forming an electrical connection with high current carrying capacity and low interconnect length, reducing power consumption per interconnect channel and achieving low time delay. In addition to the metal bonding, the dielectric layers are also bonded together, leaving no gaps between the dielectric layers and eliminating the need for filler glue, resulting in better heat dissipation and bonding strength. In this embodiment, the diagram shows two electrical chips, but depending on the requirements of the actual functional system, the number of electrical chips 300 can be one, three, or more. By forming a hybrid bonding structure between the electrical chip 300 and the optical chip 400 in the subsequent process and the first main surface of the rewiring layer 200, a more complete functional system or multifunctional system is achieved, with high flexibility and broad compatibility.

[0083] Next, see Figure 6 , executing step S3 , providing a substrate 700 and an optical fiber coupler 410 , and fixing the carrier 100 and the optical fiber coupler 410 on the substrate 700 .

[0084] Specifically, the substrate 700 may include a glass substrate, a ceramic substrate, a polymer substrate, or a similar non-metallic substrate, and may be circular, square, or any other desired shape. The size of the substrate 700 may be selected as desired and is not particularly limited herein.

[0085] As an example, refer to Figure 6 、 Figure 9 As shown, the carrier 100 is fixed to the first main surface of the substrate. The substrate 700 also includes: solder balls 701, which are arranged on the second main surface of the substrate 700 opposite the first main surface, that is, the surface facing away from the rewiring layer 200, and substrate pads 702, which are arranged on the first main surface of the substrate 700. The solder balls 701 of the substrate 700 are electrically connected to the substrate pads 702 located on the first main surface. It should be noted that although the external interconnection of the package structure is achieved based on solder balls, the present invention also covers metal bumps, solder bumps, and other methods of achieving external interconnection. Preferably, the fiber coupler 410 and the corresponding bonding pads 210 on the carrier 100 that are electrically connected to the optical chip are arranged on the substrate 700 adjacent to each other, so as to facilitate the mounting of the optical chip on the fiber coupler 410 and the carrier 100.

[0086] As an example, the fiber coupler 410 comprises an optical fiber body and a glass plate 100b. The height of the glass plate 100b matches the height of the carrier board 100 and the rewiring layer 200. The fiber coupler 410 uses its glass plate 100b to elevate the optical fiber body, thereby facilitating optical coupling between the optical fiber body of the fiber coupler 410 and the subsequently mounted optical chip. In this embodiment, the optical fiber body of the fiber coupler 410 and the optical chip are optically coupled via either end-face coupling or grating coupling. In this embodiment, the fiber coupler 410 is preferably a single-mode optical fiber, which has a relatively high bandwidth and transmission rate.

[0087] Next, see Figure 7 , execute step S4, provide an optical chip 400, the optical chip 400 has an optical chip pad 402 and a photosensitive area 401 located on the same side, bond the optical chip 400 to the first main surface of the rewiring layer 200 so that the optical chip pad 402 is electrically connected to the metal wiring layer, and at the same time, the photosensitive area 401 is optically coupled with the optical fiber coupler 410, thereby realizing horizontal interconnection between the optical chip and the electrical chip.

[0088] Specifically, an optical chip 400 is provided, comprising a photosensitive region 401. The optical chip 400 is horizontally positioned between the rewiring layer 200 and the fiber coupler 410, and the photosensitive region 401 of the optical chip is optically coupled to the fiber coupler 410. The optical fiber body is elevated by the glass plate 100b of the fiber coupler 410, allowing the optical chip 400 to be stably bonded to the first principal surface of the rewiring layer 200. This improves the welding strength of the bonding interface and facilitates the alignment of the photosensitive region 401 of the optical chip with the fiber coupler 410 to achieve optical coupling. Because the rewiring layer 200, formed using the Damascene process, has a line width and line spacing as low as 0.4 μm, and the electrical chip 300 and the optical chip 400 are both located on the same side of the rewiring layer 200 and the carrier 100, the signal transmission rate is increased, while also enhancing heat dissipation.

[0089] As an example, the specific type of the optical chip 400 can be selected according to needs. The optical chip 400 can be a chip with a larger process node, such as an optical chip with a 45nm or 32nm process.

[0090] As an example, multiple optical chips 400 are bonded to the bonding pads 210, and correspondingly, multiple optical fiber couplers 410 are arranged on the substrate. The photosensitive areas 401 of the optical chips are staggered and adjacent to the corresponding bonding pads 210 and are in contact with the corresponding optical fiber couplers 410.

[0091] See also Figures 7 and 8 , executing step S5: disposing an electrical connection component on the re-distribution layer 200 and the substrate 700 , wherein the electrical connection component is coupled between the first main surface of the re-distribution layer 200 and the substrate 700 .

[0092] like Figure 7 As shown, the electrical connection component includes a connecting wire 500 and electrical connectors 501 and 502 electrically connected to the two ends of the connecting wire 500. The electrical connection component is coupled between the bonding pad 210 and the first main surface of the substrate 700 through the connecting wire 500, the electrical connectors 501 and 502. The electrical signal of the redistribution layer 200 is transmitted and electrically led to the solder balls 701 on the second main surface of the substrate 700 through the electrical connector 501, the connecting wire 500 and the electrical connector 502 of the electrical connection component in sequence, facilitating subsequent electrical lead-out. The electrical connectors 501 and 502 can be plugged into the connecting wire 500, and the patch components include passive devices. The connecting wire 500 has a plurality of connecting wires, each of which is connected between a corresponding terminal of the electrical connector 501 and a corresponding terminal of the electrical connector 502.

[0093] As an example, Figure 10As shown, the step of setting the electrical connection component on the substrate 700 includes: forming a connection bump 802 on the first main surface of the substrate, bonding a bridge chip 800 on the first main surface of the rewiring layer 200; coupling the bridge chip 800 between the connection bump 802 and the bonding pad 210 to achieve the connection of electrical signals between the rewiring layer 200 and the substrate 700, wherein the connection bump 801 is, for example, a solder ball prepared by a reflow process, but is not limited thereto. Figure 10 As shown, due to the use of the bridge chip 800 to connect the electrical signals between the rewiring layer 200 and the substrate 700, combined with the connecting bump 802, the bridge chip 800 can be evenly coupled to the substrate 700 and the first main surface of the rewiring layer 200, ensuring the formation of good conductive contact, while improving the heat conduction and heat dissipation capabilities, as well as the mechanical strength of the packaging structure. The height of the connecting bump 802 can be adjusted based on the height difference between the substrate 700 and the top surface of the rewiring layer 200, and is not specifically limited here.

[0094] As an example, the connecting bump 802 may include or be selected from one of a solder bump and a metal bump.

[0095] As an example, the material of the metal bump may include one or a combination of copper and nickel, and the material of the solder bump may include one or a combination of copper, nickel, gold, tin and silver.

[0096] Next, see Figure 9 and Figure 11 , executing step S6, placing a heat dissipation cover plate 600 above the substrate 700 so that the heat dissipation cover plate 600 at least covers the electrical chip 300, the optical chip 400, and the electrical connection components. The heat dissipation cover plate 600 is provided with an opening 601 on a side adjacent to the optical chip 400 to allow the optical fiber coupler 410 to extend through the opening 601.

[0097] Specifically, a heat dissipation cover plate 600 is mounted above the substrate 700, and the heat dissipation cover plate 600 at least covers the electrical chip 300 and the optical chip 400. The heat dissipation cover plate 600 is in direct or indirect contact with the electrical chip 300 and the optical chip 400, respectively, to dissipate the heat generated by the electrical chip 300 during operation and reduce the impact of temperature on the electrical chip 300 and the optical chip 400. An opening 601 is provided on one side of the heat dissipation cover plate 600 adjacent to the optical chip so that the end of the optical fiber away from the optical chip passes through the opening 601 and is exposed.

[0098] As an example, the heat dissipation cover plate 120 may be made of aluminum, iron, copper or other materials.

[0099] like Figure 9 As shown, step S6 also includes: before attaching the heat dissipation cover plate 600, applying a thermal conductive adhesive material 610 on the surface of the electric chip 300 and the optical chip 400, the thermal conductive adhesive material 610 is in contact with the heat dissipation cover plate 600, so that the heat dissipation cover plate 120 and the electric chip 300 and the optical chip 400 are in indirect contact and heat conduction through the thermal conductive adhesive material 610 therebetween, that is, the electric chip pad 301 of the electric chip and the optical chip pad 402 of the optical chip are set on the re On the same side of the wiring layer 200, the rewiring layer 200 has an improved interconnection density, which is beneficial to the high-density integrated layout of the electrical chip 300, the optical chip 400 and other components, effectively shortening the transmission path between the electrical chip 300 and the optical chip 400, and the thermally conductive adhesive material 610 can compensate for the height difference between the electrical chip 300 and the optical chip 400, which is beneficial to the subsequent heat dissipation cover 120 and the electrical chip 300 and the optical chip 400 for better thermal contact and heat dissipation effect.

[0100] As an example, an adhesive material (not numbered) is further provided between the heat dissipation cover plate 600 and the base plate 700. Specifically, the heat dissipation cover plate 600 is bonded to the base plate 700 at a position where the heat dissipation cover plate 600 is supported by the adhesive material (not numbered) to further secure the heat dissipation cover plate 600.

[0101] See Figure 1 and Figure 11, this embodiment also provides a 2.5-dimensional fan-out packaging structure, the 2.5-dimensional fan-out packaging structure includes a substrate 700, a rewiring layer 200, an electrical chip 300, an optical fiber coupler 410, an optical chip 400, an electrical connection component and a heat dissipation cover 600, the substrate 700 is provided with a carrier 100; the rewiring layer 200 is formed on the carrier 100 and includes a first main surface and a second main surface opposite to each other, the first main surface of the rewiring layer 200 exposes a metal wiring layer, and the second main surface of the rewiring layer 200 is in contact with the carrier 100; the electrical chip 300 is bonded to the first main surface of the rewiring layer 200 and is electrically connected to the corresponding metal wiring layer through an electrical chip pad 301; the optical fiber coupler 410 is provided on the substrate 700 and is located near the carrier 100; the optical chip 400 has an optical chip pad 402 and a photosensitive area 40 located on the same side. 1. The optical chip 400 is mounted on the rewiring layer 200 and the optical fiber coupler 410 in a state where the optical chip pad 402 is electrically connected to the corresponding metal wiring layer and the photosensitive area 401 is optically coupled to the optical fiber coupler 410. The optical chip 400 is interconnected with the electrical chip 300 through the rewiring layer 200; the electrical connection component is coupled between the first main surface of the rewiring layer 200 and the substrate 700 to achieve connection of electrical signals between the rewiring layer 200 and the substrate 700; the heat dissipation cover 600 is mounted above the substrate 700, and the heat dissipation cover 600 at least covers the electrical chip 300, the optical chip 400 and the electrical connection component, and an opening 601 is provided on a side adjacent to the optical chip 400 to allow the optical fiber coupler 410 to pass through the opening 601 and optically couple with the photosensitive area 401 of the optical chip.

[0102] Return to see Figure 1 A bonding pad 210 is provided on the first main surface of the rewiring layer 200, and the electrical chip 300 and the optical chip 400 are arranged side by side on the bonding pad 210 and are electrically connected to the metal wiring layer 200 through the bonding pad 210. The electrical chip 300 and the optical chip 400 are interconnected through the rewiring layer 200, which can realize the transmission of electrical signals between the electrical chip 300 and the optical chip 400 of different process nodes, and can effectively shorten the transmission path of the optical chip 300 and the electrical chip 400, while taking into account cost-effectiveness and achieving high-density integration.

[0103] As an example, the fiber coupler 410 includes a fiber body and a glass plate 100 b . The fiber coupler 410 uses the glass plate 100 b to elevate the fiber body, thereby facilitating optical coupling between the fiber body of the fiber coupler 410 and the optical chip 400 .

[0104] As an example, the carrier 100 includes one of a glass carrier and a silicon-based carrier.

[0105] As an example, the rewiring layer 200 includes a metal wiring layer and an inorganic dielectric layer, and the rewiring layer 200 has a line width and line spacing as low as 0.4 μm, wherein the material of the inorganic dielectric layer includes but is not limited to phosphosilicate glass, and the material of the metal wiring layer includes but is not limited to a combination of one or more metals such as gold, silver, copper, and aluminum; preferably, the metal wiring layer is selected as a copper layer.

[0106] As an example, the rewiring layer 200 includes a metal wiring layer and an organic dielectric layer, and the rewiring layer 200 has a line width and line spacing as low as 2 μm, wherein the material of the organic dielectric layer includes but is not limited to a combination of one or more of epoxy resin, silicone, PI, PBO and BCB.

[0107] As an example, Figure 1 As shown, the electrical connection component includes a connecting wire 500 and electrical connectors 501 and 502 electrically connected to both ends of the connecting wire 500, the electrical connector includes a passive component, and the electrical connection component is coupled between the bonding pad 210 and the first main surface of the substrate 700.

[0108] As another example, the electrical connection component includes a bridge chip 800 and a connection bump 802 in contact with the bridge chip 800, wherein the bridge chip 800 is coupled between the bonding pad 210 and the connection bump 802 located on the first main surface of the substrate 700. Figure 11 As shown, the bridge chip 800 contacts the bonding pad 210 and is disposed to protrude from the end surface of the carrier 100 , and is electrically connected to the substrate 700 via a connecting bump 802 .

[0109] As an example, the electric chip pad 301 is electrically connected to the metal wiring layer of the redistribution layer 200 through bump welding; preferably, bottom filler 211 is filled between the first main surface of the redistribution layer 200 and the electric chip.

[0110] As an example, the electrical chip 400 and the metal wiring layer exposed on the first main surface of the rewiring layer 200 are electrically connected via a hybrid bonding structure at the interface between the two to achieve connection of electrical signals.

[0111] As an example, a thermally conductive adhesive material 610 is also included. The thermally conductive adhesive material 610 is applied to the surface of the electric chip and the optical chip and makes the heat dissipation cover plate indirectly contact with the electric chip 300 and the optical chip 400, and heat is conducted through the indirect contact of the thermally conductive adhesive material 610.

[0112] As an example, an adhesive material (not numbered) is further provided between the heat dissipation cover plate 600 and the base plate 700. Specifically, the heat dissipation cover plate 600 is bonded to the base plate 700 at a position where the heat dissipation cover plate 600 is supported by the adhesive material (not numbered) to further secure the heat dissipation cover plate 600.

[0113] As an example, the substrate 700 also includes solder balls 701, which are arranged on the second main surface opposite to the first main surface of the substrate 700, that is, the side of the substrate 700 facing away from the rewiring layer 200, and the solder balls 701 are electrically connected to the substrate pads 702 located on the first main surface.

[0114] In summary, the high-density optoelectronic integrated 2.5-dimensional fan-out packaging structure and its preparation method of the present invention utilize a rewiring layer to achieve signal connection between the optical chip and the electrical chip, thereby improving assembly compatibility, effectively shortening the transmission path of the optical chip and the electrical chip, and increasing efficiency; the electrical signal connection between the rewiring layer and the substrate is achieved through electrical connection components, thereby realizing a low-cost, high-density optoelectronic co-packaging structure, while making the electrical integrated circuit package in smooth contact with the heat dissipation cover plate, and improving the heat dissipation effect of the optoelectronic packaging structure.

[0115] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A 2.5-dimensional fan-out packaging structure for high-density optoelectronic integration, characterized in that: include: a substrate, wherein a carrier plate is provided on the substrate; a redistribution layer disposed on the carrier and comprising a first main surface and a second main surface opposite to each other, the first main surface of the redistribution layer exposing the metal wiring layer, and the second main surface of the redistribution layer contacting the carrier; an electrical chip bonded to the first main surface of the redistribution layer and electrically connected to the corresponding metal wiring layer via an electrical chip pad; an optical fiber coupler, the optical fiber coupler being provided on the substrate and located near the carrier; an optical chip having an optical chip bonding pad and a photosensitive area located on the same side, the optical chip being mounted on the rewiring layer and the optical fiber coupler in a state where the optical chip bonding pad is electrically connected to the corresponding metal wiring layer and the photosensitive area is optically coupled to the optical fiber coupler, and the optical chip is interconnected with the electrical chip via the rewiring layer; an electrical connection component coupled between the first main surface of the re-distribution layer and the substrate, for achieving connection of electrical signals between the re-distribution layer and the substrate; a heat dissipation cover plate, the heat dissipation cover plate being mounted above the substrate, the heat dissipation cover plate at least covering the electrical chip and the optical chip, and having an opening disposed on a side adjacent to the optical chip so that one end of the optical fiber coupler passes through the opening and optically couples with the photosensitive area of ​​the optical chip; A bonding pad is provided on the first main surface of the rewiring layer, the electrical chip and the optical chip are arranged side by side on the bonding pad and are electrically connected to the metal wiring layer through the bonding pad; The optical fiber coupler comprises an optical fiber body and a glass plate, wherein the height of the glass plate is adapted to the height of the carrier board and the redistribution layer.

2. The 2.5D fan-out packaging structure according to claim 1, wherein: The electrical connection component includes a connection line and an electrical connector electrically connected to both ends of the connection line. The electrical connection component is coupled between the bonding pad and the first main surface of the substrate.

3. The 2.5D fan-out packaging structure according to claim 1, wherein: The electrical connection component includes a bridge chip and a connection bump in contact with the bridge chip, and the bridge chip is coupled between the bonding pad and the connection bump located on the first main surface of the substrate.

4. The 2.5D fan-out packaging structure according to claim 3, wherein: The bridge chip is coupled between the bonding pad and the connection bump located on the first main surface of the substrate. Solder balls are further arranged on the second main surface of the substrate opposite to the first main surface.

5. The 2.5D fan-out packaging structure according to claim 1, wherein: The rewiring layer further includes an inorganic dielectric layer. The rewiring layer has a line width and a line spacing as low as 0.4 μm.

6. The 2.5D fan-out packaging structure according to claim 1, wherein: The electric chip pad is electrically connected to the metal wiring layer through bump welding, and the interface between the first main surface of the rewiring layer and the electric chip is filled with bottom filler.

7. The 2.5D fan-out packaging structure according to claim 1, wherein: The electric chip and the metal wiring layer are electrically connected via a hybrid bonding structure at the interface between the two.

8. A method for preparing a 2.5-dimensional fan-out packaging structure for high-density optoelectronic integration, characterized in that: The following steps are involved: Providing a carrier board, forming a redistribution layer on the carrier board, wherein the redistribution layer includes a first main surface and a second main surface opposite to each other, and the first main surface of the redistribution layer exposes the metal wiring layer; bonding an electrical chip to the first major surface of the redistribution layer so that the electrical chip pads are electrically connected to the metal wiring layer; Providing a substrate and an optical fiber coupler, and fixing the carrier plate and the optical fiber coupler on the substrate; Providing an optical chip having an optical chip bonding pad and a photosensitive area located on the same side, bonding the optical chip to the first main surface of the rewiring layer so that the optical chip bonding pad is electrically connected to the metal wiring layer and the photosensitive area is optically coupled to the fiber coupler; Disposing an electrical connection component on the substrate and the redistribution layer, wherein the electrical connection component is coupled between the first main surface of the redistribution layer and the substrate; A heat dissipation cover is mounted above the substrate so that the heat dissipation cover at least covers the electrical chip, the optical chip and the electrical connection component. An opening is provided on a side of the heat dissipation cover adjacent to the optical chip to allow the optical fiber coupler to extend through the opening.

9. The preparation method according to claim 8, characterized in that: A bonding pad is provided on the first main surface of the rewiring layer, and the optical chip is placed across the rewiring layer and the optical fiber coupler so that the optical chip is electrically connected to the metal wiring layer through the bonding pad, and the photosensitive area of ​​the optical chip is optically coupled to the optical fiber coupler.

10. The preparation method according to claim 8, characterized in that Also includes: Before attaching the heat dissipation cover plate, a heat conductive adhesive material is applied on the surfaces of the electric chip and the optical chip, and the heat conductive adhesive material is in contact with the heat dissipation cover plate.

11. The preparation method according to claim 9, characterized in that The step of providing an electrical connection component on the first main surface of the rewiring layer comprises: forming connection bumps on the first main surface of the substrate and disposing a bridge chip on the first main surface of the rewiring layer; The bridge chip is coupled between the connection bump and the bonding pad to achieve connection of electrical signals between the rewiring layer and the substrate.

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