Voltage generating circuit

Abstract

The present application provides a voltage generating circuit, comprising a first comparator, a boost circuit, a second comparator and an output circuit. The first comparator is used to compare a first reference voltage with a first feedback voltage generated based on a first output node, and generate a first control signal according to the comparison result. The boost circuit is controlled by the first control signal to output a boost voltage to the first output node. The second comparator is used to compare a second reference voltage with a second feedback voltage generated based on a second output node, and generate a second control signal according to the comparison result. The output circuit receives the boost voltage, and is controlled by the second control signal to convert the boost voltage into a driving voltage and output the driving voltage to the second output node. Wherein the boost voltage is determined by the first reference voltage, and the driving voltage is determined by the second reference voltage.

Description

Technical Field

[0001] This invention relates to a voltage generating circuit, and more particularly to a voltage generating circuit suitable for semiconductor memory devices. Background Technology

[0002] For semiconductor memory devices such as NAND and NOR flash memory, high voltages are required during incremental step pulse programming (ISPP) and incremental step pulse erase (ISPE) operations. Generally, these high voltages are boosted by a charge pump and then stably supplied to the word line via a voltage regulator. Generating high-precision high voltages is crucial to achieve a more concentrated distribution of threshold voltages across memory cells. Therefore, a large number of high-voltage components (such as electronic shifters) must be included in the voltage generation circuit, increasing both circuit area and production costs. Furthermore, under high temperature and high pressure conditions, the cutoff leakage current and impedance of high-voltage components change significantly, leading to poor linearity of voltage regulation and reduced accuracy of the high voltage. Summary of the Invention

[0003] The present invention provides a voltage generation circuit that can accurately generate the required voltage while reducing the use of high-voltage components (such as electric displacement devices).

[0004] The voltage generation circuit of the present invention includes a first comparator, a boost circuit, a second comparator, and an output circuit. The first comparator compares a first reference voltage with a first feedback voltage generated based on a first output node, and generates a first control signal based on the comparison result. The boost circuit is coupled to the first comparator and the first output node, and is controlled by the first control signal to output a boosted voltage to the first output node. The second comparator compares a second reference voltage with a second feedback voltage generated based on a second output node, and generates a second control signal based on the comparison result. The output circuit is coupled to the first output node, the second output node, and the second comparator, receives the boosted voltage, and is controlled by the second control signal to convert the boosted voltage into a drive voltage and output it to the second output node. The boosted voltage is determined by the first reference voltage, and the drive voltage is determined by the second reference voltage.

[0005] Based on the above, the voltage generation circuit of the present invention can reduce the use of high-voltage components, thereby achieving the goal of reducing area. Furthermore, it can solve the problem of decreased output accuracy caused by high-voltage components.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a circuit diagram of a voltage generation circuit according to an embodiment of the present invention;

[0008] Figure 2 This is a circuit diagram of a current source circuit according to an embodiment of the present invention;

[0009] Figure 3 This is a circuit diagram of a current source circuit according to another embodiment of the present invention. Detailed Implementation

[0010] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0011] Please refer to Figure 1 The voltage generation circuit 100 is suitable for providing a stable voltage for semiconductor memory devices such as NAND flash memory to perform read operations, programming operations, and erase operations, including the step voltage used in incremental pulse programming and incremental pulse erasing operations. The voltage generation circuit 100 includes a first comparator CMP1, a second comparator CMP2, a boost circuit 110, an output circuit 120, a first feedback circuit 130, a second feedback circuit 140, and a current source circuit 150.

[0012] The non-inverting input of the first comparator CMP1 receives a first reference voltage Vref1, and the inverting input receives a first feedback voltage Vfb1 generated based on the first output node HV_G. The first comparator CMP1 compares the first reference voltage Vref1 with the first feedback voltage Vfb1 and generates a first control signal Sc1 based on the comparison result. For example, when the first reference voltage Vref1 is greater than the first feedback voltage Vfb1, the first comparator CMP1 generates a high logic level first control signal Sc1; when the first reference voltage Vref1 is less than the first feedback voltage Vfb1, the first comparator CMP1 generates a low logic level first control signal Sc1.

[0013] The boost circuit 110 is, for example, a charge pump, coupled to the first comparator CMP1 and the first output node HV_G. The boost circuit 110 can be controlled by a first control signal Sc1 to output a boosted voltage Vcp to the first output node HV_G. For example, the boost circuit 110 can respond to a high logic level first control signal Sc1 by continuously increasing the boosted voltage Vcp until the first control signal Sc1 changes to a low logic level.

[0014] The inverting input of the second comparator CMP2 receives the second reference voltage Vref2, and the non-inverting input receives the second feedback voltage Vfb2 generated based on the second output node HV_S. The second comparator CMP2 compares the second reference voltage Vref2 with the second feedback voltage Vfb2 and generates a second control signal Sc2 based on the comparison result. For example, when the second feedback voltage Vfb2 is greater than the second reference voltage Vref2, the second comparator CMP2 generates a high logic level second control signal Sc2; when the second feedback voltage Vfb2 is less than the second reference voltage Vref2, the second comparator CMP2 generates a low logic level second control signal Sc2.

[0015] Output circuit 120 is coupled to the first output node HV_G, the second output node HV_S, and the second comparator CMP2. Output circuit 120 receives a boost voltage Vcp and, controlled by the second control signal Sc2, converts the boost voltage Vcp into a drive voltage Vds, which is then output to the second output node HV_S. Structurally, output circuit 120 includes a diode D, a first N-type field-effect transistor N1, an output resistor Rout, a second N-type field-effect transistor N2, and a first protection transistor Q1. The anode of diode D is coupled to the first output node HV_G. The drain of the first N-type field-effect transistor N1 is coupled to the cathode of diode D, and the source of the first N-type field-effect transistor N1 is coupled to the second output node HV_S. The first terminal of the output resistor Rout is coupled to the first output node HV_G, and the second terminal of the output resistor Rout is coupled to the gate of the first N-type field-effect transistor N1. The source of the second N-type field-effect transistor N2 is coupled to ground (0 volts), and the gate of the second N-type field-effect transistor N2 is coupled to the output of the second comparator CMP2 to receive the second control signal Sc2. The first terminal of the first protection transistor Q1 is coupled to the drain of the second N-type field-effect transistor N2, the second terminal is coupled to the gate of the first N-type field-effect transistor N1, and the control terminal is coupled to ground.

[0016] The first feedback circuit 130 is coupled to the inverting input of the first comparator CMP1 and the first output node HV_G. The first feedback circuit 130 generates a first feedback voltage Vfb1 based on the boost voltage Vcp and sends it to the inverting input of the first comparator CMP1. Structurally, the first feedback circuit 130 includes a first resistor R1, a second resistor R2, a first enable transistor QE1, and a second protection transistor Q2. The first resistor R1 is coupled between the first output node HV_G and the first feedback node ND1. The second resistor R2 is coupled between the first feedback node ND1 and ground potential. The first enable transistor QE1 is connected in series with the second resistor R2 in the circuit path between the first feedback node ND1 and ground potential, and is configured to be turned on or off according to the enable signal EN. The first terminal of the second protection transistor Q2 is coupled to the first feedback node ND1, the second terminal is coupled to the inverting input of the first comparator CMP1, and the control terminal is coupled to ground potential.

[0017] The second feedback circuit 140 is coupled to the non-inverting input of the second comparator CMP2 and the second output node HV_S. The second feedback circuit 140 generates a second feedback voltage Vfb2 to the non-inverting input of the second comparator CMP2 based on the driving voltage Vds. Structurally, the second feedback circuit 140 includes a third resistor R3, a fourth resistor R4, a second enable transistor QE2, and a third protection transistor Q3. The third resistor R3 is coupled between the second output node HV_S and the second feedback node ND2. The fourth resistor R4 is coupled between the second feedback node ND2 and ground potential. The second enable transistor QE2 is connected in series with the fourth resistor R4 in the circuit path between the second feedback node ND2 and ground potential, and is configured to be turned on or off according to the enable signal EN. The first terminal of the third protection transistor Q3 is coupled to the second feedback node ND2, the second terminal is coupled to the non-inverting input of the second comparator CMP2, and the control terminal is coupled to ground potential. The first protection transistor Q1, the second protection transistor Q2, and the third protection transistor Q3 are basically in a normally on state, which can protect other components.

[0018] The current source circuit 150 is coupled to the first comparator CMP1 and the second comparator CMP2. Operating at the power supply voltage VDD, the current source circuit 150 can adjust the first reference voltage Vref1 and the second reference voltage Vref2 according to the first voltage generation code VS1 and the second voltage generation code VS2.

[0019] In this embodiment, the boost voltage Vcp is determined by the first reference voltage Vref1, and the drive voltage Vds is determined by the second reference voltage Vref2. When the voltage generation circuit 100 is started, the first enable transistor QE1 and the second enable transistor QE2 will be turned on due to receiving a high logic level enable signal EN. According to the voltage divider circuit formed by the first resistor R1 and the second resistor R2, the boost voltage Vcp can be expressed by the following formula (1):

[0020] Vcp=Vfb1 (R1+R2) / R2 (1)

[0021] The boost circuit 110 will continuously increase the boost voltage Vcp until the first control signal Sc1 changes to a low logic level. Therefore, the boost voltage Vcp will enter a steady state when the first feedback voltage Vfb1 equals the first reference voltage Vref1. At this time, the boost voltage Vcp can be expressed by the following equation (2):

[0022] Vcp=Vref1 (R1+R2) / R2 (2)

[0023] Similarly, based on the voltage divider circuit formed by the third resistor R3 and the fourth resistor R4, the driving voltage Vds can be expressed by the following equation (3):

[0024] Vds=Vfb2 (R3+R4) / R4 (3)

[0025] exist Figure 1 In the above, when the second control signal Sc2 is at a low logic level, the second N-type field-effect transistor N2 is turned off, and the first N-type field-effect transistor N1 is turned on. Under this condition, the driving voltage Vds will be changed with the boost voltage Vcp until the second control signal Sc2 turns on, causing the second N-type field-effect transistor N2 to turn on and the first N-type field-effect transistor N1 to turn off. Therefore, the driving voltage Vds will enter a steady state when the second feedback voltage Vfb2 is equal to the second reference voltage Vref2. At this time, the driving voltage Vds can be expressed by the following equation (4):

[0026] Vds=Vref2 (R3+R4) / R4 (4)

[0027] As shown in equations (2) and (4) above, the voltage generation circuit 100 of this embodiment can adjust the boost voltage Vcp according to the first reference voltage Vref1 and the drive voltage Vds according to the second reference voltage Vref2, and can independently control the voltage difference between the first output node HV_G and the second output node HV_S. In this way, the boost voltage Vcp and drive voltage Vds can be accurately generated for use in various operations of the semiconductor memory device while reducing the use of high-voltage components (such as electric shifters).

[0028] In practical applications, the first resistor R1 and the third resistor R3 can be 114k ohms, and the second resistor R2 and the fourth resistor R4 can be 6k ohms. Those skilled in the art can make appropriate adjustments according to their actual needs.

[0029] The following examples illustrate the implementation details of the current source circuit. Please also refer to... Figure 1 and Figure 2 The current source circuit 150A includes a first current source CS1, a second current source CS2, a fifth resistor R5, and a sixth resistor R6. The first terminal of the first current source CS1 is coupled to the power supply voltage VDD, and the second terminal is coupled to the non-inverting input terminal of the first comparator CMP1. The first terminal of the fifth resistor R5 is coupled to the second terminal of the first current source CS1, and the second terminal is coupled to ground potential. The first terminal of the second current source CS2 is coupled to the power supply voltage VDD, and the second terminal is coupled to the inverting input terminal of the second comparator CMP2. The first terminal of the sixth resistor R6 is coupled to the second terminal of the second current source CS2, and the second terminal is coupled to ground potential. The first current source CS1 is configured to generate a first reference current Iref1 according to the first voltage generation code VS1 and the second voltage generation code VS2 to provide the first reference voltage Vref1 to the non-inverting input terminal of the first comparator CMP1. At this time, the boost voltage Vcp can be expressed by the following equation (5):

[0030] Vcp= Iref1 R5 (R1+R2) / R2 (5)

[0031] The second current source CS2 is configured to generate a second reference current Iref2 according to the first voltage generation code VS1, so as to provide the second reference voltage Vref2 to the inverting input of the second comparator CMP2. At this time, the drive voltage Vds can be expressed by the following equation (6):

[0032] Vds=Iref2 R6 (R3+R4) / R4 (6)

[0033] In practical applications, the fifth resistor R5 and the sixth resistor R6 can be selected as 100k ohms, and those skilled in the art can make appropriate adjustments according to their actual needs.

[0034] The following example illustrates the implementation details of the current source circuit. Please also refer to... Figure 1 and Figure 3 The current source circuit 150B includes a bias circuit 300, a fine-tuning current generation circuit 310, a base current generation circuit 320, an overdrive current generation circuit 330, and a current mirror circuit 340. The bias circuit 300 is used to generate a bias current Ibias (e.g., 4 microamperes).

[0035] The fine-tuning current generation circuit 310 is coupled to the bias circuit 300. The fine-tuning current generation circuit 310 generates multiple weighted currents Iw1 to Iw6 in a binary weighted increment based on the bias current Ibias, and selects the current to be summed from the weighted currents Iw1 to Iw6 according to the first voltage generation code VS1 to generate the fine-tuning current Itrim. The current values ​​of the weighted currents Iw1 to Iw6 are respectively based on the mirror ratio of the transistors in the circuit, increasing in a binary weighted increment from low to high. For example, the weighted current Iw1 is 0.1 microamps, the weighted current Iw2 is 0.2 microamps, the weighted current Iw3 is 0.4 microamps, the weighted current Iw4 is 0.8 microamps, the weighted current Iw5 is 1.6 microamps, and the weighted current Iw6 is 3.2 microamps.

[0036] The base current generating circuit 320 is coupled to the bias circuit 300 and the fine-tuning current generating circuit 310. The base current generating circuit 320 is used to generate a base current Ib. The base current Ib is used to generate the minimum drive voltage Vds, for example, 5.7 microamps.

[0037] The overdrive current generation circuit 330 is coupled to the bias circuit 300. The overdrive current generation circuit 330 generates an overdrive current Iov based on the second voltage generation code VS2. The overdrive current Iov can be used to determine the voltage difference between the boost voltage Vcp and the drive voltage Vds.

[0038] The current mirror circuit 340 is coupled to the bias circuit 300, the fine-tuning current generation circuit 310, the base current generation circuit 320, and the overdrive current generation circuit 330. The current mirror circuit 340 can sum the fine-tuning current Itrim, the base current Ib, and the overdrive current Iov to generate a first reference current Iref1, so as to provide a first reference voltage Vref1 to the non-inverting input terminal of the first comparator CMP1, and can sum the fine-tuning current Itrim and the base current Ib to generate a second reference current Iref2, so as to provide a second reference voltage Vref2 to the inverting input terminal of the second comparator CMP2. In other words, the first reference current Iref1 is equal to the sum of the fine-tuning current Itrim, the base current Ib, and the overdrive current Iov, and the second reference current Iref2 is equal to the sum of the fine-tuning current Itrim and the base current Ib. At this time, the boost voltage Vcp can be expressed as follows (7), and the drive voltage Vds can be expressed as follows (8):

[0039] Vcp = (Ib + Itrim + Iov) R5 (R1+R2) / R2 (7)

[0040] Vds = (Ib + Itrim) R6 (R3+R4) / R4 (8)

[0041] In terms of circuit structure, the current mirror circuit 340 includes a third enable transistor QE3, first to eleventh P-type field-effect transistors P1~P11, a third N-type field-effect transistor N3, a fourth N-type field-effect transistor N4, a fifth resistor R5, and a sixth resistor R6. The first terminal of the third enable transistor QE3 is coupled to the power supply voltage VDD, and the control terminal is coupled to the inverse enable signal ENB. The source of the first P-type field-effect transistor P1 is coupled to the second terminal of the third enable transistor QE3. The source of the second P-type field-effect transistor P2 is coupled to the drain of the first P-type field-effect transistor P1, and the drain of the second P-type field-effect transistor P2 is coupled to the gate of the first P-type field-effect transistor P1, a fine-tuning current generation circuit 310, and a basic current generation circuit 320. The source of the third P-type field-effect transistor is coupled to the second terminal of the third enable transistor QE3, and the gate of the third P-type field-effect transistor is coupled to the gate of the first P-type field-effect transistor P1. The source of the fourth P-type field-effect transistor P4 is coupled to the drain of the third P-type field-effect transistor P3. The drain of the fourth P-type field-effect transistor P4 is coupled to the inverting input of the second comparator CMP2. The gate of the fourth P-type field-effect transistor P4 is coupled to the gate of the second P-type field-effect transistor P2. The source of the fifth P-type field-effect transistor P5 is coupled to the second terminal of the third enable transistor QE3. The gate of the fifth P-type field-effect transistor P5 is coupled to the gate of the first P-type field-effect transistor P1. The source of the sixth P-type field-effect transistor P6 is coupled to the drain of the fifth P-type field-effect transistor P5. The drain of the sixth P-type field-effect transistor P6 is coupled to the non-inverting input of the first comparator CMP1. The gate of the sixth P-type field-effect transistor P6 is coupled to the gate of the second P-type field-effect transistor P2. The source of the seventh P-type field-effect transistor P7 is coupled to the second terminal of the third enable transistor QE3. The source of the eighth P-type field-effect transistor P8 is coupled to the drain of the seventh P-type field-effect transistor P7. The drain of the eighth P-type field-effect transistor P8 is coupled to the drain of the sixth P-type field-effect transistor P6. The gate of the eighth P-type field-effect transistor P8 is coupled to the gate of the second P-type field-effect transistor P2. The source of the ninth P-type field-effect transistor P9 is coupled to the second terminal of the third enable transistor QE3. The gate of the ninth P-type field-effect transistor P9 is coupled to the gate of the seventh P-type field-effect transistor. The source of the tenth P-type field-effect transistor P10 is coupled to the drain of the ninth P-type field-effect transistor P9. The drain of the tenth P-type field-effect transistor P10 is coupled to the gate of the ninth P-type field-effect transistor P9 and the overdrive current generating circuit 330. The gate of the tenth P-type field-effect transistor P10 is coupled to the gate of the second P-type field-effect transistor P2. The source of the eleventh P-type field-effect transistor P11 is coupled to the power supply voltage VDD. The drain and gate of the eleventh P-type field-effect transistor P11 are both coupled to the gate of the second P-type field-effect transistor P2. The drain of the third N-type field-effect transistor N3 is coupled to the drain of the eleventh P-type field-effect transistor P11. The gate of the third N-type field-effect transistor N3 is coupled to the bias circuit 300.The drain of the fourth N-type field-effect transistor N4 is coupled to the source of the third N-type field-effect transistor N3, the source of the fourth N-type field-effect transistor N4 is coupled to ground, and the gate of the fourth N-type field-effect transistor N4 is coupled to bias circuit 300. The first terminal of the fifth resistor R5 is coupled to the drain of the sixth P-type field-effect transistor P6, and the second terminal is coupled to ground. The first terminal of the sixth resistor R6 is coupled to the drain of the fourth P-type field-effect transistor P4, and the second terminal is coupled to ground.

[0042] The bias circuit 300 includes a third current source CS3, a fifth N-type field-effect transistor N5, a fourth current source CS4, a sixth N-type field-effect transistor N6, a seventh N-type field-effect transistor N7, a fourth enable transistor QE4, and a fifth enable transistor QE5. The first terminal of the third current source CS3 is coupled to the power supply voltage VDD. The drain and gate of the fifth N-type field-effect transistor N5 are both coupled to the second terminal of the third current source CS3 and the gate of the third N-type field-effect transistor N3 in the current mirror circuit 340. The source of the fifth N-type field-effect transistor N5 is coupled to ground. The first terminal of the fourth current source CS4 is coupled to the power supply voltage VDD. The drain of the sixth N-type field-effect transistor N6 is coupled to the second terminal of the fourth current source CS4, and the gate of the sixth N-type field-effect transistor N6 is coupled to the gate of the third N-type field-effect transistor N3. The drain of the seventh N-type field-effect transistor N7 is coupled to the source of the sixth N-type field-effect transistor N6. The gate of the seventh N-type field-effect transistor N7 is coupled to the drain of the sixth N-type field-effect transistor N6 and the gate of the fourth N-type field-effect transistor N4 in the current mirror circuit 340. The source of the seventh N-type field-effect transistor N7 is coupled to ground. The first terminal of the fourth enable transistor QE4 is coupled to the drain of the fifth N-type field-effect transistor N5, the second terminal is coupled to ground, and the control terminal is coupled to the inverse enable signal ENB. The first terminal of the fifth enable transistor QE5 is coupled to the drain of the sixth N-type field-effect transistor, the second terminal is coupled to ground, and the control terminal is coupled to the inverse enable signal ENB.

[0043] The fine-tuning current generation circuit 310 includes eighth to twenty-seventh N-type field-effect transistors N8 to N27. The drain of the eighth N-type field-effect transistor N8 is coupled to the drain of the second P-type field-effect transistor P2 in the current mirror circuit 340, and the gate of the eighth N-type field-effect transistor N8 is coupled to the first encoded signal TR1. The drain of the ninth N-type field-effect transistor N9 is coupled to the source of the eighth N-type field-effect transistor N8. The drain of the tenth N-type field-effect transistor N10 is coupled to the source of the ninth N-type field-effect transistor N9, and the gate of the tenth N-type field-effect transistor N10 is coupled to the gate of the ninth N-type field-effect transistor N9 and the gate of the sixth N-type field-effect transistor in the bias circuit 300. The drain of the eleventh N-type field-effect transistor N11 is coupled to the source of the tenth N-type field-effect transistor N10. The drain of the twelfth N-type field-effect transistor N12 is coupled to the source of the eleventh N-type field-effect transistor N11. The source of the twelfth N-type field-effect transistor N12 is coupled to ground potential. The gate of the twelfth N-type field-effect transistor N12 is coupled to the gate of the eleventh N-type field-effect transistor N11 and the gate of the seventh N-type field-effect transistor N7 in the bias circuit 300. The drain of the thirteenth N-type field-effect transistor N13 is coupled to the drain of the second P-type field-effect transistor P2. The gate of the thirteenth N-type field-effect transistor N13 is coupled to the second encoded signal TR2. The drain of the fourteenth N-type field-effect transistor N14 is coupled to the source of the thirteenth N-type field-effect transistor N13. The gate of the fourteenth N-type field-effect transistor N14 is coupled to the gate of the sixth N-type field-effect transistor N6. The drain of the fifteenth N-type field-effect transistor N15 is coupled to the source of the fourteenth N-type field-effect transistor N14, the source of the fifteenth N-type field-effect transistor N15 is coupled to ground, and the gate of the fifteenth N-type field-effect transistor N15 is coupled to the gate of the seventh N-type field-effect transistor N7. The drain of the sixteenth N-type field-effect transistor N16 is coupled to the drain of the second P-type field-effect transistor P2, and the gate of the sixteenth N-type field-effect transistor N16 is coupled to the third encoded signal TR3. The drain of the seventeenth N-type field-effect transistor N17 is coupled to the source of the sixteenth N-type field-effect transistor N16, and the gate of the seventeenth N-type field-effect transistor N17 is coupled to the gate of the sixth N-type field-effect transistor N6. The drain of the eighteenth N-type field-effect transistor N18 is coupled to the source of the seventeenth N-type field-effect transistor N17, the source of the eighteenth N-type field-effect transistor N18 is coupled to ground, and the gate of the eighteenth N-type field-effect transistor N18 is coupled to the gate of the seventh N-type field-effect transistor N7. The drain of the nineteenth N-type field-effect transistor N19 is coupled to the drain of the second P-type field-effect transistor P2, and the gate of the nineteenth N-type field-effect transistor N19 is coupled to the fourth coded signal TR4. The drain of the twentieth N-type field-effect transistor N20 is coupled to the source of the nineteenth N-type field-effect transistor N19, and the gate of the twentieth N-type field-effect transistor N20 is coupled to the gate of the sixth N-type field-effect transistor N6.The drain of the 21st N-type field-effect transistor N21 is coupled to the source of the 20th N-type field-effect transistor N20, and the source of the 21st N-type field-effect transistor N21 is coupled to ground. The gate of the 21st N-type field-effect transistor N21 is coupled to the gate of the 7th N-type field-effect transistor. The drain of the 22nd N-type field-effect transistor N22 is coupled to the drain of the second P-type field-effect transistor of the 22nd N-type field-effect transistor N22, and the gate of the 22nd N-type field-effect transistor N22 is coupled to the fifth encoded signal TR5. The drain of the 23rd N-type field-effect transistor N23 is coupled to the source of the 22nd N-type field-effect transistor N22, and the gate of the 23rd N-type field-effect transistor N23 is coupled to the gate of the 6th N-type field-effect transistor N6. The drain of the 24th N-type field-effect transistor N24 is coupled to the source of the 23rd N-type field-effect transistor N23, the source of the 24th N-type field-effect transistor N24 is coupled to ground, and the gate of the 24th N-type field-effect transistor N24 is coupled to the gate of the 7th N-type field-effect transistor N7. The drain of the 25th N-type field-effect transistor N25 is coupled to the drain of the 2nd P-type field-effect transistor P2, and the gate of the 25th N-type field-effect transistor N25 is coupled to the sixth encoded signal. The drain of the 26th N-type field-effect transistor N26 is coupled to the source of the 25th N-type field-effect transistor N25, and the gate of the 26th N-type field-effect transistor N26 is coupled to the gate of the 6th N-type field-effect transistor N6. The drain of the 27th N-type field-effect transistor N27 is coupled to the source of the 26th N-type field-effect transistor N26, the source of the 27th N-type field-effect transistor N27 is coupled to ground, and the gate of the 27th N-type field-effect transistor N27 is coupled to the gate of the 7th N-type field-effect transistor N7.

[0044] The basic current generating circuit 320 includes a twenty-eighth N-type field-effect transistor N28 and a twenty-nine N-type field-effect transistor N29. The drain of the twenty-eighth N-type field-effect transistor N28 is coupled to the drain of the second P-type field-effect transistor P2 in the current mirror circuit 340, and the gate of the twenty-eighth N-type field-effect transistor N28 is coupled to the gate of the sixth N-type field-effect transistor N6 in the bias circuit 300. The drain of the twenty-nine N-type field-effect transistor N29 is coupled to the source of the twenty-eighth N-type field-effect transistor N28, the source of the twenty-nine N-type field-effect transistor N29 is coupled to ground potential, and the gate of the twenty-nine N-type field-effect transistor N29 is coupled to the gate of the seventh N-type field-effect transistor N7 in the bias circuit 300.

[0045] Operationally, the logic level of the inverse enable signal ENB is complementary to the logic level of the enable signal EN. When the voltage generation circuit 100 is activated, the third enable transistor QE3 will turn on upon receiving the low logic level inverse enable signal ENB, while the fourth enable transistor QE4 and the fifth enable transistor QE5 will turn off upon receiving the low logic level inverse enable signal ENB. Consequently, the fifth P-type field-effect transistor P5, the sixth P-type field-effect transistor P6, the seventh P-type field-effect transistor P7, and the eighth P-type field-effect transistor P8... Figure 3 The circuit path formed by the parallel connection of the transistors and the series connection of the fifth resistor R5 will generate a first reference current Iref1, which is the sum of the fine-tuning current Itrim, the base current Ib, and the overdrive current Iov. The circuit path formed by the series connection of the third P-type field-effect transistor P3, the fourth P-type field-effect transistor P4, and the sixth resistor R6 will generate a second reference current Iref2, which is the sum of the fine-tuning current Itrim and the base current Ib.

[0046] Furthermore, the six bits of the first voltage generation code VS1 are input, for example, as the first to sixth encoded signals TR1~TR6, to the gates of the eighth N-type field-effect transistor N8, the thirteenth N-type field-effect transistor N13, the sixteenth N-type field-effect transistor N16, the nineteenth N-type field-effect transistor N19, the twenty-second N-type field-effect transistor N22, and the twenty-fifth N-type field-effect transistor N25, respectively, to control the on or off state of these transistors. By combining the six bits of the first voltage generation code VS1, 64 fine-tuning current Itrim can be set. In this way, the fine-tuning current Itrim can be adjusted during incremental step pulse programming and incremental step pulse erasure operations to generate appropriate boost voltage Vcp and drive voltage Vds.

[0047] It is worth mentioning that the internal structure of the basic current generation circuit 320 may be similar to that of the overdrive current generation circuit 330, thereby generating the overdrive current Iov according to the second voltage generation code VS2, but the present invention is not limited thereto.

[0048] In summary, the voltage generation circuit of the present invention can not only reduce the area occupied, but also effectively improve the accuracy of the output voltage while reducing the use of high-voltage components, thereby reducing production costs.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A voltage generating circuit, characterized in that, include: A first comparator is used to compare a first reference voltage with a first feedback voltage generated based on a first output node, and to generate a first control signal based on the comparison result. The boost circuit is coupled to the first comparator and the first output node, and is controlled by the first control signal to output the boost voltage to the first output node; The second comparator is used to compare the second reference voltage with the second feedback voltage generated based on the second output node, and to generate a second control signal based on the comparison result; as well as The output circuit, coupled to the first output node, the second output node, and the second comparator, receives the boosted voltage and, controlled by the second control signal, converts the boosted voltage into a drive voltage and outputs it to the second output node. The boost voltage is determined by the first reference voltage, and the drive voltage is determined by the second reference voltage, thereby independently controlling the voltage difference between the first output node and the second output node.

2. The voltage generating circuit according to claim 1, characterized in that, When the first reference voltage is greater than the first feedback voltage, the first comparator generates a first control signal with a high logic level; when the first reference voltage is less than the first feedback voltage, the first comparator generates a first control signal with a low logic level.

3. The voltage generating circuit according to claim 1, characterized in that, When the second feedback voltage is greater than the second reference voltage, the second comparator generates a second control signal with a high logic level; when the second feedback voltage is less than the second reference voltage, the second comparator generates a second control signal with a low logic level.

4. The voltage generating circuit according to claim 1, characterized in that, The boost circuit continuously increases the boost voltage in response to the first control signal at a high logic level until the first control signal changes to a low logic level. The boost voltage enters a steady state when the first feedback voltage equals the first reference voltage.

5. The voltage generating circuit according to claim 1, characterized in that, The output circuit includes: A diode, the anode of which is coupled to the first output node; The first N-type field-effect transistor has its drain coupled to the cathode of the diode and its source coupled to the second output node; An output resistor, the first end of which is coupled to the first output node, and the second end of which is coupled to the gate of the first N-type field-effect transistor; The second N-type field-effect transistor has its source coupled to ground potential and its gate receiving the second control signal; and The first protection transistor has a first terminal coupled to the drain of the second N-type field-effect transistor, a second terminal coupled to the gate of the first N-type field-effect transistor, and a control terminal coupled to the ground potential.

6. The voltage generating circuit according to claim 5, characterized in that, When the second control signal is at a low logic level, the second N-type field-effect transistor is turned off and the first N-type field-effect transistor is turned on. In this case, the driving voltage is changed with the boost voltage until the second control signal turns to a high logic level, causing the second N-type field-effect transistor to turn on and the first N-type field-effect transistor to turn off. The driving voltage enters a steady state when the second feedback voltage is equal to the second reference voltage.

7. The voltage generating circuit according to claim 1, characterized in that, Also includes: The first feedback circuit is coupled to the inverting input terminal of the first comparator and the first output node, and generates the first feedback voltage to the inverting input terminal of the first comparator according to the boost voltage.

8. The voltage generating circuit according to claim 7, characterized in that, The first feedback circuit includes: A first resistor is coupled between the first output node and the first feedback node, the first feedback node being coupled to the inverting input of the first comparator; and The second resistor is coupled between the first feedback node and the ground potential.

9. The voltage generating circuit according to claim 8, characterized in that, The first feedback circuit further includes: A first enabling transistor, connected in series with the second resistor in the circuit path between the first feedback node and the ground potential, is configured to be turned on or off according to an enabling signal; and The second protection transistor has a first terminal coupled to the first feedback node, a second terminal coupled to the inverting input terminal of the first comparator, and a control terminal coupled to the ground potential.

10. The voltage generating circuit according to claim 1, characterized in that, Also includes: The second feedback circuit is coupled to the non-inverting input terminal of the second comparator and the second output node, and generates the second feedback voltage to the non-inverting input terminal of the second comparator according to the driving voltage.

11. The voltage generating circuit according to claim 10, characterized in that, The second feedback circuit includes: A third resistor is coupled between the second output node and the second feedback node, the second feedback node being coupled to the non-inverting input of the second comparator; and The fourth resistor is coupled between the second feedback node and the ground potential.

12. The voltage generating circuit according to claim 11, characterized in that, The second feedback circuit also includes: A second enabling transistor, connected in series with the fourth resistor in the circuit path between the second feedback node and the ground potential, is configured to be turned on or off according to an enabling signal; and The third protection transistor has its first terminal coupled to the second feedback node, its second terminal coupled to the non-inverting input terminal of the second comparator, and its control terminal coupled to the ground potential.

13. The voltage generating circuit according to claim 1, characterized in that, Also includes: A current source circuit is coupled to the first comparator and the second comparator. The current source circuit operates under the power supply voltage and adjusts the first reference voltage according to the first voltage generation code and the second voltage generation code, and adjusts the second reference voltage according to the first voltage generation code.

14. The voltage generating circuit according to claim 13, characterized in that, The current source circuit includes: A first current source, with its first terminal coupled to the power supply voltage and its second terminal coupled to the non-inverting input terminal of the first comparator; The fifth resistor has its first end coupled to the second end of the first current source, and its second end coupled to the ground potential. A second current source, the first terminal of which is coupled to the power supply voltage, and the second terminal of which is coupled to the inverting input of the second comparator; and The sixth resistor has its first end coupled to the second end of the second current source, and its second end coupled to the ground potential. The first current source is configured to generate a first reference current according to the first voltage generation code and the second voltage generation code, so as to provide the first reference voltage to the non-inverting input terminal of the first comparator, and the second current source is configured to generate a second reference current according to the first voltage generation code, so as to provide the second reference voltage to the inverting input terminal of the second comparator.

15. The voltage generating circuit according to claim 13, characterized in that, The current source circuit includes: Bias circuit, used to generate bias current; A fine-tuning current generation circuit is coupled to the bias circuit. Based on the bias current, it generates multiple weighted currents in a binary weighted increment manner, and selects the current to be summed from the multiple weighted currents according to the first voltage generation code to generate a fine-tuning current. A base current generating circuit, coupled to the bias circuit and the fine-tuning current generating circuit, is used to generate a base current. The overdrive current generation circuit, coupled to the bias circuit, generates an overdrive current according to the second voltage generation code; and A current mirror circuit, coupled to the bias circuit, the fine-tuning current generation circuit, the base current generation circuit, and the overdrive current generation circuit, sums the fine-tuning current, the base current, and the overdrive current to generate a first reference current, which provides the first reference voltage to the non-inverting input of the first comparator, and sums the fine-tuning current and the base current to generate a second reference current, which provides the second reference voltage to the inverting input of the second comparator.

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