RISC-V vector instruction configuration determination method and device

Abstract

This specification relates to the field of computer technology and specifically discloses a RISC-V vector instruction configuration determination method and apparatus, wherein the method includes: decoding a target vsetvl instruction; performing a hash calculation on the address of the target vsetvl instruction to obtain a target address hash; determining, based on the target address hash, whether a target cache entry corresponding to the target vsetvl instruction exists in a prediction cache; the prediction cache includes multiple cache entries; each of the multiple cache entries includes an address hash, a prediction accuracy, and a vtype value; and, if it is determined that a target cache entry corresponding to the target vsetvl instruction exists in the prediction cache, if the prediction accuracy in the target cache entry is greater than or equal to a preset threshold, determining the vtype value in the target cache entry as the predicted vtype value of the target vsetvl instruction. The above-described scheme can improve CPU pipeline execution efficiency.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and in particular to a method and device for determining RISC-V vector instruction configuration. Background Art

[0002] The RISC-V vector instruction set is one of the many standard instruction set extensions of RISC-V, used to support the Single Instruction Multiple Data (SIMD) computing mode to improve the computing power and efficiency of the corresponding CPU. The register width used by SIMD instructions is generally 128 bits or wider, and each vector register contains multiple integer metadata with a width of 8 / 16 / 32 / 64 bits or 16 / 32 / 64-bit floating-point metadata. In common SIMD instruction sets, the register and data width corresponding to each instruction are fixed. A RISC-V vector instruction can be used for different register and data widths. The advantage of this is that an application using RISC-V vector instructions can run on multiple CPU implementations with different register widths without making any modifications.

[0003] In order to decouple RISC-V instructions from register width, the RISC-V vector instruction set defines multiple vector control and status registers (VCSRs) to define runtime register and data width, data type, etc. The decoding and execution of RISC-V vector instructions depend on the current VCSR register value. In the VCSR of the RISC-V vector instruction set, the two more important registers are vtype and vl. These two registers can be set by the following three configuration setting instructions: vsetvli instruction, vsetivli instruction and vsetvl instruction. Please refer to Figure 1 , shows the form of vsetvli, vsetivli and vsetvl instructions. Figure 1 As shown, the vsetvli, vsetivli, and vsetvl instructions are represented as follows:

[0004] vsetvli rd,rs1,vtypei, where rd = new vl value, rs1 = number of unprocessed metadata, and vtypei = new vtype configuration;

[0005] vsetivli rd,uimm,vtypei, where rd = new vl value, uimm = number of unprocessed metadata, vtypei = new vtype configuration;

[0006] vsetvl rd,rs1,rs2, where rd = new vl value, rs1 = number of unprocessed metadata, and rs2 = new vtype configuration.

[0007] To improve performance, modern CPU architectures typically include multiple pipeline stages. Multi-pipelined CPU architectures can present a performance-impairing issue when processing RISC-V vector instructions. In many cases, a vector instruction requires the corresponding vtype configuration during the decode phase. The vtype configuration primarily includes LMUL and SEW. LMUL indicates that the RISC-V vector architecture supports reading or writing multiple registers (called register banks) or portions of a register in a single instruction. LMUL is controlled by the LMUL field in the VCSR, with possible values ​​of [1 / 8, 1 / 4, 1 / 2, 1, 2, 4, 8]. In the RISC-V vector architecture, a vector register contains multiple metadata. SEW indicates the size of each metadata element. The size of each metadata element is controlled by the SEW field in the VCSR. SEW can be an 8-, 16-, 32-, or 64-bit integer or a 32- or 64-bit floating-point number. For example, when LMUL > 1, a vector instruction may need to be split into LMUL microinstructions, each of which operates and calculates on a specific target register. Or for read / write instructions of the Stride or Index type, the SEW value is needed to determine how many data read / write operations need to be split. The vtype value used by a vector instruction is set by the most recent vsetvli, vsetivli, or vsetvl instruction before it.

[0008] The vtype value for both the vsetvli and vsetivli instructions is included in the instruction code (opcode) and is available when the vsetvli or vsetivli instruction is decoded. This allows subsequent vector instructions to accurately determine the corresponding vtype value during the decoding phase. However, the vtype value for the vsetvl instruction comes from a register, whose value is not known until the subsequent execution phase. Because multiple clock cycles are required from the time an instruction is decoded to its execution, the vector instructions following a vsetvl instruction must wait multiple clock cycles during the decoding phase to obtain the correct vtype value. Only then can these vector instructions proceed to the decoding and subsequent pipeline stages. This means that RISC-V vector instructions following a vsetvl instruction must wait for the correct vtype value before decoding. While this functionality is correct, the multiple clock cycles of idle execution can affect overall CPU performance.

[0009] To address the above issues, no effective solutions have been proposed so far. Summary of the Invention

[0010] The embodiments of this specification provide a method and apparatus for determining the configuration of a RISC-V vector instruction to address the problem in the prior art that the vtype value corresponding to the RISC-V vector instruction after the vsetvl instruction requires waiting for multiple clock cycles to be determined, thereby affecting the overall performance of the CPU.

[0011] An embodiment of this specification provides a method for determining a RISC-V vector instruction configuration, including:

[0012] Decoding the target vsetvl instruction; performing hash calculation on the address of the target vsetvl instruction to obtain a target address hash;

[0013] Determine, based on the target address hash, whether there is a target cache entry corresponding to the target vsetvl instruction in the prediction cache; the prediction cache includes multiple cache entries; each cache entry in the multiple cache entries includes an address hash, a prediction accuracy, and a vtype value;

[0014] When it is determined that there is a target cache entry corresponding to the target vsetvl instruction in the prediction cache, if the prediction accuracy in the target cache entry is greater than or equal to a preset threshold, the vtype value in the target cache entry is determined as the predicted vtype value of the target vsetvl instruction.

[0015] In one embodiment, the method further comprises:

[0016] If the target cache entry corresponding to the target vsetvl instruction does not exist in the prediction cache or the prediction accuracy of the target cache entry is less than a preset threshold, the vtype value of the target vsetvl instruction is not predicted.

[0017] In one embodiment, the method further comprises:

[0018] If the target cache entry corresponding to the target vsetvl instruction does not exist in the prediction cache or the prediction accuracy of the target cache entry is less than a preset threshold, setting the vtype state of the target vsetvl instruction to invalid;

[0019] When it is determined that a target cache entry corresponding to the target vsetvl instruction exists in the prediction cache and the prediction accuracy in the target cache entry is greater than or equal to a preset threshold, the vtype state of the target vsetvl instruction is set to valid.

[0020] In one embodiment, the method further comprises:

[0021] When decoding a target vector instruction, if the vtype state of the target vsetvl instruction is valid, the predicted vtype value of the target vsetvl instruction is determined as the vtype value of the target vector instruction; the target vector instruction is the next vector instruction of the target vsetvl instruction.

[0022] In one embodiment, the method further comprises:

[0023] When decoding a target vector instruction, if the vtype status of the target vsetvl instruction is invalid, decoding is stopped at the target vector instruction until the vtype status of the target vsetvl instruction is valid; the target vector instruction is the next vector instruction of the target vsetvl instruction.

[0024] In one embodiment, the method further comprises:

[0025] Executing the target vsetvl instruction to obtain a target vtype value of the target vsetvl instruction;

[0026] If a target cache entry corresponding to the target vsetvl instruction exists in the prediction cache, determining whether the target vtype value is consistent with the vtype value in the target cache entry;

[0027] In a case where it is determined that the target vtype value is consistent with the vtype value in the target cache entry, the prediction accuracy in the target cache entry is increased.

[0028] In one embodiment, the method further comprises:

[0029] When it is determined that the target vtype value is inconsistent with the vtype value in the target cache item, the prediction accuracy in the target cache item is reduced, and the vtype value in the target cache item is updated to the target vtype value.

[0030] In one embodiment, the method further comprises:

[0031] If it is determined that the target vtype value is inconsistent with the vtype value in the target cache entry, determining whether the vtype value in the target cache entry has been used as the vtype value of the target vector instruction; the target vector instruction is the instruction next to the target vsetvl instruction;

[0032] If it is determined that the vtype value in the target cache entry has been used as the vtype value of the target vector instruction, the vtype value of the target vector instruction is reset to the target vtype value, and the pipeline is flushed starting from the target vector instruction.

[0033] In one embodiment, the method further comprises:

[0034] If the target cache entry corresponding to the target vsetvl instruction does not exist in the prediction cache, determining whether there is an available cache entry in the prediction cache;

[0035] When it is determined that there is an available cache entry in the prediction cache, the target vtype value and target address hash of the target vsetvl instruction are written into the available cache entry, and the prediction accuracy in the available cache entry is initialized.

[0036] In one embodiment, the method further comprises:

[0037] In the case where it is determined that there is no available cache item in the prediction cache, determining a cache item with the lowest prediction accuracy from the multiple cache items in the prediction cache;

[0038] The target vtype value and target address hash of the target vsetvl instruction are written into the cache entry with the lowest prediction accuracy, and the prediction accuracy in the cache entry with the lowest prediction accuracy is initialized.

[0039] The embodiments of this specification also provide a RISC-V vector instruction configuration determination device, including:

[0040] A decoding module, used to decode the target vsetvl instruction;

[0041] a judgment module, configured to perform a hash calculation on the address of the target vsetvl instruction to obtain a target address hash; and further configured to judge, based on the target address hash, whether a target cache entry corresponding to the target vsetvl instruction exists in a prediction cache; the prediction cache includes a plurality of cache entries; each of the plurality of cache entries includes an address hash, a prediction accuracy, and a vtype value;

[0042] A determination module is used to, when it is determined that there is a target cache entry corresponding to the target vsetvl instruction in the prediction cache, determine the vtype value in the target cache entry as the predicted vtype value of the target vsetvl instruction if the prediction accuracy in the target cache entry is greater than or equal to a preset threshold.

[0043] An embodiment of this specification also provides a computer device, including a processor and a memory for storing processor-executable instructions, wherein when the processor executes the instructions, the steps of the RISC-V vector instruction configuration determination method described in any of the above embodiments are implemented.

[0044] An embodiment of this specification also provides a computer-readable storage medium having computer instructions stored thereon, which, when executed, implement the steps of the RISC-V vector instruction configuration determination method described in any of the above embodiments.

[0045] An embodiment of this specification also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the RISC-V vector instruction configuration determination method described in any of the above embodiments.

[0046] In an embodiment of the present specification, a method for determining the configuration of a RISC-V vector instruction is provided. A prediction cache can be provided, and the prediction cache can include multiple cache items, each of which contains an address hash, a prediction accuracy, and a vtype value. When decoding a target vsetvl instruction, a hash calculation can be performed on the address of the target vsetvl instruction to obtain a target address hash, and based on the target address hash, it is determined whether a target cache item corresponding to the target vsetvl instruction exists in the prediction cache. When it is determined that a target cache item corresponding to the target vsetvl instruction exists, if the prediction accuracy in the target cache item is greater than or equal to a preset threshold, the vtype value in the target cache item is determined as the predicted vtype value of the target vsetvl instruction. Through the above scheme, by providing a prediction cache containing multiple cache items, the vtype value of the target vsetvl instruction can be determined in the decoding stage without having to wait until the vsetvl instruction is executed, thereby improving the execution efficiency of the CPU pipeline and improving the overall performance of the CPU. Furthermore, when determining the vtype value of the target vsetvl instruction, a target address hash of the target vsetvl instruction is first calculated. If the target address hash matches the address hash of a cache entry in the prediction cache, the cache entry is determined as the target cache entry. Since vsetvl instructions with the same address are likely to have the same vtype value, predicting the vtype value based on cache entries with the same instruction address can improve prediction accuracy. Furthermore, the prediction accuracy of the target cache entry is further limited, and only when the prediction accuracy is greater than or equal to a preset threshold is the vtype value of the cache entry determined as the predicted vtype value of the target vsetvl instruction, further ensuring prediction accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings described herein are for illustrative purposes only and are not intended to limit the scope of the present invention in any way. In addition, the shapes and proportional dimensions of the components in the drawings are only schematic and are used to help understand the present invention. They do not specifically limit the shapes and proportional dimensions of the components of the present invention. Those skilled in the art can select various possible shapes and proportional dimensions to implement the present invention according to the specific circumstances under the guidance of the present invention. In the drawings:

[0048] Figure 1 shows the form of the vsetvli, vsetivli, and vsetvl instructions;

[0049] Figure 2 A flowchart of a method for determining a RISC-V vector instruction configuration in an embodiment of this specification is shown;

[0050] Figure 3 A flowchart of a method for determining a RISC-V vector instruction configuration in an embodiment of this specification is shown;

[0051] Figure 4 A flowchart of a method for determining a RISC-V vector instruction configuration in an embodiment of this specification is shown;

[0052] Figure 5 A structural diagram of a RISC-V vector instruction configuration determination device in one embodiment of this specification is shown. DETAILED DESCRIPTION

[0053] The principles and spirit of this specification will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided solely to enable those skilled in the art to better understand and implement this specification, and are not intended to limit the scope of this specification in any way. Rather, these embodiments are provided to make this specification more thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art.

[0054] Those skilled in the art will appreciate that the embodiments of this specification may be implemented as a system, device, method, or computer program product. Therefore, the disclosure herein may be implemented in the following forms: entirely in hardware, entirely in software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this specification pertains. The terms used herein in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0056] The embodiments of this specification provide a method for determining the configuration of RISC-V vector instructions. Figure 1 A flowchart of a RISC-V vector instruction configuration determination method in an embodiment of this specification is shown. Although this specification provides method operation steps or device structures as shown in the following embodiments or drawings, more or fewer operation steps or module units may be included in the method or device based on routine or no creative labor. In the steps or structures where there is no necessary causal relationship logically, the execution order of these steps or the module structure of the device is not limited to the execution order or module structure described in the embodiments of this specification and shown in the drawings. When the RISC-V vector instruction configuration determination method or module structure is applied to an actual device or terminal product, it can be connected according to the method or module structure shown in the embodiment or drawings for sequential execution or parallel execution (for example, a parallel processor or multi-threaded processing environment, or even a distributed processing environment).

[0057] Specifically, if Figure 2 As shown, a RISC-V vector instruction configuration determination method provided by an embodiment of this specification may include the following steps.

[0058] Step S201, decode the target vsetvl instruction; perform hash calculation on the address of the target vsetvl instruction to obtain a target address hash.

[0059] Step S202: Determine whether there is a target cache entry corresponding to the target vsetvl instruction in the prediction cache based on the target address hash; the prediction cache includes multiple cache entries; each cache entry in the multiple cache entries includes an address hash, a prediction accuracy, and a vtype value.

[0060] Step S203, when it is determined that there is a target cache entry corresponding to the target vsetvl instruction in the prediction cache, if the prediction accuracy in the target cache entry is greater than or equal to a preset threshold, the vtype value in the target cache entry is determined as the predicted vtype value of the target vsetvl instruction.

[0061] In this embodiment, the target vsetvl instruction is a vsetvl instruction in the RISC-V extended instruction set for processing vector operations in a multi-pipelined CPU architecture. The multi-pipelined CPU architecture decomposes the instruction execution process into multiple stages (pipeline stages) and allows multiple instructions to be executed in parallel at different stages. The CPU can process multiple instructions simultaneously, thereby improving the parallelism and processing speed of instruction execution.

[0062] The vsetvl instruction is used to set the effective length (VL) and vector data type (vtype) of the vector register group. vtype contains the length of the vector element (SEW, Standard Element Width) and the size of the vector register group (LMUL, Vector Register Group Multiplier). A vector instruction needs to know the corresponding vtype configuration during the decoding stage. For example, when LMUL>1, a vector instruction may need to be split into LMUL microinstructions, each of which operates and calculates on a target register. Or for read / write instructions of the Stride or Index type, the SEW value is needed to determine how many data read / write operations a vector instruction needs to be split into. Therefore, it is very important to determine the vtype value of the vsetvl instruction.

[0063] During the decoding stage, a prediction cache may be provided. The prediction cache may contain multiple cache items. Each cache item stores an address hash, a prediction accuracy, and a vtype value. The address hash is the hash value of the instruction address of the executed vsetvl instruction. The vtype value is the vtype value of the executed vsetvl instruction. The prediction accuracy is the prediction accuracy rate of the vtype value of the unexecuted vsetvl instruction predicted by the cache item. The larger the value, the higher the accuracy. When the cache item is first assigned to the vsetvl instruction, the prediction accuracy in the cache item may be initialized. In one embodiment, an initial value may also be stored in the cache item. When the cache item is first assigned to the vsetvl instruction, the prediction accuracy may be initialized to the corresponding initial value.

[0064] In the decoding stage, the target vsetvl instruction can be decoded. The address of the target vsetvl instruction is hashed to obtain a target address hash. The target address hash is compared with the address hash in each cache item in the prediction cache. If there is a matching address hash, the cache item corresponding to the address hash is determined as the target cache item corresponding to the target vsetvl instruction. When the prediction accuracy in the target cache item is greater than a preset threshold, the vtype value in the target cache item can be determined as the predicted vtype value of the target vsetvl instruction. In one embodiment, a preset threshold can also be stored in each cache item in the prediction cache. Only when the prediction accuracy in the target cache item is greater than the preset threshold is the vtype value in the target cache item used as the predicted vtype value of the target vsetvl instruction.

[0065] In the above embodiment, by providing a prediction cache containing multiple cache entries, the vtype value of the target vsetvl instruction can be determined during the decoding phase, eliminating the need to wait until the vsetvl instruction is executed. This improves the execution efficiency of the CPU pipeline and, in turn, the overall performance of the CPU. Furthermore, when determining the vtype value of the target vsetvl instruction, the target address hash of the target vsetvl instruction is first calculated. When the target address hash matches the address hash of a cache entry in the prediction cache, the cache entry is determined as the target cache entry. Since vsetvl instructions with the same address are likely to have the same vtype value, predicting the vtype value based on cache entries with the same instruction address can improve prediction accuracy. Furthermore, by further limiting the prediction accuracy of the target cache entry, the vtype value of the cache entry is determined as the predicted vtype value of the target vsetvl instruction only when the prediction accuracy is greater than or equal to a preset threshold, further ensuring prediction accuracy.

[0066] In some embodiments of the present specification, the method may further include: if the target cache entry corresponding to the target vsetvl instruction does not exist in the prediction cache or the prediction accuracy in the target cache entry is less than a preset threshold, not predicting the vtype value of the target vsetvl instruction. In this embodiment, if the target cache entry corresponding to the target vsetvl instruction does not exist in the prediction cache, the target vsetvl instruction is not predicted. If the target cache entry corresponding to the target vsetvl instruction exists in the prediction cache, but the prediction accuracy in the target cache entry is less than a preset threshold, the target vsetvl instruction is not predicted either. In this way, it is possible to avoid the reduction in the execution speed of the CPU pipeline caused by the incorrect prediction of the vtype value of the target vsetvl instruction.

[0067] In some embodiments of the present specification, the method may further include: setting the vtype state of the target vsetvl instruction to invalid when there is no target cache item corresponding to the target vsetvl instruction in the prediction cache or the prediction accuracy in the target cache item is less than a preset threshold; setting the vtype state of the target vsetvl instruction to valid when it is determined that there is a target cache item corresponding to the target vsetvl instruction in the prediction cache and the prediction accuracy in the target cache item is greater than or equal to a preset threshold.

[0068] In this embodiment, when the target cache item corresponding to the target vsetvl instruction does not exist in the prediction cache or when the target cache item exists but the prediction accuracy in the target cache item is less than a preset threshold, the vtype status of the target vsetvl instruction can be set to invalid. When it is determined that the target cache item corresponding to the target vsetvl instruction exists in the prediction cache and the prediction accuracy in the target cache item is greater than or equal to the preset threshold, the vtype status of the target vsetvl instruction can be set to valid. In some embodiments of the present specification, the vtype status of the target vsetvl instruction can be recorded in a register. The invalid vtype status indicates that the vtype value of the target vsetvl instruction is unknown. The valid vtype status indicates that the target vsetvl instruction has a predicted vtype value. In the above manner, it can be recorded whether the target vsetvl instruction has a corresponding vtype value.

[0069] In some embodiments of the present specification, the method may further include: when decoding the target vector instruction, if the vtype state of the target vsetvl instruction is valid, determining the predicted vtype value of the target vsetvl instruction as the vtype value of the target vector instruction; the target vector instruction is the next vector instruction of the target vsetvl instruction.

[0070] In this embodiment, during the decoding phase, before decoding the next vector instruction following the target vsetvl instruction that requires a vtype value (i.e., the target vector instruction), the vtype status of the target vsetvl instruction can be read. If the vtype status of the target vsetvl instruction is valid, the predicted vtype value of the target vsetvl instruction is determined as the vtype value of the target vector instruction. The target vector instruction can then be decoded based on the vtype value of the target vector instruction. In this manner, the vtype value of the target vector instruction can be obtained during the decoding phase without waiting for multiple clock cycles, thereby improving the execution efficiency of the CPU pipeline.

[0071] In some embodiments of the present specification, the method may further include: when decoding a target vector instruction, if the vtype status of the target vsetvl instruction is invalid, stopping decoding at the target vector instruction until the vtype status of the target vsetvl instruction becomes valid; the target vector instruction is the vector instruction following the target vsetvl instruction. In this embodiment, if the vtype status of the target vsetvl instruction is invalid, it indicates that no predicted vtype value exists for the target vsetvl instruction. Therefore, decoding may be stopped at the first target vector instruction that requires the vtype value of the target vsetvl instruction until the vtype status of the target vsetvl instruction becomes valid. In one embodiment, after the target vsetvl instruction is executed, the accurate vtype value of the target vsetvl instruction can be obtained, at which point the status of the target vsetvl instruction can be updated to valid. At this point, the vtype value of the target vsetvl instruction can be used as the vtype value of the target vector instruction and decoded. In this manner, a decrease in CPU pipeline execution speed caused by an incorrect vtype value of the target vector instruction can be avoided.

[0072] In some embodiments of the present specification, the method may further include: executing the target vsetvl instruction to obtain a target vtype value of the target vsetvl instruction; when there is a target cache item corresponding to the target vsetvl instruction in the prediction cache, determining whether the target vtype value is consistent with the vtype value in the target cache item; when it is determined that the target vtype value is consistent with the vtype value in the target cache item, increasing the prediction accuracy in the target cache item.

[0073] In this embodiment, during the execution phase, the target vsetvl instruction can be executed to obtain the target vtype value of the target vsetvl instruction, that is, the accurate vtype value. In the case where there is a target cache item corresponding to the target vsetvl instruction in the prediction cache, it can be determined whether the target vtype value is consistent with the vtype value in the target cache item. If they are consistent, the prediction accuracy in the target cache item can be increased. For example, in the case where the prediction accuracy in the target cache item is less than the maximum value, the prediction accuracy in the target cache item can be increased by 1. In the above manner, in the case where the vtype value in the target cache item is consistent with the vtype of the target vsetvl instruction, the prediction accuracy in the target cache item can be increased for subsequent vtype value prediction.

[0074] In some embodiments of the present specification, the method may further include: in the case where it is determined that the target vtype value is inconsistent with the vtype value in the target cache item, reducing the prediction accuracy in the target cache item, and updating the vtype value in the target cache item to the target vtype value. In the present embodiment, in the case where the target vtype value of the target vsetvl instruction is inconsistent with the vtype value in the target cache item, the prediction accuracy in the target cache item may be reduced, and the vtype value in the target cache item may be updated to the target vtype value. For example, in the case where the prediction accuracy in the target cache item is greater than zero, the prediction accuracy in the target cache item may be reduced by 1, and the vtype value in the target cache item may be updated. In the above manner, the probability of incorrect prediction of the vtype value of the target vsetvl instruction may be reduced, and the accuracy of subsequent vtype value predictions may be improved.

[0075] In some embodiments of the present specification, the method may further include: in a case where it is determined that the target vtype value is inconsistent with the vtype value in the target cache item, determining whether the vtype value in the target cache item has been used as the vtype value of the target vector instruction; the target vector instruction is the next instruction of the target vsetvl instruction; in a case where it is determined that the vtype value in the target cache item has been used as the vtype value of the target vector instruction, resetting the vtype value of the target vector instruction to the target vtype value, and flushing the pipeline starting from the target vector instruction.

[0076] In this embodiment, when the target vtype value of the target vsetvl instruction is inconsistent with the vtype value in the target cache item, it is also necessary to determine whether to use the vtype value in the target cache item as the vtype value of the target vector instruction. The target vector instruction is the next vector instruction after the target vsetvl instruction, and the vtype values ​​of the two are the same. If the vtype value in the target cache item has been used as the vtype value of the target vector instruction, it means that the vtype value of the target vector instruction is incorrect, and it is necessary to reset the vtype value of the target vector instruction to the target vtype value, and refresh the pipeline starting from the target vector instruction and re-execute. In this way, when the vtype value prediction error occurs, correction can be made in a timely manner.

[0077] In some embodiments of the present specification, the method may further include: when there is no target cache entry corresponding to the target vsetvl instruction in the prediction cache, determining whether there is an available cache entry in the prediction cache; when it is determined that there is an available cache entry in the prediction cache, writing the target vtype value and target address hash of the target vsetvl instruction into the available cache entry, and initializing the prediction accuracy in the available cache entry.

[0078] In this embodiment, if the target cache entry corresponding to the target vsetvl instruction does not exist in the prediction cache, it can be determined whether there is an available cache entry in the prediction cache. The available cache entry can be an unused cache entry in the prediction cache. If there is an available cache entry, the available cache entry can be used as the target cache entry corresponding to the target vsetvl instruction. The target vtype value and target address hash of the target vsetvl instruction can be written into the target cache entry, and the prediction accuracy in the target cache entry can be initialized. In one embodiment, the prediction accuracy can be set to an initial value. In another embodiment, the target cache can also store an initial value and a preset threshold. In the above manner, after executing the target vsetvl instruction, if there is no target cache entry in the prediction cache that matches the target address hash of the target vsetvl instruction, an available cache entry in the prediction cache can be allocated to the target vsetvl instruction as the target cache entry, and the target address hash, target vtype value, and prediction accuracy can be recorded in the target cache entry.

[0079] In some embodiments of the present specification, the method may further include: in a case where it is determined that there is no available cache item in the prediction cache, determining a cache item with the lowest prediction accuracy from multiple cache items in the prediction cache; writing the target vtype value and target address hash of the target vsetvl instruction to the cache item with the lowest prediction accuracy, and initializing the prediction accuracy in the cache item with the lowest prediction accuracy.

[0080] In this embodiment, if no cache is available in the prediction cache, the cache entry with the lowest prediction accuracy among the multiple cache entries in the prediction cache can be assigned to the target vsetvl instruction as the target cache. The target vtype value and target address of the target vsetvl instruction can be hashed and written into the target cache, and the prediction accuracy in the target cache can be initialized to an initial value. In this manner, the cache entry with low prediction accuracy can be freed up to be assigned to the target vsetvl instruction.

[0081] In some embodiments of the present specification, the method may further include: if it is determined that no available cache items exist in the prediction cache, determining a cache item whose prediction accuracy is lower than a preset threshold from multiple cache items in the prediction cache; writing the target vtype value and target address hash of the target vsetvl instruction into the cache item whose prediction accuracy is lower than the preset threshold, and initializing the prediction accuracy of the cache item whose prediction accuracy is lower than the preset threshold. Cache items whose vtype value prediction accuracy is lower than the corresponding preset threshold (i.e., cannot be used for prediction) may be vacated and allocated to the target vsetvl instruction.

[0082] In some embodiments of the present specification, the method may further include: if it is determined that no available cache entry exists in the prediction cache, determining the least frequently used cache entry from multiple cache entries in the prediction cache; hashing the target vtype value and target address of the target vsetvl instruction into the least frequently used cache entry, and initializing the prediction accuracy of the least frequently used cache entry. The cache entry that has been used the least frequently for vtype value prediction may be vacated and allocated to the target vsetvl instruction.

[0083] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. For details, please refer to the description of the aforementioned related processing embodiments, and no further description is given here.

[0084] The foregoing description of this specification describes specific embodiments. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0085] The above method is described below with reference to a specific embodiment. However, it should be noted that this specific embodiment is only for better illustrating this specification and does not constitute an improper limitation to this specification.

[0086] This specific embodiment provides a method for determining the configuration of a RISC-V vector instruction. This invention proposes a technical solution for accurately predicting the vtype value of a vsetvl instruction. A vtype prediction buffer (VPB) is provided in the instruction decode unit. The prediction buffer can have multiple VPB entries (e.g., 8 or 16 entries), each of which contains the following: PC Tag, CONF_CNT, VLMUL, VSEW, VMA, and VTA.

[0087] Among them, PC Tag is the hash result of the vsetvl instruction address, and its number of digits is much smaller than the number of bits of PC itself (32 or 64 bits). CONF_CNT is used to record the prediction accuracy of this item. It has three corresponding parameters: bit number, INIT_VALUE and PRED_THRES. Among them, bit number can be 1 bit or more. INIT_VALUE is the initial value set to CONF_CNT when a vsetvl instruction is first assigned a VPB item. PRED_THRES is the preset threshold. When CONF_CNT of a hit VPB item is greater than or equal to PRED_THRES, the item can be used for prediction; otherwise, the item is not used for prediction. PRED_THRES can be equal to INIT_VALUE, or other values ​​can be selected. For example, it can be greater than INIT_VALUE. VLMUL / VSEW / VMA / VTA are the same fields in vtype. When predicting, these values ​​are used as prediction values. LMUL is controlled by the VLMUL field in the vtype vector VCSR, with possible values ​​of [1 / 8, 1 / 4, 1 / 2, 1, 2, 4, 8]. In the RISC-V vector architecture, a vector register contains multiple metadata. SEW is controlled by the VSEW field in the vtype vector VCSR. SEW can be an 8-, 16-, 32-, or 64-bit integer or a 32- or 64-bit floating point. The VMA field indicates how masked elements are handled. The VMA field also indicates how tail elements are handled.

[0088] During the decoding stage, there is a register used to save the current vtype value and its valid bits.

[0089] For Current_vtype_valid, 1 is a valid bit. If the value is 1, the subsequent vector instruction uses the value in Current_vtype_value as its own vtype value. Otherwise, there is no valid vtype value.

[0090] Current_vtype_value is the current vtype value.

[0091] The vsetivli and vsetvli instructions obtain their vtype values ​​during the decode pipeline stage and update Current_vtype_valid and Current_vtype_value. In this solution, if the vsetvl instruction hits a VPB and its CONF_CNT is greater than or equal to PRED_THRES, its predicted vtype value is placed in Current_vtype_value and Current_vtype_valid is set to 1. If vsetvl does not hit a VPB, or if the CONF_CNT of the VPB entry that hits is less than PRED_THRES, Current_vtype_valid is set to 0.

[0092] If Current_vtype_valid is 1, if a vector instruction using the vtype value enters the decode pipeline, the decoder uses Current_vtype_value to decode the vector instruction. If Current_vtype_valid is 0, the decoder stops decoding at the first vector instruction using vtype and resumes decoding after Current_vtype_valid is set to 1.

[0093] Please refer to Figure 3 , shows a flowchart of the vsetvl instruction decoding stage. Whether to make a prediction is determined based on whether the VPB is hit and the CONF_CNT value of the VPB entry. Figure 3 As shown, the vsetvl instruction can be decoded. Afterwards, the PC Tag can be calculated. Based on the PC Tag, it can be determined whether there is a target VPB item corresponding to the vsetvl instruction in the prediction cache. If there is no target VPB item corresponding to the vsetvl instruction, the vtype value is not predicted. If so, it is determined whether the CONF_CNT in the target VPB item is greater than or equal to PRED_THRES. If so, the vtype value in the target VPB is determined as the vtype value of the vsetvl instruction, written into Current_vtype_value, and Current_vtype_valid is set to 1. If the CONF_CNT in the target VPB item is less than PRED_THRES, the vtype value is not predicted. When the vtype value is not predicted, Current_vtype_valid is set to 0.

[0094] Please refer to Figure 4 , shows the flow chart of vsetvl execution phase. Figure 4As shown, if the vtype value is predicted incorrectly, the correct vtype value needs to be reset to Current_vtype_value, and the pipeline needs to be flushed starting from the first vector instruction (including this vector instruction) after the incorrectly predicted vsetvl. Depending on whether the prediction is correct, the CONF_CNT field in the VPB entry needs to be incremented (correct prediction) or decremented (incorrect prediction).

[0095] If there is no corresponding VPB entry for this vsetvl, a VPB entry needs to be allocated for this vsetvl. If the prediction cache is full, a VPB entry needs to be selected for replacement. The replacement algorithm used in this solution is: select the entry with the smallest CONF_CNT for replacement. If multiple VPB entries have the smallest CONF_CNT value, select the first entry (i.e., the entry with the smallest index) for replacement.

[0096] Specifically, execute a vsetvl instruction to determine whether there is a corresponding VPB entry. If there is, determine whether the VPB entry is accurate according to the execution result. If it is accurate, determine whether CONF_CNT is already the maximum value. If it is not the maximum value, then CONF_CNT++. If the VPB entry is inaccurate, determine whether CONF_CNT is greater than 0. If it is, then CONF_CNT--, and update the vtype value of the VPB entry. Then, determine whether to use the VPB entry for prediction. If so, reset the correct vtype value and flush the pipeline starting from the first vector instruction after the incorrect prediction.

[0097] Through the above solution, the vector instructions after vsetvl can be decoded using the predicted vtype value, without waiting for multiple clock cycles in the decoding stage to obtain the accurate vtype value. This can improve the throughput of vector instructions in the CPU pipeline, thereby improving the performance of the CPU in processing vector instructions.

[0098] In this solution, if the VPB is not hit or the CONF_CNT of the VPB entry < PRED_THRES, no prediction is performed. At this time, Current_vtype_valid is set to 0, and the decoder will stop decoding at the first vector instruction that uses the vtype value and will resume decoding only after Current_vtype_valid is set to 1. Another solution is not to set Current_vtype_valid to 0 in this case, so that the decoder will continue to decode the vector instructions using the old vtype value. In this solution, it is possible that the number of incorrect vtype predictions will increase significantly, thus affecting the overall performance of the CPU.

[0099] Based on the same inventive concept, a RISC-V vector instruction configuration determination device is also provided in the embodiments of this specification, as described in the following embodiments. Since the principle of solving the problem by the RISC-V vector instruction configuration determination device is similar to that of the RISC-V vector instruction configuration determination method, the implementation of the RISC-V vector instruction configuration determination device can refer to the implementation of the RISC-V vector instruction configuration determination method, and the repeated parts will not be repeated. As used below, the term "unit" or "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceived. Figure 5 This is a structural block diagram of a RISC-V vector instruction configuration determination device according to an embodiment of this specification, such as Figure 5 As shown, it includes: a decoding module 501, a judgment module 502 and a determination module 503. The structure is described below.

[0100] The decoding module 501 is used to decode the target vsetvl instruction.

[0101] The judgment module 502 is used to perform a hash calculation on the address of the target vsetvl instruction to obtain a target address hash; it is also used to determine whether there is a target cache item corresponding to the target vsetvl instruction in the prediction cache based on the target address hash; the prediction cache includes multiple cache items; each cache item in the multiple cache items contains an address hash, a prediction accuracy and a vtype value.

[0102] The determination module 503 is used to determine the vtype value in the target cache item as the predicted vtype value of the target vsetvl instruction if the prediction accuracy in the target cache item is greater than or equal to a preset threshold when it is determined that there is a target cache item corresponding to the target vsetvl instruction in the prediction cache.

[0103] In one embodiment, the determination module is further used to: not predict the vtype value of the target vsetvl instruction if there is no target cache entry corresponding to the target vsetvl instruction in the prediction cache or the prediction accuracy in the target cache entry is less than a preset threshold.

[0104] In one embodiment, the determination module is further used to: set the vtype state of the target vsetvl instruction to invalid when the target cache item corresponding to the target vsetvl instruction does not exist in the prediction cache or the prediction accuracy in the target cache item is less than a preset threshold; set the vtype state of the target vsetvl instruction to valid when it is determined that the target cache item corresponding to the target vsetvl instruction exists in the prediction cache and the prediction accuracy in the target cache item is greater than or equal to the preset threshold.

[0105] In one embodiment, the determination module is further configured to: when decoding a target vector instruction, if the vtype state of the target vsetvl instruction is valid, determine the predicted vtype value of the target vsetvl instruction as the vtype value of the target vector instruction; the target vector instruction is the next vector instruction of the target vsetvl instruction.

[0106] In one embodiment, the determination module is further configured to: when decoding a target vector instruction, if the vtype status of the target vsetvl instruction is invalid, stop decoding at the target vector instruction until the vtype status of the target vsetvl instruction is valid; the target vector instruction is the next vector instruction of the target vsetvl instruction.

[0107] In one embodiment, the device also includes an execution module, which is used to: execute the target vsetvl instruction to obtain a target vtype value of the target vsetvl instruction; when a target cache item corresponding to the target vsetvl instruction exists in the prediction cache, determine whether the target vtype value is consistent with the vtype value in the target cache item; when it is determined that the target vtype value is consistent with the vtype value in the target cache item, increase the prediction accuracy in the target cache item.

[0108] In one embodiment, the execution module is further configured to: reduce the prediction accuracy in the target cache entry when it is determined that the target vtype value is inconsistent with the vtype value in the target cache entry.

[0109] In one embodiment, the execution module is further configured to: if it is determined that the target vtype value is inconsistent with the vtype value in the target cache item, determine whether the vtype value in the target cache item has been used as the vtype value of the target vector instruction; the target vector instruction is the next instruction of the target vsetvl instruction; if it is determined that the vtype value in the target cache item has been used as the vtype value of the target vector instruction, reset the vtype value of the target vector instruction to the target vtype value, and flush the pipeline starting from the target vector instruction.

[0110] In one embodiment, the device also includes an allocation module, which is used to: when there is no target cache item corresponding to the target vsetvl instruction in the prediction cache, determine whether there is an available cache item in the prediction cache; when it is determined that there is an available cache item in the prediction cache, write the target vtype value and target address hash of the target vsetvl instruction into the available cache item, and initialize the prediction accuracy in the available cache item.

[0111] In one embodiment, the allocation module is also used to: when it is determined that there is no available cache item in the prediction cache, determine the cache item with the lowest prediction accuracy from multiple cache items in the prediction cache; write the target vtype value and target address hash of the target vsetvl instruction into the cache item with the lowest prediction accuracy, and initialize the prediction accuracy in the cache item with the lowest prediction accuracy.

[0112] The embodiments of this specification also provide a computer device that can be based on the RISC-V vector instruction configuration determination method provided in the embodiments of this specification. The computer device may specifically include an input device, a processor, and a memory. The memory is used to store processor-executable instructions. When the processor executes the instructions, the steps of the RISC-V vector instruction configuration determination method described in any of the above embodiments are implemented.

[0113] In this embodiment, the input device can specifically be one of the primary devices for exchanging information between a user and a computer system. The input device can include a keyboard, mouse, camera, scanner, light pen, handwriting input tablet, voice input device, etc.; the input device is used to input raw data and programs for processing these data into the computer. The input device can also receive data transmitted from other modules, units, and devices. The processor can be implemented in any appropriate manner. For example, the processor can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (such as software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers, etc. The memory can specifically be a memory device used to store information in modern information technology. The memory can include multiple levels. In digital systems, anything that can store binary data can be considered a memory device. In integrated circuits, a circuit with storage functionality that does not have a physical form is also called a memory device, such as a RAM or FIFO. In systems, a physical storage device is also called a memory device, such as a memory stick or a TF card.

[0114] In this embodiment, the specific functions and effects achieved by the computer device can be explained in comparison with other embodiments and will not be repeated here.

[0115] An embodiment of this specification also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the RISC-V vector instruction configuration determination method described in any of the above embodiments.

[0116] In an embodiment of the present specification, a computer storage medium based on the RISC-V vector instruction configuration determination method is also provided, wherein the computer storage medium stores computer program instructions, and when the computer program instructions are executed, the steps of the RISC-V vector instruction configuration determination method described in any of the above embodiments are implemented.

[0117] In this embodiment, the storage medium includes, but is not limited to, random access memory (RAM), read-only memory (ROM), cache, hard disk drive (HDD), or memory card. The memory can be used to store computer program instructions. The network communication unit can be an interface configured in accordance with the standards specified by the communication protocol for network connection communication.

[0118] In this embodiment, the functions and effects specifically implemented by the program instructions stored in the computer storage medium can be explained in comparison with other embodiments and will not be repeated here.

[0119] Obviously, those skilled in the art should understand that the various modules or steps of the above-mentioned embodiments of this specification can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices. Alternatively, they can be implemented using program code executable by the computing device, so that they can be stored in a storage device and executed by the computing device. In some cases, the steps shown or described can be performed in a different order than herein, or they can be made into separate integrated circuit modules, or multiple modules or steps can be made into a single integrated circuit module for implementation. Thus, the embodiments of this specification are not limited to any specific combination of hardware and software.

[0120] It should be understood that the above description is intended to be illustrative and not limiting. Numerous embodiments and applications beyond the examples provided will be readily apparent to those skilled in the art upon reading the above description. Therefore, the scope of this specification should not be determined with reference to the above description, but rather with reference to the preceding claims, along with the full scope of equivalents to which such claims are entitled.

[0121] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Those skilled in the art will readily appreciate that various modifications and variations to the embodiments of this specification are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this specification shall be within the scope of protection of this specification.

Claims

1. A method for determining RISC-V vector instruction configuration, characterized in that: include: Decoding the target vsetvl instruction; performing hash calculation on the address of the target vsetvl instruction to obtain a target address hash; Determine, based on the target address hash, whether there is a target cache entry corresponding to the target vsetvl instruction in the prediction cache; the prediction cache includes multiple cache entries; each cache entry in the multiple cache entries includes an address hash, a prediction accuracy, and a vtype value; In a case where it is determined that a target cache entry corresponding to the target vsetvl instruction exists in the prediction cache, if the prediction accuracy in the target cache entry is greater than or equal to a preset threshold, determining the vtype value in the target cache entry as the predicted vtype value of the target vsetvl instruction; The method further comprises: Executing the target vsetvl instruction to obtain a target vtype value of the target vsetvl instruction; If a target cache entry corresponding to the target vsetvl instruction exists in the prediction cache, determining whether the target vtype value is consistent with the vtype value in the target cache entry; In a case where it is determined that the target vtype value is consistent with the vtype value in the target cache entry, the prediction accuracy in the target cache entry is increased.

2. The RISC-V vector instruction configuration determination method according to claim 1, characterized in that: Also includes: If the target cache entry corresponding to the target vsetvl instruction does not exist in the prediction cache or the prediction accuracy of the target cache entry is less than a preset threshold, the vtype value of the target vsetvl instruction is not predicted.

3. The RISC-V vector instruction configuration determination method according to claim 2, characterized in that: Also includes: If the target cache entry corresponding to the target vsetvl instruction does not exist in the prediction cache or the prediction accuracy of the target cache entry is less than a preset threshold, setting the vtype state of the target vsetvl instruction to invalid; When it is determined that a target cache entry corresponding to the target vsetvl instruction exists in the prediction cache and the prediction accuracy in the target cache entry is greater than or equal to a preset threshold, the vtype state of the target vsetvl instruction is set to valid.

4. The RISC-V vector instruction configuration determination method according to claim 3, characterized in that: Also includes: When decoding a target vector instruction, if the vtype state of the target vsetvl instruction is valid, the predicted vtype value of the target vsetvl instruction is determined as the vtype value of the target vector instruction; the target vector instruction is the next vector instruction of the target vsetvl instruction.

5. The RISC-V vector instruction configuration determination method according to claim 3, characterized in that: Also includes: When decoding a target vector instruction, if the vtype status of the target vsetvl instruction is invalid, decoding is stopped at the target vector instruction until the vtype status of the target vsetvl instruction is valid; the target vector instruction is the next vector instruction of the target vsetvl instruction.

6. The RISC-V vector instruction configuration determination method according to claim 1, characterized in that: Also includes: When it is determined that the target vtype value is inconsistent with the vtype value in the target cache item, the prediction accuracy in the target cache item is reduced, and the vtype value in the target cache item is updated to the target vtype value.

7. The RISC-V vector instruction configuration determination method according to claim 1, characterized in that: Also includes: If it is determined that the target vtype value is inconsistent with the vtype value in the target cache entry, determining whether the vtype value in the target cache entry has been used as the vtype value of the target vector instruction; the target vector instruction is the instruction next to the target vsetvl instruction; If it is determined that the vtype value in the target cache entry has been used as the vtype value of the target vector instruction, the vtype value of the target vector instruction is reset to the target vtype value, and the pipeline is flushed starting from the target vector instruction.

8. The RISC-V vector instruction configuration determination method according to claim 1, characterized in that: Also includes: If the target cache entry corresponding to the target vsetvl instruction does not exist in the prediction cache, determining whether there is an available cache entry in the prediction cache; When it is determined that there is an available cache entry in the prediction cache, the target vtype value and target address hash of the target vsetvl instruction are written into the available cache entry, and the prediction accuracy in the available cache entry is initialized.

9. The RISC-V vector instruction configuration determination method according to claim 8, characterized in that: Also includes: In the case where it is determined that there is no available cache item in the prediction cache, determining a cache item with the lowest prediction accuracy from the multiple cache items in the prediction cache; The target vtype value and target address hash of the target vsetvl instruction are written into the cache entry with the lowest prediction accuracy, and the prediction accuracy in the cache entry with the lowest prediction accuracy is initialized.

10. A RISC-V vector instruction configuration determination device, characterized in that: include: A decoding module, used to decode the target vsetvl instruction; a judgment module, configured to perform a hash calculation on the address of the target vsetvl instruction to obtain a target address hash; and further configured to judge, based on the target address hash, whether a target cache entry corresponding to the target vsetvl instruction exists in a prediction cache; the prediction cache includes a plurality of cache entries; each of the plurality of cache entries includes an address hash, a prediction accuracy, and a vtype value; a determination module configured to, when determining that a target cache entry corresponding to the target vsetvl instruction exists in the prediction cache, determine the vtype value in the target cache entry as the predicted vtype value of the target vsetvl instruction if the prediction accuracy in the target cache entry is greater than or equal to a preset threshold; The device also includes an execution module, which is used to: execute the target vsetvl instruction to obtain a target vtype value of the target vsetvl instruction; if a target cache item corresponding to the target vsetvl instruction exists in the prediction cache, determine whether the target vtype value is consistent with the vtype value in the target cache item; if it is determined that the target vtype value is consistent with the vtype value in the target cache item, increase the prediction accuracy in the target cache item.

11. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the instructions are executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

12. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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