A neural network hardware centroid calculation method for cross-bar position-sensitive anode
By deploying the U-Net neural network model in the cross-strip position-sensitive anode, the speed and accuracy issues of the centroid algorithm were resolved, efficient parallel computing was achieved, and imaging performance was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN INST OF OPTICS & PRECISION MECHANICS CHINESE ACAD OF SCI
- Filing Date
- 2024-07-30
- Publication Date
- 2026-04-21
AI Technical Summary
Existing centroid algorithms are limited in processing speed, have difficulty in guaranteeing computational accuracy, and are difficult to implement in hardware, especially when processing large amounts of data.
The model is trained using a U-Net neural network and deployed on an FPGA. Centroid calculation is performed through data preprocessing and convolutional neural networks. Efficient parallel computing is achieved by leveraging the parallel characteristics and pipeline architecture of the hardware circuit.
It improves the accuracy of centroid calculation under noise interference, reduces calculation time, and enhances imaging spatial resolution and processing speed.
Smart Images
Figure CN119026655B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of neural network model training and data processing technology, specifically relating to a neural network hardware centroid calculation method for cross-bar position-sensitive anodes. Background Technology
[0002] Single-photon cameras, as a cutting-edge optical detection technology, have played an indispensable role in astronomy, physics, and other scientific research fields. Especially in deep space exploration, Earth ionospheric observation, and biological behavior analysis, these cameras have demonstrated outstanding performance and broad application prospects. However, the front-end anode structure plays a decisive role in achieving the high performance of such instruments. This structure not only affects the clarity of the image but also determines the subsequent electronic readout method, thus directly impacting the detection accuracy. In 1974, Lampton's team first proposed the resistive morphological anode. This technology effectively solved the various challenges faced by using traditional television camera tube imaging systems in space exploration missions in terms of equipment size, complexity, cost, weight, and information loss. This innovation enabled scientists to conduct deep space exploration and environmental monitoring more efficiently and also laid the foundation for subsequent anode technology development. To achieve a wider imaging area and higher resolution, various anode structures have emerged, such as wedge-shaped anodes, delay line anodes, and cross-delay line anodes. Each new anode structure is a further development based on previous technologies, aiming to push the performance limits of single-photon cameras. Among them, the Cross Strip (XS) position-sensitive anode proposed by Siegmund's team employs two layers of elongated, perpendicular strip electrodes that sample the spatial distribution of charge events departing from the microchannel plate (MCP). The signal received by each electrode is used to precisely determine the center location of the event, a unique design that significantly improves detection efficiency and accuracy. Compared to other detector structures, the XS anode detector features high parallelism, high spatial resolution, high temporal resolution, and a longer lifespan. However, this results in the generation of large amounts of data, placing higher demands on the processing capabilities of the back-end readout circuitry.
[0003] like Figure 1As shown, the front end of the cross-strip single-photon detector mainly consists of an entrance window, a photocathode, an MCP stack, and a position-sensitive anode. Both the MCP stack and the position-sensitive anode need to operate in a vacuum environment. Photons pass through the entrance window and strike the photocathode, where they are converted into photoelectrons. These photoelectrons are then accelerated and multiplied in the MCP stack, eventually forming an electron cloud composed of numerous electrons. This cloud then strikes the XS anode plate, where the charge is separated by vertically isolated and orthogonally aligned conductive microstrip electrodes. Each strip collects charge and transfers it to the detector port. Figure 2 As shown, taking the X-direction as an example, the charge on each anode strip reaches the charge-sensitive amplifier at the back end, where it is shaped and amplified into a voltage signal that can be acquired by the ADC. Subsequently, the voltage signals corresponding to the strips are sampled in parallel by the ADC. Finally, these digital signals are processed by FPGAs in two directions respectively to calculate the center coordinates of the electron cloud in the X and Y directions. The two FPGAs interact to obtain the center coordinates (X, Y). Each coordinate is transmitted to the computer via Gigabit Ethernet.
[0004] The main performance indicators of the XS single-photon detector are high spatial resolution and high count rate. The centroid algorithm is one of the main factors affecting its performance. Currently known centroid algorithms include simple weighted averaging, function fitting, and interpolation convolution.
[0005] The simple weighted average algorithm calculates the centroid by averaging the data from each strip based on the mathematical definition of the centroid. This method is easier to implement using FPGA. The calculation formula is shown below. Taking the x-direction as an example, Xi represents the channel i where the event occurs, l is the lower boundary of the channel, n is the upper boundary of the channel, and Vi is the state value (peak value, average value, etc.) of the i-th channel when the event occurs. This method mainly involves simple and independent mathematical operations, making it suitable for implementation on FPGA. Its advantages include low computational load, extremely high speed, and small fluctuations in the calculation results. However, its disadvantage is that the limited number of event channels (limited available weighted data) can affect accuracy, causing the result to deviate from the actual value.
[0006]
[0007] Function fitting algorithms refer to using software to fit the charge distribution of a band. In early international solutions, the FPGA only served as a bridge between the ADC board and the PC, receiving data and sending it to the host computer. In the host computer, software reads the sampled values of each channel, compares them, and determines the channel position corresponding to the sampling peak. Then, function fitting is performed, selecting 3 to 7 signal points adjacent to the channel corresponding to the sampling peak and substituting them into the function for fitting calculation (Gaussian function yields the best results). The advantage of this approach is that it only requires comparing the sampled values of each channel to find a few signal points near the sampling peak. Furthermore, using software processing makes implementation simpler and easier. It also provides good resolution at edges because even if the electron cloud falls at the edge, only a few points are needed to calculate the result. However, the software code runs sequentially, resulting in slow processing speed. To achieve high fitting accuracy, multiple iterations with small steps are required, which consumes significant time and computing power.
[0008] Interpolation convolution algorithms refer to methods that use interpolation convolution to find the centroid of a charge cloud. This involves convolving the charge distribution of a strip with a centrosymmetric bipolar convolution kernel based on the average charge distribution. The zeros of the convolution result, interpolated to the sub-strip positions, are interpreted as the centroid of the charge cloud. The advantage of this method is its insensitivity to any baseline shift because the sum of the kernels is zero. This kernel also acts as a matched filter, as it is based on the average charge distribution, thus weighting strips with higher signal-to-noise ratios accordingly. The disadvantage of this method is that, if implemented using an FPGA for integrated ADC acquisition and computation, determining different Gaussian kernels for electron clouds of different sizes is a complex process.
[0009] In summary, the centroid algorithm currently faces three main challenges: First, the XS anode signal path is multiplied, which affects the processing speed of the centroid algorithm when dealing with large amounts of data; second, although the XS anode signal path is multiplied, the number of strips received from the falling electron cloud is relatively small, that is, there are few high-value signal paths and few high-value data, making it difficult to guarantee the calculation accuracy of the centroid algorithm; and third, there are issues with the hardware implementation and deployment of the centroid algorithm on FPGAs. Summary of the Invention
[0010] To overcome the shortcomings of the centroid algorithm, such as limited processing speed, difficulty in guaranteeing computational accuracy, and difficulty in hardware implementation, this invention proposes a neural network hardware centroid calculation method for cross-strip position-sensitive anodes.
[0011] The technical solution adopted by this invention to solve its technical problem is:
[0012] A neural network hardware centroid calculation method for cross-strip position-sensitive anodes includes the following steps:
[0013] Step S1, Model Establishment
[0014] The dataset was created by combining the measured dataset generated from the anode readout signal and the simulated dataset generated by MATLAB. Training and test sets were randomly generated from this dataset. A U-Net neural network was selected as the model, and Python was used for training. After training, the model parameters were exported.
[0015] Step S2, Hardware Implementation
[0016] The U-Net neural network, combined with the derived model parameters, is deployed on an FPGA. The algorithm deployment utilizes an FPGA chip. The FPGA chip includes a processor unit (PS), a programmable logic unit (PL), and an AXI bus. The PS and PL work collaboratively. The convolutional neural network (CNN) algorithm is implemented in the PL, while the PS controls the data flow. Data is transmitted between the PS and PL via the AXI bus. This results in an FPGA chip with centroid calculation capabilities.
[0017] The above-described centroid calculation method, specifically step S1 model establishment, further includes:
[0018] The signal collected by the cross-strip anode plate is then amplified by a charge-sensitive amplifier, and the ADC acquires the voltage signal corresponding to each strip.
[0019] An ideal Gaussian signal was generated using MATLAB. The ideal Gaussian signal is a noise-free original electron cloud. The noise-free original electron cloud was superimposed with noise signals of different amplitudes and frequencies to form a simulated dataset. The peak values of the small Gaussian signals obtained by striping in the x and y directions were superimposed to obtain a two-dimensional matrix as the measured dataset. The measured dataset and the simulated dataset were then combined to form a dataset.
[0020] The U-Net neural network is trained using a training set. The model training process consists of two phases: the forward propagation phase, where training data is propagated from lower to higher levels; and the backpropagation phase, where the error is propagated from higher to lower levels when the forward propagation result does not match the expectation. The distance between the centroids of the x-coordinates and y-coordinates in the backpropagation phase is used as the loss function, and the network parameters are optimized using the backpropagation algorithm. In the network parameter optimization, the centroid calculation error is reduced, and the model training is complete when the centroid calculation error is lower than a predetermined value.
[0021] In the above centroid calculation method, the dataset consists of 10,000 images, with 80% randomly selected as the training set and the remaining 20% as the test set.
[0022] The above-described centroid calculation method, wherein step S2 is implemented in hardware, further includes:
[0023] The programmable logic unit (PL) includes a data receiving and preprocessing module and a convolutional neural network module, while the processor unit (PS) includes a centroid calculation result output module.
[0024] The data is read from the ADC, converted into a two-dimensional matrix by the data receiving and preprocessing module, stored in the data memory RAM, and then sent to the convolutional neural network module via the AXI bus.
[0025] In the above-described centroid calculation method, the process of converting the data preprocessing module into a two-dimensional matrix graphic in step S2 hardware implementation is as follows:
[0026] The ADC reads the strip information into x-channel and y-channel, and performs parallel addition operations on the peak values of any x-channel and y-channel.
[0027] In the above-described centroid calculation method, the process of implementing the Convolutional Neural Network (CNN) algorithm in the PL (Programming Language) during step S2 hardware implementation is as follows:
[0028] The convolutional neural network module includes an image processing submodule and a data caching submodule. The image processing submodule comprises convolutional layer modules, max / min pooling layer modules, activation function modules, and fully connected layer modules, using a pipelined architecture to connect the various layers of the convolutional neural network within it. The data caching submodule includes a data flow control module, a weight storage module, a bias storage module, and RAM. The data flow control module receives preprocessed image data via the AXI bus, moves the weight and bias data to participate in neural network computation, and obtains the centroid calculation result. This centroid calculation result is sent to RAM and then back to the PS end via the AXI bus.
[0029] The above-mentioned centroid calculation method also includes step S3, in which the centroid calculation result output module sends the centroid calculation result to the host computer.
[0030] The beneficial effects of this invention are:
[0031] A neural network hardware centroid calculation method for cross-strip position-sensitive anodes is proposed. The method uses a convolutional neural network to train the model and optimizes the centroid error of noisy and noiseless electron clouds through U-Net. This method can reduce noise interference to a certain extent, effectively solve the problem of high-precision centroid calculation under noise interference, and improve the spatial resolution of imaging.
[0032] A neural network hardware centroid calculation method for cross-strip position-sensitive anodes addresses the problem of multiple signal paths, large data volume, and long calculation time for centroids in XS anodes. It fully utilizes the high-speed parallel characteristics of hardware circuits, preprocesses the strip signal, directly performs parallel addition operations on the peak values of arbitrary x and y channels to convert them into the prediction pattern required by the neural network, and improves the calculation speed by combining a pipeline architecture, thereby reducing the time for centroid calculation.
[0033] A neural network hardware centroid calculation method for cross-strip position-sensitive anodes addresses the problem of numerous signal paths but few high-value signal paths and data in XS anodes. This method utilizes convolutional neural networks to extract local features and reduce dimensionality of images, thereby capturing key information from a large number of signals, reducing the number of parameters and computational load, and lowering the time required to calculate the centroid. Attached Figure Description
[0034] Figure 1 This is a schematic diagram of the photon conversion process in existing technology;
[0035] Figure 2 This is a schematic diagram of the existing technology for determining the location of electronic cloud clusters;
[0036] Figure 3 This is a flowchart of the centroid calculation method according to an embodiment of the present invention. Detailed Implementation
[0037] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0038] Example 1
[0039] A neural network hardware centroid calculation method for cross-strip position-sensitive anodes includes the following steps:
[0040] 1.1 Overall Software and Hardware Implementation Plan
[0041] U-Net is a fully convolutional neural network (CNN) widely used for image correlation processing. The overall hardware and software implementation scheme based on the convolutional neural network algorithm is as follows: Figure 3As shown, the main body is divided into model building and hardware implementation. The software implementation primarily involves creating a dataset from the anode readout signal and simulated data generated by MATLAB. This dataset is then divided into training and testing sets, and a suitable network structure is selected for model training using Python. After model training is completed on the computer, the model parameters are exported. The hardware implementation mainly involves deploying the U-Net neural network, combined with the trained model parameters, onto an FPGA. The algorithm deployment uses an FPGA chip, which internally contains a processor unit (PS) and a programmable logic unit (PL). The PS and PL work together; the convolutional neural network (CNN) algorithm is mainly implemented in the PL, while the PS controls the data flow. Data is transmitted between the two via an AXI bus.
[0042] 1.2 Overall Software Implementation Plan
[0043] After the signal collected by the cross-strip anode plates passes through a charge-sensitive amplifier, the ADC can acquire the voltage signal corresponding to each strip. Since the electron cloud is Gaussian distributed, the voltage signal acquired for each strip is also a small Gaussian signal. The dataset consists of two parts: a simulated dataset and a measured dataset. First, an ideal Gaussian signal is generated using MATLAB as the noise-free original electron cloud, and then noise signals of different amplitudes and frequencies are superimposed to form the simulated dataset. The measured dataset is obtained by superimposing the peak values of the small Gaussian signals obtained from the x and y direction strips of the signal sampled by the ADC, forming a two-dimensional matrix. The dataset contains 10,000 images; 80% are randomly selected as the training set, and 20% as the test set.
[0044] To achieve high-precision calculation of the centroid of a cross-line anode under noise interference, a centroid physical information neural network will be employed. The main process involves training a U-Net neural network using a labeled dataset. The model training process includes two phases: the forward propagation phase, where data is propagated from lower to higher levels; and the backpropagation phase, where the error is propagated from higher to lower levels when the forward propagation result does not match the expectation. The horizontal and vertical coordinate distances between the centroids in the x-back and y-back directions are used as the loss function, and the backpropagation algorithm is used to optimize the network parameters. Through continuous parameter optimization, the centroid calculation error is reduced, and high-quality model parameters are obtained when the error is minimized.
[0045] 1.3 Overall Hardware Implementation Plan
[0046] The overall hardware structure includes a data receiving and preprocessing module, a convolutional neural network module, an AXI bus control module, and a centroid calculation result output module.
[0047] The data receiving and preprocessing module first reads the strip information from the ADC via SPI drive. The data preprocessing module then converts the peak values of any x and y channels into a two-dimensional matrix graphic required by the neural network through parallel addition operations. The data is then stored in a high-speed first-in-first-out data memory. Finally, the data is sent to the convolutional neural network module via the AXI bus.
[0048] The convolutional neural network (CNN) module is the core of the hardware, comprising an image processing submodule and a data caching submodule. The image processing submodule consists of convolutional layer modules, max / min pooling layer modules, activation function modules, and fully connected layer modules. A pipelined architecture connects the various layers of the CNN within this submodule, improving computational efficiency. The data caching submodule consists of a data flow control module, a weight storage module, a bias storage module, and RAM. The data flow control module is primarily responsible for receiving preprocessed image data via the AXI bus, transferring weight and bias data for neural network computation, sending the computed data to RAM, and finally transmitting it back to the PS (Power Positioner) via the AXI bus.
[0049] The AXI bus control module provides a high-speed signal path for data transmission between the PS and PL.
[0050] The centroid calculation result output module is responsible for sending the centroid calculation results to the host computer.
Claims
1. A neural network hardware centroid calculation method for cross-bar position sensitive anodes, characterized by, Includes the following steps: Step S1, Model Building: The measured dataset generated from the anode readout signal and the simulated dataset generated by MATLAB were used to randomly select training and test sets. The U-Net neural network was selected as the model and trained using Python. After the model training is complete, export the model parameters; The signal collected by the cross-strip anode plate is then amplified by a charge-sensitive amplifier, and the ADC acquires the voltage signal corresponding to each strip. An ideal Gaussian signal was generated using MATLAB. The ideal Gaussian signal is a noise-free original electron cloud. The noise-free original electron cloud was superimposed with noise signals of different amplitudes and frequencies to form a simulated dataset. The peak values of the small Gaussian signals obtained by striping in the x and y directions were superimposed to obtain a two-dimensional matrix as the measured dataset. The measured dataset and the simulated dataset were then combined to form a dataset. Train the U-Net neural network using the training set; The model training process includes two stages: the forward propagation stage, in which training data is propagated from lower to higher levels; and the backpropagation stage, in which the error is propagated from higher to lower levels when the results of forward propagation do not match expectations. The horizontal and vertical coordinate distances between the centroids of the x and y backward propagation are used as the loss function, and the backpropagation algorithm is used to optimize the network parameters. The centroid calculation error is reduced during network parameter optimization, and the model training is completed when the centroid calculation error is lower than a predetermined value. Step S2, Hardware Implementation: The U-Net neural network, combined with the derived model parameters, is deployed on an FPGA. The algorithm deployment uses an FPGA chip. The FPGA chip includes a processor unit (PS), a programmable logic unit (PL), and an AXI bus. The PS and PL work together. The convolutional neural network (CNN) algorithm is implemented in the PL, the PS controls the data flow, and the PS and PL transmit data via the AXI bus. This results in an FPGA chip with centroid calculation capabilities. The programmable logic unit (PL) includes a data receiving and preprocessing module and a convolutional neural network module; the processor unit (PS) includes a centroid calculation result output module. The data is read from the ADC, converted into a two-dimensional matrix by the data receiving and preprocessing module, stored in the data memory RAM, and sent to the convolutional neural network module by the AXI bus. The implementation process of the Convolutional Neural Network (CNN) algorithm in PL is as follows: The convolutional neural network module includes an image processing submodule and a data caching submodule. The image processing submodule includes a convolutional layer module, a max / min pooling layer module, an activation function module, and a fully connected layer module. A pipelined architecture is used to connect the various layers of the convolutional neural network in the image processing submodule. The data caching submodule includes a data flow control module, a weight storage module, a bias storage module, and RAM. The data flow control module receives preprocessed image data, moves weight data and bias data to participate in neural network calculations via the AXI bus, and the resulting data is the centroid calculation result. The centroid calculation result is sent to RAM and then sent back to the PS end via the AXI bus.
2. The method of claim 1, wherein, The dataset consists of 10,000 images. 80% of the dataset is randomly selected as the training set, and the remaining 20% is used as the test set.
3. The method of claim 1, wherein, In the hardware implementation of step S2, the process of the data preprocessing module converting the data into a two-dimensional matrix graphic is as follows: The ADC reads the strip information into x-channel and y-channel, and performs parallel addition operations on the peak values of any x-channel and y-channel.
4. The method of claim 1 to 3, wherein, It also includes step S3, where the centroid calculation result output module sends the centroid calculation result to the host computer.