Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the method comprising: providing a wafer, the wafer comprising a functional surface and a non-functional surface; forming a functional layer structure on the functional surface; obtaining a warping condition of the wafer; and forming an epitaxial stress layer on the non-functional surface according to the warping condition, the epitaxial stress layer generating stress in a direction opposite to that generated by the wafer warping. The warping condition of the wafer is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor structure and a forming method of the semiconductor structure. BACKGROUND

[0002] With the development of technology following Moore's law, three-dimensional integrated circuits (3D IC) are increasingly attracting the attention of researchers. The development direction of existing three-dimensional integrated circuits has turned from the horizontal plane to the vertical plane, such as 3D memory, 3D through silicon via, and monolithic 3D, etc.

[0003] Due to the mismatch of the coefficient of thermal expansion (CTE) between different stack materials deposited on the wafer, as the temperature decreases, the thin film and the wafer shrink at different rates, and the residual stress generated in the wafer causes the wafer to bend upward or downward, resulting in warpage of the wafer.

[0004] If the bending or warpage of the wafer is too large or the warpage in different directions is different, it will limit the processing of the wafer or even make the wafer unable to be processed on the same machine, increasing the cost of device manufacturing.

[0005] Therefore, improving the warpage of the wafer is a continuous problem to be solved. SUMMARY

[0006] The technical problem solved by the present application is to provide a semiconductor structure and a forming method of the semiconductor structure to improve the warpage of the wafer.

[0007] To solve the above technical problem, the technical scheme of the present application provides a forming method of a semiconductor structure, comprising: providing a wafer, the wafer comprising a functional surface and a non-functional surface; forming a functional layer structure on the surface of the functional surface; obtaining the warpage condition of the wafer; and forming an epitaxial stress layer on the surface of the non-functional surface according to the warpage condition, the stress direction generated by the epitaxial stress layer being opposite to the stress direction generated by the warpage of the wafer.

[0008] Optionally, the warpage condition of the wafer comprises that the wafer bends towards the non-functional surface, or the wafer bends towards the functional surface.

[0009] Optionally, when the wafer bends towards the functional surface, the surface of the non-functional surface has tensile stress; and the epitaxial stress layer has compressive stress.

[0010] Optionally, the material of the epitaxial stress layer comprises carbon silicon.

[0011] Optionally, when the wafer bends towards the non-functional surface, the surface of the non-functional surface has compressive stress; and the epitaxial stress layer has tensile stress.

[0012] Optionally, the material of the epitaxial stress layer comprises silicon germanium.

[0013] Optionally, according to the warping condition, the epitaxial stress layer is formed on the non-functional surface, comprising: obtaining the warping degree of the wafer; if the warping degree of the wafer is within a first preset value range, an epitaxial stress layer with a first stress is formed; if the warping degree of the wafer is within a second preset value range, an epitaxial stress layer with a second stress is formed, the second preset value range is greater than the first preset value range, and the second stress is greater than the first stress.

[0014] Optionally, the first preset value range is less than 200 microns, and the second preset value range is 200 microns to 500 microns.

[0015] Optionally, the wafer is curved towards the non-functional surface, the material of the epitaxial stress layer includes silicon germanium, and the mass range of germanium elements in the epitaxial stress layer with the first stress is less than the mass range of germanium elements in the epitaxial stress layer with the second stress.

[0016] Optionally, the mass range of germanium elements in the epitaxial stress layer with the first stress is 5% to 10%, and the mass range of germanium elements in the epitaxial stress layer with the second stress is 10% to 25%.

[0017] Optionally, the process of forming the epitaxial stress layer with the first stress includes a first epitaxial growth process, and the parameters of the first epitaxial growth process include: the reaction gas includes silane and germane, and the flow rate ratio range of the silane and the germane is 10:1 to 20:1; the process of forming the epitaxial stress layer with the second stress includes a second epitaxial growth process, and the parameters of the second epitaxial growth process include: the reaction gas includes silane and germane, and the flow rate ratio range of the silane and the germane is 4:1 to 10:1.

[0018] Optionally, the wafer is curved towards the functional surface, the material of the epitaxial stress layer includes carbon silicon, and the mass range of carbon elements in the epitaxial stress layer with the first stress is less than the mass range of carbon elements in the epitaxial stress layer with the second stress.

[0019] Optionally, the mass range of carbon elements in the epitaxial stress layer with the first stress is 1% to 1.5%, and the mass range of carbon elements in the epitaxial stress layer with the second stress is 1.5% to 2%.

[0020] Optionally, the process of forming the epitaxial stress layer with the first stress comprises a first epitaxial growth process, parameters of the first epitaxial growth process comprising: the reaction gas comprises neopentasilane and SiCH6, and a flow rate ratio of the neopentasilane and SiCH6 ranges from 75:1 to 100:1; the process of forming the epitaxial stress layer with the second stress comprises a second epitaxial growth process, parameters of the second epitaxial growth process comprising: the reaction gas comprises neopentasilane and SiCH6, and a flow rate ratio of the neopentasilane and SiCH6 ranges from 50:1 to 75:1.

[0021] Optionally, before forming the initial stress layer on the non-functional surface, the method further comprises: forming a protective layer on the functional layer structure surface.

[0022] Optionally, the method further comprises: obtaining the warping condition of the wafer, and the warping degree of the wafer is within a preset range.

[0023] Correspondingly, the technical scheme of the present application further provides a semiconductor structure, comprising: a wafer, the wafer comprising a functional surface and a non-functional surface; a functional layer structure located on the functional surface; and an epitaxial stress layer located on the non-functional surface, the stress direction generated by the epitaxial stress layer being opposite to the stress direction generated by the warping of the wafer, and the warping degree of the wafer being within a preset range.

[0024] Optionally, the warping condition of the wafer comprises: the wafer bending towards the non-functional surface, or the wafer bending towards the functional surface.

[0025] Optionally, when the wafer bends towards the functional surface, the non-functional surface has tensile stress; and the epitaxial stress layer has compressive stress.

[0026] Optionally, the material of the epitaxial stress layer comprises carbon silicon.

[0027] Optionally, when the wafer bends towards the non-functional surface, the non-functional surface has compressive stress; and the epitaxial stress layer has tensile stress.

[0028] Optionally, the material of the epitaxial stress layer comprises silicon germanium.

[0029] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0030] The forming method of the present application can neutralize and offset the stress on the wafer surface by forming the epitaxial stress layer on the non-functional surface, the stress direction generated by the epitaxial stress layer being opposite to the stress direction generated by the warping of the wafer, so that the warping condition of the wafer is improved, and the warping degree of the wafer meets the preset range.

[0031] Further, when the wafer is bent towards the functional surface, the non-functional surface has a tensile stress, the epitaxial stress layer has a compressive stress, and the material of the epitaxial stress layer includes carbon silicon. When the wafer is bent towards the non-functional surface, the non-functional surface has a compressive stress, the epitaxial stress layer has a tensile stress, and the material of the epitaxial stress layer includes silicon germanium. The epitaxial stress layer is arranged according to the warping of the wafer, so that the epitaxial stress layer can neutralize the stress on the wafer surface, and the warping of the wafer is improved, and the warping of the wafer meets the preset range.

[0032] Further, when the warping of the wafer is within a first preset value range, the epitaxial stress layer with a first stress is formed; when the warping of the wafer is within a second preset value range, the epitaxial stress layer with a second stress is formed, the second preset value range is greater than the first preset value range, and the second stress is greater than the first stress. The stress of the epitaxial stress layer is segmented according to the specific warping of the wafer, so that the warping of the wafer can be better adjusted, the warping of the wafer is improved, and the warping of the wafer meets the preset range. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a flowchart of a method for forming a semiconductor structure in an embodiment of the present application;

[0034] Figures 2 to 4 is a structural diagram of a forming process of a semiconductor structure in an embodiment of the present application;

[0035] Figure 5 and Figure 6 is a structural diagram of a forming process of a semiconductor structure in another embodiment of the present application. DETAILED DESCRIPTION

[0036] As described in the background, improving the warping of the wafer is a persistent problem to be solved.

[0037] Specifically, the method for improving the warping of the wafer generally includes: (1) thermal annealing: generally used to solve the isotropic wafer warping, has the whole piece heating attribute, the speed of the rapid heating of each region of the wafer is inconsistent, the temperature field distribution is uneven, and thus the wafer is deformed unevenly by heating; (2) ion implantation: by doping ions to generate stress opposite to the warping to reduce the warping degree, but at the same time, the backside mask and the implantation process need to be increased, and the process is complex; (3) thin film deposition: the backside forms an auxiliary thin film opposite to the stress type of the wafer to offset the stress of the wafer. The conventional PECVD can prepare the thin film by a high-frequency power source, but the stress of the thin film is low, and the warping of the wafer cannot be effectively improved.

[0038] To solve the above problems, the technical scheme of the present application provides a semiconductor structure and a forming method of the semiconductor structure, an epitaxial stress layer is formed on the surface of the non-functional surface, the stress direction generated by the epitaxial stress layer is opposite to the stress direction generated by the wafer warping, the stress on the wafer surface can be neutralized and offset, the wafer warping condition is improved, and the wafer warping degree meets the preset range.

[0039] In order to make the above-mentioned objects, characteristics and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0040] Figure 1 It is a flowchart of the forming method of the semiconductor structure in the embodiment of the present application.

[0041] Please refer to Figure 1 , the flow of the forming method of the semiconductor structure includes:

[0042] Step S10: providing a wafer, the wafer includes a functional surface and a non-functional surface;

[0043] Step S20: forming a functional layer structure on the surface of the functional surface;

[0044] Step S30: obtaining the wafer warping condition;

[0045] Step S40: according to the wafer warping condition, forming an epitaxial stress layer on the surface of the non-functional surface, the stress direction generated by the epitaxial stress layer is opposite to the stress direction generated by the wafer warping.

[0046] The forming method, by forming an epitaxial stress layer on the surface of the non-functional surface, the stress direction generated by the epitaxial stress layer is opposite to the stress direction generated by the wafer warping, the stress on the wafer surface can be neutralized and offset, the wafer warping condition is improved, and the wafer warping degree meets the preset range.

[0047] The wafer warping condition includes: the wafer is curved towards the non-functional surface, or the wafer is curved towards the functional surface.

[0048] In an embodiment, when the wafer is curved towards the functional surface, the surface of the non-functional surface has tensile stress; the epitaxial stress layer has compressive stress.

[0049] In the embodiment, when the wafer is curved towards the non-functional surface, the surface of the non-functional surface has compressive stress; the epitaxial stress layer has tensile stress.

[0050] Next, combined with Figures 2 to 4 each step is analyzed and described. Figures 2 to 4 It is a structure diagram of the forming process of the semiconductor structure in an embodiment of the present application.

[0051] Please refer to Figure 2 Performing step S10: providing a wafer 100, the wafer 100 comprising a functional surface S1 and a non-functional surface S2; performing step S20: forming a functional layer structure on the functional surface S1.

[0052] The functional layer structure comprises a stack of multiple thin films, the stress between the multiple thin films is not matched, the stress between the functional layer structure and the wafer 100 is not matched.

[0053] In the embodiment, the material of the wafer comprises silicon.

[0054] In other embodiments, the material of the wafer comprises silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0055] Please continue to refer to Figure 2 Further comprising: forming a protective layer 101 on the surface of the functional layer structure.

[0056] The protective layer 101 is used to protect the surface of the functional layer structure.

[0057] In the embodiment, the material of the protective layer 101 comprises silicon oxide.

[0058] Please continue to refer to Figure 2 Performing step S30: obtaining the warping condition of the wafer 100.

[0059] In the embodiment, the warping condition of the wafer 100 comprises that the wafer 100 is curved towards the non-functional surface S2.

[0060] In the embodiment, the warping condition of the wafer 100 further comprises that the warping degree of the wafer 100 curved towards the non-functional surface S2 is greater than a preset value.

[0061] The preset value is a standard value for determining whether the wafer warping will affect production and yield, and the wafer with a warping degree within the preset range meets the production and yield requirements.

[0062] Please continue to refer to Figure 3 Performing step S40: forming an epitaxial stress layer 102 on the non-functional surface S2 according to the warping condition, the stress generated by the epitaxial stress layer 102 is in the opposite direction to the stress generated by the wafer 100 warping.

[0063] In the embodiment, according to the warping condition, the epitaxial stress layer 102 is formed on the non-functional surface S2 of the wafer 100, including: obtaining the warping degree of the wafer 100; if the warping degree of the wafer 100 is within a first preset value range, forming the epitaxial stress layer 102 with a first stress; if the warping degree of the wafer 100 is within a second preset value range, forming the epitaxial stress layer 102 with a second stress, the second preset value range is greater than the first preset value range, and the second stress is greater than the first stress.

[0064] According to the specific case of the warping degree of the wafer 100, the stress of the epitaxial stress layer 102 is segmented, which can better adjust the warping degree of the wafer 100, so that the warping condition of the wafer 100 is improved, and the warping degree of the wafer 100 meets the preset range.

[0065] In the embodiment, the first preset value range is less than 200 microns, and the second preset value range is 200 microns to 500 microns.

[0066] Preferably, the first preset value range is greater than 20 microns and less than 200 microns.

[0067] That is, when the wafer 100 bends to the non-functional surface S2 with a small warping degree, the epitaxial stress layer 102 with a small stress is formed; when the wafer 100 bends to the non-functional surface S2 with a large warping degree, the epitaxial stress layer 102 with a large stress is formed.

[0068] In the embodiment, the wafer 100 bends to the non-functional surface S2, and a compressive stress is generated on the non-functional surface S2 of the wafer 100; the epitaxial stress layer 102 has a tensile stress.

[0069] In the embodiment, the material of the epitaxial stress layer 102 includes silicon germanium. The process of forming the epitaxial stress layer 102 includes an epitaxial growth process.

[0070] The lattice constant of silicon is 5.431 Å, the lattice constant of germanium is 5.653 Å, and the mismatch rate of silicon and germanium is 4.09%, so that the lattice constant of silicon germanium is greater than that of pure silicon. The silicon germanium strain material is epitaxially grown on the silicon substrate. A part of germanium forms a silicon germanium structure with the silicon substrate at the interface, and the distance between atoms is greater than that between pure silicon atoms, so that the substrate silicon is subjected to a tensile stress outward.

[0071] In the embodiment, when the first preset value range is less than 200 microns, the epitaxial stress layer 102 with a first stress is formed; when the first preset value range is 200 microns to 500 microns, the epitaxial stress layer 102 with a second stress is formed.

[0072] In the embodiment, the mass range of the germanium element in the epitaxial stress layer 102 with the first stress is less than the mass range of the germanium element in the epitaxial stress layer 102 with the second stress.

[0073] In the embodiment, the mass range of the germanium element in the epitaxial stress layer 102 with the first stress is 5% to 10%, and the mass range of the germanium element in the epitaxial stress layer 102 with the second stress is 10% to 25%.

[0074] The process of forming the epitaxial stress layer 102 with the first stress includes a first epitaxial growth process, and parameters of the first epitaxial growth process include that the reaction gas includes silane and germane, and the flow rate ratio of the silane and the germane ranges from 10:1 to 20:1.

[0075] The process of forming the epitaxial stress layer 102 with the second stress includes a second epitaxial growth process, and parameters of the second epitaxial growth process include that the reaction gas includes silane and germane, and the flow rate ratio of the silane and the germane ranges from 4:1 to 10:1.

[0076] In the embodiment, the flow rate ratio of the silane and the germane for forming the epitaxial stress layer 102 with the first stress is greater than the flow rate ratio of the silane and the germane for forming the epitaxial stress layer 102 with the second stress, so that the mass range of the germanium element in the epitaxial stress layer 102 with the first stress is less than the mass range of the germanium element in the epitaxial stress layer 102 with the second stress.

[0077] Please continue to refer to Figure 4 In the embodiment, the method further includes: obtaining the warping of the wafer 100, and the warping degree of the wafer is within a preset range.

[0078] In the embodiment, the preset range includes: less than or equal to 20 microns.

[0079] Correspondingly, the embodiment of the application further provides a semiconductor structure, please continue to refer to Figure 4 , comprising:

[0080] The wafer 100 includes a functional surface S1 and a non-functional surface S2;

[0081] The functional layer structure is located on the surface of the functional surface S1;

[0082] The epitaxial stress layer 102 is located on the surface of the non-functional surface S2, the stress direction generated by the epitaxial stress layer 102 is opposite to the stress direction generated by the warping of the wafer 100, and the warping degree of the wafer 100 is within a preset range.

[0083] In the embodiment, when the wafer 100 is curved to the non-functional surface S2, the non-functional surface S2 has compressive stress; and the epitaxial stress layer 102 has tensile stress.

[0084] In the embodiment, the material of the epitaxial stress layer 102 includes silicon germanium.

[0085] Figure 5 and Figure 6 is a structural schematic diagram of a forming process of a semiconductor structure in another embodiment of the present application.

[0086] Please refer to Figure 5 , Figure 5 and Figure 2 The difference between the embodiments is that, in the embodiment, the warping of the wafer 100 includes that the wafer 100 is curved to the functional surface S1.

[0087] In the embodiment, the warping of the wafer 100 further includes that the warping degree of the wafer 100 curved to the functional surface S1 is greater than a preset value.

[0088] Please refer to Figure 6 , according to the warping, an epitaxial stress layer 202 is formed on the functional surface S1, and the stress generated by the epitaxial stress layer 202 is in the opposite direction to the stress generated by the warping of the wafer 100.

[0089] In the embodiment, according to the warping, the epitaxial stress layer 202 is formed on the non-functional surface S2, including: obtaining the warping degree of the wafer 100; if the warping degree of the wafer 100 is within a first preset value range, an epitaxial stress layer 202 with a first stress is formed; if the warping degree of the wafer 100 is within a second preset value range, an epitaxial stress layer 202 with a second stress is formed, the second preset value range is greater than the first preset value range, and the second stress is greater than the first stress.

[0090] According to the specific circumstances of the warping degree of the wafer 100, the stress of the epitaxial stress layer 202 is segmented, which can better adjust the warping degree of the wafer 100, so that the warping of the wafer 100 is improved, and the warping degree of the wafer 100 meets the preset range.

[0091] In the embodiment, the first preset value range is less than 200 microns; and the second preset value range is 200 microns to 500 microns.

[0092] Preferably, the first preset value range is greater than 20 microns and less than 200 microns.

[0093] That is, the wafer 100 is curved to the functional surface S1 with a small warping degree, and the epitaxial stress layer 202 with a small stress is formed; the wafer 100 is curved to the functional surface S1 with a large warping degree, and the epitaxial stress layer 202 with a large stress is formed.

[0094] In the embodiment, the wafer 100 is curved to the functional surface S1, and tensile stress is generated on the surface of the non-functional surface S2 of the wafer 100; the epitaxial stress layer 202 has compressive stress.

[0095] In the embodiment, the material of the epitaxial stress layer 202 includes carbon silicon. The process of forming the epitaxial stress layer 202 includes an epitaxial growth process.

[0096] The lattice constant of silicon is 5.431 Å, the lattice constant of carbon is 3.57 Å, and the mismatch rate of carbon and silicon is 34.27%, so that the lattice constant of carbon silicon is smaller than that of pure silicon, and the lattice constant of carbon is much smaller than that of pure silicon, and carbon silicon only needs a small amount of carbon atoms to obtain a high stress. When epitaxially growing carbon silicon strain material on a silicon substrate, a part of carbon atoms and the silicon substrate form a carbon silicon structure at the interface, the distance between the atoms is smaller than the distance between pure silicon atoms, and the substrate silicon is subjected to inward compressive stress.

[0097] In the embodiment, when the first preset value range is less than 200 microns, the epitaxial stress layer 202 with the first stress is formed; when the first preset value range is 200 microns to 500 microns, the epitaxial stress layer 202 with the second stress is formed.

[0098] In the embodiment, the mass range of carbon elements in the epitaxial stress layer 202 with the first stress is smaller than the mass range of carbon elements in the epitaxial stress layer 202 with the second stress.

[0099] In the embodiment, the mass range of carbon elements in the epitaxial stress layer 202 with the first stress is 1% to 1.5%, and the mass range of carbon elements in the epitaxial stress layer 202 with the second stress is 1.5% to 2%.

[0100] The process of forming the epitaxial stress layer 202 with the first stress includes a first epitaxial growth process, and the parameters of the first epitaxial growth process include that the reaction gas includes neopentasilane and SiCH6, and the flow rate ratio of the neopentasilane and SiCH6 is 75:1 to 100:1.

[0101] The process of forming the epitaxial stress layer 202 with the second stress includes a second epitaxial growth process, and the parameters of the second epitaxial growth process include that the reaction gas includes neopentasilane and SiCH6, and the flow rate ratio of the neopentasilane and SiCH6 is 50:1 to 75:1.

[0102] In the embodiment, the flow rate ratio range of neopentasilane and SiCH6 for forming the epitaxial stress layer 202 with the first stress is larger than that for forming the epitaxial stress layer 202 with the second stress, so that the mass range of carbon element in the epitaxial stress layer 202 with the first stress is smaller than that in the epitaxial stress layer 202 with the second stress.

[0103] Please continue to refer to Figure 6 In the embodiment, the wafer 100 is warped, and the warping degree of the wafer 100 is within a preset range.

[0104] In the embodiment, the preset range includes: less than or equal to 20 microns.

[0105] Correspondingly, the embodiment of the present application further provides a semiconductor structure, please continue to refer to Figure 6 , comprising:

[0106] The wafer 100 includes a functional surface S1 and a non-functional surface S2;

[0107] The functional layer structure is located on the surface of the functional surface S1;

[0108] The epitaxial stress layer 202 is located on the surface of the non-functional surface S2, the stress direction generated by the epitaxial stress layer 202 is opposite to the stress direction generated by the warping of the wafer 100, and the warping degree of the wafer 100 is within a preset range.

[0109] In the embodiment, when the wafer 100 is curved to the functional surface S1, the non-functional surface S2 has a tensile stress; and the epitaxial stress layer 102 has a compressive stress.

[0110] In the embodiment, the material of the epitaxial stress layer 102 includes carbon silicon.

[0111] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be subject to the range defined by the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The application relates to a wafer forming method. The wafer forming method comprises the following steps: providing a wafer, the wafer comprising a functional surface and a non-functional surface; forming a functional layer structure on the functional surface; obtaining the wafer warping condition; forming an epitaxial stress layer on the non-functional surface according to the wafer warping condition, the stress generated by the epitaxial stress layer being in the opposite direction to the stress generated by the wafer warping; the wafer warping condition comprises obtaining the wafer warping degree; 2. The method of forming a semiconductor structure of claim 1, wherein, if the wafer warping degree is within a first preset value range, an epitaxial stress layer with a first stress is formed; if the wafer warping degree is within a second preset value range, an epitaxial stress layer with a second stress is formed, the second preset value range being larger than the first preset value range, and the second stress being larger than the first stress.

3. The method of forming a semiconductor structure of claim 2, wherein, The wafer warping condition comprises that the wafer bends towards the non-functional surface or the wafer bends towards the functional surface.

4. The method of forming a semiconductor structure of claim 3, wherein, When the wafer bends towards the functional surface, the non-functional surface has tensile stress; and the epitaxial stress layer has compressive stress.

5. The method of forming a semiconductor structure of claim 2, wherein, The material of the epitaxial stress layer comprises carbon silicon.

6. The method of forming a semiconductor structure of claim 5, wherein, When the wafer bends towards the non-functional surface, the non-functional surface has compressive stress; and the epitaxial stress layer has tensile stress.

7. The method of forming a semiconductor structure of claim 1, wherein, The material of the epitaxial stress layer comprises silicon germanium.

8. The method of forming a semiconductor structure of claim 1, wherein, The first preset value range is less than 200 microns; and the second preset value range is 200 microns to 500 microns.

9. The method of forming a semiconductor structure of claim 8, wherein, When the wafer bends towards the non-functional surface, the material of the epitaxial stress layer comprises silicon germanium; the mass range of germanium in the epitaxial stress layer with the first stress is smaller than the mass range of germanium in the epitaxial stress layer with the second stress.

10. The method of forming a semiconductor structure of claim 9, wherein, The mass range of germanium in the epitaxial stress layer with the first stress is 5% to 10%; and the mass range of germanium in the epitaxial stress layer with the second stress is 10% to 25%.

11. The method of forming a semiconductor structure of claim 1, wherein The process of forming the epitaxial stress layer with the first stress comprises a first epitaxial growth process, the parameters of the first epitaxial growth process comprising that the reaction gas comprises silane and germane, and the flow rate ratio of the silane and the germane ranges from 10:1 to 20:1; the process of forming the epitaxial stress layer with the second stress comprises a second epitaxial growth process, the parameters of the second epitaxial growth process comprising that the reaction gas comprises silane and germane, and the flow rate ratio of the silane and the germane ranges from 4:1 to 10:

1.

12. The method of forming a semiconductor structure of claim 11, wherein, When the wafer bends towards the functional surface, the material of the epitaxial stress layer comprises carbon silicon; the mass range of carbon in the epitaxial stress layer with the first stress is smaller than the mass range of carbon in the epitaxial stress layer with the second stress. The mass range of carbon in the epitaxial stress layer with the first stress is 1% to 1.5%; and the mass range of carbon in the epitaxial stress layer with the second stress is 1.5% to 2%.

13. The method of forming a semiconductor structure of claim 12, wherein, The process of forming the epitaxial stress layer with the first stress includes a first epitaxial growth process, parameters of the first epitaxial growth process include: the reaction gas includes neopentasilane and SiCH6, and a flow rate ratio of the neopentasilane and SiCH6 ranges from 75:1 to 100:1; the process of forming the epitaxial stress layer with the second stress includes a second epitaxial growth process, parameters of the second epitaxial growth process include: the reaction gas includes neopentasilane and SiCH6, and a flow rate ratio of the neopentasilane and SiCH6 ranges from 50:1 to 75:

1.

14. The method of forming a semiconductor structure of claim 1, wherein, Before forming the initial stress layer on the non-functional surface, the method further includes forming a protective layer on the functional layer structure surface.

15. The method of forming a semiconductor structure of claim 1, wherein The method further includes: The warping of the wafer is within a preset range.

16. A semiconductor structure, characterized by The method includes: The wafer includes a functional surface and a non-functional surface; A functional layer structure is located on the functional surface; An epitaxial stress layer is located on the non-functional surface, a stress direction generated by the epitaxial stress layer is opposite to a stress direction generated by warping of the wafer, and a warping degree of the wafer is within a preset range, If the warping degree of the wafer is within a first preset value range, the epitaxial stress layer has a first stress; if the warping degree of the wafer is within a second preset value range, the epitaxial stress layer has a second stress, the second preset value range is greater than the first preset value range, and the second stress is greater than the first stress.

17. The semiconductor structure of claim 16, wherein, The warping of the wafer includes: the wafer bends towards the non-functional surface, or the wafer bends towards the functional surface.

18. The semiconductor structure of claim 17, wherein, When the wafer bends towards the functional surface, the non-functional surface has a tensile stress; and the epitaxial stress layer has a compressive stress.

19. The semiconductor structure of claim 18, wherein, The material of the epitaxial stress layer includes carbon silicon.

20. The semiconductor structure of claim 17, wherein, When the wafer bends towards the non-functional surface, the non-functional surface has a compressive stress; and the epitaxial stress layer has a tensile stress.

21. The semiconductor structure of claim 20, wherein, The material of the epitaxial stress layer includes silicon germanium.

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