Wafer edge finding positioning and id number recognition control system and control method thereof

Abstract

The application discloses a wafer edge searching positioning and ID number identification control system and a control method thereof. The system comprises the following steps: an FPGA controller sends a laser emission instruction to a laser emitter; the laser emitter sends a parallel line laser signal to a wafer to be detected; a photoelectric sensor collects an edge position electric signal generated after the parallel line laser signal passes through the edge of the wafer to be detected, and transmits the edge position electric signal to an ARM processor through the FPGA controller; the ARM processor calculates wafer offset data according to the edge position electric signal, and controls an edge searching motion module to move according to the wafer offset data; the ARM processor also sends a wafer image collection instruction to an image sensor; the image sensor acquires a wafer surface image; and an OCR identification component identifies an ID number according to the wafer surface image and outputs the ID number. The application realizes integrated design of wafer edge searching positioning and ID number identification functions, has high integration, low cost, small space occupation, and high work efficiency and stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor production equipment, in particular to a wafer edge positioning and ID number identification control system and a control method thereof. BACKGROUND

[0002] In the semiconductor production process, in order to ensure the identification of the edge position of the wafer when it is transferred between different process equipment, a dedicated wafer edge positioning equipment is needed. At the same time, the identification code (i.e. ID number) in the wafer needs to be read in order to manage the wafer transmission or to perform the next step of processing according to the preset requirements.

[0003] At present, the wafer clamping assembly PA and the OCR (Optical Character Recognition) assembly are installed separately in the industry, and after adjusting to the appropriate position, the wafer clamping assembly is used to correct the position of the wafer, and then the ID number of the wafer is read through the OCR assembly. This method needs to control the wafer clamping assembly and the OCR assembly respectively, and then assemble according to the actual process requirements to realize the integrated application of wafer edge positioning and ID number identification. This way, the stability of the equipment is poor, the production cost is increased, the work efficiency is low, the whole mechanism assembled occupies a large space, and the clamping action of the clamp is easy to cause damage to the wafer during operation. SUMMARY

[0004] Therefore, the present application provides a wafer edge positioning and ID number identification control system and a control method thereof to solve the problems of poor equipment stability, high production cost, low work efficiency, large equipment space occupation and easy damage to the wafer in the existing wafer edge positioning and ID number identification technology.

[0005] The present application provides a wafer edge positioning and ID number identification control system, which comprises a FPGA controller, a laser emitter, a photoelectric sensor, an ARM processor, an image sensor, an OCR identification assembly and an edge motion module.

[0006] The laser emitter and the photoelectric sensor are electrically connected to the FPGA controller, the FPGA controller is in communication connection with the ARM processor, and the image sensor, the OCR identification assembly and the edge motion module are electrically connected to the ARM processor.

[0007] The FPGA controller is used to send a laser emission instruction to the laser emitter.

[0008] The laser emitter is used to send a parallel line laser signal to the wafer to be detected according to the received laser emission instruction.

[0009] The photoelectric sensor is configured to collect an edge position electrical signal generated by the parallel line laser signal after passing through the edge of the wafer to be detected and transmit the edge position electrical signal to the FPGA controller.

[0010] The FPGA controller is configured to transmit the received edge position electrical signal to the ARM processor.

[0011] The ARM processor is configured to calculate wafer offset data according to the received edge position electrical signal and control the edge searching motion module to move according to the wafer offset data to position the wafer to be detected.

[0012] The ARM processor is further configured to send a wafer image collection instruction to the image sensor.

[0013] The image sensor is configured to acquire a wafer surface image of the wafer to be detected according to the received image collection instruction and transmit the wafer surface image to the OCR recognition component through the ARM processor.

[0014] The OCR recognition component is configured to identify an ID number of the wafer to be detected according to the received wafer surface image and output the ID number.

[0015] Optionally, the control system further comprises a first PWM control unit.

[0016] The FPGA controller is electrically connected to the laser emitter through the first PWM control unit.

[0017] The FPGA controller is specifically configured to:

[0018] send the laser emission instruction to the first PWM control unit;

[0019] The first PWM control unit is configured to generate a first PWM control signal according to the received laser emission instruction and send the first PWM control signal to the laser emitter.

[0020] The laser emitter is specifically configured to:

[0021] send the parallel line laser signal to the wafer to be detected under the control of the first PWM control signal.

[0022] Optionally, the control system further comprises an ADC converter.

[0023] The photoelectric sensor is electrically connected to the FPGA controller through the ADC converter.

[0024] The ADC converter is used for converting the analog edge position electric signal collected by the photosensor into an edge position digital signal, transmitting the edge position digital signal to the FPGA controller, and transmitting the edge position digital signal to the ARM processor through the FPGA controller.

[0025] Optionally, the wafer offset data includes a center offset position and a cutting edge offset angle of the wafer under test.

[0026] The ARM processor calculates wafer offset data according to the received edge position electric signal, specifically including:

[0027] According to the edge position digital signal transmitted by the FPGA controller, the edge position coordinates of the wafer under test are calculated.

[0028] According to the edge position coordinates, the edge curve of the wafer under test is obtained by curve fitting using the least square method.

[0029] According to the edge curve, the center offset position and the cutting edge offset angle of the wafer under test are calculated.

[0030] Optionally, the OCR recognition component identifies the ID number of the wafer under test according to the received wafer surface image and outputs, specifically including:

[0031] Based on the DB optimization method, the wafer surface image is text detected to obtain text region polygon information.

[0032] The text region polygon information is cropped and perspective transformed to obtain a text region rectangular frame.

[0033] Based on the SVTR text recognition method, the text region rectangular frame is text recognized to obtain the ID number of the wafer under test and output.

[0034] Optionally, the OCR recognition component detects the text of the wafer surface image based on the DB optimization method to obtain text region polygon information, specifically including:

[0035] The backbone network is used for feature extraction of the wafer surface image to obtain multi-stage features.

[0036] The neck network structure of DBFPN is used for feature fusion of the multi-stage features to obtain fusion features.

[0037] The fusion features are decoded to obtain a probability feature map and a threshold feature map, and the probability feature map and the threshold feature map are fused to obtain a binary feature map.

[0038] respectively, to obtain a probability map loss, a threshold map loss and a binary map loss;

[0039] The model is trained using the probability map loss, the threshold map loss and the binary map loss, and the text detection model is trained, and the text region polygon information corresponding to the wafer surface image is obtained.

[0040] Optionally, the OCR recognition component performs text recognition on the text region rectangular frame based on an SVTR text recognition method to obtain and output the ID number of the wafer under test, specifically including:

[0041] The text region rectangular frame is input into a preset text recognition model to obtain a target text region.

[0042] The target text region is processed using a progressive overlapping patch embedding method to obtain a plurality of formats of character components.

[0043] All the character components are gradually down-sampled in height, and a parallel linear prediction method is used to decode all the character components after the gradual down-sampling in height to obtain and output the ID number of the wafer under test.

[0044] Optionally, the control system further comprises a second PWM control unit and a light supplementing lamp.

[0045] The ARM processor is electrically connected to the light supplementing lamp through the second PWM control unit.

[0046] The ARM processor is further configured to send a light supplementing instruction to the second PWM control unit while sending the wafer collection instruction to the image sensor.

[0047] The second PWM control unit is configured to generate a second PWM control signal according to the received light supplementing instruction and send the second PWM control signal to the light supplementing lamp.

[0048] The light supplementing lamp is configured to emit a light supplementing light source to the wafer under test under the control of the second PWM control signal to supplement light on the surface of the wafer under test.

[0049] Optionally, the control system further comprises a stage control component.

[0050] The stage control component is electrically connected to the ARM processor, and the stage control component is further connected to a stage for placing the wafer under test.

[0051] The ARM processor is further configured to send a stage motion instruction to the stage control component before sending a wafer image acquisition instruction to the image sensor and before the FPGA controller sends a laser emission instruction to the laser emitter.

[0052] The stage control component is configured to control rotation of a stage on which the wafer under test is placed according to the received stage motion instruction.

[0053] Furthermore, the present application also provides a control method for wafer edge finding and ID number identification, which adopts the wafer edge finding and ID number identification control system as described above to perform wafer edge finding and ID number identification, and the control method comprises the following steps:

[0054] The FPGA controller is configured to send a laser emission instruction to the laser emitter.

[0055] The laser emitter is configured to send a parallel line laser signal to the wafer under test according to the received laser emission instruction.

[0056] The photoelectric sensor is configured to acquire an edge position electrical signal generated after the parallel line laser signal passes through the edge of the wafer under test and transmit the edge position electrical signal to the FPGA controller.

[0057] The FPGA controller is configured to transmit the received edge position electrical signal to the ARM processor.

[0058] The ARM processor is configured to calculate wafer offset data according to the received edge position electrical signal and control the edge finding motion module to move according to the wafer offset data so as to perform edge finding positioning on the wafer under test.

[0059] The ARM processor is configured to send a wafer image acquisition instruction to the image sensor.

[0060] The image sensor is configured to acquire a wafer surface image of the wafer under test according to the received image acquisition instruction and transmit the wafer surface image to the OCR identification component through the ARM processor.

[0061] The OCR identification component is configured to identify an ID number of the wafer under test according to the received wafer surface image and output the ID number.

[0062] The beneficial effects of the present application: in the whole control system, by using the integration between the laser emitter, the photoelectric sensor and the FPGA controller, the edge position electric signal generated after the parallel line laser signal passes through the edge of the wafer to be detected is obtained, then through the data interaction between the FPGA controller and the ARM processor, the wafer offset data is obtained according to the edge position electric signal by using the ARM processor, and then the wafer edge positioning is realized by controlling the edge searching motion module to move according to the wafer offset data; then by using the integration between the image sensor, the OCR identification component and the ARM processor, the wafer surface image is obtained, and the ID number of the wafer to be detected is identified and output according to the obtained wafer surface image, so as to realize the identification of the wafer ID number, and further ensure the identification alignment requirement of the edge cutting position and the management requirement of the wafer transmission when the wafer circulates between different process equipment.

[0063] The wafer edge positioning and ID number identification control system and the control method thereof realize the design of integrating the wafer edge positioning function and the ID number identification function, greatly improve the integration degree of the wafer positioning equipment, reduce the equipment development cost, the equipment occupies small space, the working efficiency is high, and the phenomenon that the clamp clamping action causes damage to the wafer will not occur, and the stability of the equipment is high. BRIEF DESCRIPTION OF DRAWINGS

[0064] The features and advantages of the present application will be more clearly understood through reference to the following drawings, which are presented as exemplary and should not be construed as limiting the present application, in which:

[0065] Figure 1 A structure diagram of a wafer edge positioning and ID number identification control system in the embodiment one of the present application is shown;

[0066] Figure 2 A structure diagram of another wafer edge positioning and ID number identification control system in the embodiment one of the present application is shown;

[0067] Figure 3 A flow chart of a wafer edge positioning and ID number identification control method in the embodiment two of the present application is shown. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme in the embodiments of the present application will be described clearly and completely below by combining the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0069] Embodiment one

[0070] A wafer edge positioning and ID number identification control system, as shown in Figure 1 The control system comprises an FPGA controller, a laser emitter, a photoelectric sensor, an ARM processor, an image sensor, an OCR identification component and an edge positioning motion module.

[0071] The laser emitter and the photoelectric sensor are electrically connected with the FPGA controller, the FPGA controller is in communication connection with the ARM processor, and the image sensor, the OCR identification component and the edge positioning motion module are electrically connected with the ARM processor.

[0072] The FPGA controller is used for sending a laser emission instruction to the laser emitter.

[0073] The laser emitter is used for sending a parallel line laser signal to a wafer to be detected according to the received laser emission instruction.

[0074] The photoelectric sensor is used for collecting an edge position electric signal generated after the parallel line laser signal passes through the edge of the wafer to be detected, and transmitting the edge position electric signal to the FPGA controller.

[0075] The FPGA controller is used for transmitting the received edge position electric signal to the ARM processor.

[0076] The ARM processor is used for calculating wafer offset data according to the received edge position electric signal, and controlling the edge positioning motion module to move to position the wafer to be detected according to the wafer offset data.

[0077] The ARM processor is also used for sending a wafer image acquisition instruction to the image sensor.

[0078] The image sensor is used for acquiring a wafer surface image of the wafer to be detected according to the received image acquisition instruction, and transmitting the wafer surface image to the OCR identification component through the ARM processor.

[0079] The OCR identification component is used for identifying an ID number of the wafer to be detected according to the received wafer surface image and outputting.

[0080] The embodiment utilizes the integration among the laser emitter, the photoelectric sensor and the FPGA controller in the whole control system to obtain the edge position electric signal generated after the parallel line laser signal passes through the edge of the wafer to be detected, and then utilizes the data interaction between the FPGA controller and the ARM processor to obtain the wafer offset data according to the edge position electric signal by the ARM processor, and then controls the edge searching motion module to move according to the wafer offset data, so as to realize the edge searching positioning of the wafer. Then, the integration among the image sensor, the OCR identification component and the ARM processor is utilized to obtain the wafer surface image, and the ID number of the wafer to be detected is identified and output according to the obtained wafer surface image, so as to realize the identification of the wafer ID number, and then ensure the identification alignment requirement of the edge cutting position and the management requirement of the wafer transmission when the wafer circulates between different process equipment.

[0081] The control system for wafer edge searching positioning and ID number identification of the embodiment realizes the design of integrating the wafer edge searching positioning function and the ID number identification function, greatly improves the integration degree of the wafer positioning equipment, reduces the equipment development cost, occupies small space, has high work efficiency, and will not cause the phenomenon that the clamp clamping action damages the wafer, and has high stability.

[0082] Specifically, in the embodiment, the FPGA (Field-Programmable Gate Array) controller is a field programmable gate array, which contains a large number of programmable logic units, memories and input / output interfaces, and can use a hardware description language (such as VHDL or Verilog) to write programs to realize specific hardware logic functions. The ARM (Advanced RISC Machine) processor is a microprocessor architecture, which adopts the RISC (Reduced Instruction Set Computer) architecture, has the characteristics of low power consumption, high performance and low cost, and can provide various hardware resources through software programming to realize various complex functions.

[0083] Preferably, as shown in Figure 2 The control system further comprises a first PWM control unit;

[0084] The FPGA controller is electrically connected with the laser emitter through the first PWM control unit;

[0085] The FPGA controller is specifically used for:

[0086] sending the laser emission instruction to the first PWM control unit;

[0087] The first PWM control unit is used for generating a first PWM control signal according to the received laser emission instruction, and sending the first PWM control signal to the laser emitter;

[0088] The laser emitter is specifically used for:

[0089] Under the control of the first PWM control signal, the parallel line laser signal is sent to the wafer to be detected.

[0090] In this embodiment, when the parallel line laser signal is triggered, the first PWM control signal generated by the first PWM control unit is used for control, and the output power of the laser can be controlled by adjusting the pulse width based on the PWM technology, and energy is only output during the pulse, thereby reducing energy waste during non-working time, improving the overall energy efficiency, and reducing energy consumption compared with the continuous control mode. The pulse width of the first PWM control signal can be accurately controlled by using the PMW technology, thereby realizing fine adjustment of the laser output power and high-precision control of the triggering of the parallel line laser signal, and further realizing fine control of the edge positioning of the entire wafer.

[0091] Preferably, as Figure 2 The control system further comprises an ADC converter;

[0092] The photoelectric sensor is electrically connected to the FPGA controller through the ADC converter;

[0093] The ADC converter is used to convert the analog edge position electrical signal collected by the photoelectric sensor into a digital edge position signal, transmit the digital edge position signal to the FPGA controller, and transmit the digital edge position signal to the ARM processor through the FPGA controller.

[0094] When the parallel line laser signal emitted by the laser emitter irradiates the surface of the wafer, the laser signal passing through the edge of the wafer to be detected is different due to the edges at different positions of the wafer. By collecting and photoelectrically sensing the laser signal passing through the edge of the wafer, different edge position electrical signals are obtained, which are analog electrical signals. In this embodiment, the ADC converter between the photoelectric sensor and the FPGA controller is used to conveniently convert the analog electrical signal into a digital electrical signal (i.e., a digital edge position signal), and then the signal format supported by the FPGA controller can be used for signal transmission and subsequent signal analysis by the ARM processor, wafer offset data is obtained, and edge positioning of the wafer is realized.

[0095] In the actual production and manufacturing process of the wafer, the wafer is usually placed on the stage by manual or mechanical hand. When the wafer is placed on the stage, the wafer is fixed on the stage by the negative pressure adsorption assembly built in the stage. If the wafer is offset, the center of the wafer and the center of the stage will be offset, and the cut edge or cut angle (cut edge or cut angle are usually used for directional marking and auxiliary processing in wafer manufacturing) on the wafer will be angularly offset.

[0096] In the embodiment, the wafer offset data includes a center offset position and a cutting edge offset angle of the wafer to be detected.

[0097] Based on the wafer offset data, the subsequent edge searching motion module can accurately search and position the wafer, and ensure that the wafer to be detected can be manufactured according to the set position and direction.

[0098] Preferably, the ARM processor calculates wafer offset data according to the received edge position electrical signal, specifically including:

[0099] According to the edge position digital signal transmitted by the FPGA controller, the edge position coordinates of the wafer to be detected are calculated;

[0100] According to the edge position coordinates, the edge curve of the wafer to be detected is obtained by curve fitting using the least square method;

[0101] According to the edge curve, the center offset position and the cutting edge offset angle of the wafer to be detected are calculated.

[0102] The above method can accurately fit the actual position of the wafer to be detected, and further determine the wafer offset data (including the center offset position and the cutting edge offset angle) between the wafer to be detected and the ideal set position (i.e. the ideal position without center offset and angle offset). The subsequent ARM processor can control the edge searching motion module to accurately search and position the wafer to be detected according to the center offset position and the cutting edge offset angle, and ensure the identification and alignment of the cutting edge position when the wafer is transferred between different process equipment.

[0103] The internal operation unit calculates the edge position coordinates according to the edge position digital signal, and calculates the center offset position and the cutting edge offset angle using the fitted edge curve, which can be calculated using mathematical geometry knowledge and mathematical trigonometric function knowledge, which is a conventional technology. The specific operation method of curve fitting by the least square method is also a conventional operation method, and the specific details are not repeated here.

[0104] The embodiment uses the integration of the above laser emitter, photoelectric sensor, FPGA controller, ARM processor and edge searching motion module to realize accurate edge searching and positioning of the wafer, and effectively ensure the identification and alignment of the cutting edge position when the wafer is transferred between different process equipment.

[0105] Preferably, the OCR recognition component identifies and outputs the ID number of the wafer to be detected according to the received wafer surface image, specifically including:

[0106] Based on the DB optimization method, text detection is performed on the wafer surface image to obtain text region polygon information.

[0107] The text region polygon information is subjected to clipping processing and perspective transformation processing to obtain a text region rectangular frame.

[0108] Based on the SVTR text recognition method, text recognition is performed on the text region rectangular frame to obtain the ID number of the wafer under test and output.

[0109] In the OCR recognition component described above, the DB optimization method is used for text detection, and the SVTR text recognition method is used for text recognition, forming a PP-OCRv3 model framework to realize OCR recognition of the wafer ID number, which effectively improves the recognition accuracy and speed, reduces the recognition error rate, effectively ensures the demand for wafer transmission management in the wafer manufacturing process, and helps the automation and intelligentization of wafer manufacturing.

[0110] Specifically, the OCR recognition component performs text detection on the wafer surface image based on the DB optimization method to obtain text region polygon information, specifically including:

[0111] The backbone network is used to extract features from the wafer surface image to obtain multi-stage features.

[0112] The neck network structure of the DBFPN is used to fuse the multi-stage features to obtain fused features.

[0113] The fused features are decoded to obtain a probability feature map and a threshold feature map, and the probability feature map and the threshold feature map are fused to obtain a binary feature map.

[0114] The loss functions of the probability feature map, the threshold feature map and the binary feature map are calculated respectively to obtain a probability map loss, a threshold map loss and a binary map loss.

[0115] The probability map loss, the threshold map loss and the binary map loss are used for model training, and based on the trained text detection model, the text region polygon information corresponding to the wafer surface image is obtained.

[0116] The backbone network is used to extract features, which can obtain multi-stage features containing rich image information, facilitating subsequent feature analysis. The DBFPN neck network structure is used for feature fusion, which can realize features at different stages, enhance the robustness and diversity of feature representation, and enable the model to capture text information at different scales at the same time. Through decoding, a probability feature map and a threshold feature map can be obtained. The probability feature map is used to represent the probability of each pixel in the image belonging to the text region. The threshold feature map is a graph with the same size as the probability feature map, which represents the threshold to be used when binarizing each pixel position in the probability feature map. Based on the probability feature map and the threshold feature map obtained by decoding, an approximate binary feature map can be calculated through a differentiable binarization operation, so that the entire network can be trained end-to-end. Finally, the model is trained using the probability map loss, threshold map loss and binary map loss, which can ensure accurate prediction of the boundaries of the text region in the wafer surface image and obtain text region polygon information containing character position information.

[0117] In this embodiment, when the backbone network is used to extract features from the wafer surface image, the scale parameter (a parameter used to adjust the network width, also referred to as a parameter used to adjust the number of channels) of the backbone network is adjusted from 1x to 0.5x. While ensuring accuracy and efficiency, the number of feature map channels is reduced and the network structure is simplified. At the same time, since the SE module (Squeeze-and-Excitation) of the network is a kind of attention mechanism for enhancing the performance of convolutional neural network (CNN), the accuracy improvement is very limited when extracting features from high-resolution pictures, but the time cost is very high. Therefore, the SE module of the network is also omitted in the actual process, which can reduce the overall running time of the model.

[0118] In this embodiment, when the DBFPN (Deep Bilateral Feature Pyramid Network) neck network structure is used to fuse multi-stage features, the inner_channels (which refers to reducing the number of channels of the feature map to the same number of channels using a 1x1 convolution for the convenience of merging feature maps of different channels during feature fusion) is reduced from 256 to 96, which reduces the size of the model while ensuring accuracy.

[0119] Specifically, the OCR recognition component performs text recognition on the text region rectangular frame based on the SVTR text recognition method to obtain and output the ID number of the wafer under test. Specifically, the method comprises the following steps:

[0120] The text region rectangular frame is input into a preset text recognition model to obtain a target text region.

[0121] The target text region is processed by using a progressive overlapping patch embedding method to obtain a plurality of formats of character components.

[0122] All the character components are subjected to height gradual downsampling, and a parallel linear prediction method is used to decode all the character components subjected to height gradual downsampling to obtain the ID number of the wafer under test and output the ID number.

[0123] The preset text recognition model can select a suitable model according to actual conditions, such as a model based on a convolutional neural network (CNN), which can recognize target text regions, which can be words, lines, or paragraphs. Then, a progressive overlapping patch embedding method is used for processing, which can divide the recognized target text regions into smaller blocks (patches), which can overlap to capture more contextual information, and each patch can contain partial characters or character components (such as strokes, line segments, etc.), providing a basis for subsequent recognition steps. Then, the representations of the character components are subjected to height gradual downsampling before being converted into final character sequences, which helps to convert character components or patches of different sizes into a uniform size for subsequent parallel processing; finally, a parallel linear predictor (such as an RNN optimized by CTC-Loss, a Transformer, etc.) is used to decode the uniform representations to achieve parallel linear prediction, which can predict the most likely character sequence based on the feature representations of the character components, and then obtain the final ID number of the wafer under test and output the ID number. The entire text recognition process is accurate and reliable, and the obtained ID number has high accuracy.

[0124] Specifically, in the present embodiment, the text region rectangular frame is input into the preset text recognition model, which can output an image in HxWx3 format, and a plurality of character components (CharacterComponents) are obtained by using a progressive overlapping patch embedding method.

[0125] Before height gradual downsampling is performed on all the character components, the mixed blocks output by each output in the network model are also used for feature extraction, fusion, merging, or combination at different scales to form uniform representations of the character components, and then the character components in the uniform representations are subjected to height gradual downsampling, and character components or patches of different sizes are converted into a uniform size.

[0126] ​​Specifically, in the text recognition process based on the SVTR text recognition method described in the embodiment, the SVTR_LCNet network is adopted, all ReLU (Rectified Linear Unit) activation functions in the entire SVTR_LCNet network are replaced with h-swish activation functions, the h-swish activation functions combine the advantages of Sigmoid and linear functions, can more smoothly activate negative input, thereby possibly bringing better gradient flow and model learning ability, after being replaced with the h-swish, the model can possibly capture more nonlinear features, thereby improving the overall accuracy by 1% to 2%. In the fifth stage of the SVTR_LCNet network, the kernel size of the depthwise separable convolution (DW) is changed from the default size (that is, 3x3) to 5x5, which can capture more complex spatial features, and help the model better understand global features, thereby improving the overall accuracy by 0.5% to 1%. At the same time, the SE (Squeeze-and-Excitation) module is added in the last two SEP blocks of the fifth stage of the SVTR_LCNet network, which can enhance the model's ability to judge the importance of features, enhance important features and suppress unimportant features, thereby improving the overall accuracy by 0.5% to 1%. In the SVTR_LCNet network, a 1280-dimensional fully connected (FC) layer is added after the global average pooling (GAP) layer, the global average pooling layer is usually used to reduce the spatial dimension of the feature map to 1x1, thereby retaining the most important features; then a high-dimensional fully connected layer is added, which can further increase the non-linear expression ability and feature fusion ability of the model, this additional FC layer can help the model learn more complex feature combinations, thereby improving the accuracy of classification or regression tasks, thereby improving the overall accuracy by 2% to 3%.

[0127] Preferably, as shown in Figure 2 the control system further comprises a second PWM control unit and a light supplement lamp;

[0128] The ARM processor is electrically connected with the light supplement lamp through the second PWM control unit;

[0129] The ARM processor is further configured to send a light supplement instruction to the second PWM control unit while sending the wafer collection instruction to the image sensor;

[0130] The second PWM control unit is configured to generate a second PWM control signal according to the received light supplement instruction, and send the second PWM control signal to the light supplement lamp.

[0131] The light supplement lamp is configured to emit light supplement light source to the wafer under test under the control of the second PWM control signal, so as to supplement light to the surface of the wafer under test.

[0132] The control system described above in the embodiment can not only collect wafer surface images, but also trigger the light supplement lamp to emit light supplement light source to supplement light to the surface of the wafer under test through the second PWM control unit, so as to ensure the quality of the collected wafer surface images, thereby on the one hand, the entire control system can adapt to different use environments, and on the other hand, the subsequent identification accuracy of the wafer ID number can be effectively improved based on the high-quality wafer surface images. At the same time, the second PWM control unit is used to control the light supplement lamp in the same way as the first PWM control unit, so as to realize high-precision control of the triggering of the light supplement light source.

[0133] In the embodiment, the second PWM control unit can be the same as or different from the first PWM control unit, the pulse width of the first PWM control signal used to control the laser emitter can be the same as or different from the pulse width of the second PWM control signal used to control the light supplement lamp, and the two do not interfere with each other, so as to realize independent control of the laser emitter and the light supplement lamp.

[0134] Preferably, as shown in the embodiment, the control system further comprises a stage control assembly; Figure 2

[0135] The stage control assembly is electrically connected with the ARM processor, and the stage control assembly is further connected with a stage for placing the wafer under test.

[0136] The ARM processor is further configured to send a stage motion instruction to the stage control assembly before sending a wafer image collection instruction to the image sensor and before the FPGA controller sends a laser emission instruction to the laser emitter.

[0137] The stage control assembly is configured to control the stage on which the wafer under test is placed to rotate according to the received stage motion instruction.

[0138] ​Before triggering the parallel line laser signal emission and before triggering the wafer surface image collection, the stage control assembly is also controlled by the ARM processor to drive the stage on which the wafer to be detected is placed to rotate, so as to ensure that the wafer surface images collected subsequently are real-time, and to ensure that the edge position electric signals obtained subsequently are at different positions of the edge of the wafer to be detected, and to ensure that the ID number and wafer offset data obtained finally are accurate, and to ensure the stability and reliability of the control system in which the wafer edge-finding positioning function and the ID number identification function are integrated.

[0139] It should be understood that the stage in the embodiment is a commonly used device in wafer production, and the specific structure is not listed here. The edge-finding motion module is specifically a motion module configured for the stage and capable of moving in three dimensions of X (translation on the x-axis), Y (translation on the y-axis), and R (rotation in the xy plane), and the stage control assembly is specifically a motor module capable of controlling the rotation of the stage in the xy plane.

[0140] The photoelectric sensor is specifically a linear array CCD sensor, the image sensor is specifically a CCD area array camera, and the edge-finding motion module is connected to the ARM chip through an Ethernet communication interface. The light supplementing lamp is specifically an LED light source. The above components, the FPGA controller, and the ARM processor can all be selected according to actual conditions, and specific models or product types are not listed here.

[0141] Embodiment Two

[0142] A control method for wafer edge-finding positioning and ID number identification, which uses the control system for wafer edge-finding positioning and ID number identification in Embodiment One to perform wafer edge-finding positioning and ID number identification, as shown in Figure 3 The control method comprises the following steps:

[0143] S1: using the FPGA controller to send a laser emission instruction to the laser emitter;

[0144] S2: using the laser emitter to send a parallel line laser signal to the wafer to be detected according to the received laser emission instruction;

[0145] S3: using the photoelectric sensor to collect an edge position electric signal generated after the parallel line laser signal passes through the edge of the wafer to be detected, and transmitting the edge position electric signal to the FPGA controller;

[0146] S4: using the FPGA controller to transmit the received edge position electric signal to the ARM processor;

[0147] S5: calculating wafer offset data according to the received edge position electrical signal by using the ARM processor, and controlling the edge-searching motion module to move according to the wafer offset data, so as to position the wafer to be detected;

[0148] S6: sending wafer image acquisition instructions to the image sensor by using the ARM processor;

[0149] S7: acquiring a wafer surface image of the wafer to be detected according to the received image acquisition instructions by using the image sensor, and transmitting the wafer surface image to the OCR recognition component through the ARM processor;

[0150] S8: identifying the ID number of the wafer to be detected according to the received wafer surface image by using the OCR recognition component and outputting the ID number.

[0151] In this embodiment, the edge position electrical signal generated after the parallel line laser signal passes through the edge of the wafer to be detected is acquired by using the integration between the laser emitter, the photoelectric sensor and the FPGA controller, and then the wafer offset data is obtained by using the ARM processor according to the edge position electrical signal through the data interaction between the FPGA controller and the ARM processor. Then, the edge-searching motion module is controlled to move according to the wafer offset data, so as to realize the edge-searching positioning of the wafer. Then, the wafer surface image is acquired by using the integration between the image sensor, the OCR recognition component and the ARM processor, and the ID number of the wafer to be detected is identified and output according to the acquired wafer surface image, so as to realize the identification of the ID number of the wafer, and further ensure the identification alignment requirement of the edge cutting position and the management requirement of the wafer transmission when the wafer flows between different process equipment.

[0152] The control method for wafer edge-searching positioning and ID number identification in this embodiment realizes the design of integrating the wafer edge-searching positioning function and the ID number identification function, greatly improves the integration degree of the wafer positioning equipment, reduces the equipment development cost, occupies small space, has high work efficiency, and will not cause the phenomenon that the clamp clamping action damages the wafer, and has high stability.

[0153] It should be understood that the wafer edge-searching positioning described in steps S1-S5 and the wafer ID number identification described in steps S6-S8 can be executed simultaneously or sequentially, and the present embodiment does not make any limitation.

[0154] The control system for wafer edge-searching positioning and ID number identification used in the control method described in this embodiment has the same structure as the control system for wafer edge-searching positioning and ID number identification described in Embodiment One, and the details not described in this embodiment are described in detail in Embodiment One and Figures 1 to 2 , and will not be described here again.

[0155] While embodiments of the present application have been described in conjunction with the appended drawings, various modifications and changes can be suggested by persons skilled in the art, and all such modifications and changes are believed to fall within the scope of the present application as defined by the appended claims.

Claims

1. A control system for wafer edge finding positioning and ID number recognition, characterized by, The control system comprises an FPGA controller, a laser emitter, a photoelectric sensor, an ARM processor, an image sensor, an OCR identification component and an edge-searching motion module; The laser emitter and the photoelectric sensor are electrically connected with the FPGA controller, the FPGA controller is in communication connection with the ARM processor, and the image sensor, the OCR identification component and the edge-searching motion module are electrically connected with the ARM processor; The FPGA controller is used for sending a laser emission instruction to the laser emitter; The laser emitter is used for sending a parallel line laser signal to a wafer to be detected according to the received laser emission instruction; The photoelectric sensor is used for collecting an edge position electric signal generated after the parallel line laser signal passes through an edge of the wafer to be detected and transmitting the edge position electric signal to the FPGA controller; The FPGA controller is used for transmitting the received edge position electric signal to the ARM processor; The ARM processor is used for calculating wafer offset data according to the received edge position electric signal and controlling the edge-searching motion module to move to position the wafer to be detected according to the wafer offset data; The ARM processor is also used for sending a wafer image collection instruction to the image sensor; The image sensor is used for acquiring a wafer surface image of the wafer to be detected according to the received image collection instruction and transmitting the wafer surface image to the OCR identification component through the ARM processor; The OCR identification component is used for identifying an ID number of the wafer to be detected according to the received wafer surface image and outputting the ID number.

2. The wafer edge finding positioning and ID number identifying control system of claim 1, wherein, The control system further comprises a first PWM control unit; The FPGA controller is electrically connected with the laser emitter through the first PWM control unit; The FPGA controller is specifically used for: sending the laser emission instruction to the first PWM control unit; The first PWM control unit is used for generating a first PWM control signal according to the received laser emission instruction and sending the first PWM control signal to the laser emitter; The laser emitter is specifically used for: sending the parallel line laser signal to the wafer to be detected under the control of the first PWM control signal.

3. The wafer edge finding positioning and ID number identifying control system of claim 1, wherein, The control system further comprises an ADC converter; The photoelectric sensor is electrically connected with the FPGA controller through the ADC converter; The ADC converter is used for converting an analog edge position electric signal collected by the photoelectric sensor into an edge position digital signal, transmitting the edge position digital signal to the FPGA controller and transmitting the edge position digital signal to the ARM processor through the FPGA controller.

4. The wafer edge finding positioning and ID number identifying control system of claim 3, wherein, The wafer offset data comprises a center offset position and a cutting edge offset angle of the wafer to be detected; The ARM processor calculates wafer offset data according to the received edge position electric signal, specifically comprising: According to the edge position digital signal transmitted by the FPGA controller, the edge position coordinates of the wafer to be detected are calculated; According to the edge position coordinates, a curve fitting is performed by using a least square method to obtain an edge curve of the wafer to be detected; According to the edge curve, the center offset position and the edge offset angle of the wafer to be detected are calculated.

5. The wafer edge finding positioning and ID number identifying control system of claim 1, wherein, The OCR recognition component identifies the ID number of the wafer to be detected according to the received wafer surface image and outputs the ID number, specifically including: Based on the DB optimization method, text detection is performed on the wafer surface image to obtain text region polygon information; The text region polygon information is subjected to cropping processing and perspective transformation processing to obtain a text region rectangular frame; Based on the SVTR text recognition method, text recognition is performed on the text region rectangular frame to obtain the ID number of the wafer to be detected and output the ID number.

6. The wafer edge finding positioning and ID number identifying control system of claim 5, wherein, The OCR recognition component performs text detection on the wafer surface image based on the DB optimization method to obtain text region polygon information, specifically including: The wafer surface image is subjected to feature extraction by using a backbone network to obtain multi-stage features; The multi-stage features are subjected to feature fusion by using the neck network structure of the DBFPN to obtain fused features; The fused features are decoded to obtain a probability feature map and a threshold feature map, and the probability feature map and the threshold feature map are fused to obtain a binary feature map; Loss functions of the probability feature map, the threshold feature map and the binary feature map are calculated respectively to obtain a probability map loss, a threshold map loss and a binary map loss; The probability map loss, the threshold map loss and the binary map loss are used for model training, and the wafer surface image corresponding to the text region polygon information is obtained according to the trained text detection model.

7. The wafer edge finding positioning and ID number identifying control system of claim 5, wherein, The OCR recognition component performs text recognition on the text region rectangular frame based on the SVTR text recognition method to obtain the ID number of the wafer to be detected and output the ID number, specifically including: The text region rectangular frame is input into a preset text recognition model to obtain a target text region; The target text region is processed by using a progressive overlapping patch embedding method to obtain a plurality of formats of character components; All character components are subjected to height gradual down-sampling, and parallel linear prediction method is used to decode all character components after height gradual down-sampling to obtain the ID number of the wafer to be detected and output the ID number.

8. The wafer edge finding positioning and ID number identifying control system of claim 1, wherein, The control system further comprises a second PWM control unit and a light supplement lamp; The ARM processor is electrically connected to the light supplement lamp through the second PWM control unit; The ARM processor is further configured to send a light supplement instruction to the second PWM control unit while sending the wafer collection instruction to the image sensor; The second PWM control unit is configured to generate a second PWM control signal according to the received light supplement instruction and send the second PWM control signal to the light supplement lamp; The light supplement lamp is used for emitting light supplement light source to the wafer to be detected under the control of the second PWM control signal, so as to supplement light to the surface of the wafer to be detected.

9. The wafer edge location and ID number identification control system according to any one of claims 1 to 8, wherein, The control system further comprises a stage control assembly; The stage control assembly is electrically connected with the ARM processor, and the stage control assembly is further connected with a stage for placing the wafer to be detected. The ARM processor is further configured to send a stage motion instruction to the stage control assembly before sending a wafer image acquisition instruction to the image sensor and before the FPGA controller sends a laser emission instruction to the laser emitter. The stage control assembly is configured to control the stage on which the wafer to be detected is placed to rotate according to the received stage motion instruction.

10. A control method for wafer edge finding positioning and ID number recognition, characterized by, The control method comprises: sending a laser emission instruction to the laser emitter by using the FPGA controller; sending parallel line laser signals to the wafer to be detected according to the received laser emission instruction by using the laser emitter; acquiring an edge position electric signal generated after the parallel line laser signals pass through the edge of the wafer to be detected by using the photoelectric sensor, and transmitting the edge position electric signal to the FPGA controller; transmitting the received edge position electric signal to the ARM processor by using the FPGA controller; calculating wafer offset data according to the received edge position electric signal by using the ARM processor, and controlling the edge searching motion module to move according to the wafer offset data, so as to position the wafer to be detected; sending a wafer image acquisition instruction to the image sensor by using the ARM processor; acquiring a wafer surface image of the wafer to be detected according to the received image acquisition instruction by using the image sensor, and transmitting the wafer surface image to the OCR recognition assembly through the ARM processor; identifying the ID number of the wafer to be detected according to the received wafer surface image by using the OCR recognition assembly, and outputting the ID number.

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